August 2021 - U-Boot

Pull request: u-boot-rockchip-20210812
by Kever Yang 13 Aug '21

13 Aug '21

Hi Tom, Please pull the rockchip updates/fixes: - Add Rockchip SFC driver support; - DTS sync from kernel; - emmc hs400 support for rk3399; - Fix for spinore bootdevice and MMC boot order; CI: https://source.denx.de/u-boot/custodians/u-boot-rockchip/-/pipelines/8670 Thanks, - Kever The following changes since commit 3e5b62f78888740530e6f3a2e989f4c361a9d52b: configs: Resync with savedefconfig (2021-08-10 15:08:46 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-rockchip.git tags/u-boot-rockchip-20210812 for you to fetch changes up to 60df49d22d2586f50bba11eaa59a55f2baa4671f: rockchip: px30: Support configure SFC (2021-08-12 09:34:11 +0800) ---------------------------------------------------------------- Alex Bee (1): rockchip: Fix MMC boot order Artem Lapkin (1): rk3399: boot_devices fix spinor node name Chris Morgan (5): spi: rockchip_sfc: add support for Rockchip SFC rockchip: px30: Add support for using SFC rockchip: px30: add the serial flash controller mtd: spi-nor-ids: Add XTX XT25F128B rockchip: px30: add support for SFC for Odroid Go Advance Johan Gunnarsson (1): rockchip: Fix u-boot-rockchip.bin build Johan Jonker (5): rockchip: rk3188-cru-common: sync clock dt-binding header from Linux ARM: dts: rockchip: update rk3xxx.dtsi rockchip: rk3188-power: sync power domain dt-binding header from Linux ARM: dts: rockchip: update rk3188.dtsi ARM: dts: rockchip: update rk3188-radxarock.dts Jon Lin (1): rockchip: px30: Support configure SFC Peter Robinson (3): arm: dts: sync the Rockhip 3399 SoCs from Linux arm: dts: sync the Rockhip 3328 SoCs from Linux arm: dts: sync the Rockhip 3368 SoCs from Linux Xiaobo Tian (3): arm64: rk3399: r4s: correct the LEDS label name arm64: rk3399: r4s: Inheritance uses the sdmmc definition in dtsi arm64: rk3399: r4s: Remove undesirable MAC address fetching methods for ethernet Yifeng Zhao (3): mmc: rockchip_sdhci: add phy and clock config for rk3399 mmc: rockchip_sdhci: Add support for RK3568 rockchip: config: evb-rk3399: add hs400 and SDMA support arch/arm/Kconfig | 2 +- arch/arm/dts/px30.dtsi | 38 ++ arch/arm/dts/rk3188-radxarock-u-boot.dtsi | 38 +- arch/arm/dts/rk3188-radxarock.dts | 88 ++-- arch/arm/dts/rk3188-u-boot.dtsi | 13 + arch/arm/dts/rk3188.dtsi | 480 +++++++++++++------ arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi | 17 + arch/arm/dts/rk3326-odroid-go2.dts | 16 + arch/arm/dts/rk3328-evb.dts | 23 +- arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi | 2 +- arch/arm/dts/rk3328-nanopi-r2s.dts | 51 +- arch/arm/dts/rk3328-roc-cc-u-boot.dtsi | 2 +- arch/arm/dts/rk3328-roc-cc.dts | 41 +- arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi | 4 +- arch/arm/dts/rk3328-rock-pi-e.dts | 439 ++++++++++------- arch/arm/dts/rk3328-rock64-u-boot.dtsi | 2 +- arch/arm/dts/rk3328-rock64.dts | 72 +-- arch/arm/dts/rk3328.dtsi | 109 +++-- arch/arm/dts/rk3368-geekbox.dts | 70 +-- arch/arm/dts/rk3368-lion-haikou.dts | 4 + arch/arm/dts/rk3368-lion.dtsi | 21 +- arch/arm/dts/rk3368-px5-evb.dts | 178 +++---- arch/arm/dts/rk3368.dtsi | 65 ++- arch/arm/dts/rk3399-evb.dts | 4 + arch/arm/dts/rk3399-ficus.dts | 29 +- arch/arm/dts/rk3399-firefly.dts | 178 ++++++- arch/arm/dts/rk3399-gru.dtsi | 14 +- arch/arm/dts/rk3399-khadas-edge.dtsi | 40 +- arch/arm/dts/rk3399-leez-p710.dts | 14 +- arch/arm/dts/rk3399-nanopc-t4.dts | 1 + arch/arm/dts/rk3399-nanopi-r4s.dts | 135 +++--- arch/arm/dts/rk3399-nanopi4.dtsi | 18 +- arch/arm/dts/rk3399-opp.dtsi | 40 +- arch/arm/dts/rk3399-orangepi.dts | 72 ++- arch/arm/dts/rk3399-pinebook-pro.dts | 120 +++-- arch/arm/dts/rk3399-puma-haikou.dts | 10 +- arch/arm/dts/rk3399-puma.dtsi | 61 +-- arch/arm/dts/rk3399-roc-pc-mezzanine.dts | 22 +- arch/arm/dts/rk3399-roc-pc.dtsi | 59 ++- arch/arm/dts/rk3399-rock-pi-4.dtsi | 29 +- arch/arm/dts/rk3399-rock-pi-4a.dts | 2 +- arch/arm/dts/rk3399-rock-pi-4b.dts | 6 +- arch/arm/dts/rk3399-rock-pi-4c.dts | 6 +- arch/arm/dts/rk3399-rock960.dts | 82 ++-- arch/arm/dts/rk3399-rock960.dtsi | 10 +- arch/arm/dts/rk3399-rockpro64.dtsi | 95 +++- arch/arm/dts/rk3399.dtsi | 269 ++++++----- arch/arm/dts/rk3399pro-vmarc-som.dtsi | 12 +- arch/arm/dts/rk3xxx-u-boot.dtsi | 35 ++ arch/arm/dts/rk3xxx.dtsi | 215 ++++++--- arch/arm/mach-rockchip/px30/px30.c | 64 +++ arch/arm/mach-rockchip/rk3399/rk3399.c | 2 +- configs/evb-rk3399_defconfig | 2 + drivers/clk/rockchip/clk_px30.c | 32 ++ drivers/mmc/rockchip_sdhci.c | 422 +++++++++++++++-- drivers/mtd/spi/Kconfig | 6 + drivers/mtd/spi/spi-nor-ids.c | 4 + drivers/spi/Kconfig | 8 + drivers/spi/Makefile | 1 + drivers/spi/rockchip_sfc.c | 646 ++++++++++++++++++++++++++ include/configs/rockchip-common.h | 6 +- include/dt-bindings/clock/rk3188-cru-common.h | 12 +- include/dt-bindings/power/rk3188-power.h | 24 + 63 files changed, 3337 insertions(+), 1245 deletions(-) create mode 100644 arch/arm/dts/rk3xxx-u-boot.dtsi create mode 100644 drivers/spi/rockchip_sfc.c create mode 100644 include/dt-bindings/power/rk3188-power.h

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[PATCH v2 0/3] efi: Minimal revert to rodata change
by Simon Glass 13 Aug '21

13 Aug '21

The changes to move from devicetree to rodata take things in the wrong direction for various reasons: - devicetree is where config should be stored - it provides no memory production in any case, particularly when U-Boot is relocated - testing becomes harder, with the suggestion of adding an entire new sandbox build just for this Revert this until a new direction can be established. Changes in v2: - Also revert two other patches, based on comment from Takahiro Simon Glass (3): Revert "doc: Update CapsuleUpdate READMEs" Revert "mkeficapsule: Remove dtb related options" Revert "efi_capsule: Move signature from DTB to .rodata" board/emulation/common/Makefile | 1 + board/emulation/common/qemu_capsule.c | 43 ++++ doc/board/emulation/qemu_capsule_update.rst | 203 +++++++++++++++++ doc/develop/uefi/uefi.rst | 125 ----------- include/asm-generic/sections.h | 2 - lib/efi_loader/Kconfig | 7 - lib/efi_loader/Makefile | 8 - lib/efi_loader/efi_capsule.c | 18 +- lib/efi_loader/efi_capsule_key.S | 17 -- tools/mkeficapsule.c | 229 +++++++++++++++++++- 10 files changed, 472 insertions(+), 181 deletions(-) create mode 100644 board/emulation/common/qemu_capsule.c create mode 100644 doc/board/emulation/qemu_capsule_update.rst delete mode 100644 lib/efi_loader/efi_capsule_key.S -- 2.32.0.554.ge1b32706d8-goog

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[PATCH 2/2] armv8: Ensure EL1&0 VMSA is enabled
by Peter Hoyes 13 Aug '21

13 Aug '21

From: Peter Hoyes <Peter.Hoyes(a)arm.com> On Armv8-R, the EL1&0 memory system architecture is configurable as a VMSA or PMSA, and resets to an "architecturally unknown" value. Add code to armv8_switch_to_el1_m which detects whether the MSA at EL1&0 is configurable using the id_aa64mmfr0_el1 register MSA fields. If it is we must ensure the VMSA is enabled so that a rich OS can boot. The MSA and MSA_FRAC fields are described in the Armv8-R architecture profile supplement (section G1.3.7): https://developer.arm.com/documentation/ddi0600/latest/ Signed-off-by: Peter Hoyes <Peter.Hoyes(a)arm.com> --- arch/arm/include/asm/macro.h | 17 +++++++++++++++++ arch/arm/include/asm/system.h | 24 ++++++++++++++++++++++++ 2 files changed, 41 insertions(+) diff --git a/arch/arm/include/asm/macro.h b/arch/arm/include/asm/macro.h index e1eefc283f..ecd8221c0d 100644 --- a/arch/arm/include/asm/macro.h +++ b/arch/arm/include/asm/macro.h @@ -316,6 +316,23 @@ lr .req x30 csel \tmp, \tmp2, \tmp, eq msr hcr_el2, \tmp + /* + * Detect whether the system has a configurable memory system + * architecture at EL1&0 + */ + mrs \tmp, id_aa64mmfr0_el1 + lsr \tmp, \tmp, #48 + and \tmp, \tmp, #((ID_AA64MMFR0_EL1_MSA_MASK | \ + ID_AA64MMFR0_EL1_MSA_FRAC_MASK) >> 48) + cmp \tmp, #((ID_AA64MMFR0_EL1_MSA_USE_FRAC | \ + ID_AA64MMFR0_EL1_MSA_FRAC_VMSA) >> 48) + bne 2f + + /* Ensure the EL1&0 VMSA is enabled */ + mov \tmp, #(VTCR_EL2_MSA) + msr vtcr_el2, \tmp +2: + /* Return to the EL1_SP1 mode from EL2 */ ldr \tmp, =(SPSR_EL_DEBUG_MASK | SPSR_EL_SERR_MASK |\ SPSR_EL_IRQ_MASK | SPSR_EL_FIQ_MASK |\ diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 77aa18909e..e4c11e830a 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -83,6 +83,30 @@ #define HCR_EL2_RW_AARCH32 (0 << 31) /* Lower levels are AArch32 */ #define HCR_EL2_HCD_DIS (1 << 29) /* Hypervisor Call disabled */ +/* + * VTCR_EL2 bits definitions + */ +#define VTCR_EL2_MSA (1 << 31) /* EL1&0 memory architecture */ + +/* + * ID_AA64MMFR0_EL1 bits definitions + */ +#define ID_AA64MMFR0_EL1_MSA_FRAC_MASK (0xFUL << 52) /* Memory system + architecture + frac */ +#define ID_AA64MMFR0_EL1_MSA_FRAC_VMSA (0x2UL << 52) /* EL1&0 supports + VMSA */ +#define ID_AA64MMFR0_EL1_MSA_FRAC_PMSA (0x1UL << 52) /* EL1&0 only + supports PMSA*/ +#define ID_AA64MMFR0_EL1_MSA_FRAC_NO_PMSA (0x0UL << 52) /* No PMSA + support */ +#define ID_AA64MMFR0_EL1_MSA_MASK (0xFUL << 48) /* Memory system + architecture */ +#define ID_AA64MMFR0_EL1_MSA_USE_FRAC (0xFUL << 48) /* Use MSA_FRAC */ +#define ID_AA64MMFR0_EL1_MSA_VMSA (0x0UL << 48) /* Memory system + architecture + is VMSA */ + /* * ID_AA64ISAR1_EL1 bits definitions */ -- 2.25.1

1 0

[PATCH v2 0/6] Support SiFive Composable cache driver
by Zong Li 13 Aug '21

13 Aug '21

This patch set contains the SiFive composable cache support, and indroduce an interface to do cache initialization, each platform can overwrite it by their own implementation. Changed in v2: - Refine the ccache driver by Sean's suggestions - Introduce a common interface for cache initialization Zong Li (6): cache: add sifive composable cache driver board: sifive: use ccache driver instead of helper function riscv: lib: introduce cache_init interface riscv: sifive: use common cache_init instead of duplicated implementation riscv: lib: move platform-related libraries to sperate folder riscv: lib: modify the indent arch/riscv/Kconfig | 12 ++++ arch/riscv/cpu/fu540/Kconfig | 2 + arch/riscv/cpu/fu540/Makefile | 1 - arch/riscv/cpu/fu540/cache.c | 55 --------------- arch/riscv/cpu/fu740/Kconfig | 2 + arch/riscv/cpu/fu740/Makefile | 1 - arch/riscv/cpu/fu740/cache.c | 55 --------------- arch/riscv/include/asm/arch-fu540/cache.h | 14 ---- arch/riscv/include/asm/arch-fu740/cache.h | 14 ---- arch/riscv/include/asm/cache.h | 3 +- arch/riscv/lib/Makefile | 8 +-- arch/riscv/lib/andestech/Kconfig | 8 +++ arch/riscv/lib/andestech/Makefile | 7 ++ arch/riscv/lib/{ => andestech}/andes_plic.c | 0 arch/riscv/lib/cache.c | 5 ++ arch/riscv/lib/sifive/Kconfig | 8 +++ arch/riscv/lib/sifive/Makefile | 9 +++ arch/riscv/lib/sifive/sifive_cache.c | 27 ++++++++ arch/riscv/lib/{ => sifive}/sifive_clint.c | 0 board/sifive/unleashed/unleashed.c | 12 +--- board/sifive/unmatched/unmatched.c | 11 +-- drivers/cache/Kconfig | 7 ++ drivers/cache/Makefile | 1 + drivers/cache/cache-sifive-ccache.c | 75 +++++++++++++++++++++ 24 files changed, 173 insertions(+), 164 deletions(-) delete mode 100644 arch/riscv/cpu/fu540/cache.c delete mode 100644 arch/riscv/cpu/fu740/cache.c delete mode 100644 arch/riscv/include/asm/arch-fu540/cache.h delete mode 100644 arch/riscv/include/asm/arch-fu740/cache.h create mode 100644 arch/riscv/lib/andestech/Kconfig create mode 100644 arch/riscv/lib/andestech/Makefile rename arch/riscv/lib/{ => andestech}/andes_plic.c (100%) create mode 100644 arch/riscv/lib/sifive/Kconfig create mode 100644 arch/riscv/lib/sifive/Makefile create mode 100644 arch/riscv/lib/sifive/sifive_cache.c rename arch/riscv/lib/{ => sifive}/sifive_clint.c (100%) create mode 100644 drivers/cache/cache-sifive-ccache.c -- 2.32.0

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[PATCH 1/1] riscv: show code leading to exception
by Heinrich Schuchardt 13 Aug '21

13 Aug '21

To make analyzing exceptions easier output the code that leads to it. We already do the same on the ARM platform. Here is an example: => exception ebreak Unhandled exception: Breakpoint EPC: 000000008ff5d50e RA: 000000008ff5d62c TVAL: 0000000000000000 EPC: 000000008020b50e RA: 000000008020b62c reloc adjusted Code: 2785 0693 07a0 dce3 fef6 47a5 d563 00e7 (9002) To disassemble the code we can use the decodecode script: $ echo 'Code: 2785 0693 07a0 dce3 fef6 47a5 d563 00e7 (9002)' | \ CROSS_COMPILE=riscv64-linux-gnu- scripts/decodecode Code: 2785 0693 07a0 dce3 fef6 47a5 d563 00e7 (9002) All code ======== 0: 2785 addiw a5,a5,1 2: 07a00693 li a3,122 6: fef6dce3 bge a3,a5,0xfffffffffffffffe a: 47a5 li a5,9 c: 00e7d563 bge a5,a4,0x16 10:* 9002 ebreak <-- trapping instruction ... Code starting with the faulting instruction =========================================== 0: 9002 ebreak ... As it is not always clear if the first 16 bits are at the start or in the middle of a 32bit instruction it may become necessary to strip the first u16 from the output before calling decodecode to get the correct disassembled code. Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- arch/riscv/lib/interrupts.c | 42 +++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/riscv/lib/interrupts.c b/arch/riscv/lib/interrupts.c index 7525c152b8..31b8a6603c 100644 --- a/arch/riscv/lib/interrupts.c +++ b/arch/riscv/lib/interrupts.c @@ -51,6 +51,47 @@ static void show_regs(struct pt_regs *regs) #endif } +/** + * instr_len() - get instruction length + * + * @i: low 16 bits of the instruction + * Return: number of u16 in instruction + */ +static int instr_len(u16 i) +{ + if ((i & 0x03) != 0x03) + return 1; + if ((i & 0x1c) != 0x1c) + return 2; + if ((i & 0x3f) == 0x1f) + return 3; + if ((i & 0x7f) == 0x3f) + return 4; + i = (i >> 12) & 0x07; + if (i < 7) + return i + 5; + /* Encoding for >= 192 bits is not yet defined */ + return 1; +} + +/** + * show_code() - display code leading to exception + * + * @epc: program counter + */ +static void show_code(ulong epc) +{ + u16 *pos = (u16 *)(epc & ~1UL); + int i, len = instr_len(*pos); + + printf("\nCode: "); + for (i = -8; i; ++i) + printf("%04x ", pos[i]); + printf("("); + for (i = 0; i < len; ++i) + printf("%04x%s", pos[i], i + 1 == len ? ")\n" : " "); +} + static void _exit_trap(ulong code, ulong epc, ulong tval, struct pt_regs *regs) { static const char * const exception_code[] = { @@ -85,6 +126,7 @@ static void _exit_trap(ulong code, ulong epc, ulong tval, struct pt_regs *regs) epc - gd->reloc_off, regs->ra - gd->reloc_off); show_regs(regs); + show_code(epc); show_efi_loaded_images(epc); panic("\n"); } -- 2.30.2

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[PATCH] x86: crownbay: Enable CONFIG_SPI_FLASH_SMART_HWCAPS
by Bin Meng 13 Aug '21

13 Aug '21

Now that the spi-nor fix has been made in u-boot/master via: commit 87e7219f9c6a ("mtd: spi-nor: Respect flash's hwcaps in spi_nor_adjust_hwcaps()") enable CONFIG_SPI_FLASH_SMART_HWCAPS on Intel Crown Bay again. Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- configs/crownbay_defconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/configs/crownbay_defconfig b/configs/crownbay_defconfig index 1923f89b9a..58c370a989 100644 --- a/configs/crownbay_defconfig +++ b/configs/crownbay_defconfig @@ -47,7 +47,6 @@ CONFIG_TFTP_TSIZE=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_CPU=y -# CONFIG_SPI_FLASH_SMART_HWCAPS is not set CONFIG_E1000=y CONFIG_SOUND=y CONFIG_SOUND_I8254=y -- 2.25.1

2 2

[PATCH 1/2] x86: crownbay: Enable SeaBIOS support
by Bin Meng 13 Aug '21

13 Aug '21

Enable SeaBIOS support for any kernel that requires legacy BIOS services. Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- configs/crownbay_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/crownbay_defconfig b/configs/crownbay_defconfig index d7ee0fe45e..1923f89b9a 100644 --- a/configs/crownbay_defconfig +++ b/configs/crownbay_defconfig @@ -12,6 +12,7 @@ CONFIG_DISABLE_IGD=y CONFIG_SMP=y CONFIG_GENERATE_PIRQ_TABLE=y CONFIG_GENERATE_MP_TABLE=y +CONFIG_SEABIOS=y CONFIG_FIT=y CONFIG_SHOW_BOOT_PROGRESS=y CONFIG_USE_BOOTARGS=y -- 2.25.1

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Proposal: U-Boot MTD (rewriting old story)
by Jagan Teki 12 Aug '21

12 Aug '21

Yes, this is the old discussion and triggered again now since we had a discussion on the last U-Boot contributor call. I will brief the main points here, as most of the details are mentioned in previous threads. Here are the couple of old and new implementations on the SPI-NOR side. http://u-boot.10912.n7.nabble.com/PATCH-v10-00-27-dm-Generic-MTD-Subsystem-… http://u-boot.10912.n7.nabble.com/PATCH-0-5-mtd-Implement-MTD-UCLASS-use-SP… https://patchwork.ozlabs.org/project/uboot/cover/20200709111709.68904-1-jag… Idea is to 1. Create MTD_UCLASS, already present 2. Create DM MTD Operations, above patchset does. 3. Create Flash specific MTD UClass's like UCLASS_NAND UCLASS_SPI_NAND UCLASS_SPI_NOR UCLASS_NOR UCLASS_UBI and register to UCLASS_MTD as interface slaves like how MMC, SCSI are registered to UCLASS_BLK 4. Sync only respective flash specific code, and drop __UBOOT__ 5. Interface mtd, sf, and nand commands to UCLASS_MTD. Hard points: 1. Hard to arrange Linux specific code and drop unneeded _UBOOT_ code, but possible. 2. Requires a lot of testing. Any inputs? Jagan.

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[RFC PATCH v8 0/5] rockchip_sfc: add support for Rockchip SFC
by Jon Lin 12 Aug '21

12 Aug '21

Changes in v8: - Move speed operation to set_speed logic - Use read_poll - Change debug to dev_dbg - Simply exec_op dma logic - Change to use tx single line to make a good compatible - Change spiflash dts node Changes in v7: - Make sfc-use-dma configurable - Make px30 SFC clock configurable Changes in v6: - Fix dma transfer logic - Fix the error of the way to wait for dma transfer finished status Changes in v5: - Support dma transfer - Add CONFIG_IS_ENABLED(CLK) limitation - Support spinand devices - Support SFC ver4 ver5 - Using "rockchip, sfc" as compatible id - Get clock from the index to compatible with those case which's clock-names is not parsed - px30 use "rockchip, sfc" as compatible id Changes in v4: - None Changes in v3: - Added "rockchip_sfc_adjust_op_work()" function from proposed Linux driver to fix potential issue on hardware. Note I never noticed this issue while testing, so I cannot test if it fixed any specific issue for me. - Updated of-compatible string back to "rockchip,sfc" to match what is currently proposed for upstream driver. The hardware itself has multiple versions but a register is present in the hardware that is read by the driver to set version specific functionality. - Updated px30.dtsi and rk3266-odroid-go2.dts device-trees so that sfc nodes match what is in upstream. Changes in v2: - Resending due to glitch with patch file truncating final two lines on patch 1/5 and incorrect patch version number on patch 5/5. Changes in v1: - Reworked code to utilize spi-mem framework, and based it closely off of work in progress code for mainline Linux. - Removed DMA, as it didn't offer much performance benefit for booting (in my test cases), added complexity to the code, and interfered with A-TF. - Updated the names of the bindings to match the work in progress Linux code. - Moved alias to u-boot specific device-tree for Odroid Go Advance. Alias is updated with the spi0 node pointing to the SFC to help the sf command as well as facilitate booting from the SFC. - Note 2 below no longer applies, as rebasing this off of upstream code should allow the device to work for NAND, and by utilizing the spi-mem framework it no longer has to extract the parameters Chris Morgan (4): spi: rockchip_sfc: add support for Rockchip SFC rockchip: px30: Add support for using SFC rockchip: px30: add the serial flash controller rockchip: px30: add support for SFC for Odroid Go Advance Jon Lin (1): rockchip: px30: Support configure SFC arch/arm/dts/px30.dtsi | 38 ++ arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi | 17 + arch/arm/dts/rk3326-odroid-go2.dts | 16 + arch/arm/mach-rockchip/px30/px30.c | 64 ++ drivers/clk/rockchip/clk_px30.c | 32 + drivers/spi/Kconfig | 8 + drivers/spi/Makefile | 1 + drivers/spi/rockchip_sfc.c | 646 +++++++++++++++++++++ 8 files changed, 822 insertions(+) create mode 100644 drivers/spi/rockchip_sfc.c -- 2.17.1

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[RFC PATCH v8 0/6] rockchip_sfc: add support for Rockchip SFC
by Jon Lin 12 Aug '21

12 Aug '21

Changes in v8: - Move speed operation to set_speed logic - Use read_poll - Change debug to dev_dbg - Simply exec_op dma logic - Change to use tx single line to make a good compatible - Change spiflash dts node Changes in v7: - Make sfc-use-dma configurable - Make px30 SFC clock configurable Changes in v6: - Fix dma transfer logic - Fix the error of the way to wait for dma transfer finished status Changes in v5: - Support dma transfer - Add CONFIG_IS_ENABLED(CLK) limitation - Support spinand devices - Support SFC ver4 ver5 - Using "rockchip, sfc" as compatible id - Get clock from the index to compatible with those case which's clock-names is not parsed - px30 use "rockchip, sfc" as compatible id Changes in v4: - None Changes in v3: - Added "rockchip_sfc_adjust_op_work()" function from proposed Linux driver to fix potential issue on hardware. Note I never noticed this issue while testing, so I cannot test if it fixed any specific issue for me. - Updated of-compatible string back to "rockchip,sfc" to match what is currently proposed for upstream driver. The hardware itself has multiple versions but a register is present in the hardware that is read by the driver to set version specific functionality. - Updated px30.dtsi and rk3266-odroid-go2.dts device-trees so that sfc nodes match what is in upstream. Changes in v2: - Resending due to glitch with patch file truncating final two lines on patch 1/5 and incorrect patch version number on patch 5/5. Changes in v1: - Reworked code to utilize spi-mem framework, and based it closely off of work in progress code for mainline Linux. - Removed DMA, as it didn't offer much performance benefit for booting (in my test cases), added complexity to the code, and interfered with A-TF. - Updated the names of the bindings to match the work in progress Linux code. - Moved alias to u-boot specific device-tree for Odroid Go Advance. Alias is updated with the spi0 node pointing to the SFC to help the sf command as well as facilitate booting from the SFC. - Note 2 below no longer applies, as rebasing this off of upstream code should allow the device to work for NAND, and by utilizing the spi-mem framework it no longer has to extract the parameters Chris Morgan (4): spi: rockchip_sfc: add support for Rockchip SFC rockchip: px30: Add support for using SFC rockchip: px30: add the serial flash controller rockchip: px30: add support for SFC for Odroid Go Advance Jon Lin (1): rockchip: px30: Support configure SFC Tom Rini (1): CI: Update to LLVM-12 .azure-pipelines.yml | 4 +- .gitlab-ci.yml | 4 +- arch/arm/dts/px30.dtsi | 38 ++ arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi | 17 + arch/arm/dts/rk3326-odroid-go2.dts | 16 + arch/arm/mach-rockchip/px30/px30.c | 64 ++ drivers/clk/rockchip/clk_px30.c | 32 + drivers/spi/Kconfig | 8 + drivers/spi/Makefile | 1 + drivers/spi/rockchip_sfc.c | 646 +++++++++++++++++++++ tools/docker/Dockerfile | 6 +- 11 files changed, 829 insertions(+), 7 deletions(-) create mode 100644 drivers/spi/rockchip_sfc.c -- 2.17.1

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