August 2021 - U-Boot

[PATCH 1/1] doc: rename Freescale to NXP
by Heinrich Schuchardt 16 Aug '21

16 Aug '21

Freescale Semiconductor, Inc. was merged into NXP Semiconductors in 2015. Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- doc/board/index.rst | 2 +- doc/board/{freescale => nxp}/imx8mm_evk.rst | 0 doc/board/{freescale => nxp}/imx8mn_evk.rst | 0 doc/board/{freescale => nxp}/imx8mp_evk.rst | 0 doc/board/{freescale => nxp}/imx8mq_evk.rst | 0 doc/board/{freescale => nxp}/imx8qxp_mek.rst | 0 doc/board/{freescale => nxp}/imxrt1020-evk.rst | 0 doc/board/{freescale => nxp}/imxrt1050-evk.rst | 0 doc/board/{freescale => nxp}/index.rst | 4 ++-- doc/board/{freescale => nxp}/mx6sabreauto.rst | 0 doc/board/{freescale => nxp}/mx6sabresd.rst | 0 doc/board/{freescale => nxp}/mx6ul_14x14_evk.rst | 0 doc/board/{freescale => nxp}/mx6ullevk.rst | 0 doc/board/{freescale => nxp}/psb.rst | 0 14 files changed, 3 insertions(+), 3 deletions(-) rename doc/board/{freescale => nxp}/imx8mm_evk.rst (100%) rename doc/board/{freescale => nxp}/imx8mn_evk.rst (100%) rename doc/board/{freescale => nxp}/imx8mp_evk.rst (100%) rename doc/board/{freescale => nxp}/imx8mq_evk.rst (100%) rename doc/board/{freescale => nxp}/imx8qxp_mek.rst (100%) rename doc/board/{freescale => nxp}/imxrt1020-evk.rst (100%) rename doc/board/{freescale => nxp}/imxrt1050-evk.rst (100%) rename doc/board/{freescale => nxp}/index.rst (86%) rename doc/board/{freescale => nxp}/mx6sabreauto.rst (100%) rename doc/board/{freescale => nxp}/mx6sabresd.rst (100%) rename doc/board/{freescale => nxp}/mx6ul_14x14_evk.rst (100%) rename doc/board/{freescale => nxp}/mx6ullevk.rst (100%) rename doc/board/{freescale => nxp}/psb.rst (100%) diff --git a/doc/board/index.rst b/doc/board/index.rst index 9e90978891..33087074fa 100644 --- a/doc/board/index.rst +++ b/doc/board/index.rst @@ -14,11 +14,11 @@ Board-specific doc congatec/index coreboot/index emulation/index - freescale/index google/index intel/index kontron/index microchip/index + nxp/index openpiton/index qualcomm/index rockchip/index diff --git a/doc/board/freescale/imx8mm_evk.rst b/doc/board/nxp/imx8mm_evk.rst similarity index 100% rename from doc/board/freescale/imx8mm_evk.rst rename to doc/board/nxp/imx8mm_evk.rst diff --git a/doc/board/freescale/imx8mn_evk.rst b/doc/board/nxp/imx8mn_evk.rst similarity index 100% rename from doc/board/freescale/imx8mn_evk.rst rename to doc/board/nxp/imx8mn_evk.rst diff --git a/doc/board/freescale/imx8mp_evk.rst b/doc/board/nxp/imx8mp_evk.rst similarity index 100% rename from doc/board/freescale/imx8mp_evk.rst rename to doc/board/nxp/imx8mp_evk.rst diff --git a/doc/board/freescale/imx8mq_evk.rst b/doc/board/nxp/imx8mq_evk.rst similarity index 100% rename from doc/board/freescale/imx8mq_evk.rst rename to doc/board/nxp/imx8mq_evk.rst diff --git a/doc/board/freescale/imx8qxp_mek.rst b/doc/board/nxp/imx8qxp_mek.rst similarity index 100% rename from doc/board/freescale/imx8qxp_mek.rst rename to doc/board/nxp/imx8qxp_mek.rst diff --git a/doc/board/freescale/imxrt1020-evk.rst b/doc/board/nxp/imxrt1020-evk.rst similarity index 100% rename from doc/board/freescale/imxrt1020-evk.rst rename to doc/board/nxp/imxrt1020-evk.rst diff --git a/doc/board/freescale/imxrt1050-evk.rst b/doc/board/nxp/imxrt1050-evk.rst similarity index 100% rename from doc/board/freescale/imxrt1050-evk.rst rename to doc/board/nxp/imxrt1050-evk.rst diff --git a/doc/board/freescale/index.rst b/doc/board/nxp/index.rst similarity index 86% rename from doc/board/freescale/index.rst rename to doc/board/nxp/index.rst index aa192effab..63956287c5 100644 --- a/doc/board/freescale/index.rst +++ b/doc/board/nxp/index.rst @@ -1,7 +1,7 @@ .. SPDX-License-Identifier: GPL-2.0+ -Freescale -========= +NXP Semiconductors +================== .. toctree:: :maxdepth: 2 diff --git a/doc/board/freescale/mx6sabreauto.rst b/doc/board/nxp/mx6sabreauto.rst similarity index 100% rename from doc/board/freescale/mx6sabreauto.rst rename to doc/board/nxp/mx6sabreauto.rst diff --git a/doc/board/freescale/mx6sabresd.rst b/doc/board/nxp/mx6sabresd.rst similarity index 100% rename from doc/board/freescale/mx6sabresd.rst rename to doc/board/nxp/mx6sabresd.rst diff --git a/doc/board/freescale/mx6ul_14x14_evk.rst b/doc/board/nxp/mx6ul_14x14_evk.rst similarity index 100% rename from doc/board/freescale/mx6ul_14x14_evk.rst rename to doc/board/nxp/mx6ul_14x14_evk.rst diff --git a/doc/board/freescale/mx6ullevk.rst b/doc/board/nxp/mx6ullevk.rst similarity index 100% rename from doc/board/freescale/mx6ullevk.rst rename to doc/board/nxp/mx6ullevk.rst diff --git a/doc/board/freescale/psb.rst b/doc/board/nxp/psb.rst similarity index 100% rename from doc/board/freescale/psb.rst rename to doc/board/nxp/psb.rst -- 2.30.2

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[ANN] U-Boot v2021.10-rc2 released
by Tom Rini 16 Aug '21

16 Aug '21

Hey all, So, whoops. It's a week later than release day should be because my reminders were off by a week. With that, here's v2021.10-rc2. I don't think it's really bigger than it should otherwise be, all things considered. One thing I'm working through currently is migrating some of the I2C related CONFIG symbols in to Kconfig (or out of the CONFIG namespace). This should be posted soon, but I think will only be safe to merge once -next opens up. In terms of a changelog, git log --merges v2021.10-rc1..v2021.10-rc2 contains what I've pulled but as always, better PR messages and tags will provide better results here. Given that I'm off by a week, we'll continue with every other week from here out, and that shouldn't impact the October 4th, 2021 release date. Thanks all! -- Tom

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[PULL] Pull request for u-boot master / v2021.10 = u-boot-stm32-20210816
by Patrice CHOTARD 16 Aug '21

16 Aug '21

Hi Tom Please pull the STM32 related patches for u-boot/master, v2021.10: u-boot-stm32-20210816 CI status : https://source.denx.de/u-boot/custodians/u-boot-stm/-/pipelines/8728 Thanks Patrice ---------------------------------------------------------------- Highlights: - Handle TF-A boot with FIP for STM32MP1 - Fix board_get_usable_ram_top(0) for STM32MP1 - DT alignement with kernel v5.14 for STM32MP1 - SPI-NOR DT update for DHSOM - Add UCLASS API for ECDSA singnature and implement it for STM32MP1 ---------------------------------------------------------------- The following changes since commit fdc4fda33051bcb9eb782001afe2bdd3c0d09eae: Merge tag 'efi-2021-10-rc2-2' of https://source.denx.de/u-boot/custodians/u-boot-efi (2021-08-15 13:42:42 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-stm.git for you to fetch changes up to 46a738a4ec81959c7545a4bb07e4f5232bbcfefe: test: dm: Add test for ECDSA UCLASS support (2021-08-16 10:49:35 +0200) ---------------------------------------------------------------- Alexandru Gagniuc (5): dm: crypto: Define UCLASS API for ECDSA signature verification lib: ecdsa: Implement UCLASS_ECDSA verification on target arm: stm32mp1: Implement ECDSA signature verification Kconfig: FIT_SIGNATURE should not select RSA_VERIFY test: dm: Add test for ECDSA UCLASS support Marek Vasut (2): ARM: stm32: Set environment sector size to 4k on DHSOM ARM: dts: stm32: Reduce DHCOR SPI NOR frequency to 50 MHz Patrick Delaunay (8): clk: stm32mp1: add support of BSEC clock arm: stm32mp: add config for STM32IMAGE support arm: stm32mp: handle the OP-TEE nodes in DT with FIP support arm: stm32mp: add defconfig for trusted boot with FIP doc: st: stm32mp1: Add FIP support for trusted boot stm32mp1: stm32prog: remove stm32prog_get_tee_partitions with FIP stm32mp: correctly handle board_get_usable_ram_top(0) arm: dts: stm32mp15: alignment with v5.14 arch/arm/dts/stm32mp15-pinctrl.dtsi | 33 +++ arch/arm/dts/stm32mp151.dtsi | 16 +- arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi | 9 +- ...m32mp157a-microgea-stm32mp1-microdev2.0-of7.dts | 2 +- arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi | 9 +- arch/arm/dts/stm32mp15xx-dhcor-io3v3.dtsi | 2 +- arch/arm/mach-stm32mp/Kconfig | 16 + arch/arm/mach-stm32mp/Makefile | 1 + .../arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c | 2 + arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c | 4 + arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h | 2 + arch/arm/mach-stm32mp/config.mk | 2 +- arch/arm/mach-stm32mp/dram_init.c | 3 + arch/arm/mach-stm32mp/ecdsa_romapi.c | 102 +++++++ arch/arm/mach-stm32mp/fdt.c | 11 +- arch/arm/mach-stm32mp/include/mach/stm32prog.h | 2 + board/st/common/Kconfig | 21 +- board/st/common/stm32mp_mtdparts.c | 31 +- board/st/stm32mp1/MAINTAINERS | 1 + board/st/stm32mp1/stm32mp1.c | 10 +- common/Kconfig.boot | 8 +- configs/sandbox_defconfig | 2 + configs/stm32mp15_defconfig | 158 ++++++++++ configs/stm32mp15_dhcom_basic_defconfig | 2 +- configs/stm32mp15_dhcor_basic_defconfig | 2 +- configs/stm32mp15_trusted_defconfig | 1 + doc/board/st/stm32mp1.rst | 328 +++++++++++++++------ drivers/clk/clk_stm32mp1.c | 1 + include/crypto/ecdsa-uclass.h | 39 +++ include/dm/uclass-id.h | 1 + lib/Kconfig | 1 + lib/Makefile | 1 + lib/ecdsa/Kconfig | 23 ++ lib/ecdsa/Makefile | 1 + lib/ecdsa/ecdsa-verify.c | 134 +++++++++ test/dm/Makefile | 1 + test/dm/ecdsa.c | 38 +++ 37 files changed, 887 insertions(+), 133 deletions(-) create mode 100644 arch/arm/mach-stm32mp/ecdsa_romapi.c create mode 100644 configs/stm32mp15_defconfig create mode 100644 include/crypto/ecdsa-uclass.h create mode 100644 lib/ecdsa/Kconfig create mode 100644 lib/ecdsa/Makefile create mode 100644 lib/ecdsa/ecdsa-verify.c create mode 100644 test/dm/ecdsa.c

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[PATCH 0/5] arm: mach-k3: Fixes for j721e/j7200 clock data and drivers
by Dave Gerlach 16 Aug '21

16 Aug '21

Hi, This series contains several fixes for TI j721e and j7200 platforms data and also some fixes for TI clock drivers that make use of this data. All fixes are related to PLL post dividers reporting the wrong frequency, and now the new frequencies for below clocks match what registers are actually configured for. Clock: Old Frequency -> New Frequency ----------------------------------------- postdiv2_16fft_main_0_hsdivout6_clk: 66666667 -> 200000000 postdiv2_16fft_main_1_hsdivout5_clk: 320000000 -> 960000000 postdiv2_16fft_main_1_hsdivout7_clk: 320000000 -> 960000000 Regards, Dave Dave Gerlach (2): arm: mach-k3: Add note to auto-generated files clk: ti: k3-pll: Change DIV_CTRL programming to read-modify-write Suman Anna (3): arm: mach-k3: j721e: Fix clk-data parenting for postdiv PLL clocks arm: mach-k3: j7200: Fix clk-data parenting for postdiv PLL clocks clk: ti: k3: Update driver to account for divider flags arch/arm/mach-k3/j7200/clk-data.c | 87 ++++++++++++----------- arch/arm/mach-k3/j7200/dev-data.c | 2 + arch/arm/mach-k3/j721e/clk-data.c | 113 +++++++++++++++--------------- arch/arm/mach-k3/j721e/dev-data.c | 2 + drivers/clk/ti/clk-k3-pll.c | 13 +++- drivers/clk/ti/clk-k3.c | 4 +- include/k3-clk.h | 30 ++++---- 7 files changed, 137 insertions(+), 114 deletions(-) -- 2.28.0

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[PATCH v1 0/5] board: toradex: prepare and add colibri imx6ull 1gb (emmc) support
by Marcel Ziswiler 16 Aug '21

16 Aug '21

From: Marcel Ziswiler <marcel.ziswiler(a)toradex.com> Some preparatory steps concerning tdx-cfg-block including a fix for the interactive mode IT handling and adding them new SKUs and then adding initial support for the Toradex Colibri iMX6ULL 1GB (eMMC) V1.1A module. They are now strapped to boot from eFuses which are factory fused to properly boot from their on-module eMMC. Functionality wise the following is known to be working: - 4-bit MMC/SD card slot - 8-bit eMMC (fused default boot) - bmode usb (imx_usb or uuu e.g. as used by the Toradex Easy Installer) - Ethernet - GPIOs - I2C - parallel RGB display - USB device (e.g. for ums) - USB host (e.g. for storage devices) U-Boot 2021.10-rc1-00128-g4877bdab7e6 (Aug 16 2021 - 13:59:21 +0200) CPU: Freescale i.MX6ULL rev1.1 792 MHz (running at 396 MHz) CPU: Industrial temperature grade (-40C to 105C) at 59C Reset cause: WDOG DRAM: 1 GiB MMC: FSL_SDHC: 1, FSL_SDHC: 0 Loading Environment from MMC... OK In: serial Out: serial Err: serial Model: Toradex Colibri iMX6ULL 1GB IT (eMMC) V1.1A, Serial# 06906494 Net: eth1: ethernet@20b4000 Hit any key to stop autoboot: 0 Colibri iMX6ULL # Denys Drozdov (1): toradex: configblock: fix interactive mode it handling Marcel Ziswiler (2): toradex: take over maintainership toradex: tdx-cfg-block: add new i.mx 6ull and 8m plus skus Max Krummenacher (1): colibri-imx6ull: add emmc variant Philippe Schenker (1): colibri-imx6ull: imximage.cfg: integrate new 1GiB RAM variant arch/arm/dts/Makefile | 1 + arch/arm/dts/imx6ull-colibri-emmc.dts | 49 ++++++++++ arch/arm/dts/imx6ull-colibri.dts | 34 ++++++- arch/arm/dts/imx6ull-colibri.dtsi | 32 +------ board/toradex/apalis-imx8x/MAINTAINERS | 2 +- board/toradex/apalis_imx6/MAINTAINERS | 2 +- board/toradex/colibri-imx6ull/Kconfig | 54 ++++++++++- board/toradex/colibri-imx6ull/MAINTAINERS | 6 +- .../toradex/colibri-imx6ull/colibri-imx6ull.c | 27 +++++- board/toradex/colibri-imx6ull/imximage.cfg | 13 ++- board/toradex/colibri_imx6/MAINTAINERS | 2 +- board/toradex/colibri_imx7/MAINTAINERS | 2 +- board/toradex/colibri_t20/MAINTAINERS | 2 +- board/toradex/colibri_t30/MAINTAINERS | 2 +- board/toradex/colibri_vf/MAINTAINERS | 2 +- board/toradex/common/tdx-cfg-block.c | 34 +++++-- board/toradex/common/tdx-cfg-block.h | 5 ++ board/toradex/verdin-imx8mm/MAINTAINERS | 2 +- configs/colibri-imx6ull-emmc_defconfig | 90 +++++++++++++++++++ configs/colibri-imx6ull_defconfig | 1 + include/configs/colibri-imx6ull.h | 53 ++++++++--- 21 files changed, 343 insertions(+), 72 deletions(-) create mode 100644 arch/arm/dts/imx6ull-colibri-emmc.dts create mode 100644 configs/colibri-imx6ull-emmc_defconfig -- 2.26.2

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[PATCH u-boot-mvebu 0/3] turris_omnia: Disable MCU watchdog in SPL when booting over UART
by Marek Behún 16 Aug '21

16 Aug '21

Hello Stefan, while debugging Omnia, when sending U-Boot over UART, some USB-TTY controllers are too slow and Omnia's MCU watchdog resets the board before U-Boot proper is sent. This patch series changes Omnia board code so that when booting via UART, we disable MCU watchdog in SPL, prior loading U-Boot proper. Marek Marek Behún (3): arm: mvebu: Move get_boot_device() to cpu.c and make visible arm: mvebu: turris_omnia: don't guard by CONFIG_SPL_BUILD macro arm: mvebu: turris_omnia: disable MCU watchdog in SPL when booting over UART arch/arm/mach-mvebu/cpu.c | 60 ++++++++++++++++++ arch/arm/mach-mvebu/include/mach/cpu.h | 2 + arch/arm/mach-mvebu/spl.c | 77 +++--------------------- board/CZ.NIC/turris_omnia/turris_omnia.c | 25 +++++--- configs/turris_omnia_defconfig | 1 + 5 files changed, 88 insertions(+), 77 deletions(-) -- 2.31.1

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[PATCH] clk: stm32mp1: add support of BSEC clock
by Patrick Delaunay 16 Aug '21

16 Aug '21

Add the support of the BSEC clock used by the STM32MP misc driver since the commit 622c956cada0 ("stm32mp: bsec: manage clock when present in device tree") even if this clock is not yet defined in kernel device tree stm32mp151.dtsi. This patch avoids issue for basic boot when this secure clock are not provided by secure world with SCMI. Signed-off-by: Patrick Delaunay <patrick.delaunay(a)foss.st.com> --- drivers/clk/clk_stm32mp1.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/clk_stm32mp1.c index 48c9514ba0..96e175f221 100644 --- a/drivers/clk/clk_stm32mp1.c +++ b/drivers/clk/clk_stm32mp1.c @@ -552,6 +552,7 @@ static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = { STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL), STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 3, I2C6_K, _I2C46_SEL), STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 8, RTCAPB, _PCLK5), + STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 16, BSEC, _UNKNOWN_SEL), STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL), STM32MP1_CLK_SET_CLR_F(RCC_MP_AHB2ENSETR, 5, ADC12, _HCLK2), -- 2.25.1

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[PATCH v3 0/5] stm32mp1: handle TF-A boot with FIP
by Patrick Delaunay 16 Aug '21

16 Aug '21

In next TF-A version the stm32mp1 platform will support the Firmware Image Package (FIP) [1], a container filled with: - the U-Boot binary = u-boot-nodtb.bin - the U-Boot device tree = u-boot.dtb - the Secure OS (OP-TEE) or the secure monitor (SP_MIN) Upstream is in progress on TF-A side ([3] but reviews don't yet start). Each part of the FIP is loaded by TF-A BL2 and U-Boot is executed with its device tree address as parameter (nt_fw_dtb = r2 introduced by commit 4ac345220afa ("board: stm32mp1: use FDT address provided by TF-A at boot time") This FIP container simplifies the OP-TEE management (same number of partition with or without OP-TEE, OP-TEE dynamically updates the U-Boot device tree to add the required OP-TEE nodes) and allow support of generic TF-A features as PKI [2]. This serie allows to generate U-Boot configured for the TF-A BL2 image types: - STM32IMAGE: stm32mp15_trusted_defconfig (current behavior) - FIP: stm32mp15_defconfig (NEW) The FIP will be the STMicroelectronics recommended image type for STM32MP15x and the STM32IMAGE support should be marked deprecated in a future TF-A release. To prepare this migration, the serie move all the specific code or device tree nodes for TF-A load of STM32IMAGE under compilation flag CONFIG_STM32MP15x_STM32IMAGE. This V3 serie of [4] is rebased on top for u-boot-stm32/master. I just update documentation after [5] message to clarify TF-A compilation step. [1] 4.11. Firmware Image Package (FIP) fiphttps://trustedfirmware-a.readthedocs.io/en/latest/design/firmware-design.html stm32mp1: handle TF-A boot with FIP [2] Authentication Framework & Chain of Trust https://trustedfirmware-a.readthedocs.io/en/latest/design/auth-framework.ht… [3] TF-A Serie proposal : FIP and FCONF for STM32MP1 https://github.com/Yann-lms/arm-trusted-firmware/commits/fip_fconf [4] stm32mp1: handle TF-A boot with FIP http://patchwork.ozlabs.org/project/uboot/list/?series=253677&state=* [5] U-BOOT 2021.07 and STM32MP15x issues for Trusted Boot Chain https://lists.denx.de/pipermail/u-boot/2021-July/455750.html Changes in v3: - add reference for STM32 WIKI, TF-A and OP-TEE - add information about TF-A compilation and clarify the output files Changes in v2: - synchronize defconfig with latest change - fix one typo: s/ enought / enough Patrick Delaunay (5): arm: stm32mp: add config for STM32IMAGE support arm: stm32mp: handle the OP-TEE nodes in DT with FIP support arm: stm32mp: add defconfig for trusted boot with FIP doc: st: stm32mp1: Add FIP support for trusted boot stm32mp1: stm32prog: remove stm32prog_get_tee_partitions with FIP arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi | 9 +- arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi | 9 +- arch/arm/mach-stm32mp/Kconfig | 7 + .../cmd_stm32prog/cmd_stm32prog.c | 2 + .../mach-stm32mp/cmd_stm32prog/stm32prog.c | 4 + .../mach-stm32mp/cmd_stm32prog/stm32prog.h | 2 + arch/arm/mach-stm32mp/config.mk | 2 +- arch/arm/mach-stm32mp/fdt.c | 11 +- .../arm/mach-stm32mp/include/mach/stm32prog.h | 2 + board/st/common/Kconfig | 21 +- board/st/common/stm32mp_mtdparts.c | 31 +- board/st/stm32mp1/MAINTAINERS | 1 + board/st/stm32mp1/stm32mp1.c | 10 +- configs/stm32mp15_defconfig | 158 +++++++++ configs/stm32mp15_trusted_defconfig | 1 + doc/board/st/stm32mp1.rst | 328 +++++++++++++----- 16 files changed, 481 insertions(+), 117 deletions(-) create mode 100644 configs/stm32mp15_defconfig -- 2.25.1

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[PATCH] arm: dts: stm32mp15: alignment with v5.14
by Patrick Delaunay 16 Aug '21

16 Aug '21

Device tree alignment with Linux kernel v5.14-rc3 - ARM: dts: stm32: move stmmac axi config in ethernet node on stm32mp15 - ARM: dts: stm32: Configure qspi's mdma transfer to block for stm32mp151 - ARM: dts: stm32: add a new DCMI pins group on stm32mp15 - ARM: dts: stm32: fix ltdc pinctrl on microdev2.0-of7 Signed-off-by: Patrick Delaunay <patrick.delaunay(a)foss.st.com> --- arch/arm/dts/stm32mp15-pinctrl.dtsi | 33 +++++++++++++++++++ arch/arm/dts/stm32mp151.dtsi | 16 ++++----- ...157a-microgea-stm32mp1-microdev2.0-of7.dts | 2 +- 3 files changed, 42 insertions(+), 9 deletions(-) diff --git a/arch/arm/dts/stm32mp15-pinctrl.dtsi b/arch/arm/dts/stm32mp15-pinctrl.dtsi index 060baa8b7e..5b60ecbd71 100644 --- a/arch/arm/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/dts/stm32mp15-pinctrl.dtsi @@ -118,6 +118,39 @@ }; }; + dcmi_pins_b: dcmi-1 { + pins { + pinmux = <STM32_PINMUX('A', 4, AF13)>,/* DCMI_HSYNC */ + <STM32_PINMUX('B', 7, AF13)>,/* DCMI_VSYNC */ + <STM32_PINMUX('A', 6, AF13)>,/* DCMI_PIXCLK */ + <STM32_PINMUX('C', 6, AF13)>,/* DCMI_D0 */ + <STM32_PINMUX('H', 10, AF13)>,/* DCMI_D1 */ + <STM32_PINMUX('H', 11, AF13)>,/* DCMI_D2 */ + <STM32_PINMUX('E', 1, AF13)>,/* DCMI_D3 */ + <STM32_PINMUX('E', 11, AF13)>,/* DCMI_D4 */ + <STM32_PINMUX('D', 3, AF13)>,/* DCMI_D5 */ + <STM32_PINMUX('E', 13, AF13)>,/* DCMI_D6 */ + <STM32_PINMUX('B', 9, AF13)>;/* DCMI_D7 */ + bias-disable; + }; + }; + + dcmi_sleep_pins_b: dcmi-sleep-1 { + pins { + pinmux = <STM32_PINMUX('A', 4, ANALOG)>,/* DCMI_HSYNC */ + <STM32_PINMUX('B', 7, ANALOG)>,/* DCMI_VSYNC */ + <STM32_PINMUX('A', 6, ANALOG)>,/* DCMI_PIXCLK */ + <STM32_PINMUX('C', 6, ANALOG)>,/* DCMI_D0 */ + <STM32_PINMUX('H', 10, ANALOG)>,/* DCMI_D1 */ + <STM32_PINMUX('H', 11, ANALOG)>,/* DCMI_D2 */ + <STM32_PINMUX('E', 1, ANALOG)>,/* DCMI_D3 */ + <STM32_PINMUX('E', 11, ANALOG)>,/* DCMI_D4 */ + <STM32_PINMUX('D', 3, ANALOG)>,/* DCMI_D5 */ + <STM32_PINMUX('E', 13, ANALOG)>,/* DCMI_D6 */ + <STM32_PINMUX('B', 9, ANALOG)>;/* DCMI_D7 */ + }; + }; + ethernet0_rgmii_pins_a: rgmii-0 { pins1 { pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */ diff --git a/arch/arm/dts/stm32mp151.dtsi b/arch/arm/dts/stm32mp151.dtsi index 177927d14e..8e0a0bc1dd 100644 --- a/arch/arm/dts/stm32mp151.dtsi +++ b/arch/arm/dts/stm32mp151.dtsi @@ -1399,8 +1399,8 @@ reg = <0x58003000 0x1000>, <0x70000000 0x10000000>; reg-names = "qspi", "qspi_mm"; interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&mdma1 22 0x2 0x100002 0x0 0x0>, - <&mdma1 22 0x2 0x100008 0x0 0x0>; + dmas = <&mdma1 22 0x2 0x10100002 0x0 0x0>, + <&mdma1 22 0x2 0x10100008 0x0 0x0>; dma-names = "tx", "rx"; clocks = <&rcc QSPI_K>; resets = <&rcc QSPI_R>; @@ -1446,12 +1446,6 @@ status = "disabled"; }; - stmmac_axi_config_0: stmmac-axi-config { - snps,wr_osr_lmt = <0x7>; - snps,rd_osr_lmt = <0x7>; - snps,blen = <0 0 0 0 16 8 4>; - }; - ethernet0: ethernet@5800a000 { compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a"; reg = <0x5800a000 0x2000>; @@ -1477,6 +1471,12 @@ snps,axi-config = <&stmmac_axi_config_0>; snps,tso; status = "disabled"; + + stmmac_axi_config_0: stmmac-axi-config { + snps,wr_osr_lmt = <0x7>; + snps,rd_osr_lmt = <0x7>; + snps,blen = <0 0 0 0 16 8 4>; + }; }; usbh_ohci: usb@5800c000 { diff --git a/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts b/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts index 674b2d330d..5670b23812 100644 --- a/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts +++ b/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts @@ -89,7 +89,7 @@ }; &pinctrl { - ltdc_pins: ltdc { + ltdc_pins: ltdc-0 { pins { pinmux = <STM32_PINMUX('G', 10, AF14)>, /* LTDC_B2 */ <STM32_PINMUX('H', 12, AF14)>, /* LTDC_R6 */ -- 2.25.1

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[PATCH] ARM: Prevent the compiler from using NEON registers
by Samuel Holland 16 Aug '21

16 Aug '21

For ARMv8-A, NEON is standard, so the compiler can use it even when no special target flags are provided. For example, it can use stores from NEON registers to zero-initialize large structures. GCC 11 decides to do this inside the DRAM init code for the Allwinner H6, which breaks boot on that platform, as NEON is not available in SPL. Fix this by restricting the compiler to using GPRs only, not vector registers. Signed-off-by: Samuel Holland <samuel(a)sholland.org> --- arch/arm/config.mk | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/config.mk b/arch/arm/config.mk index 16c63e12667..964c6b026ec 100644 --- a/arch/arm/config.mk +++ b/arch/arm/config.mk @@ -25,6 +25,7 @@ endif PLATFORM_RELFLAGS += -fno-common -ffixed-r9 PLATFORM_RELFLAGS += $(call cc-option, -msoft-float) \ + $(call cc-option,-mgeneral-regs-only) \ $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) # LLVM support -- 2.31.1

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