July 2021 - U-Boot

[PATCH v2 0/6] arm64: synquacer: DeveloperBox updates
by Masami Hiramatsu 12 Jul '21

12 Jul '21

Hi, Here is the 2nd version of the series to update the DeveloperBox support. This version is just fixing coding style and typo. So no functional changes. [1/6] board: synquacer: Initialize SCBM SMMU at board_init() - This is a driver cleanup, split the SMMU setup from the driver. [2/6] configs: synquacer: Make U-Boot binary position independent - This makes U-Boot position independent for usability. [3/6] dts: synquacer: Add partition information to the spi-nor [4/6] configs: synquacer: Remove mtdparts settings and update DFU setting - These are the fixes according to the MTD subsystem update. (Thanks Marek!) [5/6] configs: synquacer: Drop Ext2/4 support by default [6/6] configs: synquacer: Enable UEFI secure boot - These are making U-Boot more likely to EDK2 behaviors. Thank you, --- Masami Hiramatsu (6): board: synquacer: Initialize SCBM SMMU at board_init() configs: synquacer: Make U-Boot binary position independent dts: synquacer: Add partition information to the spi-nor configs: synquacer: Remove mtdparts settings and update DFU setting configs: synquacer: Drop Ext2/4 support by default configs: synquacer: Enable UEFI secure boot .../dts/synquacer-sc2a11-developerbox-u-boot.dtsi | 49 ++++++++++++++++++++ board/socionext/developerbox/developerbox.c | 15 ++++++ configs/synquacer_developerbox_defconfig | 9 ++-- drivers/net/sni_netsec.c | 7 --- include/configs/synquacer.h | 2 - 5 files changed, 69 insertions(+), 13 deletions(-) -- Masami Hiramatsu <masami.hiramatsu(a)linaro.org>

2 8

[PATCH V1] arm: add initial support for the Phytium Pomelo Board
by nicholas_zheng＠outlook.com 12 Jul '21

12 Jul '21

From: weichangzheng <nicholas_zheng(a)outlook.com> This adds platform code and the device tree for the Phytium Pomelo Board. The initial support comprises the UART and the PCIE. Signed-off-by: weichangzheng <nicholas_zheng(a)outlook.com> Changes since v1: - updated to DT --- arch/arm/Kconfig | 8 ++ arch/arm/dts/Makefile | 1 + arch/arm/dts/phytium-pomelo.dts | 113 +++++++++++++++++++++ board/phytium/pomelo/Kconfig | 12 +++ board/phytium/pomelo/MAINTAINERS | 8 ++ board/phytium/pomelo/Makefile | 14 +++ board/phytium/pomelo/cpu.h | 73 ++++++++++++++ board/phytium/pomelo/ddr.c | 164 +++++++++++++++++++++++++++++++ board/phytium/pomelo/pcie.c | 61 ++++++++++++ board/phytium/pomelo/pll.c | 75 ++++++++++++++ board/phytium/pomelo/pomelo.c | 120 ++++++++++++++++++++++ board/phytium/pomelo/sec.c | 40 ++++++++ configs/pomelo_defconfig | 36 +++++++ include/configs/pomelo.h | 45 +++++++++ 14 files changed, 770 insertions(+) create mode 100644 arch/arm/dts/phytium-pomelo.dts create mode 100644 board/phytium/pomelo/Kconfig create mode 100644 board/phytium/pomelo/MAINTAINERS create mode 100644 board/phytium/pomelo/Makefile create mode 100644 board/phytium/pomelo/cpu.h create mode 100644 board/phytium/pomelo/ddr.c create mode 100644 board/phytium/pomelo/pcie.c create mode 100644 board/phytium/pomelo/pll.c create mode 100644 board/phytium/pomelo/pomelo.c create mode 100644 board/phytium/pomelo/sec.c create mode 100644 configs/pomelo_defconfig create mode 100644 include/configs/pomelo.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 0448787b8b..0afbb86640 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1818,6 +1818,13 @@ config TARGET_DURIAN Support for durian platform. It has 2GB Sdram, uart and pcie. +config TARGET_POMELO + bool "Support Phytium Pomelo Platform" + select ARM64 + help + Support for pomelo platform. + It has 2GB Sdram, uart and pcie. + config TARGET_PRESIDIO_ASIC bool "Support Cortina Presidio ASIC Platform" select ARM64 @@ -2038,6 +2045,7 @@ source "board/toradex/colibri_pxa270/Kconfig" source "board/variscite/dart_6ul/Kconfig" source "board/vscom/baltos/Kconfig" source "board/phytium/durian/Kconfig" +source "board/phytium/pomelo/Kconfig" source "board/xen/xenguest_arm64/Kconfig" source "board/keymile/Kconfig" diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 9fb38682e6..45d0340bd3 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1107,6 +1107,7 @@ dtb-$(CONFIG_TARGET_MX53PPD) += imx53-ppd.dtb dtb-$(CONFIG_TARGET_TOTAL_COMPUTE) += total_compute.dtb dtb-$(CONFIG_TARGET_DURIAN) += phytium-durian.dtb +dtb-$(CONFIG_TARGET_POMELO) += phytium-pomelo.dtb dtb-$(CONFIG_TARGET_PRESIDIO_ASIC) += ca-presidio-engboard.dtb diff --git a/arch/arm/dts/phytium-pomelo.dts b/arch/arm/dts/phytium-pomelo.dts new file mode 100644 index 0000000000..3869475902 --- /dev/null +++ b/arch/arm/dts/phytium-pomelo.dts @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * dts file for Phytium Pomelo board + * Copyright (C) 2021, Phytium Ltd. + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ +/dts-v1/; + +/ { + model = "Phytium Pomelo"; + compatible = "phytium,pomelo"; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = &uart0; + }; + + cpus { + #address-cells = <0x2>; + #size-cells = <0x0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + numa-node-id = <0>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x1>; + enable-method = "psci"; + numa-node-id = <0>; + }; + + cpu2: cpu@4 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x100>; + enable-method = "psci"; + numa-node-id = <0>; + }; + + cpu3: cpu@5 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x101>; + enable-method = "psci"; + numa-node-id = <0>; + }; + + cpu4: cpu@8 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x200>; + enable-method = "psci"; + numa-node-id = <0>; + }; + + cpu5: cpu@9 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x201>; + enable-method = "psci"; + numa-node-id = <0>; + }; + + cpu6: cpu@12 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x300>; + enable-method = "psci"; + numa-node-id = <0>; + }; + + cpu7: cpu@13 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x301>; + enable-method = "psci"; + numa-node-id = <0>; + }; + }; + + pcie-controller@40000000 { + compatible = "pci-host-ecam-generic"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + reg = <0x0 0x40000000 0x0 0x10000000>; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x00 0x00000000 0x0 0x50000000 0x0 0x00F00000>, + <0x02000000 0x00 0x58000000 0x0 0x58000000 0x0 0x28000000>, + <0x43000000 0x10 0x00000000 0x10 0x00000000 0x10 0x00000000>; + }; + + sysclk_48mhz: clk48mhz { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <48000000>; + clock-output-names = "sysclk_48mhz"; + }; + + uart0: uart@28001000 { + compatible = "arm,pl011"; + reg = <0x0 0x28001000 0x0 0x1000>; + clocks = <&sysclk_48mhz>; + }; +}; diff --git a/board/phytium/pomelo/Kconfig b/board/phytium/pomelo/Kconfig new file mode 100644 index 0000000000..281aa8feff --- /dev/null +++ b/board/phytium/pomelo/Kconfig @@ -0,0 +1,12 @@ +if TARGET_POMELO + +config SYS_BOARD + default "pomelo" + +config SYS_VENDOR + default "phytium" + +config SYS_CONFIG_NAME + default "pomelo" + +endif diff --git a/board/phytium/pomelo/MAINTAINERS b/board/phytium/pomelo/MAINTAINERS new file mode 100644 index 0000000000..950449392b --- /dev/null +++ b/board/phytium/pomelo/MAINTAINERS @@ -0,0 +1,8 @@ +POMELO BOARD +M: lixinde <lixinde(a)phytium.com.cn> +M: weichangzheng <weichangzheng(a)phytium.com.cn> +S: Maintained +F: board/phytium/pomelo/* +F: include/configs/pomelo.h +F: configs/pomelo_defconfig + diff --git a/board/phytium/pomelo/Makefile b/board/phytium/pomelo/Makefile new file mode 100644 index 0000000000..b9cb3609bd --- /dev/null +++ b/board/phytium/pomelo/Makefile @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2021 +# lixinde <lixinde(a)phytium.com.cn> +# weichangzheng <weichangzheng(a)phytium.com.cn> +# + +obj-y += pomelo.o +obj-y += pll.o +obj-y += pcie.o +obj-y += ddr.o +obj-y += sec.o + + diff --git a/board/phytium/pomelo/cpu.h b/board/phytium/pomelo/cpu.h new file mode 100644 index 0000000000..e15917609b --- /dev/null +++ b/board/phytium/pomelo/cpu.h @@ -0,0 +1,73 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2021 + * Phytium Technology Ltd <www.phytium.com> + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ + +#ifndef _FT_POMELO_H +#define _FT_POMELO_H + +/* SMCCC ID */ +#define CPU_SVC_VERSION 0xC2000F00 +#define CPU_GET_RST_SOURCE 0xC2000F01 +#define CPU_INIT_PLL 0xC2000F02 +#define CPU_INIT_PCIE 0xC2000F03 +#define CPU_INIT_MEM 0xC2000F04 +#define CPU_INIT_SEC_SVC 0xC2000F05 + +/*CPU RESET*/ +#define CPU_RESET_POWER_ON 0x1 +#define CPU_RESET_PLL 0x4 +#define CPU_RESET_WATCH_DOG 0x8 + +/* PLL */ +#define PARAMETER_PLL_MAGIC 0x54460010 + +/* PCIE */ +#define PARAMETER_PCIE_MAGIC 0x54460011 +#define CONFIG_INDEPENDENT_TREE 0x0 +#define PCI_PEU0 0x1 +#define PCI_PEU1 0x1 +#define PEU1_OFFSET 16 +#define PEU_C_OFFSET_MODE 16 +#define PEU_C_OFFSET_SPEED 0 +#define RC_MODE 0x1 +#define X8X8 0x1 +#define GEN3 3 + +/* DDR */ +#define PARAMETER_MCU_MAGIC 0x54460014 +#define PARAM_MCU_VERSION 0x1 +#define PARAM_MCU_SIZE 0x100 +#define PARAM_CH_ENABLE 0x3 +#define PARAM_ECC_ENABLE 0x3 +#define PARAM_FORCE_SPD_DISABLE 0x0 +#define PARAM_MCU_MISC_ENABLE 0x0 + +#define UDIMM_TYPE 0x2 +#define DIMM_X8 0x1 +#define NO_MIRROR 0x0 +#define NO_ECC_TYPE 0 +#define DDR4_TYPE 0xC + +/* SEC */ +#define PARAMETER_COMMON_MAGIC 0x54460013 + +/* FLUSH L3 CASHE */ +#define HNF_COUNT 0x8 +#define HNF_PSTATE_REQ (HNF_BASE + 0x10) +#define HNF_PSTATE_STAT (HNF_BASE + 0x18) +#define HNF_PSTATE_OFF 0x0 +#define HNF_PSTATE_SFONLY 0x1 +#define HNF_PSTATE_HALF 0x2 +#define HNF_PSTATE_FULL 0x3 +#define HNF_STRIDE 0x10000 +#define HNF_BASE (unsigned long)(0x3A200000) +void ddr_init(void); +void sec_init(void); +void check_reset(void); +void pcie_init(void); + +#endif /* _FT_POMELO_H */ diff --git a/board/phytium/pomelo/ddr.c b/board/phytium/pomelo/ddr.c new file mode 100644 index 0000000000..88756f5fc1 --- /dev/null +++ b/board/phytium/pomelo/ddr.c @@ -0,0 +1,164 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ + +#include <stdio.h> +#include <linux/arm-smccc.h> +#include "cpu.h" + +struct ddr_spd { + /******************* read from spd *****************/ + unsigned char dimm_type; /* 1: RDIMM;2: UDIMM;3: SODIMM;4: LRDIMM */ + unsigned char data_width; /* 0: x4; 1: x8; 2: x16 */ + unsigned char mirror_type; /* 0: stardard; 1: mirror */ + unsigned char ecc_type; /* 0: no-ecc; 1:ecc */ + unsigned char dram_type; /* 0xB: DDR3; 0xC: DDR4 */ + unsigned char rank_num; + unsigned char row_num; + unsigned char col_num; + + unsigned char bg_num; /*only DDR4*/ + unsigned char bank_num; + unsigned short int module_manufacturer_id; + unsigned short int taamin; + unsigned short int trcdmin; + + unsigned short int trpmin; + unsigned short int trasmin; + unsigned short int trcmin; + unsigned short int tfawmin; + + unsigned short int trrd_smin; /*only DDR4*/ + unsigned short int trrd_lmin; /*only DDR4*/ + unsigned short int tccd_lmin; /*only DDR4*/ + unsigned short int twrmin; + + unsigned short int twtr_smin; /*only DDR4*/ + unsigned short int twtr_lmin; /*only DDR4*/ + unsigned short int twtrmin; /*only DDR3*/ + unsigned short int trrdmin; /*only DDR3*/ + + /******************* RCD control words *****************/ + unsigned char f0rc03; /*bit[3:2]:CS bit[1:0]:CA */ + unsigned char f0rc04; /*bit[3:2]:ODT bit[1:0]:CKE */ + unsigned char f0rc05; /*bit[3:2]:CLK-A side bit[1:0]:CLK-B side */ + unsigned char bc00; + unsigned char bc01; + unsigned char bc02; + unsigned char bc03; + unsigned char bc04; + + unsigned char bc05; + unsigned char f5bc5x; + unsigned char f5bc6x; + /******************* LRDIMM special *****************/ + unsigned char vrefdq_pr0; + unsigned char vrefdq_mdram; + unsigned char rtt_mdram_1866; + unsigned char rtt_mdram_2400; + unsigned char rtt_mdram_3200; + + unsigned char drive_dram; + unsigned char odt_dram_1866; + unsigned char odt_dram_2400; + unsigned char odt_dram_3200; + unsigned char park_dram_1866; + unsigned char park_dram_2400; + unsigned char park_dram_3200; + unsigned char rcd_num; +} __attribute((aligned(4))); + +struct mcu_config { + unsigned int magic; + unsigned int version; + unsigned int size; + unsigned char rev1[4]; + + unsigned char ch_enable; + unsigned char misc1_enable; + unsigned char misc2_enable; + unsigned char force_spd_enable; + unsigned char misc3_enable; + unsigned char train_debug; + unsigned char train_recover; + unsigned char rev2[9]; + + struct ddr_spd ddr_spd_info[2]; +} __attribute((aligned(4))); + +static void get_mcu_up_info_default(struct mcu_config *pm) +{ + pm->magic = PARAMETER_MCU_MAGIC; + pm->version = PARAM_MCU_VERSION; + pm->size = PARAM_MCU_SIZE; + pm->ch_enable = PARAM_CH_ENABLE; + pm->misc1_enable = PARAM_ECC_ENABLE; + pm->force_spd_enable = PARAM_FORCE_SPD_DISABLE; + pm->misc3_enable = PARAM_MCU_MISC_ENABLE; + pm->train_recover = 0x0; +} + +static unsigned char init_dimm_param(unsigned char ch, struct mcu_config *pm) +{ + printf("manual config dimm info...\n"); + pm->ddr_spd_info[ch].dimm_type = UDIMM_TYPE; + pm->ddr_spd_info[ch].data_width = DIMM_X8; + pm->ddr_spd_info[ch].mirror_type = NO_MIRROR; + pm->ddr_spd_info[ch].ecc_type = NO_ECC_TYPE; + pm->ddr_spd_info[ch].dram_type = DDR4_TYPE; + pm->ddr_spd_info[ch].rank_num = 1; + pm->ddr_spd_info[ch].row_num = 16; + pm->ddr_spd_info[ch].col_num = 10; + pm->ddr_spd_info[ch].bg_num = 4; + pm->ddr_spd_info[ch].bank_num = 4; + pm->ddr_spd_info[ch].taamin = 13750; + pm->ddr_spd_info[ch].trcdmin = 13750; + + pm->ddr_spd_info[ch].trpmin = 13750; + pm->ddr_spd_info[ch].trasmin = 32000; + pm->ddr_spd_info[ch].trcmin = 45750; + pm->ddr_spd_info[ch].tfawmin = 21000; + + pm->ddr_spd_info[ch].trrd_smin = 3000; + pm->ddr_spd_info[ch].trrd_lmin = 4900; + pm->ddr_spd_info[ch].tccd_lmin = 5000; + pm->ddr_spd_info[ch].twrmin = 15000; + + pm->ddr_spd_info[ch].twtr_smin = 2500; + pm->ddr_spd_info[ch].twtr_lmin = 7500; + + return 0; +} + +void get_default_mcu_info(unsigned char *data) +{ + get_mcu_up_info_default((struct mcu_config *)data); +} + +void fix_mcu_info(unsigned char *data) +{ + unsigned char ch; + struct mcu_config *mcu_info = (struct mcu_config *)data; + + for (ch = 0; ch < 2; ch++) + init_dimm_param(ch, mcu_info); +} + +void ddr_init(void) +{ + unsigned char buffer[0x100]; + struct arm_smccc_res res; + + get_default_mcu_info(buffer); + fix_mcu_info(buffer); + + arm_smccc_smc(CPU_INIT_MEM, 0, (u64)buffer, 0, 0, 0, 0, 0, &res); + if (res.a0 != 0) { + printf("error x0: 0x%lx, x1: 0x%lx\n", res.a0, res.a1); + while (true) + ; + } +} diff --git a/board/phytium/pomelo/pcie.c b/board/phytium/pomelo/pcie.c new file mode 100644 index 0000000000..3754d8eb9b --- /dev/null +++ b/board/phytium/pomelo/pcie.c @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ + +#include <stdio.h> +#include <string.h> +#include <linux/arm-smccc.h> +#include "cpu.h" + +struct pcu_ctr { + unsigned int base_config[3]; + unsigned int equalization[3]; + unsigned char rev[80]; +} __attribute((aligned(4))); + +struct pcu_config { + unsigned int magic; + unsigned int version; + unsigned int size; + unsigned char rev1[4]; + unsigned int independent_tree; + unsigned int base_cfg; + unsigned char rev2[16]; + struct pcu_ctr ctr_cfg[2]; +} __attribute((aligned(4))); + +struct pcu_config const peu_base_info = { + .magic = PARAMETER_PCIE_MAGIC, + .version = 0x2, + .size = 0x100, + .independent_tree = CONFIG_INDEPENDENT_TREE, + .base_cfg = ((PCI_PEU1 | (X8X8 << 1)) << PEU1_OFFSET | (PCI_PEU0 | (X8X8 << 1))), + .ctr_cfg[0].base_config[0] = (RC_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED), + .ctr_cfg[0].base_config[1] = (RC_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED), + .ctr_cfg[0].base_config[2] = (RC_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED), + .ctr_cfg[1].base_config[0] = (RC_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED), + .ctr_cfg[1].base_config[1] = (RC_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED), + .ctr_cfg[1].base_config[2] = (RC_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED), + .ctr_cfg[0].equalization[0] = 0x7, + .ctr_cfg[0].equalization[1] = 0x7, + .ctr_cfg[0].equalization[2] = 0x7, + .ctr_cfg[1].equalization[0] = 0x7, + .ctr_cfg[1].equalization[1] = 0x7, + .ctr_cfg[1].equalization[2] = 0x7, +}; + +void pcie_init(void) +{ + unsigned char buffer[0x100]; + struct arm_smccc_res res; + + memcpy(buffer, &peu_base_info, sizeof(peu_base_info)); + arm_smccc_smc(CPU_INIT_PCIE, 0, (u64)buffer, 0, 0, 0, 0, 0, &res); + if (res.a0 != 0) { + while (true) + ; + } +} diff --git a/board/phytium/pomelo/pll.c b/board/phytium/pomelo/pll.c new file mode 100644 index 0000000000..1227b7dd80 --- /dev/null +++ b/board/phytium/pomelo/pll.c @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ + +#include <stdio.h> +#include <string.h> +#include <asm/io.h> +#include <linux/arm-smccc.h> +#include "cpu.h" + +struct pll_config { + unsigned int magic; + unsigned int version; + unsigned int size; + unsigned char rev1[4]; + unsigned int core_pll; + unsigned int res1; + unsigned int lmu_pll; + unsigned int res2; + unsigned int res3; + unsigned int res4; + unsigned int res5; +} __attribute((aligned(4))); + +struct pll_config const pll_base_info = { + .magic = PARAMETER_PLL_MAGIC, + .version = 0x1, + .size = 0x30, + .core_pll = 2300, /*MHz*/ + .lmu_pll = 667, /*MHz*/ +}; + +unsigned int get_reset_source(void) +{ + struct arm_smccc_res res; + + arm_smccc_smc(CPU_GET_RST_SOURCE, 0, 0, 0, 0, 0, 0, 0, &res); + return res.a0; +} + +void pll_init(void) +{ + unsigned char buffer[0x100]; + struct arm_smccc_res res; + + memcpy(buffer, &pll_base_info, sizeof(pll_base_info)); + arm_smccc_smc(CPU_INIT_PLL, 0, (u64)buffer, 0, 0, 0, 0, 0, &res); + if (res.a0 != 0) { + while (true) + ; + } +} + +void check_reset(void) +{ + unsigned int rst; + + rst = get_reset_source(); + + switch (rst) { + case CPU_RESET_POWER_ON: + pll_init(); + break; + case CPU_RESET_PLL: + break; + case CPU_RESET_WATCH_DOG: + break; + default: + while (true) + ; + } +} diff --git a/board/phytium/pomelo/pomelo.c b/board/phytium/pomelo/pomelo.c new file mode 100644 index 0000000000..693e891d20 --- /dev/null +++ b/board/phytium/pomelo/pomelo.c @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ + +#include <stdio.h> +#include <command.h> +#include <init.h> +#include <asm/armv8/mmu.h> +#include <asm/io.h> +#include <linux/arm-smccc.h> +#include <scsi.h> +#include "cpu.h" + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + gd->mem_clk = 0; + gd->ram_size = PHYS_SDRAM_1_SIZE; + + printf("Phytium ddr init\n"); + + ddr_init(); + sec_init(); + printf("PBF relocate done\n"); + + return 0; +} + +int board_init(void) +{ + return 0; +} + +void reset_cpu(void) +{ + struct arm_smccc_res res; + + printf("run in reset cpu\n"); + arm_smccc_smc(0x84000009, 0, 0, 0, 0, 0, 0, 0, &res); + printf("reset cpu error, %lx\n", res.a0); +} + +int mach_cpu_init(void) +{ + check_reset(); + return 0; +} + +int board_early_init_f(void) +{ + pcie_init(); + return 0; +} + +int board_early_init_r(void) +{ + return 0; +} + +static struct mm_region pomelo_mem_map[] = { + { + .virt = 0x0UL, + .phys = 0x0UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | + PTE_BLOCK_UXN + }, + { + .virt = (u64)PHYS_SDRAM_1, + .phys = (u64)PHYS_SDRAM_1, + .size = (u64)PHYS_SDRAM_1_SIZE, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_NS | + PTE_BLOCK_INNER_SHARE + }, + { + 0, + } +}; + +struct mm_region *mem_map = pomelo_mem_map; + +int __asm_flush_l3_dcache(void) +{ + int i, pstate; + + for (i = 0; i < HNF_COUNT; i++) + writeq(HNF_PSTATE_SFONLY, HNF_PSTATE_REQ + i * HNF_STRIDE); + for (i = 0; i < HNF_COUNT; i++) { + do { + pstate = readq(HNF_PSTATE_STAT + i * HNF_STRIDE); + } while ((pstate & 0xf) != (HNF_PSTATE_SFONLY << 2)); + } + + for (i = 0; i < HNF_COUNT; i++) + writeq(HNF_PSTATE_FULL, HNF_PSTATE_REQ + i * HNF_STRIDE); + + return 0; +} + +int last_stage_init(void) +{ + int ret; + + /* pci e */ + pci_init(); + /* scsi scan */ + ret = scsi_scan(true); + if (ret) { + printf("scsi scan failed\n"); + return CMD_RET_FAILURE; + } + return ret; +} diff --git a/board/phytium/pomelo/sec.c b/board/phytium/pomelo/sec.c new file mode 100644 index 0000000000..8ec0fa797b --- /dev/null +++ b/board/phytium/pomelo/sec.c @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ + +#include <stdio.h> +#include <string.h> +#include <linux/arm-smccc.h> +#include "cpu.h" + +struct common_config { + unsigned int magic; + unsigned int version; + unsigned int size; + unsigned char rev1[4]; + unsigned long long core_bit_map; +} __attribute((aligned(4))); + +struct common_config const common_base_info = { + .magic = PARAMETER_COMMON_MAGIC, + .version = 0x1, + .core_bit_map = 0x3333, +}; + +void sec_init(void) +{ + unsigned char buffer[0x100]; + struct arm_smccc_res res; + + memcpy(buffer, &common_base_info, sizeof(common_base_info)); + arm_smccc_smc(CPU_INIT_SEC_SVC, 0, (u64)buffer, 0, 0, 0, 0, 0, &res); + + if (res.a0 != 0) { + printf("error ret %lx\n", res.a0); + while (true) + ; + } +} diff --git a/configs/pomelo_defconfig b/configs/pomelo_defconfig new file mode 100644 index 0000000000..3e6c18196d --- /dev/null +++ b/configs/pomelo_defconfig @@ -0,0 +1,36 @@ +CONFIG_ARM=y +CONFIG_ARM_SMCCC=y +CONFIG_TARGET_POMELO=y +CONFIG_SYS_TEXT_BASE=0x180000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x1000 +# CONFIG_PSCI_RESET is not set +CONFIG_DEFAULT_DEVICE_TREE="phytium-pomelo" +CONFIG_AHCI=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyAMA0,115200 earlycon=pl011,0x28001000 root=/dev/sda2 rw" +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_LAST_STAGE_INIT=y +CONFIG_SYS_PROMPT="pomelo#" +# CONFIG_CMD_LZMADEC is not set +# CONFIG_CMD_UNZIP is not set +CONFIG_CMD_PCI=y +CONFIG_OF_CONTROL=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +# CONFIG_NET is not set +CONFIG_DM=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y +CONFIG_BLK=y +# CONFIG_MMC is not set +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCI_PHYTIUM=y +CONFIG_PCIE_ECAM_GENERIC=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_DM_SERIAL=y +CONFIG_PL01X_SERIAL=y diff --git a/include/configs/pomelo.h b/include/configs/pomelo.h new file mode 100644 index 0000000000..69c4195d86 --- /dev/null +++ b/include/configs/pomelo.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2021 + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ + +#ifndef __POMELO_CONFIG_H__ +#define __POMELO_CONFIG_H__ + +/* SDRAM Bank #1 start address */ +#define PHYS_SDRAM_1 0x80000000 +#define PHYS_SDRAM_1_SIZE 0x7B000000 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 + +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000000) + +/* SIZE of malloc pool */ +#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024 + CONFIG_ENV_SIZE) +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_EARLY_INIT_R + +#define CONFIG_SYS_INIT_SP_ADDR (0x29800000 + 0x1a000) + +/* PCI CONFIG */ +#define CONFIG_SYS_PCI_64BIT 1 +#define CONFIG_PCI_SCAN_SHOW + +/* SCSI */ +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE 128 +#define CONFIG_SCSI_AHCI_PLAT +#define CONFIG_SYS_SATA_MAX_DEVICE 4 + +/*BOOT*/ +#define CONFIG_SYS_BOOTM_LEN (60 * 1024 * 1024) + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "load_kernel=ext4load scsi 0:1 0x90100000 uImage_old\0" \ + "load_fdt=ext4load scsi 0:1 0x95000000 ft-d2000.dtb\0"\ + "boot_fdt=bootm 0x90100000 -:- 0x17c000\0" \ + "distro_bootcmd=run load_kernel; run boot_fdt" + +#endif -- 2.17.1

1 0

[PATCH v2 11/14] board: freescale: ls2081ardb: Update I2C mux config
by Stephen Carlson 12 Jul '21

12 Jul '21

Updates the board configuration to enable use of the PCA9547 I2C mux. Signed-off-by: Stephen Carlson <stcarlso(a)linux.microsoft.com> --- configs/ls2081ardb_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/ls2081ardb_defconfig b/configs/ls2081ardb_defconfig index ab1a9e22e0..d9134d6a01 100644 --- a/configs/ls2081ardb_defconfig +++ b/configs/ls2081ardb_defconfig @@ -65,3 +65,4 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_FSL_USE_PCA9547_MUX=y -- 2.17.1

2 1

[PATCH v2 01/14] board: freescale: Refactor NXP common mux code
by Stephen Carlson 12 Jul '21

12 Jul '21

Refactors similar mux code from multiple NXP boards into a common location, and allows it to be disabled in config. New config: CONFIG_FSL_USE_PCA9547_MUX to enable PCA9547 mux functionality. Signed-off-by: Stephen Carlson <stcarlso(a)linux.microsoft.com> --- board/freescale/common/Kconfig | 6 +++ board/freescale/common/Makefile | 11 ++++++ board/freescale/common/i2c_common.c | 34 +++++++++++++++++ board/freescale/common/i2c_common.h | 30 +++++++++++++++ board/freescale/common/i2c_mux.c | 40 ++++++++++++++++++++ board/freescale/common/i2c_mux.h | 15 ++++++++ board/freescale/common/vid.c | 58 ++++++----------------------- 7 files changed, 148 insertions(+), 46 deletions(-) create mode 100644 board/freescale/common/i2c_common.c create mode 100644 board/freescale/common/i2c_common.h create mode 100644 board/freescale/common/i2c_mux.c create mode 100644 board/freescale/common/i2c_mux.h diff --git a/board/freescale/common/Kconfig b/board/freescale/common/Kconfig index 17db755951..ab9c14ae88 100644 --- a/board/freescale/common/Kconfig +++ b/board/freescale/common/Kconfig @@ -21,6 +21,12 @@ config CMD_ESBC_VALIDATE esbc_validate - validate signature using RSA verification esbc_halt - put the core in spin loop (Secure Boot Only) +config FSL_USE_PCA9547_MUX + bool "Enable PCA9547 I2C Mux on Freescale boards" + default n + help + This option enables the PCA9547 I2C mux on Freescale boards. + config VID depends on DM_I2C bool "Enable Freescale VID" diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index 114b7ba8f9..45aaa16ca4 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -15,6 +15,15 @@ ifdef MINIMAL # necessary to create built-in.o obj- := __dummy__.o else +# include i2c_common.o once if either VID or FSL_USE_PCA9547_MUX +I2C_COMMON= +ifdef CONFIG_VID +I2C_COMMON=y +endif +ifdef CONFIG_FSL_USE_PCA9547_MUX +I2C_COMMON=y +endif + obj-$(CONFIG_FSL_CADMUS) += cadmus.o obj-$(CONFIG_FSL_VIA) += cds_via.o obj-$(CONFIG_FMAN_ENET) += fman.o @@ -22,6 +31,8 @@ obj-$(CONFIG_FSL_PIXIS) += pixis.o ifndef CONFIG_SPL_BUILD obj-$(CONFIG_FSL_NGPIXIS) += ngpixis.o endif +obj-$(I2C_COMMON) += i2c_common.o +obj-$(CONFIG_FSL_USE_PCA9547_MUX) += i2c_mux.o obj-$(CONFIG_VID) += vid.o obj-$(CONFIG_FSL_QIXIS) += qixis.o obj-$(CONFIG_PQ_MDS_PIB) += pq-mds-pib.o diff --git a/board/freescale/common/i2c_common.c b/board/freescale/common/i2c_common.c new file mode 100644 index 0000000000..0f09ed7d34 --- /dev/null +++ b/board/freescale/common/i2c_common.c @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2020-21 NXP + * Copyright 2021 Microsoft Corporation + */ + +#include <common.h> +#include <i2c.h> +#include "i2c_common.h" + +#ifdef CONFIG_DM_I2C + +/* If DM is in use, retrieve the chip for the specified bus number */ +int fsl_i2c_get_device(int address, int bus, DEVICE_HANDLE_T *dev) +{ + int ret = i2c_get_chip_for_busnum(bus, address, 1, dev); + + if (ret) + printf("I2C: Bus %d has no device with address 0x%02X\n", + bus, address); + return ret; +} + +#else + +/* Handle is passed directly */ +int fsl_i2c_get_device(int address, int bus, DEVICE_HANDLE_T *dev) +{ + *dev = address; + return 0; +} + +#endif diff --git a/board/freescale/common/i2c_common.h b/board/freescale/common/i2c_common.h new file mode 100644 index 0000000000..840ad66183 --- /dev/null +++ b/board/freescale/common/i2c_common.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2020-21 NXP + * Copyright 2021 Microsoft Corporation + */ + +#ifndef __NXP_I2C_COMMON_H__ +#define __NXP_I2C_COMMON_H__ + +/* Common functionality shared by the I2C drivers for VID and the mux. */ +#ifdef CONFIG_DM_I2C +#define DEVICE_HANDLE_T struct udevice * + +#define I2C_READ(dev, register, data, length) \ + dm_i2c_read(dev, register, data, length) +#define I2C_WRITE(dev, register, data, length) \ + dm_i2c_write(dev, register, data, length) +#else +#define DEVICE_HANDLE_T int + +#define I2C_READ(dev, register, data, length) \ + i2c_read(dev, register, 1, data, length) +#define I2C_WRITE(dev, register, data, length) \ + i2c_write(dev, register, 1, data, length) +#endif + +int fsl_i2c_get_device(int address, int bus, DEVICE_HANDLE_T *dev); + +#endif diff --git a/board/freescale/common/i2c_mux.c b/board/freescale/common/i2c_mux.c new file mode 100644 index 0000000000..54f89e2576 --- /dev/null +++ b/board/freescale/common/i2c_mux.c @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2020-21 NXP + * Copyright 2021 Microsoft Corporation + */ + +#include <common.h> +#include <i2c.h> +#include "i2c_common.h" +#include "i2c_mux.h" + +/* + * A new Kconfig option for something that used to always be built should be + * “default y”. + */ +#ifdef CONFIG_FSL_USE_PCA9547_MUX + +int select_i2c_ch_pca9547(u8 ch, int bus) +{ + int ret; + DEVICE_HANDLE_T dev; + + /* Open device handle */ + ret = fsl_i2c_get_device(I2C_MUX_PCA_ADDR_PRI, bus, &dev); + if (ret) { + printf("PCA: No PCA9547 device found\n"); + return ret; + } + + ret = I2C_WRITE(dev, 0, &ch, sizeof(ch)); + if (ret) { + printf("PCA: Unable to select channel %d (%d)\n", (int)ch, ret); + return ret; + } + + return 0; +} + +#endif diff --git a/board/freescale/common/i2c_mux.h b/board/freescale/common/i2c_mux.h new file mode 100644 index 0000000000..0870c1918e --- /dev/null +++ b/board/freescale/common/i2c_mux.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2020-21 NXP + * Copyright 2021 Microsoft Corporation + */ + +#ifndef __NXP_I2C_MUX_H__ +#define __NXP_I2C_MUX_H__ + +#ifdef CONFIG_FSL_USE_PCA9547_MUX +int select_i2c_ch_pca9547(u8 ch, int bus); +#endif + +#endif diff --git a/board/freescale/common/vid.c b/board/freescale/common/vid.c index 13ef101e7f..d2c9bbbfe9 100644 --- a/board/freescale/common/vid.c +++ b/board/freescale/common/vid.c @@ -20,8 +20,13 @@ #include <asm/immap_85xx.h> #endif #include <linux/delay.h> +#include "i2c_common.h" #include "vid.h" +#ifndef I2C_VOL_MONITOR_BUS +#define I2C_VOL_MONITOR_BUS 0 +#endif + /* Voltages are generally handled in mV to keep them as integers */ #define MV_PER_V 1000 @@ -95,44 +100,6 @@ u16 __weak soc_get_fuse_vid(int vid_index) #define I2C_VOL_MONITOR_ADDR 0 #endif -#if CONFIG_IS_ENABLED(DM_I2C) -#define DEVICE_HANDLE_T struct udevice * - -#ifndef I2C_VOL_MONITOR_BUS -#define I2C_VOL_MONITOR_BUS 0 -#endif - -/* If DM is in use, retrieve the udevice chip for the specified bus number */ -static int vid_get_device(int address, DEVICE_HANDLE_T *dev) -{ - int ret = i2c_get_chip_for_busnum(I2C_VOL_MONITOR_BUS, address, 1, dev); - - if (ret) - printf("VID: Bus %d has no device with address 0x%02X\n", - I2C_VOL_MONITOR_BUS, address); - return ret; -} - -#define I2C_READ(dev, register, data, length) \ - dm_i2c_read(dev, register, data, length) -#define I2C_WRITE(dev, register, data, length) \ - dm_i2c_write(dev, register, data, length) -#else -#define DEVICE_HANDLE_T int - -/* If DM is not in use, I2C addresses are passed directly */ -static int vid_get_device(int address, DEVICE_HANDLE_T *dev) -{ - *dev = address; - return 0; -} - -#define I2C_READ(dev, register, data, length) \ - i2c_read(dev, register, 1, data, length) -#define I2C_WRITE(dev, register, data, length) \ - i2c_write(dev, register, 1, data, length) -#endif - #if defined(CONFIG_VOL_MONITOR_IR36021_SET) || \ defined(CONFIG_VOL_MONITOR_IR36021_READ) /* @@ -158,7 +125,7 @@ static int find_ir_chip_on_i2c(void) /* Check all the address */ for (i = 0; i < (sizeof(ir_i2c_addr)/sizeof(ir_i2c_addr[0])); i++) { i2caddress = ir_i2c_addr[i]; - ret = vid_get_device(i2caddress, &dev); + ret = fsl_i2c_get_device(i2caddress, I2C_VOL_MONITOR_BUS, &dev); if (!ret) { ret = I2C_READ(dev, IR36021_MFR_ID_OFFSET, (void *)&mfrID, sizeof(mfrID)); @@ -202,7 +169,7 @@ static int read_voltage_from_INA220(int i2caddress) DEVICE_HANDLE_T dev; /* Open device handle */ - ret = vid_get_device(i2caddress, &dev); + ret = fsl_i2c_get_device(i2caddress, I2C_VOL_MONITOR_BUS, &dev); if (ret) return ret; @@ -243,7 +210,7 @@ static int read_voltage_from_IR(int i2caddress) DEVICE_HANDLE_T dev; /* Open device handle */ - ret = vid_get_device(i2caddress, &dev); + ret = fsl_i2c_get_device(i2caddress, I2C_VOL_MONITOR_BUS, &dev); if (ret) return ret; @@ -344,7 +311,7 @@ static int read_voltage_from_pmbus(int i2caddress) DEVICE_HANDLE_T dev; /* Open device handle */ - ret = vid_get_device(i2caddress, &dev); + ret = fsl_i2c_get_device(i2caddress, I2C_VOL_MONITOR_BUS, &dev); if (ret) return ret; @@ -457,7 +424,7 @@ static int set_voltage_to_IR(int i2caddress, int vdd) DEVICE_HANDLE_T dev; /* Open device handle */ - ret = vid_get_device(i2caddress, &dev); + ret = fsl_i2c_get_device(i2caddress, I2C_VOL_MONITOR_BUS, &dev); if (ret) return ret; @@ -503,7 +470,7 @@ static int set_voltage_to_pmbus(int i2caddress, int vdd) DEVICE_HANDLE_T dev; /* Open device handle */ - ret = vid_get_device(i2caddress, &dev); + ret = fsl_i2c_get_device(i2caddress, I2C_VOL_MONITOR_BUS, &dev); if (ret) return ret; @@ -653,7 +620,7 @@ int adjust_vdd(ulong vdd_override) debug("VID: IR Chip found on I2C address 0x%02x\n", i2caddress); } - ret = vid_get_device(i2caddress, &dev); + ret = fsl_i2c_get_device(i2caddress, I2C_VOL_MONITOR_BUS, &dev); if (ret) return ret; @@ -785,7 +752,6 @@ exit: i2c_multiplexer_select_vid_channel(I2C_MUX_CH_DEFAULT); return ret < 0 ? -1 : 0; - } static int do_vdd_override(struct cmd_tbl *cmdtp, -- 2.17.1

2 1

[PATCH 1/4] configs: ls1088aqds.h: Update mc size in env
by Priyanka Jain 12 Jul '21

12 Jul '21

Increase MC firmware size from 1MB to 2MB in read commands in env. Signed-off-by: Priyanka Jain <priyanka.jain(a)nxp.com> --- include/configs/ls1088aqds.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/include/configs/ls1088aqds.h b/include/configs/ls1088aqds.h index 4d04833c50..3d83b6715a 100644 --- a/include/configs/ls1088aqds.h +++ b/include/configs/ls1088aqds.h @@ -387,7 +387,7 @@ unsigned long get_board_ddr_clk(void); "kernel_start=0x1000000\0" \ "kernel_load=0xa0000000\0" \ "kernel_size=0x2800000\0" \ - "mcinitcmd=sf probe 0:0;sf read 0xa0a00000 0xa00000 0x100000;" \ + "mcinitcmd=sf probe 0:0;sf read 0xa0a00000 0xa00000 0x200000;" \ "sf read 0xa0640000 0x640000 0x4000; esbc_validate 0xa0640000;" \ "sf read 0xa0e00000 0xe00000 0x100000;" \ "sf read 0xa0680000 0x680000 0x4000;esbc_validate 0xa0680000;" \ @@ -396,11 +396,11 @@ unsigned long get_board_ddr_clk(void); #else /* if !(CONFIG_NXP_ESBC) */ #ifdef CONFIG_TFABOOT #define QSPI_MC_INIT_CMD \ - "sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \ + "sf probe 0:0;sf read 0x80000000 0xA00000 0x200000;" \ "sf read 0x80100000 0xE00000 0x100000;" \ "fsl_mc start mc 0x80000000 0x80100000\0" #define SD_MC_INIT_CMD \ - "mmcinfo;mmc read 0x80000000 0x5000 0x800;" \ + "mmcinfo;mmc read 0x80000000 0x5000 0x1000;" \ "mmc read 0x80100000 0x7000 0x800;" \ "fsl_mc start mc 0x80000000 0x80100000\0" #define IFC_MC_INIT_CMD \ @@ -422,7 +422,7 @@ unsigned long get_board_ddr_clk(void); "kernel_load=0xa0000000\0" \ "kernel_size=0x2800000\0" \ "kernel_size_sd=0x14000\0" \ - "mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \ + "mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x200000;" \ "sf read 0x80100000 0xE00000 0x100000;" \ "fsl_mc start mc 0x80000000 0x80100000\0" \ "mcmemsize=0x70000000 \0" \ @@ -481,7 +481,7 @@ unsigned long get_board_ddr_clk(void); "kernel_start=0x1000000\0" \ "kernel_load=0xa0000000\0" \ "kernel_size=0x2800000\0" \ - "mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \ + "mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x200000;" \ "sf read 0x80100000 0xE00000 0x100000;" \ "fsl_mc start mc 0x80000000 0x80100000\0" \ "mcmemsize=0x70000000 \0" @@ -499,7 +499,7 @@ unsigned long get_board_ddr_clk(void); "kernel_start=0x8000\0" \ "kernel_load=0xa0000000\0" \ "kernel_size=0x14000\0" \ - "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;" \ + "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x1000;" \ "mmc read 0x80100000 0x7000 0x800;" \ "fsl_mc start mc 0x80000000 0x80100000\0" \ "mcmemsize=0x70000000 \0" -- 2.17.1

1 3

[PATCH] ARM: dts: rmobile: Disable RPC HF by default
by Marek Vasut 11 Jul '21

11 Jul '21

The RPC HF might be locked by ATF, and any access to its register space would result in complete hang. Disable the RPC HF by default. The ATF should be patched to set RPC node status = "okay" in the DT fragment it passes to U-Boot in case the RPC HF access is unlocked, and that way U-Boot could access the RPC HF safely. Signed-off-by: Marek Vasut <marek.vasut+renesas(a)gmail.com> --- ATF patch: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/10622 --- arch/arm/dts/r8a77950-salvator-x-u-boot.dts | 2 +- arch/arm/dts/r8a77950-ulcb-u-boot.dts | 2 +- arch/arm/dts/r8a77960-salvator-x-u-boot.dts | 2 +- arch/arm/dts/r8a77960-ulcb-u-boot.dts | 2 +- arch/arm/dts/r8a77965-salvator-x-u-boot.dts | 2 +- arch/arm/dts/r8a77965-ulcb-u-boot.dts | 2 +- arch/arm/dts/r8a77990-ebisu-u-boot.dts | 2 +- arch/arm/dts/r8a77995-draak-u-boot.dts | 2 +- 8 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm/dts/r8a77950-salvator-x-u-boot.dts b/arch/arm/dts/r8a77950-salvator-x-u-boot.dts index bb83bc1d7b..d94ad91973 100644 --- a/arch/arm/dts/r8a77950-salvator-x-u-boot.dts +++ b/arch/arm/dts/r8a77950-salvator-x-u-boot.dts @@ -27,7 +27,7 @@ &rpc { reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0x04000000>; - status = "okay"; + status = "disabled"; }; &sdhi0 { diff --git a/arch/arm/dts/r8a77950-ulcb-u-boot.dts b/arch/arm/dts/r8a77950-ulcb-u-boot.dts index 16d9e38b70..ff00ccdb5b 100644 --- a/arch/arm/dts/r8a77950-ulcb-u-boot.dts +++ b/arch/arm/dts/r8a77950-ulcb-u-boot.dts @@ -39,7 +39,7 @@ &rpc { reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0x04000000>; - status = "okay"; + status = "disabled"; }; &sdhi0 { diff --git a/arch/arm/dts/r8a77960-salvator-x-u-boot.dts b/arch/arm/dts/r8a77960-salvator-x-u-boot.dts index dda3567e9e..79a54f38c1 100644 --- a/arch/arm/dts/r8a77960-salvator-x-u-boot.dts +++ b/arch/arm/dts/r8a77960-salvator-x-u-boot.dts @@ -27,7 +27,7 @@ &rpc { reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0x04000000>; - status = "okay"; + status = "disabled"; }; &sdhi0 { diff --git a/arch/arm/dts/r8a77960-ulcb-u-boot.dts b/arch/arm/dts/r8a77960-ulcb-u-boot.dts index e4f77ae262..1e9e8b87d5 100644 --- a/arch/arm/dts/r8a77960-ulcb-u-boot.dts +++ b/arch/arm/dts/r8a77960-ulcb-u-boot.dts @@ -39,7 +39,7 @@ &rpc { reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0x04000000>; - status = "okay"; + status = "disabled"; }; &sdhi0 { diff --git a/arch/arm/dts/r8a77965-salvator-x-u-boot.dts b/arch/arm/dts/r8a77965-salvator-x-u-boot.dts index e651e889bc..4272ecc110 100644 --- a/arch/arm/dts/r8a77965-salvator-x-u-boot.dts +++ b/arch/arm/dts/r8a77965-salvator-x-u-boot.dts @@ -27,7 +27,7 @@ &rpc { reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0x04000000>; - status = "okay"; + status = "disabled"; }; &sdhi0 { diff --git a/arch/arm/dts/r8a77965-ulcb-u-boot.dts b/arch/arm/dts/r8a77965-ulcb-u-boot.dts index 3574d6da6f..d9c680b171 100644 --- a/arch/arm/dts/r8a77965-ulcb-u-boot.dts +++ b/arch/arm/dts/r8a77965-ulcb-u-boot.dts @@ -39,7 +39,7 @@ &rpc { reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0x04000000>; - status = "okay"; + status = "disabled"; }; &sdhi0 { diff --git a/arch/arm/dts/r8a77990-ebisu-u-boot.dts b/arch/arm/dts/r8a77990-ebisu-u-boot.dts index 7022a2ba84..55699bafc4 100644 --- a/arch/arm/dts/r8a77990-ebisu-u-boot.dts +++ b/arch/arm/dts/r8a77990-ebisu-u-boot.dts @@ -43,7 +43,7 @@ &rpc { reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0x04000000>; - status = "okay"; + status = "disabled"; }; &sdhi0 { diff --git a/arch/arm/dts/r8a77995-draak-u-boot.dts b/arch/arm/dts/r8a77995-draak-u-boot.dts index 10fb9cb3b6..0ea2570c1d 100644 --- a/arch/arm/dts/r8a77995-draak-u-boot.dts +++ b/arch/arm/dts/r8a77995-draak-u-boot.dts @@ -10,5 +10,5 @@ &rpc { reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0x04000000>; - status = "okay"; + status = "disabled"; }; -- 2.30.2

1 0

[PATCH] ARM: dts: rmobile: Remove multiple unused DT properties on R-Car Gen3
by Marek Vasut 11 Jul '21

11 Jul '21

Filter out dmas dma-names interrupt-parent interrupts interrupts-extended interrupt-names interrupt-map interrupt-map-mask iommus DT properties on R-Car Gen3, since they are not used by U-Boot and only take space. Signed-off-by: Marek Vasut <marek.vasut+renesas(a)gmail.com> --- configs/r8a77970_eagle_defconfig | 2 ++ configs/r8a77980_condor_defconfig | 2 ++ configs/r8a77990_ebisu_defconfig | 2 ++ configs/r8a77995_draak_defconfig | 2 ++ configs/rcar3_salvator-x_defconfig | 2 ++ configs/rcar3_ulcb_defconfig | 2 ++ 6 files changed, 12 insertions(+) diff --git a/configs/r8a77970_eagle_defconfig b/configs/r8a77970_eagle_defconfig index 2532154978..eb9f4ab663 100644 --- a/configs/r8a77970_eagle_defconfig +++ b/configs/r8a77970_eagle_defconfig @@ -31,6 +31,8 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y +CONFIG_OF_DTB_PROPS_REMOVE=y +CONFIG_OF_REMOVE_PROPS="dmas dma-names interrupt-parent interrupts interrupts-extended interrupt-names interrupt-map interrupt-map-mask iommus" CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y diff --git a/configs/r8a77980_condor_defconfig b/configs/r8a77980_condor_defconfig index 02f008ad35..db260a34f2 100644 --- a/configs/r8a77980_condor_defconfig +++ b/configs/r8a77980_condor_defconfig @@ -32,6 +32,8 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y +CONFIG_OF_DTB_PROPS_REMOVE=y +CONFIG_OF_REMOVE_PROPS="dmas dma-names interrupt-parent interrupts interrupts-extended interrupt-names interrupt-map interrupt-map-mask iommus" CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y diff --git a/configs/r8a77990_ebisu_defconfig b/configs/r8a77990_ebisu_defconfig index e5cab47f9f..295c1d89cb 100644 --- a/configs/r8a77990_ebisu_defconfig +++ b/configs/r8a77990_ebisu_defconfig @@ -33,6 +33,8 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y +CONFIG_OF_DTB_PROPS_REMOVE=y +CONFIG_OF_REMOVE_PROPS="dmas dma-names interrupt-parent interrupts interrupts-extended interrupt-names interrupt-map interrupt-map-mask iommus" CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y diff --git a/configs/r8a77995_draak_defconfig b/configs/r8a77995_draak_defconfig index acae38a6c0..7a3d50851f 100644 --- a/configs/r8a77995_draak_defconfig +++ b/configs/r8a77995_draak_defconfig @@ -32,6 +32,8 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y +CONFIG_OF_DTB_PROPS_REMOVE=y +CONFIG_OF_REMOVE_PROPS="dmas dma-names interrupt-parent interrupts interrupts-extended interrupt-names interrupt-map interrupt-map-mask iommus" CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y diff --git a/configs/rcar3_salvator-x_defconfig b/configs/rcar3_salvator-x_defconfig index 709e6435ae..a985345efe 100644 --- a/configs/rcar3_salvator-x_defconfig +++ b/configs/rcar3_salvator-x_defconfig @@ -35,6 +35,8 @@ CONFIG_OF_CONTROL=y CONFIG_OF_LIST="r8a77950-salvator-x-u-boot r8a77960-salvator-x-u-boot r8a77965-salvator-x-u-boot" CONFIG_MULTI_DTB_FIT_LZO=y CONFIG_MULTI_DTB_FIT_USER_DEFINED_AREA=y +CONFIG_OF_DTB_PROPS_REMOVE=y +CONFIG_OF_REMOVE_PROPS="dmas dma-names interrupt-parent interrupts interrupts-extended interrupt-names interrupt-map interrupt-map-mask iommus" CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y diff --git a/configs/rcar3_ulcb_defconfig b/configs/rcar3_ulcb_defconfig index e0d72d940d..0ef1f2de08 100644 --- a/configs/rcar3_ulcb_defconfig +++ b/configs/rcar3_ulcb_defconfig @@ -35,6 +35,8 @@ CONFIG_OF_CONTROL=y CONFIG_OF_LIST="r8a77950-ulcb-u-boot r8a77960-ulcb-u-boot r8a77965-ulcb-u-boot" CONFIG_MULTI_DTB_FIT_LZO=y CONFIG_MULTI_DTB_FIT_USER_DEFINED_AREA=y +CONFIG_OF_DTB_PROPS_REMOVE=y +CONFIG_OF_REMOVE_PROPS="dmas dma-names interrupt-parent interrupts interrupts-extended interrupt-names interrupt-map interrupt-map-mask iommus" CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y -- 2.30.2

1 0

RFC: Devices for files and partitions
by Simon Glass 11 Jul '21

11 Jul '21

Hi, At present U-Boot avoids the concept of 'opening' a file. Being in a bootloader environment, it is normally better to take the action immediately and avoid any caching, for example, since there is no background task to clean up afterwards. Having said that, the concept of a file is quite useful, for example to write the output of a command to a file, or to open a file and read it a line at a time. Another case has come to light in that EFI wants to access files using a file handle. This currently uses parallel data structures and does not map very well in U-Boot. Finally, partitions has a similar issue, where defining them as a device can have benefits, e.g. to specify the device to use directly, rather than with the 'type dev:part' approach, perhaps providing them in the devicetree, etc. For the above reasons, I propose that we implement, as an option, support for files and partitions within driver model. Regards, Simon

3 3

[PATCH] gpio: mcp230xx: Introduce new driver
by Sebastian Reichel 11 Jul '21

11 Jul '21

Introduce driver for I2C based MCP230xx GPIO chips, which are quite common and already well supported by the Linux kernel. Signed-off-by: Sebastian Reichel <sebastian.reichel(a)collabora.com> --- drivers/gpio/Kconfig | 10 ++ drivers/gpio/Makefile | 1 + drivers/gpio/mcp230xx_gpio.c | 235 +++++++++++++++++++++++++++++++++++ 3 files changed, 246 insertions(+) create mode 100644 drivers/gpio/mcp230xx_gpio.c diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index de4dc51d4b48..f93e736639bb 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -179,6 +179,16 @@ config LPC32XX_GPIO help Support for the LPC32XX GPIO driver. +config MCP230XX_GPIO + bool "MCP230XX GPIO driver" + depends on DM + help + Support for Microchip's MCP230XX I2C connected GPIO devices. + The following chips are supported: + - MCP23008 + - MCP23017 + - MCP23018 + config MSCC_SGPIO bool "Microsemi Serial GPIO driver" depends on DM_GPIO && SOC_VCOREIII diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 8541ba0b0aec..00ffcc753534 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -24,6 +24,7 @@ obj-$(CONFIG_KIRKWOOD_GPIO) += kw_gpio.o obj-$(CONFIG_KONA_GPIO) += kona_gpio.o obj-$(CONFIG_MARVELL_GPIO) += mvgpio.o obj-$(CONFIG_MARVELL_MFP) += mvmfp.o +obj-$(CONFIG_MCP230XX_GPIO) += mcp230xx_gpio.o obj-$(CONFIG_MXC_GPIO) += mxc_gpio.o obj-$(CONFIG_MXS_GPIO) += mxs_gpio.o obj-$(CONFIG_PCA953X) += pca953x.o diff --git a/drivers/gpio/mcp230xx_gpio.c b/drivers/gpio/mcp230xx_gpio.c new file mode 100644 index 000000000000..44def86ca7d9 --- /dev/null +++ b/drivers/gpio/mcp230xx_gpio.c @@ -0,0 +1,235 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2021, Collabora Ltd. + * Copyright (C) 2021, General Electric Company + * Author(s): Sebastian Reichel <sebastian.reichel(a)collabora.com> + */ + +#define LOG_CATEGORY UCLASS_GPIO + +#include <common.h> +#include <errno.h> +#include <dm.h> +#include <i2c.h> +#include <asm/gpio.h> +#include <dm/device_compat.h> +#include <dt-bindings/gpio/gpio.h> + +enum mcp230xx_type { + UNKNOWN = 0, + MCP23008, + MCP23017, + MCP23018, +}; + +#define MCP230XX_IODIR 0x00 +#define MCP230XX_GPPU 0x06 +#define MCP230XX_GPIO 0x09 +#define MCP230XX_OLAT 0x0a + +#define BANKSIZE 8 + +static int mcp230xx_read(struct udevice *dev, uint reg, uint offset) +{ + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + int bank = offset / BANKSIZE; + int mask = 1 << (offset % BANKSIZE); + int shift = (uc_priv->gpio_count / BANKSIZE) - 1; + int ret; + + ret = dm_i2c_reg_read(dev, (reg << shift) + bank); + if (ret < 0) + return ret; + return !!(ret & mask); +} + +static int mcp230xx_write(struct udevice *dev, uint reg, uint offset, bool val) +{ + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + int bank = offset / BANKSIZE; + int mask = 1 << (offset % BANKSIZE); + int shift = (uc_priv->gpio_count / BANKSIZE) - 1; + int regval; + + regval = dm_i2c_reg_read(dev, (reg << shift) + bank); + if (regval < 0) + return regval; + + regval &= ~mask; + if (val) + regval |= mask; + + return dm_i2c_reg_write(dev, (reg << shift) + bank, regval); +} + +static int mcp230xx_get_value(struct udevice *dev, uint offset) +{ + int ret; + + ret = mcp230xx_read(dev, MCP230XX_GPIO, offset); + if (ret < 0) { + dev_err(dev, "%s error: %d\n", __func__, ret); + return ret; + } + + return ret; +} + +static int mcp230xx_set_value(struct udevice *dev, uint offset, int val) +{ + int ret; + + ret = mcp230xx_write(dev, MCP230XX_GPIO, offset, val); + if (ret < 0) { + dev_err(dev, "%s error: %d\n", __func__, ret); + return ret; + } + + return ret; +} + +static int mcp230xx_get_flags(struct udevice *dev, unsigned int offset, + ulong *flags) +{ + int direction, pullup; + + pullup = mcp230xx_read(dev, MCP230XX_GPPU, offset); + if (pullup < 0) { + dev_err(dev, "%s error: %d\n", __func__, pullup); + return pullup; + } + + direction = mcp230xx_read(dev, MCP230XX_IODIR, offset); + if (direction < 0) { + dev_err(dev, "%s error: %d\n", __func__, direction); + return direction; + } + + *flags = direction ? GPIOD_IS_IN : GPIOD_IS_OUT; + + if (pullup) + *flags |= GPIOD_PULL_UP; + + return 0; +} + +static int mcp230xx_set_flags(struct udevice *dev, uint offset, ulong flags) +{ + int direction = !(flags & GPIOD_IS_OUT); + int pullup = !!(flags & GPIOD_PULL_UP); + ulong supported_mask; + int ret; + + /* Note: active-low is ignored (handled by core) */ + supported_mask = GPIOD_ACTIVE_LOW | GPIOD_IS_IN | GPIOD_IS_OUT | GPIOD_PULL_UP; + if (flags & ~supported_mask) + return -EINVAL; + + ret = mcp230xx_write(dev, MCP230XX_GPPU, offset, pullup); + if (ret) { + dev_err(dev, "%s error: %d\n", __func__, ret); + return ret; + } + + ret = mcp230xx_write(dev, MCP230XX_IODIR, offset, direction); + if (ret) { + dev_err(dev, "%s error: %d\n", __func__, ret); + return ret; + } + + return 0; +} + +static int mcp230xx_direction_input(struct udevice *dev, uint offset) +{ + return mcp230xx_set_flags(dev, offset, GPIOD_IS_IN); +} + +static int mcp230xx_direction_output(struct udevice *dev, uint offset, int val) +{ + int ret = mcp230xx_set_value(dev, offset, val); + if (ret < 0) { + dev_err(dev, "%s error: %d\n", __func__, ret); + return ret; + } + return mcp230xx_set_flags(dev, offset, GPIOD_IS_OUT); +} + +static int mcp230xx_get_function(struct udevice *dev, uint offset) +{ + int ret; + + ret = mcp230xx_read(dev, MCP230XX_IODIR, offset); + if (ret < 0) { + dev_err(dev, "%s error: %d\n", __func__, ret); + return ret; + } + + return ret ? GPIOF_INPUT : GPIOF_OUTPUT; +} + +static const struct dm_gpio_ops mcp230xx_ops = { + .direction_input = mcp230xx_direction_input, + .direction_output = mcp230xx_direction_output, + .get_value = mcp230xx_get_value, + .set_value = mcp230xx_set_value, + .get_function = mcp230xx_get_function, + .set_flags = mcp230xx_set_flags, + .get_flags = mcp230xx_get_flags, +}; + +static int mcp230xx_probe(struct udevice *dev) +{ + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + char name[32], label[8], *str; + int addr, gpio_count, size; + const u8 *tmp; + + switch (dev_get_driver_data(dev)) { + case MCP23008: + gpio_count = 8; + break; + case MCP23017: + case MCP23018: + gpio_count = 16; + break; + default: + return -ENODEV; + } + + addr = dev_read_addr(dev); + tmp = dev_read_prop(dev, "label", &size); + if (tmp) { + memcpy(label, tmp, sizeof(label) - 1); + label[sizeof(label) - 1] = '\0'; + snprintf(name, sizeof(name), "%s@%x_", label, addr); + } else { + snprintf(name, sizeof(name), "gpio@%x_", addr); + } + + str = strdup(name); + if (!str) + return -ENOMEM; + + uc_priv->bank_name = str; + uc_priv->gpio_count = gpio_count; + + dev_dbg(dev, "%s is ready\n", str); + + return 0; +} + +static const struct udevice_id mcp230xx_ids[] = { + { .compatible = "microchip,mcp23008", .data = MCP23008, }, + { .compatible = "microchip,mcp23017", .data = MCP23017, }, + { .compatible = "microchip,mcp23018", .data = MCP23018, }, + { } +}; + +U_BOOT_DRIVER(mcp230xx) = { + .name = "mcp230xx", + .id = UCLASS_GPIO, + .ops = &mcp230xx_ops, + .probe = mcp230xx_probe, + .of_match = mcp230xx_ids, +}; -- 2.30.2

2 1

[PATCH 0/2] Add MNT Reform 2 board support
by Patrick Wildt 11 Jul '21

11 Jul '21

The MNT Reform 2 is a modular DIY laptop. In its initial version it is based on the BoundaryDevices i.MX8MQ SoM. Some parts have been lifted from BoundaryDevices official U-Boot downstream project. The device tree has not yet been merged into mainline Linux, but it's already available as v4 on the Linux ARM Kernel Architecture mailing list, which hopefully will now be merged as is. This U-Boot patchset supports the serial console, the SD card and eMMC, and Gigabit Ethernet. Best regards, Patrick Patrick Wildt (2): arm: dts: imx8mq: add MNT Reform 2 board: mntre: imx8mq: Add MNT Reform 2 board support arch/arm/dts/Makefile | 1 + arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi | 11 + arch/arm/dts/imx8mq-mnt-reform2.dts | 164 +++ arch/arm/dts/imx8mq-nitrogen-som.dtsi | 275 +++++ arch/arm/mach-imx/imx8m/Kconfig | 6 + board/mntre/imx8mq_reform2/Kconfig | 12 + board/mntre/imx8mq_reform2/MAINTAINERS | 7 + board/mntre/imx8mq_reform2/Makefile | 12 + board/mntre/imx8mq_reform2/imx8mq_reform2.c | 215 ++++ board/mntre/imx8mq_reform2/lpddr4_timing.c | 1014 +++++++++++++++++ .../mntre/imx8mq_reform2/lpddr4_timing_ch2.h | 95 ++ board/mntre/imx8mq_reform2/spl.c | 260 +++++ configs/imx8mq_reform2_defconfig | 56 + include/configs/imx8mq_reform2.h | 149 +++ 14 files changed, 2277 insertions(+) create mode 100644 arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi create mode 100644 arch/arm/dts/imx8mq-mnt-reform2.dts create mode 100644 arch/arm/dts/imx8mq-nitrogen-som.dtsi create mode 100644 board/mntre/imx8mq_reform2/Kconfig create mode 100644 board/mntre/imx8mq_reform2/MAINTAINERS create mode 100644 board/mntre/imx8mq_reform2/Makefile create mode 100644 board/mntre/imx8mq_reform2/imx8mq_reform2.c create mode 100644 board/mntre/imx8mq_reform2/lpddr4_timing.c create mode 100644 board/mntre/imx8mq_reform2/lpddr4_timing_ch2.h create mode 100644 board/mntre/imx8mq_reform2/spl.c create mode 100644 configs/imx8mq_reform2_defconfig create mode 100644 include/configs/imx8mq_reform2.h -- 2.32.0

1 2