July 2021 - U-Boot

[PATCH] x86: Ensure the e820 map is installed in all cases
by Simon Glass 10 Aug '21

10 Aug '21

This is a revert of a recent logic change in setup_zimage(). We do actually need to install this information always. Change it to install from the Coreboot tables if available, else the normal source. Fixes: e7bae8283fe ("x86: Allow installing an e820 when booting from coreboot") Signed-off-by: Simon Glass <sjg(a)chromium.org> --- arch/x86/lib/zimage.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/x86/lib/zimage.c b/arch/x86/lib/zimage.c index 90fc8a466d7..cf4210cd4ba 100644 --- a/arch/x86/lib/zimage.c +++ b/arch/x86/lib/zimage.c @@ -313,12 +313,12 @@ int setup_zimage(struct boot_params *setup_base, char *cmd_line, int auto_boot, int bootproto = get_boot_protocol(hdr, false); log_debug("Setup E820 entries\n"); - if (ll_boot_init()) { - setup_base->e820_entries = install_e820_map( - ARRAY_SIZE(setup_base->e820_map), setup_base->e820_map); - } else if (IS_ENABLED(CONFIG_COREBOOT_SYSINFO)) { + if (IS_ENABLED(CONFIG_COREBOOT_SYSINFO)) { setup_base->e820_entries = cb_install_e820_map( ARRAY_SIZE(setup_base->e820_map), setup_base->e820_map); + } else { + setup_base->e820_entries = install_e820_map( + ARRAY_SIZE(setup_base->e820_map), setup_base->e820_map); } if (bootproto == 0x0100) { -- 2.32.0.93.g670b81a890-goog

3 3

[PATCH] Revert "arm: bootm: Disable LMB reservation for command line and board info on arm64"
by Jan Kiszka 09 Aug '21

09 Aug '21

From: Jan Kiszka <jan.kiszka(a)siemens.com> This reverts commit 2359fa7a87848626bcbd3399e92c657595880cd7. While the goal is valid and there is surely unused memory in that area, we also have a lot of crucial things still located at the top-of-memory while running lmb_alloc_base. Such things are the page table (tlb_addr), relocated U-Boot and the active stack. Possibly more. So this patch was premature, we will need relocations of those things first if we want to use the range. Fixes booting on the IOT2050, but likely also on other boards. It got stuck on relocating the FDT - over the relocated U-Boot code. Signed-off-by: Jan Kiszka <jan.kiszka(a)siemens.com> --- Practically, void arch_lmb_reserve(struct lmb *lmb) { lmb_reserve(lmb, gd->relocaddr, gd->ram_top - gd->relocaddr); } worked as well for me - but it left the stack in danger. arch/arm/lib/bootm.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c index 23b99a541c..f60ee3a7e6 100644 --- a/arch/arm/lib/bootm.c +++ b/arch/arm/lib/bootm.c @@ -43,7 +43,6 @@ DECLARE_GLOBAL_DATA_PTR; static struct tag *params; -#ifndef CONFIG_ARM64 static ulong get_sp(void) { ulong ret; @@ -87,7 +86,6 @@ void arch_lmb_reserve(struct lmb *lmb) break; } } -#endif __weak void board_quiesce_devices(void) { -- 2.26.2

5 38

[PATCH 1/5] ARM: board: warp: Import dts files
by Peter Robinson 09 Aug '21

09 Aug '21

Import the i.MX6 based Warp dts files from Linux 5.12-rc1. Signed-off-by: Peter Robinson <pbrobinson(a)gmail.com> Cc: Fabio Estevam <fabio.estevam(a)nxp.com> Cc: Stefano Babic <sbabic(a)denx.de> --- arch/arm/dts/Makefile | 4 +- arch/arm/dts/imx6sl-warp.dts | 234 +++++++++++++++++++++++++++++++++++ 2 files changed, 237 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/imx6sl-warp.dts diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 116f75192f..1481a6ec46 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -734,7 +734,9 @@ dtb-y += \ endif -dtb-$(CONFIG_MX6SL) += imx6sl-evk.dtb +dtb-$(CONFIG_MX6SL) += \ + imx6sl-evk.dtb \ + imx6sl-warp.dtb dtb-$(CONFIG_MX6SLL) += imx6sll-evk.dtb diff --git a/arch/arm/dts/imx6sl-warp.dts b/arch/arm/dts/imx6sl-warp.dts new file mode 100644 index 0000000000..9d7c888489 --- /dev/null +++ b/arch/arm/dts/imx6sl-warp.dts @@ -0,0 +1,234 @@ +/* + * Copyright 2014, 2015 O.S. Systems Software LTDA. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include "imx6sl.dtsi" + +/ { + model = "Revotics WaRP Board"; + compatible = "revotics,imx6sl-warp", "fsl,imx6sl"; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + usdhc3_pwrseq: usdhc3_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>, /* WL_REG_ON */ + <&gpio4 7 GPIO_ACTIVE_LOW>, /* WL_HOSTWAKE */ + <&gpio3 25 GPIO_ACTIVE_LOW>, /* BT_REG_ON */ + <&gpio3 27 GPIO_ACTIVE_LOW>, /* BT_HOSTWAKE */ + <&gpio4 4 GPIO_ACTIVE_LOW>, /* BT_WAKE */ + <&gpio4 6 GPIO_ACTIVE_LOW>; /* BT_RST_N */ + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + uart-has-rtscts; + status = "okay"; +}; + +&usbotg1 { + dr_mode = "peripheral"; + disable-over-current; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <4>; + non-removable; + keep-power-in-suspend; + wakeup-source; + mmc-pwrseq = <&usdhc3_pwrseq>; + status = "okay"; +}; + +&iomuxc { + imx6sl-warp { + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x41b0b1 + MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x41b0b1 + >; + }; + + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6SL_PAD_AUD_RXC__UART3_RX_DATA 0x41b0b1 + MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x41b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6SL_PAD_ECSPI1_SCLK__UART5_RX_DATA 0x41b0b1 + MX6SL_PAD_ECSPI1_MOSI__UART5_TX_DATA 0x41b0b1 + MX6SL_PAD_ECSPI1_MISO__UART5_RTS_B 0x4130b1 + MX6SL_PAD_ECSPI1_SS0__UART5_CTS_B 0x4130b1 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6SL_PAD_SD2_CMD__SD2_CMD 0x417059 + MX6SL_PAD_SD2_CLK__SD2_CLK 0x410059 + MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x417059 + MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x417059 + MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x417059 + MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x417059 + MX6SL_PAD_SD2_DAT4__SD2_DATA4 0x417059 + MX6SL_PAD_SD2_DAT5__SD2_DATA5 0x417059 + MX6SL_PAD_SD2_DAT6__SD2_DATA6 0x417059 + MX6SL_PAD_SD2_DAT7__SD2_DATA7 0x417059 + MX6SL_PAD_SD2_RST__SD2_RESET 0x417059 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX6SL_PAD_SD2_CMD__SD2_CMD 0x4170b9 + MX6SL_PAD_SD2_CLK__SD2_CLK 0x4100b9 + MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x4170b9 + MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x4170b9 + MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x4170b9 + MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x4170b9 + MX6SL_PAD_SD2_DAT4__SD2_DATA4 0x4170b9 + MX6SL_PAD_SD2_DAT5__SD2_DATA5 0x4170b9 + MX6SL_PAD_SD2_DAT6__SD2_DATA6 0x4170b9 + MX6SL_PAD_SD2_DAT7__SD2_DATA7 0x4170b9 + MX6SL_PAD_SD2_RST__SD2_RESET 0x4170b9 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX6SL_PAD_SD2_CMD__SD2_CMD 0x4170f9 + MX6SL_PAD_SD2_CLK__SD2_CLK 0x4100f9 + MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x4170f9 + MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x4170f9 + MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x4170f9 + MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x4170f9 + MX6SL_PAD_SD2_DAT4__SD2_DATA4 0x4170f9 + MX6SL_PAD_SD2_DAT5__SD2_DATA5 0x4170f9 + MX6SL_PAD_SD2_DAT6__SD2_DATA6 0x4170f9 + MX6SL_PAD_SD2_DAT7__SD2_DATA7 0x4170f9 + MX6SL_PAD_SD2_RST__SD2_RESET 0x4170f9 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6SL_PAD_SD3_CMD__SD3_CMD 0x417059 + MX6SL_PAD_SD3_CLK__SD3_CLK 0x410059 + MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x417059 + MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x417059 + MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x417059 + MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x417059 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins = < + MX6SL_PAD_SD3_CMD__SD3_CMD 0x4170b9 + MX6SL_PAD_SD3_CLK__SD3_CLK 0x4100b9 + MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x4170b9 + MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x4170b9 + MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x4170b9 + MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x4170b9 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins = < + MX6SL_PAD_SD3_CMD__SD3_CMD 0x4170f9 + MX6SL_PAD_SD3_CLK__SD3_CLK 0x4100f9 + MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x4170f9 + MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x4170f9 + MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x4170f9 + MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x4170f9 + >; + }; + }; +}; -- 2.31.1

5 13

[PATCH] dm: migrate the dm_warn to use the log macro
by Patrick Delaunay 09 Aug '21

09 Aug '21

Migrate the dm_warn function to log macro with LOGC_DM category and LOGL_WARNING level. This macro allows filtering with log command and allows output on all log backend. Signed-off-by: Patrick Delaunay <patrick.delaunay(a)foss.st.com> --- drivers/core/util.c | 11 ----------- include/dm/util.h | 2 +- 2 files changed, 1 insertion(+), 12 deletions(-) diff --git a/drivers/core/util.c b/drivers/core/util.c index 91e93b0cf1..5be4ee79de 100644 --- a/drivers/core/util.c +++ b/drivers/core/util.c @@ -11,17 +11,6 @@ #include <linux/libfdt.h> #include <vsprintf.h> -#if CONFIG_IS_ENABLED(DM_WARN) -void dm_warn(const char *fmt, ...) -{ - va_list args; - - va_start(args, fmt); - vprintf(fmt, args); - va_end(args); -} -#endif - int list_count_items(struct list_head *head) { struct list_head *node; diff --git a/include/dm/util.h b/include/dm/util.h index 138893c935..c634e470e7 100644 --- a/include/dm/util.h +++ b/include/dm/util.h @@ -7,7 +7,7 @@ #define __DM_UTIL_H #if CONFIG_IS_ENABLED(DM_WARN) -void dm_warn(const char *fmt, ...); +#define dm_warn(fmt...) log(LOGC_DM, LOGL_WARNING, ##fmt) #else static inline void dm_warn(const char *fmt, ...) { -- 2.25.1

2 2

[PATCH V4 00/44] imx: add i.MX8ULP support
by Peng Fan (OSS) 07 Aug '21

07 Aug '21

From: Peng Fan <peng.fan(a)nxp.com> V4: Fix checkpatch errors Fix some checkpatch warnings, there are still warnings such as pin header and dts exceed 100. Tom, Stefano, please see whether you are happy with this patchset. V3: Fix build error which break 8MN, pass buildman for i.MX. Select GPIO_EXTRA_HEADER for 8ULP to fix build break which caused by upstream change. Rebased Drop 7ULP, since already been picked up. V2: Rebased and test on new revision silicon with upower included. The i.MX 8ULP crossover applications processor family brings ultra-low power processing and advanced integrated security with EdgeLockTM secure enclave to the intelligent edge. It includes an uPower core for handling power related functions. This patchset is to add initial support for i.MX8ULP, with core soc functions, clock, dtsi, and evk board. Peng Fan (24): arm: imx: add i.MX8ULP basic Kconfig option arm: imx: add i.MX8ULP cpu type and helper arm: imx: sys_proto: move boot mode define to common header arm: imx8ulp: support print cpu info imx: imx8ulp: add get reset cause arm: imx: basic i.MX8ULP support arm: imx: parse-container: guard included header files arm: imx: move container Kconfig under mach-imx net: fec_mxc: support i.MX8ULP driver: serial: fsl_lpuart: support i.MX8ULP arm: imx8ulp: add clock support drivers: mmc: fsl_esdhc_imx: support i.MX8ULP arm: imx8ulp: disable wdog3 arm: imx8ulp: add rdc support arm: imx8ulp: add trdc release request arm: imx8ulp: release trdc and assign lpav from RTD to APD imx8ulp: unify rdc functions arm: imx8ulp: add dummy imx_get_mac_from_fuse arm: imx8ulp: add iomuxc support imx8ulp: soc: correct reset cause imx8ulp: move struct mu_type to common header imx8ulp: add upower api support arm: dts: add i.MX8ULP dtsi arm: imx: add i.MX8ULP EVK support Ye Li (20): arm: imx8: Move container parser and image to mach-imx common folder arm: imx8: Move container image header file to mach-imx arm: imx8ulp: add container support driver: misc: Add MU and S400 API to communicate with Sentinel pinctrl: Add pinctrl driver for imx8ulp arm: imx8ulp: soc: Change to use CMC1 to get bootcfg arm: imx8ulp: Enable full L2 cache in SPL arm: imx8ulp: Update the reset vector in u-boot drivers: misc: s400_api: Update S400_SUCCESS_IND to 0xd6 drivers: misc: imx8ulp: Add S400 API for image authentication drivers: misc: imx8ulp: Update S400 API for release RDC drivers: misc: s400_api: Update API for fuse read and write arm: imx8ulp: release and configure XRDC at early phase arm: imx8ulp: Probe the S400 MU device in arch init arm: iMX8ULP: Add boot device relevant functions arm: imx8ulp: Allocate DCNANO and MIPI_DSI to AD domain driver: misc: imx8ulp: Add fuse driver for imx8ulp imx8ulp: Use DGO_GP5 to get boot config imx8ulp: Add workaround for eMMC boot ddr: Add DDR driver for iMX8ULP Peng Fan (24): arm: imx: add i.MX8ULP basic Kconfig option arm: imx: add i.MX8ULP cpu type and helper arm: imx: sys_proto: move boot mode define to common header arm: imx8ulp: support print cpu info imx: imx8ulp: add get reset cause arm: imx: basic i.MX8ULP support arm: imx: parse-container: guard included header files arm: imx: move container Kconfig under mach-imx net: fec_mxc: support i.MX8ULP driver: serial: fsl_lpuart: support i.MX8ULP arm: imx8ulp: add clock support drivers: mmc: fsl_esdhc_imx: support i.MX8ULP arm: imx8ulp: disable wdog3 arm: imx8ulp: add rdc support arm: imx8ulp: add trdc release request arm: imx8ulp: release trdc and assign lpav from RTD to APD imx8ulp: unify rdc functions arm: imx8ulp: add dummy imx_get_mac_from_fuse arm: imx8ulp: add iomuxc support imx8ulp: soc: correct reset cause imx8ulp: move struct mu_type to common header imx8ulp: add upower api support arm: dts: add i.MX8ULP dtsi arm: imx: add i.MX8ULP EVK support Ye Li (20): arm: imx8: Move container parser and image to mach-imx common folder arm: imx8: Move container image header file to mach-imx arm: imx8ulp: add container support driver: misc: Add MU and S400 API to communicate with Sentinel pinctrl: Add pinctrl driver for imx8ulp arm: imx8ulp: soc: Change to use CMC1 to get bootcfg arm: imx8ulp: Enable full L2 cache in SPL arm: imx8ulp: Update the reset vector in u-boot drivers: misc: s400_api: Update S400_SUCCESS_IND to 0xd6 drivers: misc: imx8ulp: Add S400 API for image authentication drivers: misc: imx8ulp: Update S400 API for release RDC drivers: misc: s400_api: Update API for fuse read and write arm: imx8ulp: release and configure XRDC at early phase arm: imx8ulp: Probe the S400 MU device in arch init arm: iMX8ULP: Add boot device relevant functions arm: imx8ulp: Allocate DCNANO and MIPI_DSI to AD domain driver: misc: imx8ulp: Add fuse driver for imx8ulp imx8ulp: Use DGO_GP5 to get boot config imx8ulp: Add workaround for eMMC boot ddr: Add DDR driver for iMX8ULP arch/arm/Kconfig | 11 + arch/arm/Makefile | 4 +- arch/arm/dts/Makefile | 3 + arch/arm/dts/imx8ulp-evk-u-boot.dtsi | 40 + arch/arm/dts/imx8ulp-evk.dts | 223 ++++ arch/arm/dts/imx8ulp-pinfunc.h | 978 ++++++++++++++ arch/arm/dts/imx8ulp.dtsi | 728 +++++++++++ arch/arm/include/asm/arch-imx/cpu.h | 4 + arch/arm/include/asm/arch-imx8ulp/cgc.h | 130 ++ arch/arm/include/asm/arch-imx8ulp/clock.h | 41 + arch/arm/include/asm/arch-imx8ulp/ddr.h | 38 + arch/arm/include/asm/arch-imx8ulp/gpio.h | 20 + arch/arm/include/asm/arch-imx8ulp/imx-regs.h | 162 +++ .../include/asm/arch-imx8ulp/imx8ulp-pins.h | 60 + arch/arm/include/asm/arch-imx8ulp/iomux.h | 82 ++ arch/arm/include/asm/arch-imx8ulp/mu_hal.h | 12 + arch/arm/include/asm/arch-imx8ulp/pcc.h | 139 ++ arch/arm/include/asm/arch-imx8ulp/rdc.h | 27 + arch/arm/include/asm/arch-imx8ulp/s400_api.h | 41 + arch/arm/include/asm/arch-imx8ulp/sys_proto.h | 19 + arch/arm/include/asm/arch-imx8ulp/upower.h | 15 + arch/arm/include/asm/arch-mx7ulp/sys_proto.h | 9 - arch/arm/include/asm/global_data.h | 5 + .../asm/{arch-imx8 => mach-imx}/image.h | 2 + arch/arm/include/asm/mach-imx/sys_proto.h | 13 +- arch/arm/mach-imx/Kconfig | 15 +- arch/arm/mach-imx/Makefile | 5 + arch/arm/mach-imx/cmd_dek.c | 2 +- .../{imx8/image.c => image-container.c} | 51 +- arch/arm/mach-imx/imx8/Kconfig | 13 - arch/arm/mach-imx/imx8/Makefile | 3 - arch/arm/mach-imx/imx8/ahab.c | 2 +- arch/arm/mach-imx/imx8ulp/Kconfig | 23 + arch/arm/mach-imx/imx8ulp/Makefile | 11 + arch/arm/mach-imx/imx8ulp/cgc.c | 455 +++++++ arch/arm/mach-imx/imx8ulp/clock.c | 397 ++++++ arch/arm/mach-imx/imx8ulp/iomux.c | 58 + arch/arm/mach-imx/imx8ulp/lowlevel_init.S | 26 + arch/arm/mach-imx/imx8ulp/pcc.c | 449 +++++++ arch/arm/mach-imx/imx8ulp/rdc.c | 411 ++++++ arch/arm/mach-imx/imx8ulp/soc.c | 545 ++++++++ arch/arm/mach-imx/imx8ulp/upower/Makefile | 6 + arch/arm/mach-imx/imx8ulp/upower/upower_api.c | 486 +++++++ arch/arm/mach-imx/imx8ulp/upower/upower_api.h | 258 ++++ arch/arm/mach-imx/imx8ulp/upower/upower_hal.c | 180 +++ .../arm/mach-imx/{imx8 => }/parse-container.c | 4 +- arch/arm/mach-imx/spl_imx_romapi.c | 172 ++- board/freescale/imx8ulp_evk/Kconfig | 14 + board/freescale/imx8ulp_evk/MAINTAINERS | 6 + board/freescale/imx8ulp_evk/Makefile | 7 + board/freescale/imx8ulp_evk/ddr_init.c | 207 +++ board/freescale/imx8ulp_evk/imx8ulp_evk.c | 67 + board/freescale/imx8ulp_evk/lpddr4_timing.c | 1159 +++++++++++++++++ board/freescale/imx8ulp_evk/spl.c | 105 ++ configs/imx8ulp_evk_defconfig | 103 ++ drivers/Makefile | 1 + drivers/ddr/imx/Kconfig | 1 + drivers/ddr/imx/imx8ulp/Kconfig | 11 + drivers/ddr/imx/imx8ulp/Makefile | 9 + drivers/ddr/imx/imx8ulp/ddr_init.c | 217 +++ drivers/misc/Makefile | 1 + drivers/misc/imx8ulp/Makefile | 4 + drivers/misc/imx8ulp/fuse.c | 198 +++ drivers/misc/imx8ulp/imx8ulp_mu.c | 234 ++++ drivers/misc/imx8ulp/s400_api.c | 244 ++++ drivers/mmc/Kconfig | 2 +- drivers/mmc/fsl_esdhc_imx.c | 12 +- drivers/net/Kconfig | 2 +- drivers/net/fec_mxc.c | 2 +- drivers/pinctrl/nxp/Kconfig | 14 + drivers/pinctrl/nxp/Makefile | 1 + drivers/pinctrl/nxp/pinctrl-imx8ulp.c | 44 + include/configs/imx8ulp_evk.h | 107 ++ include/dt-bindings/clock/imx8ulp-clock.h | 247 ++++ include/fsl_lpuart.h | 2 +- 75 files changed, 9313 insertions(+), 86 deletions(-) create mode 100644 arch/arm/dts/imx8ulp-evk-u-boot.dtsi create mode 100644 arch/arm/dts/imx8ulp-evk.dts create mode 100644 arch/arm/dts/imx8ulp-pinfunc.h create mode 100644 arch/arm/dts/imx8ulp.dtsi create mode 100644 arch/arm/include/asm/arch-imx8ulp/cgc.h create mode 100644 arch/arm/include/asm/arch-imx8ulp/clock.h create mode 100644 arch/arm/include/asm/arch-imx8ulp/ddr.h create mode 100644 arch/arm/include/asm/arch-imx8ulp/gpio.h create mode 100644 arch/arm/include/asm/arch-imx8ulp/imx-regs.h create mode 100644 arch/arm/include/asm/arch-imx8ulp/imx8ulp-pins.h create mode 100644 arch/arm/include/asm/arch-imx8ulp/iomux.h create mode 100644 arch/arm/include/asm/arch-imx8ulp/mu_hal.h create mode 100644 arch/arm/include/asm/arch-imx8ulp/pcc.h create mode 100644 arch/arm/include/asm/arch-imx8ulp/rdc.h create mode 100644 arch/arm/include/asm/arch-imx8ulp/s400_api.h create mode 100644 arch/arm/include/asm/arch-imx8ulp/sys_proto.h create mode 100644 arch/arm/include/asm/arch-imx8ulp/upower.h rename arch/arm/include/asm/{arch-imx8 => mach-imx}/image.h (95%) rename arch/arm/mach-imx/{imx8/image.c => image-container.c} (79%) create mode 100644 arch/arm/mach-imx/imx8ulp/Kconfig create mode 100644 arch/arm/mach-imx/imx8ulp/Makefile create mode 100644 arch/arm/mach-imx/imx8ulp/cgc.c create mode 100644 arch/arm/mach-imx/imx8ulp/clock.c create mode 100644 arch/arm/mach-imx/imx8ulp/iomux.c create mode 100644 arch/arm/mach-imx/imx8ulp/lowlevel_init.S create mode 100644 arch/arm/mach-imx/imx8ulp/pcc.c create mode 100644 arch/arm/mach-imx/imx8ulp/rdc.c create mode 100644 arch/arm/mach-imx/imx8ulp/soc.c create mode 100644 arch/arm/mach-imx/imx8ulp/upower/Makefile create mode 100644 arch/arm/mach-imx/imx8ulp/upower/upower_api.c create mode 100644 arch/arm/mach-imx/imx8ulp/upower/upower_api.h create mode 100644 arch/arm/mach-imx/imx8ulp/upower/upower_hal.c rename arch/arm/mach-imx/{imx8 => }/parse-container.c (98%) create mode 100644 board/freescale/imx8ulp_evk/Kconfig create mode 100644 board/freescale/imx8ulp_evk/MAINTAINERS create mode 100644 board/freescale/imx8ulp_evk/Makefile create mode 100644 board/freescale/imx8ulp_evk/ddr_init.c create mode 100644 board/freescale/imx8ulp_evk/imx8ulp_evk.c create mode 100644 board/freescale/imx8ulp_evk/lpddr4_timing.c create mode 100644 board/freescale/imx8ulp_evk/spl.c create mode 100644 configs/imx8ulp_evk_defconfig create mode 100644 drivers/ddr/imx/imx8ulp/Kconfig create mode 100644 drivers/ddr/imx/imx8ulp/Makefile create mode 100644 drivers/ddr/imx/imx8ulp/ddr_init.c create mode 100644 drivers/misc/imx8ulp/Makefile create mode 100644 drivers/misc/imx8ulp/fuse.c create mode 100644 drivers/misc/imx8ulp/imx8ulp_mu.c create mode 100644 drivers/misc/imx8ulp/s400_api.c create mode 100644 drivers/pinctrl/nxp/pinctrl-imx8ulp.c create mode 100644 include/configs/imx8ulp_evk.h create mode 100644 include/dt-bindings/clock/imx8ulp-clock.h -- 2.30.0

2 49

Problem on imx: add rom api support on imx8mn
by Michael Nazzareno Trimarchi 06 Aug '21

06 Aug '21

Hi all I have some problems that I have understood and fixed but I can not explain. Right now I have on imx8mn that can boot from boot0 or boot1 partition after remove a condition in the is_boot_from_stream_device This is a boot from mmcblk0boot0 with some debug U-Boot SPL 2020.04-5.4.70-2.3.2+gf3bcbdfc62 (Jul 03 2021 - 17:00:27 +0000) power_bd71837_init DDRINFO: start DRAM init DDRINFO: DRAM rate 1600MTS DDRINFO:ddrphy calibration done DDRINFO: ddrmix config done Normal Boot Trying to boot from BOOTROM ROM API interface 2 from boot 131073 Interface is 2 MMC and boot is 131073 and according to this static int is_boot_from_stream_device(u32 boot) +{ + u32 interface; + + interface = boot >> 16; + if (interface >= BT_DEV_TYPE_USB) + return 1; + + if (interface == BT_DEV_TYPE_MMC && (boot & 1)) + return 1; + + return 0; +} means a stream interface but it does not boot. Boot from boot1 give 131072 that is boot1 this let device boot because is_boot_from_stream_device is 0 and romapi use spl_romapi_load_image_seekable Remove boot & 1 condition let me boot from mmcblk0boot0 and mmcblk0boot1 without any problem mmc partconf 0 EXT_CSD[179], PARTITION_CONFIG: BOOT_ACK: 0x0 BOOT_PARTITION_ENABLE: 0x1 PARTITION_ACCESS: 0x0 and the board was fused already. Any idea why? Michael

3 8

[PATCH 0/4] xilinx: Add RTC support for Xilinx ZynqMP
by Michal Simek 06 Aug '21

06 Aug '21

Hi, this series is correcting RTC uclass behavior to match RTC aliases to enable RTC_EMULATION driver with ZYNQMP driver. If DT node is present ZynqMP RTC is used. If not RTC emaulation is used. The driver has been tested on Xilinx zcu104 also with booting to Linux to make sure that U-Boot format match with Linux format. Thanks, Michal Michal Simek (4): dm: rtc: uclass: Add flag to control sequence numbering cmd: date: rtc: Update command to read the first RTC with seq 0 rtc: zynqmp: Add support for ZynqMP RTC xilinx: zynqmp: Enable CMD_RTC command with Zynqmp RTC driver MAINTAINERS | 1 + cmd/date.c | 9 +- configs/xilinx_zynqmp_virt_defconfig | 2 + drivers/rtc/Kconfig | 7 ++ drivers/rtc/Makefile | 1 + drivers/rtc/rtc-uclass.c | 1 + drivers/rtc/zynqmp_rtc.c | 158 +++++++++++++++++++++++++++ 7 files changed, 176 insertions(+), 3 deletions(-) create mode 100644 drivers/rtc/zynqmp_rtc.c -- 2.32.0

2 5

[PATCH] reset: zynqmp: Add reset controller for ZynqMP SoC
by Michal Simek 06 Aug '21

06 Aug '21

Add firmware based reset controller for Xilinx ZynqMP SoC to let other drivers to call reset functions. Driver is only tested on Xilinx ZynqMP but support for Xilinx Versal can be simply added. That's why reset_id and nr_reset are assigned in probe folder. Driver is inpired by driver from Linux kernel. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- MAINTAINERS | 1 + drivers/reset/Kconfig | 9 +++ drivers/reset/Makefile | 1 + drivers/reset/reset-zynqmp.c | 100 ++++++++++++++++++++++++++ include/zynqmp_firmware.h | 131 +++++++++++++++++++++++++++++++++++ 5 files changed, 242 insertions(+) create mode 100644 drivers/reset/reset-zynqmp.c diff --git a/MAINTAINERS b/MAINTAINERS index 483a45840803..868d4e145ca2 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -600,6 +600,7 @@ F: drivers/mtd/nand/raw/zynq_nand.c F: drivers/net/phy/xilinx_phy.c F: drivers/net/zynq_gem.c F: drivers/serial/serial_zynq.c +F: drivers/reset/reset-zynqmp.c F: drivers/rtc/zynqmp_rtc.c F: drivers/spi/zynq_qspi.c F: drivers/spi/zynq_spi.c diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index a42b3f0077c9..d73daf5e3189 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -197,4 +197,13 @@ config RESET_SCMI Enable this option if you want to support reset controller devices exposed by a SCMI agent based on SCMI reset domain protocol communication with a SCMI server. + +config RESET_ZYNQMP + bool "Reset Driver for Xilinx ZynqMP SoC's" + depends on DM_RESET && ZYNQMP_FIRMWARE + help + Support for reset controller on Xilinx ZynqMP SoC. Driver is only + passing request via Xilinx firmware interface to TF-A and PMU + firmware. + endmenu diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 8a0f5280761a..d69486bdeb9e 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -29,3 +29,4 @@ obj-$(CONFIG_RESET_SIFIVE) += reset-sifive.o obj-$(CONFIG_RESET_SYSCON) += reset-syscon.o obj-$(CONFIG_RESET_RASPBERRYPI) += reset-raspberrypi.o obj-$(CONFIG_RESET_SCMI) += reset-scmi.o +obj-$(CONFIG_RESET_ZYNQMP) += reset-zynqmp.o diff --git a/drivers/reset/reset-zynqmp.c b/drivers/reset/reset-zynqmp.c new file mode 100644 index 000000000000..57652346738d --- /dev/null +++ b/drivers/reset/reset-zynqmp.c @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 Xilinx, Inc. - Michal Simek + */ + +#define LOG_CATEGORY UCLASS_RESET + +#include <common.h> +#include <dm.h> +#include <dm/device_compat.h> +#include <reset-uclass.h> +#include <zynqmp_firmware.h> + +#define ZYNQMP_NR_RESETS (ZYNQMP_PM_RESET_END - ZYNQMP_PM_RESET_START) +#define ZYNQMP_RESET_ID ZYNQMP_PM_RESET_START + +struct zynqmp_reset_priv { + u32 reset_id; + u32 nr_reset; +}; + +static int zynqmp_pm_reset_assert(const u32 reset, + const enum zynqmp_pm_reset_action assert_flag) +{ + return xilinx_pm_request(PM_RESET_ASSERT, reset, assert_flag, 0, 0, + NULL); +} + +static int zynqmp_reset_assert(struct reset_ctl *rst) +{ + struct zynqmp_reset_priv *priv = dev_get_priv(rst->dev); + + dev_dbg(rst->dev, "%s(rst=%p) (id=%lu)\n", __func__, rst, rst->id); + + return zynqmp_pm_reset_assert(priv->reset_id + rst->id, + PM_RESET_ACTION_ASSERT); +} + +static int zynqmp_reset_deassert(struct reset_ctl *rst) +{ + struct zynqmp_reset_priv *priv = dev_get_priv(rst->dev); + + dev_dbg(rst->dev, "%s(rst=%p) (id=%lu)\n", __func__, rst, rst->id); + + return zynqmp_pm_reset_assert(priv->reset_id + rst->id, + PM_RESET_ACTION_RELEASE); +} + +static int zynqmp_reset_request(struct reset_ctl *rst) +{ + struct zynqmp_reset_priv *priv = dev_get_priv(rst->dev); + + dev_dbg(rst->dev, "%s(rst=%p) (id=%lu) (nr_reset=%d)\n", __func__, + rst, rst->id, priv->nr_reset); + + if (rst->id > priv->nr_reset) + return -EINVAL; + + return 0; +} + +static int zynqmp_reset_free(struct reset_ctl *rst) +{ + struct zynqmp_reset_priv *priv = dev_get_priv(rst->dev); + + dev_dbg(rst->dev, "%s(rst=%p) (id=%lu) (nr_reset=%d)\n", __func__, + rst, rst->id, priv->nr_reset); + + return 0; +} + +static int zynqmp_reset_probe(struct udevice *dev) +{ + struct zynqmp_reset_priv *priv = dev_get_priv(dev); + + priv->reset_id = ZYNQMP_RESET_ID; + priv->nr_reset = ZYNQMP_NR_RESETS; + return 0; +} + +const struct reset_ops zynqmp_reset_ops = { + .request = zynqmp_reset_request, + .rfree = zynqmp_reset_free, + .rst_assert = zynqmp_reset_assert, + .rst_deassert = zynqmp_reset_deassert, +}; + +static const struct udevice_id zynqmp_reset_ids[] = { + { .compatible = "xlnx,zynqmp-reset" }, + { } +}; + +U_BOOT_DRIVER(zynqmp_reset) = { + .name = "zynqmp_reset", + .id = UCLASS_RESET, + .of_match = zynqmp_reset_ids, + .ops = &zynqmp_reset_ops, + .probe = zynqmp_reset_probe, + .priv_auto = sizeof(struct zynqmp_reset_priv), +}; diff --git a/include/zynqmp_firmware.h b/include/zynqmp_firmware.h index 669af6765ce9..90ee1f6b2a78 100644 --- a/include/zynqmp_firmware.h +++ b/include/zynqmp_firmware.h @@ -67,6 +67,137 @@ enum pm_api_id { PM_API_MAX, }; +enum zynqmp_pm_reset_action { + PM_RESET_ACTION_RELEASE = 0, + PM_RESET_ACTION_ASSERT = 1, + PM_RESET_ACTION_PULSE = 2, +}; + +enum zynqmp_pm_reset { + ZYNQMP_PM_RESET_START = 1000, + ZYNQMP_PM_RESET_PCIE_CFG = ZYNQMP_PM_RESET_START, + ZYNQMP_PM_RESET_PCIE_BRIDGE = 1001, + ZYNQMP_PM_RESET_PCIE_CTRL = 1002, + ZYNQMP_PM_RESET_DP = 1003, + ZYNQMP_PM_RESET_SWDT_CRF = 1004, + ZYNQMP_PM_RESET_AFI_FM5 = 1005, + ZYNQMP_PM_RESET_AFI_FM4 = 1006, + ZYNQMP_PM_RESET_AFI_FM3 = 1007, + ZYNQMP_PM_RESET_AFI_FM2 = 1008, + ZYNQMP_PM_RESET_AFI_FM1 = 1009, + ZYNQMP_PM_RESET_AFI_FM0 = 1010, + ZYNQMP_PM_RESET_GDMA = 1011, + ZYNQMP_PM_RESET_GPU_PP1 = 1012, + ZYNQMP_PM_RESET_GPU_PP0 = 1013, + ZYNQMP_PM_RESET_GPU = 1014, + ZYNQMP_PM_RESET_GT = 1015, + ZYNQMP_PM_RESET_SATA = 1016, + ZYNQMP_PM_RESET_ACPU3_PWRON = 1017, + ZYNQMP_PM_RESET_ACPU2_PWRON = 1018, + ZYNQMP_PM_RESET_ACPU1_PWRON = 1019, + ZYNQMP_PM_RESET_ACPU0_PWRON = 1020, + ZYNQMP_PM_RESET_APU_L2 = 1021, + ZYNQMP_PM_RESET_ACPU3 = 1022, + ZYNQMP_PM_RESET_ACPU2 = 1023, + ZYNQMP_PM_RESET_ACPU1 = 1024, + ZYNQMP_PM_RESET_ACPU0 = 1025, + ZYNQMP_PM_RESET_DDR = 1026, + ZYNQMP_PM_RESET_APM_FPD = 1027, + ZYNQMP_PM_RESET_SOFT = 1028, + ZYNQMP_PM_RESET_GEM0 = 1029, + ZYNQMP_PM_RESET_GEM1 = 1030, + ZYNQMP_PM_RESET_GEM2 = 1031, + ZYNQMP_PM_RESET_GEM3 = 1032, + ZYNQMP_PM_RESET_QSPI = 1033, + ZYNQMP_PM_RESET_UART0 = 1034, + ZYNQMP_PM_RESET_UART1 = 1035, + ZYNQMP_PM_RESET_SPI0 = 1036, + ZYNQMP_PM_RESET_SPI1 = 1037, + ZYNQMP_PM_RESET_SDIO0 = 1038, + ZYNQMP_PM_RESET_SDIO1 = 1039, + ZYNQMP_PM_RESET_CAN0 = 1040, + ZYNQMP_PM_RESET_CAN1 = 1041, + ZYNQMP_PM_RESET_I2C0 = 1042, + ZYNQMP_PM_RESET_I2C1 = 1043, + ZYNQMP_PM_RESET_TTC0 = 1044, + ZYNQMP_PM_RESET_TTC1 = 1045, + ZYNQMP_PM_RESET_TTC2 = 1046, + ZYNQMP_PM_RESET_TTC3 = 1047, + ZYNQMP_PM_RESET_SWDT_CRL = 1048, + ZYNQMP_PM_RESET_NAND = 1049, + ZYNQMP_PM_RESET_ADMA = 1050, + ZYNQMP_PM_RESET_GPIO = 1051, + ZYNQMP_PM_RESET_IOU_CC = 1052, + ZYNQMP_PM_RESET_TIMESTAMP = 1053, + ZYNQMP_PM_RESET_RPU_R50 = 1054, + ZYNQMP_PM_RESET_RPU_R51 = 1055, + ZYNQMP_PM_RESET_RPU_AMBA = 1056, + ZYNQMP_PM_RESET_OCM = 1057, + ZYNQMP_PM_RESET_RPU_PGE = 1058, + ZYNQMP_PM_RESET_USB0_CORERESET = 1059, + ZYNQMP_PM_RESET_USB1_CORERESET = 1060, + ZYNQMP_PM_RESET_USB0_HIBERRESET = 1061, + ZYNQMP_PM_RESET_USB1_HIBERRESET = 1062, + ZYNQMP_PM_RESET_USB0_APB = 1063, + ZYNQMP_PM_RESET_USB1_APB = 1064, + ZYNQMP_PM_RESET_IPI = 1065, + ZYNQMP_PM_RESET_APM_LPD = 1066, + ZYNQMP_PM_RESET_RTC = 1067, + ZYNQMP_PM_RESET_SYSMON = 1068, + ZYNQMP_PM_RESET_AFI_FM6 = 1069, + ZYNQMP_PM_RESET_LPD_SWDT = 1070, + ZYNQMP_PM_RESET_FPD = 1071, + ZYNQMP_PM_RESET_RPU_DBG1 = 1072, + ZYNQMP_PM_RESET_RPU_DBG0 = 1073, + ZYNQMP_PM_RESET_DBG_LPD = 1074, + ZYNQMP_PM_RESET_DBG_FPD = 1075, + ZYNQMP_PM_RESET_APLL = 1076, + ZYNQMP_PM_RESET_DPLL = 1077, + ZYNQMP_PM_RESET_VPLL = 1078, + ZYNQMP_PM_RESET_IOPLL = 1079, + ZYNQMP_PM_RESET_RPLL = 1080, + ZYNQMP_PM_RESET_GPO3_PL_0 = 1081, + ZYNQMP_PM_RESET_GPO3_PL_1 = 1082, + ZYNQMP_PM_RESET_GPO3_PL_2 = 1083, + ZYNQMP_PM_RESET_GPO3_PL_3 = 1084, + ZYNQMP_PM_RESET_GPO3_PL_4 = 1085, + ZYNQMP_PM_RESET_GPO3_PL_5 = 1086, + ZYNQMP_PM_RESET_GPO3_PL_6 = 1087, + ZYNQMP_PM_RESET_GPO3_PL_7 = 1088, + ZYNQMP_PM_RESET_GPO3_PL_8 = 1089, + ZYNQMP_PM_RESET_GPO3_PL_9 = 1090, + ZYNQMP_PM_RESET_GPO3_PL_10 = 1091, + ZYNQMP_PM_RESET_GPO3_PL_11 = 1092, + ZYNQMP_PM_RESET_GPO3_PL_12 = 1093, + ZYNQMP_PM_RESET_GPO3_PL_13 = 1094, + ZYNQMP_PM_RESET_GPO3_PL_14 = 1095, + ZYNQMP_PM_RESET_GPO3_PL_15 = 1096, + ZYNQMP_PM_RESET_GPO3_PL_16 = 1097, + ZYNQMP_PM_RESET_GPO3_PL_17 = 1098, + ZYNQMP_PM_RESET_GPO3_PL_18 = 1099, + ZYNQMP_PM_RESET_GPO3_PL_19 = 1100, + ZYNQMP_PM_RESET_GPO3_PL_20 = 1101, + ZYNQMP_PM_RESET_GPO3_PL_21 = 1102, + ZYNQMP_PM_RESET_GPO3_PL_22 = 1103, + ZYNQMP_PM_RESET_GPO3_PL_23 = 1104, + ZYNQMP_PM_RESET_GPO3_PL_24 = 1105, + ZYNQMP_PM_RESET_GPO3_PL_25 = 1106, + ZYNQMP_PM_RESET_GPO3_PL_26 = 1107, + ZYNQMP_PM_RESET_GPO3_PL_27 = 1108, + ZYNQMP_PM_RESET_GPO3_PL_28 = 1109, + ZYNQMP_PM_RESET_GPO3_PL_29 = 1110, + ZYNQMP_PM_RESET_GPO3_PL_30 = 1111, + ZYNQMP_PM_RESET_GPO3_PL_31 = 1112, + ZYNQMP_PM_RESET_RPU_LS = 1113, + ZYNQMP_PM_RESET_PS_ONLY = 1114, + ZYNQMP_PM_RESET_PL = 1115, + ZYNQMP_PM_RESET_PS_PL0 = 1116, + ZYNQMP_PM_RESET_PS_PL1 = 1117, + ZYNQMP_PM_RESET_PS_PL2 = 1118, + ZYNQMP_PM_RESET_PS_PL3 = 1119, + ZYNQMP_PM_RESET_END = ZYNQMP_PM_RESET_PS_PL3 +}; + enum pm_query_id { PM_QID_INVALID = 0, PM_QID_CLOCK_GET_NAME = 1, -- 2.32.0

2 1

[PATCH] firmware: xilinx: Use explicit values for all enum values
by Michal Simek 06 Aug '21

06 Aug '21

Based on discussion at https://lore.kernel.org/r/20200318125003.GA2727094@kroah.com we got recommendation to use explicit values for all enum values. The patch is following this recommendation. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> Link: https://lore.kernel.org/r/daeb67ded45d8a8f6a96717d1fb9c84439dd2ae8.16123616… --- include/zynqmp_firmware.h | 93 +++++++++++++++++++++------------------ 1 file changed, 49 insertions(+), 44 deletions(-) diff --git a/include/zynqmp_firmware.h b/include/zynqmp_firmware.h index f6f82bf8828e..669af6765ce9 100644 --- a/include/zynqmp_firmware.h +++ b/include/zynqmp_firmware.h @@ -10,54 +10,59 @@ enum pm_api_id { PM_GET_API_VERSION = 1, - PM_SET_CONFIGURATION, - PM_GET_NODE_STATUS, - PM_GET_OPERATING_CHARACTERISTIC, - PM_REGISTER_NOTIFIER, - PM_REQUEST_SUSPEND, - PM_SELF_SUSPEND, - PM_FORCE_POWERDOWN, - PM_ABORT_SUSPEND, - PM_REQUEST_WAKEUP, - PM_SET_WAKEUP_SOURCE, - PM_SYSTEM_SHUTDOWN, - PM_REQUEST_NODE, - PM_RELEASE_NODE, - PM_SET_REQUIREMENT, - PM_SET_MAX_LATENCY, - PM_RESET_ASSERT, - PM_RESET_GET_STATUS, - PM_MMIO_WRITE, - PM_MMIO_READ, - PM_PM_INIT_FINALIZE, - PM_FPGA_LOAD, - PM_FPGA_GET_STATUS, - PM_GET_CHIPID, + PM_SET_CONFIGURATION = 2, + PM_GET_NODE_STATUS = 3, + PM_GET_OPERATING_CHARACTERISTIC = 4, + PM_REGISTER_NOTIFIER = 5, + /* API for suspending */ + PM_REQUEST_SUSPEND = 6, + PM_SELF_SUSPEND = 7, + PM_FORCE_POWERDOWN = 8, + PM_ABORT_SUSPEND = 9, + PM_REQUEST_WAKEUP = 10, + PM_SET_WAKEUP_SOURCE = 11, + PM_SYSTEM_SHUTDOWN = 12, + PM_REQUEST_NODE = 13, + PM_RELEASE_NODE = 14, + PM_SET_REQUIREMENT = 15, + PM_SET_MAX_LATENCY = 16, + /* Direct control API functions: */ + PM_RESET_ASSERT = 17, + PM_RESET_GET_STATUS = 18, + PM_MMIO_WRITE = 19, + PM_MMIO_READ = 20, + PM_PM_INIT_FINALIZE = 21, + PM_FPGA_LOAD = 22, + PM_FPGA_GET_STATUS = 23, + PM_GET_CHIPID = 24, + /* ID 25 is been used by U-boot to process secure boot images */ + /* Secure library generic API functions */ PM_SECURE_SHA = 26, - PM_SECURE_RSA, - PM_PINCTRL_REQUEST, - PM_PINCTRL_RELEASE, - PM_PINCTRL_GET_FUNCTION, - PM_PINCTRL_SET_FUNCTION, - PM_PINCTRL_CONFIG_PARAM_GET, - PM_PINCTRL_CONFIG_PARAM_SET, - PM_IOCTL, - PM_QUERY_DATA, - PM_CLOCK_ENABLE, - PM_CLOCK_DISABLE, - PM_CLOCK_GETSTATE, - PM_CLOCK_SETDIVIDER, - PM_CLOCK_GETDIVIDER, - PM_CLOCK_SETRATE, - PM_CLOCK_GETRATE, - PM_CLOCK_SETPARENT, - PM_CLOCK_GETPARENT, - PM_SECURE_IMAGE, + PM_SECURE_RSA = 27, + PM_PINCTRL_REQUEST = 28, + PM_PINCTRL_RELEASE = 29, + PM_PINCTRL_GET_FUNCTION = 30, + PM_PINCTRL_SET_FUNCTION = 31, + PM_PINCTRL_CONFIG_PARAM_GET = 32, + PM_PINCTRL_CONFIG_PARAM_SET = 33, + PM_IOCTL = 34, + PM_QUERY_DATA = 35, + PM_CLOCK_ENABLE = 36, + PM_CLOCK_DISABLE = 37, + PM_CLOCK_GETSTATE = 38, + PM_CLOCK_SETDIVIDER = 39, + PM_CLOCK_GETDIVIDER = 40, + PM_CLOCK_SETRATE = 41, + PM_CLOCK_GETRATE = 42, + PM_CLOCK_SETPARENT = 43, + PM_CLOCK_GETPARENT = 44, + PM_SECURE_IMAGE = 45, PM_FPGA_READ = 46, - PM_SECURE_AES, + PM_SECURE_AES = 47, PM_CLOCK_PLL_GETPARAM = 49, + /* PM_REGISTER_ACCESS API */ PM_REGISTER_ACCESS = 52, - PM_EFUSE_ACCESS, + PM_EFUSE_ACCESS = 53, PM_FEATURE_CHECK = 63, PM_API_MAX, }; -- 2.32.0

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[PATCH v2 0/4] xilinx: zynqmp: Add support for dfu_alt_info setup at runtime
by Michal Simek 06 Aug '21

06 Aug '21

Hi, this series is just for composing dfu_alt_info string for capsule update to work automatically based on current setup. QSPI/MMC FAT bootmodes are handled and supported. Other bootmodes are ignored for now. Thanks, Michal Changes in v2: - no need to free local buf variable Michal Simek (4): xilinx: zynqmp: Change multi_boot() to return value xilinx: zynqmp: use zynqmp_mmio_read() in multi_boot() xilinx: zynqmp: Config non zero SYS_SPI_U_BOOT_OFFS xilinx: zynqmp: Add support for runtime dfu_alt_info setup board/xilinx/zynqmp/zynqmp.c | 67 +++++++++++++++++++++++++--- configs/xilinx_zynqmp_virt_defconfig | 2 + 2 files changed, 63 insertions(+), 6 deletions(-) -- 2.32.0

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