June 2021 - U-Boot

[PATCH v3 0/8] common: Introduce crypt-style password support
by Steffen Jaeckel 07 Jul '21

07 Jul '21

This patchset introduces support for crypt-style passwords to unlock the console in autoboot mode. The implementation of crypt-sha256 and crypt-sha512 originate from libxcrypt at https://github.com/besser82/libxcrypt.git Version v4.4.17 Git commit hash 6b110bc I didn't re-format those two files to make diffing to the original versions from libxcrypt easier, which leads to a huge load of checkpatch.pl warnings&errors. Please advise on whether they should be re-formatted or can be kept as is. The remaining warnings from checkpatch.pl are intentional resp. open for discussion. A sandbox defconfig with password entry has been added. I'm not sure whether this should be kept or not, it's just there as an example. Cheers, Steffen Changes in v3: Add unit-tests for autoboot Introduce `bootstopusesha256` to allow fallback to plain SHA256-based hashing Add AUTOBOOT_FLUSH_STDIN option Drop the changes to bcm963158_ram_defconfig Changes in v2: Update Kconfig way of enabling, setting hashes etc. Changes in v1: Added unit-tests of crypt_compare() Wrapped crypt functions to encapsulate errno Steffen Jaeckel (8): lib: add crypt subsystem lib: wrap crypt API to hide errno usage common: integrate crypt-based passwords common: Rename macro appropriately common: allow disabling of timeout for password entry common: add AUTOBOOT_FLUSH_STDIN option common: add support to fallback to plain SHA256 test: add first autoboot unit tests common/Kconfig.boot | 65 ++++++- common/autoboot.c | 135 ++++++++++++-- common/console.c | 5 + configs/sandbox_defconfig | 11 ++ include/console.h | 17 ++ include/crypt.h | 14 ++ include/test/common.h | 15 ++ include/test/suites.h | 1 + lib/Kconfig | 1 + lib/Makefile | 1 + lib/crypt/Kconfig | 28 +++ lib/crypt/Makefile | 10 ++ lib/crypt/alg-sha256.h | 11 ++ lib/crypt/alg-sha512.h | 11 ++ lib/crypt/crypt-port.h | 30 ++++ lib/crypt/crypt-sha256.c | 335 ++++++++++++++++++++++++++++++++++ lib/crypt/crypt-sha512.c | 350 ++++++++++++++++++++++++++++++++++++ lib/crypt/crypt.c | 76 ++++++++ test/Kconfig | 9 + test/Makefile | 1 + test/cmd_ut.c | 1 + test/common/Makefile | 3 + test/common/cmd_ut_common.c | 22 +++ test/common/test_autoboot.c | 90 ++++++++++ test/lib/Makefile | 1 + test/lib/test_crypt.c | 64 +++++++ 26 files changed, 1285 insertions(+), 22 deletions(-) create mode 100644 include/crypt.h create mode 100644 include/test/common.h create mode 100644 lib/crypt/Kconfig create mode 100644 lib/crypt/Makefile create mode 100644 lib/crypt/alg-sha256.h create mode 100644 lib/crypt/alg-sha512.h create mode 100644 lib/crypt/crypt-port.h create mode 100644 lib/crypt/crypt-sha256.c create mode 100644 lib/crypt/crypt-sha512.c create mode 100644 lib/crypt/crypt.c create mode 100644 test/common/Makefile create mode 100644 test/common/cmd_ut_common.c create mode 100644 test/common/test_autoboot.c create mode 100644 test/lib/test_crypt.c -- 2.31.1

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[U-Boot] [PATCH v3 00/20] Bring NAND support to Nintendo NES Classic
by Miquel Raynal 07 Jul '21

07 Jul '21

Hello, This series first adds fixes and enhancements to sunxi NAND drivers (SPL and U-Boot). Once this is done, the SPL NAND driver is converted to use PIO instead of DMA with the goal to support all SoCs with this IP without the need for DMA-related code. Finally, NAND support is added to Nintendo NES Classic through Kconfig and DT additions. Thanks, Miquèl Changes since v2: ================= - Added Boris and Maxime Acked-by tags. - Removed extra space in nand_reset_column() - Fixed the useless wait period on failure in nand_change_column(). - Changed the title "sunxi: allow NAND support to be compiled for..." (removed the "in SPL" precision which is wrong). - Enbraced the deassertion of the reset line by #if statements about the SoCs in use. Wolfgang Denk made a comment on my proposal but I could not find a better solution, so I kept it for now. - s/alwinner,[pin,functions]/[pin,functions]/ in the DT. - Change Alwinner-specific parts in the SPL to generic sentences. Changes since v1: ================= All: ---- - Enhance all commit messages. - Rebased on top of master branch (I should have done that earlier but I forgot I was on an old revision). Fix binman_sym output check --------------------------- - SPL seems to be broken for a few weeks when using raw NAND, fix it by changing the error condition. Fix strength ------------ - Add comment explaining the added line and moved the line for clarification on why it is needed. - Add forgotten Boris' Suggested-by tag. Fix second case of modulo by zero error ---------------------------------------- - Added a reference to the first occurence of this issue. Allow SPL to be compiled for sun8i platforms -------------------------------------------- - This commit is not about compiling the SPL, but the NAND support in the SPL, as corrected by Maxime. Enhancements and cleaning ------------------------- - Patch split into several logical chunks, as requested. - Removed useless udelay(1), that was added for debugging purpose. - Introduced the nand_exec_cmd() helper to mutualize code one step further. - Add an udelay(1) after changing the column to respect the minimum tCCS delay (Change Column Setup time). - Canceled moving to global scope the ecc_strength array. Use PIO instead of DMA ---------------------- - Change commit message/title. - Cancel removing NFC related definitions: they can be useful as the this IP is quite under-documented. - Merge nand_reset_column and nand_change_column (in another patch). - Moved the copy of the data after the check of the ECC status. - ECC chunks are read manually, return if the first chunk is empty only (needed for configuration research), otherwise it should not be treated as an error. Add NAND node to sun8i ---------------------- - U-Boot master branch already has this node, remove the patch. Enable NAND on NES classic -------------------------- - Change the DT cells size from 2 to 1. Add NAND support for NES classic -------------------------------- - Split in several patches, moving SPL_NAND_SUPPORT and NAND_SUNXI out of the defconfig files (NES and CHIP pro) to be automatically selected depending on NAND_SUNXI and ARCH_SUNXI. - Moved the NAND parameters to Kconfig (only for SUNXI because the tool did not work as expected, maybe due to some definitions that are not "numbers" but multiplications and sometimes use other definitions (NAND page size, 2K_SZ, etc). Miquel Raynal (20): spl: fix binman_sym output check mtd: nand: sunxi: fix ECC strength choice spl: nand: sunxi: fix second case of modulo by zero error spl: nand: sunxi: fix typo on register name spl: nand: sunxi: introduce the nand_wait_int() helper spl: nand: sunxi: introduce the nand_wait_cmd_fifo_empty() helper spl: nand: sunxi: add missing status clear spl: nand: sunxi: create an helper to handle command execution spl: nand: sunxi: ensure enough time has passed after changing the column spl: nand: sunxi: make the reset column helper more generic sunxi: spl: deassert the NAND controller reset line spl: nand: sunxi: declare the ecc_bytes array globally spl: nand: sunxi: use PIO instead of DMA sunxi: spl: remove DMA related settings of the NAND controller sunxi: allow NAND support to be compiled for sun8i platforms sunxi: dts: enable NAND on NES classic sunxi: automatically select SPL_NAND_SUPPORT in Kconfig sunxi: make NAND_SUNXI use ARCH_SUNXI as default in Kconfig sunxi: move the NAND parameters to Kconfig configs: add NAND support for NES Classic arch/arm/dts/sun8i-a23-a33.dtsi | 17 ++ .../dts/sun8i-r16-nintendo-nes-classic-edition.dts | 14 ++ arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 6 + board/sunxi/board.c | 7 +- common/spl/spl.c | 10 +- configs/CHIP_pro_defconfig | 6 +- configs/Nintendo_NES_Classic_Edition_defconfig | 4 + drivers/mtd/nand/Kconfig | 26 ++- drivers/mtd/nand/sunxi_nand.c | 8 +- drivers/mtd/nand/sunxi_nand_spl.c | 242 ++++++++++----------- 10 files changed, 208 insertions(+), 132 deletions(-) -- 2.14.1

5 31

[PATCH 1/1] efi_loader: improve block device integration with DM
by Heinrich Schuchardt 07 Jul '21

07 Jul '21

Up to now when devices became available after executing the UEFI sub-system initialization where not available for EFI applications. With the patch block devices are added to the UEFI object list whenever they are probed. Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- drivers/core/device.c | 7 +++ include/efi_loader.h | 6 +++ lib/efi_driver/Makefile | 1 + lib/efi_driver/efi_dm_integration.c | 36 +++++++++++++++ lib/efi_loader/efi_disk.c | 72 +++++++++++++++++------------ 5 files changed, 93 insertions(+), 29 deletions(-) create mode 100644 lib/efi_driver/efi_dm_integration.c diff --git a/drivers/core/device.c b/drivers/core/device.c index cb960f8ec4..7355a5c2a9 100644 --- a/drivers/core/device.c +++ b/drivers/core/device.c @@ -14,6 +14,7 @@ #include <asm/global_data.h> #include <asm/io.h> #include <clk.h> +#include <efi_loader.h> #include <fdtdec.h> #include <fdt_support.h> #include <malloc.h> @@ -579,6 +580,12 @@ int device_probe(struct udevice *dev) if (dev->parent && device_get_uclass_id(dev) == UCLASS_PINCTRL) pinctrl_select_state(dev, "default"); + if (CONFIG_IS_ENABLED(EFI_LOADER)) { + ret = efi_post_probe_device(dev); + if (ret) + goto fail_uclass; + } + return 0; fail_uclass: if (device_remove(dev, DM_REMOVE_NORMAL)) { diff --git a/include/efi_loader.h b/include/efi_loader.h index 0a9c82a257..78dd687913 100644 --- a/include/efi_loader.h +++ b/include/efi_loader.h @@ -17,6 +17,7 @@ #include <pe.h> struct blk_desc; +struct udevice; static inline int guidcmp(const void *g1, const void *g2) { @@ -28,6 +29,9 @@ static inline void *guidcpy(void *dst, const void *src) return memcpy(dst, src, sizeof(efi_guid_t)); } +/* Called by device_probe() */ +int efi_post_probe_device(struct udevice *dev); + /* No need for efi loader support in SPL */ #if CONFIG_IS_ENABLED(EFI_LOADER) @@ -420,6 +424,8 @@ efi_status_t EFIAPI efi_convert_pointer(efi_uintn_t debug_disposition, void efi_carve_out_dt_rsv(void *fdt); /* Called by bootefi to make console interface available */ efi_status_t efi_console_register(void); +/* Called when a block devices has been probed */ +efi_status_t efi_block_device_register(struct udevice *dev); /* Called by bootefi to make all disk storage accessible as EFI objects */ efi_status_t efi_disk_register(void); /* Called by efi_init_obj_list() to install EFI_RNG_PROTOCOL */ diff --git a/lib/efi_driver/Makefile b/lib/efi_driver/Makefile index 83baa1c9a4..f0d5fa5074 100644 --- a/lib/efi_driver/Makefile +++ b/lib/efi_driver/Makefile @@ -5,6 +5,7 @@ # This file only gets included with CONFIG_EFI_LOADER set, so all # object inclusion implicitly depends on it +obj-y += efi_dm_integration.o obj-y += efi_uclass.o ifeq ($(CONFIG_BLK)$(CONFIG_PARTITIONS),yy) obj-y += efi_block_device.o diff --git a/lib/efi_driver/efi_dm_integration.c b/lib/efi_driver/efi_dm_integration.c new file mode 100644 index 0000000000..9c6c339473 --- /dev/null +++ b/lib/efi_driver/efi_dm_integration.c @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2021, Heinrich Schuchardt <xypron.glpk(a)gmx.de> + */ + +#define LOG_CATEGORY LOGC_EFI + +#include <common.h> +#include <dm.h> +#include <efi_loader.h> +#include <log.h> + +/** + * efi_post_probe_device() - set up handle for probed device + * + * This function is called by device_probe(). After the UEFI sub-system is + * initialized this function adds handles for new devices. + * + * @dev: probed device + * Return: 0 on success + */ +int efi_post_probe_device(struct udevice *dev) +{ + if (!dev || !dev->uclass) + return -EINVAL; + + switch (dev->uclass->uc_drv->id) { + case UCLASS_BLK: + if (efi_block_device_register(dev) != EFI_SUCCESS) + log_err("Failed to register %s\n", dev->name); + default: + break; + } + + return 0; +} diff --git a/lib/efi_loader/efi_disk.c b/lib/efi_loader/efi_disk.c index 988907ecb9..b798cab345 100644 --- a/lib/efi_loader/efi_disk.c +++ b/lib/efi_loader/efi_disk.c @@ -10,6 +10,7 @@ #include <common.h> #include <blk.h> #include <dm.h> +#include <dm/device-internal.h> #include <efi_loader.h> #include <fs.h> #include <log.h> @@ -535,6 +536,41 @@ int efi_disk_create_partitions(efi_handle_t parent, struct blk_desc *desc, return disks; } +/** + * efi_block_device_register() - register a block device in the UEFI sub-system + * + * @dev: block device + * Return: status code + */ +efi_status_t efi_block_device_register(struct udevice *dev) +{ + struct blk_desc *desc = dev_get_uclass_plat(dev); + const char *if_typename = blk_get_if_type_name(desc->if_type); + struct efi_disk_obj *disk; + efi_status_t ret; + + /* Add block device for the full device */ + ret = device_probe(dev); + if (ret) + return EFI_NOT_FOUND; + log_info("Scanning disk %s...\n", dev->name); + ret = efi_disk_add_dev(NULL, NULL, if_typename, + desc, desc->devnum, NULL, 0, &disk); + if (ret == EFI_NOT_READY) { + log_notice("Disk %s not ready\n", dev->name); + return ret; + } else if (ret != EFI_SUCCESS) { + log_err("ERROR: failure to add disk device %s, r = %lu\n", + dev->name, ret & ~EFI_ERROR_MASK); + return ret; + } + + /* Partitions show up as block devices in EFI */ + efi_disk_create_partitions(&disk->header, desc, if_typename, + desc->devnum, dev->name); + return ret; +} + /** * efi_disk_register() - register block devices * @@ -552,38 +588,16 @@ int efi_disk_create_partitions(efi_handle_t parent, struct blk_desc *desc, */ efi_status_t efi_disk_register(void) { - struct efi_disk_obj *disk; - int disks = 0; - efi_status_t ret; #ifdef CONFIG_BLK struct udevice *dev; - + /* Probe all block devices */ for (uclass_first_device_check(UCLASS_BLK, &dev); dev; - uclass_next_device_check(&dev)) { - struct blk_desc *desc = dev_get_uclass_plat(dev); - const char *if_typename = blk_get_if_type_name(desc->if_type); - - /* Add block device for the full device */ - log_info("Scanning disk %s...\n", dev->name); - ret = efi_disk_add_dev(NULL, NULL, if_typename, - desc, desc->devnum, NULL, 0, &disk); - if (ret == EFI_NOT_READY) { - log_notice("Disk %s not ready\n", dev->name); - continue; - } - if (ret) { - log_err("ERROR: failure to add disk device %s, r = %lu\n", - dev->name, ret & ~EFI_ERROR_MASK); - return ret; - } - disks++; - - /* Partitions show up as block devices in EFI */ - disks += efi_disk_create_partitions( - &disk->header, desc, if_typename, - desc->devnum, dev->name); - } + uclass_next_device_check(&dev)) + ; #else + struct efi_disk_obj *disk; + int disks = 0; + efi_status_t ret; int i, if_type; /* Search for all available disk devices */ @@ -630,8 +644,8 @@ efi_status_t efi_disk_register(void) if_typename, i, devname); } } -#endif log_info("Found %d disks\n", disks); +#endif return EFI_SUCCESS; } -- 2.30.2

4 4

[PATCH] serial: serial_msm: Ensure BAM/single character mode are disabled
by Stephan Gerhold 07 Jul '21

07 Jul '21

At the moment, the U-Boot serial_msm driver does not initialize the UART_DM_DMEN register with the required value. Usually this does not cause any problems, because there is Qualcomm's LK bootloader running before U-Boot which initializes the register with the correct value. It's important that this register is initialized correctly, because the U-Boot driver does not make use of the BAM/DMA or single character mode functionality of the UART controller. A different bootloader before U-Boot might initialize the register differently. For example, on DragonBoard 410c U-Boot can also be installed to the "aboot" partition (replacing LK entirely). In this case U-Boot is loaded directly by SBL, which seems to use the single-character mode for some reason. In single character mode there is always just one char in the FIFO, instead of the 4 characters expected by msm_serial_fetch(). It also causes issues with "earlycon" later in the Linux kernel, which tries to output 4 chars at once, but only the first char will be written. This causes early UART log in Linux to be corrupted like this: [ 00ano:ameoi .Q1B[ 00ac _idaM00080oo'ahani-lcle._20). 15NdNii 5 SPMSJ20:U2 [ 00rkoolmsamel [ 00Fw ]elamletopsioble [ 00ore instead of [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd030] [ 0.000000] Machine model: Qualcomm Technologies, Inc. APQ 8016 SBC [ 0.000000] earlycon: msm_serial_dm0 at MMIO 0x00000000078b0000 (options '') [ 0.000000] printk: bootconsole [msm_serial_dm0] enabled Make sure to initialize UART_DM_DMEN correctly to fix this issue when loading U-Boot directly after SBL (instead of through LK). There is no functional difference when loading U-Boot through LK since LK also initializes UART_DM_DMEN to 0x0. [1] [1]: https://git.linaro.org/landing-teams/working/qualcomm/lk.git/tree/platform/… Cc: Ramon Fried <rfried.dev(a)gmail.com> Signed-off-by: Stephan Gerhold <stephan(a)gerhold.net> --- drivers/serial/serial_msm.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/serial/serial_msm.c b/drivers/serial/serial_msm.c index d8c6c2f6b5..d8dd5c1104 100644 --- a/drivers/serial/serial_msm.c +++ b/drivers/serial/serial_msm.c @@ -23,6 +23,7 @@ /* Serial registers - this driver works in uartdm mode*/ #define UARTDM_DMRX 0x34 /* Max RX transfer length */ +#define UARTDM_DMEN 0x3C /* DMA/data-packing mode */ #define UARTDM_NCF_TX 0x40 /* Number of chars to TX */ #define UARTDM_RXFS 0x50 /* RX channel status register */ @@ -197,6 +198,9 @@ static void uart_dm_init(struct msm_serial_data *priv) writel(MSM_BOOT_UART_DM_8_N_1_MODE, priv->base + UARTDM_MR2); writel(MSM_BOOT_UART_DM_CMD_RESET_RX, priv->base + UARTDM_CR); writel(MSM_BOOT_UART_DM_CMD_RESET_TX, priv->base + UARTDM_CR); + + /* Make sure BAM/single character mode is disabled */ + writel(0x0, priv->base + UARTDM_DMEN); } static int msm_serial_probe(struct udevice *dev) { -- 2.32.0

3 9

[PATCH] arm: dts: db410c: Add missing cd-gpios for SD card detection
by Stephan Gerhold 07 Jul '21

07 Jul '21

It looks like SD card detection is broken at the moment for DB410c. The eMMC is detected correctly, but the SD card is not. This is probably similar to the issue fixed in commit 850514740358 ("mmc: msm_sdhci: Use mmc_of_parse for setting host_caps") for eMMC, except that the SD card does not have a property like "non-removable" that skips the card detection. The SDHCI on DB410c cannot detect itself if a SD card is inserted, so add the necessary cd-gpios to make SD card detection work again. While at it, fix the #gpio-cells for the soc_gpios to avoid DTC warnings - the soc_gpios are actually already used with two cells for the gpio-leds so this was just wrong all the time. Cc: Ramon Fried <rfried.dev(a)gmail.com> Signed-off-by: Stephan Gerhold <stephan(a)gerhold.net> --- arch/arm/dts/dragonboard410c.dts | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/dragonboard410c.dts b/arch/arm/dts/dragonboard410c.dts index fa348bc621..7e56140df2 100644 --- a/arch/arm/dts/dragonboard410c.dts +++ b/arch/arm/dts/dragonboard410c.dts @@ -8,6 +8,7 @@ /dts-v1/; #include "skeleton64.dtsi" +#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/pinctrl/pinctrl-snapdragon.h> / { @@ -91,7 +92,7 @@ gpio-controller; gpio-count = <122>; gpio-bank-name="soc"; - #gpio-cells = <1>; + #gpio-cells = <2>; }; ehci@78d9000 { @@ -123,6 +124,7 @@ bus-width = <0x4>; clock = <&clkc 1>; clock-frequency = <200000000>; + cd-gpios = <&soc_gpios 38 GPIO_ACTIVE_LOW>; }; wcnss { -- 2.32.0

3 2

[PATCH 1/2] arm: snapdragon: Use correct GICC register on APQ8016
by Sheep Sun 07 Jul '21

07 Jul '21

The GICC register used by u-boot is 0x0a20c000, which is actually a GICC for WCNSS, the WLAN processor. U-boot runs on the Application Processor, therefore it should use APCS GICC instead. Hence, correct it with APCS GICC register address. Signed-off-by: Sheep Sun <sunxiaoyang2003(a)gmail.com> --- arch/arm/mach-snapdragon/include/mach/sysmap-apq8016.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-snapdragon/include/mach/sysmap-apq8016.h b/arch/arm/mach-snapdragon/include/mach/sysmap-apq8016.h index 520e2e6bd7..d9a3b1af98 100644 --- a/arch/arm/mach-snapdragon/include/mach/sysmap-apq8016.h +++ b/arch/arm/mach-snapdragon/include/mach/sysmap-apq8016.h @@ -8,7 +8,7 @@ #define _MACH_SYSMAP_APQ8016_H #define GICD_BASE (0x0b000000) -#define GICC_BASE (0x0a20c000) +#define GICC_BASE (0x0b002000) /* Clocks: (from CLK_CTL_BASE) */ #define GPLL0_STATUS (0x2101C) -- 2.30.2

2 3

[PATCH v2 1/8] lpc32xx: Kconfig: switch to CONFIG_CONS_INDEX
by Trevor Woerner 07 Jul '21

07 Jul '21

There's nothing special or unique to the lpc32xx that requires its own config parameter for specifying the console uart index. Therefore instead of using the lpc32xx-specific CONFIG_SYS_LPC32XX_UART include parameter, use the already-available CONFIG_CONS_INDEX from Kconfig. Signed-off-by: Trevor Woerner <twoerner(a)gmail.com> --- (no changes since v1) arch/arm/include/asm/arch-lpc32xx/config.h | 4 ++-- arch/arm/mach-lpc32xx/devices.c | 3 +-- board/timll/devkit3250/devkit3250.c | 2 +- board/timll/devkit3250/devkit3250_spl.c | 2 +- board/work-microwave/work_92105/work_92105.c | 2 +- board/work-microwave/work_92105/work_92105_spl.c | 2 +- configs/devkit3250_defconfig | 2 ++ configs/work_92105_defconfig | 2 ++ include/configs/devkit3250.h | 5 ----- include/configs/work_92105.h | 5 ----- scripts/config_whitelist.txt | 1 - 11 files changed, 11 insertions(+), 19 deletions(-) diff --git a/arch/arm/include/asm/arch-lpc32xx/config.h b/arch/arm/include/asm/arch-lpc32xx/config.h index 0836091af2..45e46f9946 100644 --- a/arch/arm/include/asm/arch-lpc32xx/config.h +++ b/arch/arm/include/asm/arch-lpc32xx/config.h @@ -12,8 +12,8 @@ /* Basic CPU architecture */ /* UART configuration */ -#if (CONFIG_SYS_LPC32XX_UART == 1) || (CONFIG_SYS_LPC32XX_UART == 2) || \ - (CONFIG_SYS_LPC32XX_UART == 7) +#if (CONFIG_CONS_INDEX == 1) || (CONFIG_CONS_INDEX == 2) || \ + (CONFIG_CONS_INDEX == 7) #if !defined(CONFIG_LPC32XX_HSUART) #define CONFIG_LPC32XX_HSUART #endif diff --git a/arch/arm/mach-lpc32xx/devices.c b/arch/arm/mach-lpc32xx/devices.c index e1e2e0d094..0a4fef295a 100644 --- a/arch/arm/mach-lpc32xx/devices.c +++ b/arch/arm/mach-lpc32xx/devices.c @@ -23,8 +23,7 @@ void lpc32xx_uart_init(unsigned int uart_id) return; /* Disable loopback mode, if it is set by S1L bootloader */ - clrbits_le32(&ctrl->loop, - UART_LOOPBACK(CONFIG_SYS_LPC32XX_UART)); + clrbits_le32(&ctrl->loop, UART_LOOPBACK(uart_id)); if (uart_id < 3 || uart_id > 6) return; diff --git a/board/timll/devkit3250/devkit3250.c b/board/timll/devkit3250/devkit3250.c index 3c744b943f..9d4ffb0f97 100644 --- a/board/timll/devkit3250/devkit3250.c +++ b/board/timll/devkit3250/devkit3250.c @@ -38,7 +38,7 @@ void reset_periph(void) int board_early_init_f(void) { - lpc32xx_uart_init(CONFIG_SYS_LPC32XX_UART); + lpc32xx_uart_init(CONFIG_CONS_INDEX); lpc32xx_i2c_init(1); lpc32xx_i2c_init(2); lpc32xx_ssp_init(); diff --git a/board/timll/devkit3250/devkit3250_spl.c b/board/timll/devkit3250/devkit3250_spl.c index 47af78ae0b..12e8ae9c39 100644 --- a/board/timll/devkit3250/devkit3250_spl.c +++ b/board/timll/devkit3250/devkit3250_spl.c @@ -49,7 +49,7 @@ void spl_board_init(void) /* First of all silence buzzer controlled by GPO_20 */ writel((1 << 20), &gpio->p3_outp_clr); - lpc32xx_uart_init(CONFIG_SYS_LPC32XX_UART); + lpc32xx_uart_init(CONFIG_CONS_INDEX); preloader_console_init(); ddr_init(&dram_64mb); diff --git a/board/work-microwave/work_92105/work_92105.c b/board/work-microwave/work_92105/work_92105.c index bdcecff730..5d12f84cfe 100644 --- a/board/work-microwave/work_92105/work_92105.c +++ b/board/work-microwave/work_92105/work_92105.c @@ -37,7 +37,7 @@ void reset_periph(void) int board_early_init_f(void) { /* initialize serial port for console */ - lpc32xx_uart_init(CONFIG_SYS_LPC32XX_UART); + lpc32xx_uart_init(CONFIG_CONS_INDEX); /* enable I2C, SSP, MAC, NAND */ lpc32xx_i2c_init(1); /* only I2C1 has devices, I2C2 has none */ lpc32xx_ssp_init(); diff --git a/board/work-microwave/work_92105/work_92105_spl.c b/board/work-microwave/work_92105/work_92105_spl.c index a31553a2d2..d9401145f2 100644 --- a/board/work-microwave/work_92105/work_92105_spl.c +++ b/board/work-microwave/work_92105/work_92105_spl.c @@ -58,7 +58,7 @@ const struct emc_dram_settings dram_128mb = { void spl_board_init(void) { /* initialize serial port for console */ - lpc32xx_uart_init(CONFIG_SYS_LPC32XX_UART); + lpc32xx_uart_init(CONFIG_CONS_INDEX); /* initialize console */ preloader_console_init(); /* init DDR and NAND to chainload U-Boot */ diff --git a/configs/devkit3250_defconfig b/configs/devkit3250_defconfig index 93c048cee8..9ae70f7d46 100644 --- a/configs/devkit3250_defconfig +++ b/configs/devkit3250_defconfig @@ -51,6 +51,8 @@ CONFIG_PHYLIB=y CONFIG_PHY_ADDR_ENABLE=y CONFIG_PHY_ADDR=31 CONFIG_PHY_SMSC=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_CONS_INDEX=5 CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_USB=y diff --git a/configs/work_92105_defconfig b/configs/work_92105_defconfig index c3f666dcfe..e9605adedd 100644 --- a/configs/work_92105_defconfig +++ b/configs/work_92105_defconfig @@ -48,5 +48,7 @@ CONFIG_MTD_RAW_NAND=y CONFIG_PHYLIB=y CONFIG_PHY_ADDR_ENABLE=y CONFIG_PHY_SMSC=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_CONS_INDEX=5 CONFIG_SYS_NS16550=y CONFIG_SPI=y diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h index 5d2b77b4a3..921a38c01e 100644 --- a/include/configs/devkit3250.h +++ b/include/configs/devkit3250.h @@ -30,11 +30,6 @@ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_4K \ - GENERATED_GBL_DATA_SIZE) -/* - * Serial Driver - */ -#define CONFIG_SYS_LPC32XX_UART 5 /* UART5 */ - /* * DMA */ diff --git a/include/configs/work_92105.h b/include/configs/work_92105.h index 7874b77f3f..076a1b065e 100644 --- a/include/configs/work_92105.h +++ b/include/configs/work_92105.h @@ -35,11 +35,6 @@ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_512K \ - GENERATED_GBL_DATA_SIZE) -/* - * Serial Driver - */ -#define CONFIG_SYS_LPC32XX_UART 5 /* UART5 - NS16550 */ - /* * Ethernet Driver */ diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 0f5ac8ff52..13281bf6b1 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -2735,7 +2735,6 @@ CONFIG_SYS_LOW CONFIG_SYS_LOWMEM_BASE CONFIG_SYS_LOW_RES_TIMER CONFIG_SYS_LPAE_SDRAM_BASE -CONFIG_SYS_LPC32XX_UART CONFIG_SYS_LS1_DDR_BLOCK1_SIZE CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS -- 2.30.0.rc0

3 10

[PATCH] arm: iproc: Add higher speed configurations
by Chris Packham 07 Jul '21

07 Jul '21

Add support for 1.3GHz, 1.35GHz and 1.4GHz parts. This is based on equivalent code in Broadcom's LDK 5.0.6. Signed-off-by: Chris Packham <judge.packham(a)gmail.com> --- As Broadcom are currently migrating users to the BCM58525BB1KF14G part I suspect others may want this. In our case because we wanted to still run at 1.2GHz we also had to set CONFIG_ARMCLK to 1200. arch/arm/cpu/armv7/iproc-common/armpll.c | 29 +++++++++++++----------- 1 file changed, 16 insertions(+), 13 deletions(-) diff --git a/arch/arm/cpu/armv7/iproc-common/armpll.c b/arch/arm/cpu/armv7/iproc-common/armpll.c index efa3d9e5a9bd..8c3a323f0654 100644 --- a/arch/arm/cpu/armv7/iproc-common/armpll.c +++ b/arch/arm/cpu/armv7/iproc-common/armpll.c @@ -19,19 +19,22 @@ struct armpll_parameters { }; struct armpll_parameters armpll_clk_tab[] = { - { 25, 64, 1, 1, 0}, - { 100, 64, 1, 1, 2}, - { 400, 64, 1, 1, 6}, - { 448, 71, 713050, 1, 6}, - { 500, 80, 1, 1, 6}, - { 560, 89, 629145, 1, 6}, - { 600, 96, 1, 1, 6}, - { 800, 64, 1, 1, 7}, - { 896, 71, 713050, 1, 7}, - { 1000, 80, 1, 1, 7}, - { 1100, 88, 1, 1, 7}, - { 1120, 89, 629145, 1, 7}, - { 1200, 96, 1, 1, 7}, + { 25, 64, 1, 1, 0}, + { 100, 64, 1, 1, 2}, + { 400, 64, 1, 1, 6}, + { 448, 71, 713050, 1, 6}, + { 500, 80, 1, 1, 6}, + { 560, 89, 629145, 1, 6}, + { 600, 96, 1, 1, 6}, + { 800, 64, 1, 1, 7}, + { 896, 71, 713050, 1, 7}, + { 1000, 80, 1, 1, 7}, + { 1100, 88, 1, 1, 7}, + { 1120, 89, 629145, 1, 7}, + { 1200, 96, 1, 1, 7}, + { 1300, 104, 1, 1, 7}, + { 1350, 108, 1, 1, 7}, + { 1400, 112, 1, 1, 7}, }; uint32_t armpll_config(uint32_t clkmhz) -- 2.31.1

2 4

[PATCH] ARM: integrator: Drop PCI support
by Linus Walleij 07 Jul '21

07 Jul '21

We didn't convert the Integrator to use DM for PCI in time, and we don't use it either so let's just drop PCI support from the Integrator. Signed-off-by: Linus Walleij <linus.walleij(a)linaro.org> --- board/armltd/integrator/Makefile | 1 - board/armltd/integrator/integrator.c | 1 - board/armltd/integrator/pci.c | 462 ------------------------ board/armltd/integrator/pci_v3.h | 187 ---------- configs/integratorap_cm720t_defconfig | 4 - configs/integratorap_cm920t_defconfig | 4 - configs/integratorap_cm926ejs_defconfig | 4 - configs/integratorap_cm946es_defconfig | 4 - 8 files changed, 667 deletions(-) delete mode 100644 board/armltd/integrator/pci.c delete mode 100644 board/armltd/integrator/pci_v3.h diff --git a/board/armltd/integrator/Makefile b/board/armltd/integrator/Makefile index 8c906e3f072b..107e59bf0fa2 100644 --- a/board/armltd/integrator/Makefile +++ b/board/armltd/integrator/Makefile @@ -10,5 +10,4 @@ obj-y := lowlevel_init.o obj-y += integrator.o -obj-$(CONFIG_PCI) += pci.o obj-y += timer.o diff --git a/board/armltd/integrator/integrator.c b/board/armltd/integrator/integrator.c index 3e864e8e7a5c..388795809dfd 100644 --- a/board/armltd/integrator/integrator.c +++ b/board/armltd/integrator/integrator.c @@ -181,7 +181,6 @@ int board_eth_init(struct bd_info *bis) #ifdef CONFIG_SMC91111 rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); #endif - rc += pci_eth_init(bis); return rc; } #endif diff --git a/board/armltd/integrator/pci.c b/board/armltd/integrator/pci.c deleted file mode 100644 index 28efc33f1f42..000000000000 --- a/board/armltd/integrator/pci.c +++ /dev/null @@ -1,462 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger(a)sysgo.de> - * - * (C) Copyright 2002 - * David Mueller, ELSOFT AG, <d.mueller(a)elsoft.ch> - * - * (C) Copyright 2003 - * Texas Instruments, <www.ti.com> - * Kshitij Gupta <Kshitij(a)ti.com> - * - * (C) Copyright 2004 - * ARM Ltd. - * Philippe Robin, <philippe.robin(a)arm.com> - * - * (C) Copyright 2011 - * Linaro - * Linus Walleij <linus.walleij(a)linaro.org> - */ -#include <common.h> -#include <init.h> -#include <log.h> -#include <pci.h> -#include <asm/io.h> -#include <linux/bug.h> -#include <linux/delay.h> -#include "integrator-sc.h" -#include "pci_v3.h" - -#define INTEGRATOR_BOOT_ROM_BASE 0x20000000 -#define INTEGRATOR_HDR0_SDRAM_BASE 0x80000000 - -/* - * These are in the physical addresses on the CPU side, i.e. - * where we read and write stuff - you don't want to try to - * move these around - */ -#define PHYS_PCI_MEM_BASE 0x40000000 -#define PHYS_PCI_IO_BASE 0x60000000 /* PCI I/O space base */ -#define PHYS_PCI_CONFIG_BASE 0x61000000 -#define PHYS_PCI_V3_BASE 0x62000000 /* V360EPC registers */ -#define SZ_256M 0x10000000 - -/* - * These are in the PCI BUS address space - * Set to 0x00000000 in the Linux kernel, 0x40000000 in Boot monitor - * we follow the example of the kernel, because that is the address - * range that devices actually use - what would they be doing at - * 0x40000000? - */ -#define PCI_BUS_NONMEM_START 0x00000000 -#define PCI_BUS_NONMEM_SIZE SZ_256M - -#define PCI_BUS_PREMEM_START (PCI_BUS_NONMEM_START + PCI_BUS_NONMEM_SIZE) -#define PCI_BUS_PREMEM_SIZE SZ_256M - -#if PCI_BUS_NONMEM_START & 0x000fffff -#error PCI_BUS_NONMEM_START must be megabyte aligned -#endif -#if PCI_BUS_PREMEM_START & 0x000fffff -#error PCI_BUS_PREMEM_START must be megabyte aligned -#endif - -/* - * Initialize PCI Devices, report devices found. - */ - -#ifndef CONFIG_PCI_PNP -#define PCI_ENET0_IOADDR 0x60000000 /* First card in PCI I/O space */ -#define PCI_ENET0_MEMADDR 0x40000000 /* First card in PCI memory space */ -static struct pci_config_table pci_integrator_config_table[] = { - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID, - pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }}, - { } -}; -#endif /* CONFIG_PCI_PNP */ - -/* V3 access routines */ -#define v3_writeb(o, v) __raw_writeb(v, PHYS_PCI_V3_BASE + (unsigned int)(o)) -#define v3_readb(o) (__raw_readb(PHYS_PCI_V3_BASE + (unsigned int)(o))) - -#define v3_writew(o, v) __raw_writew(v, PHYS_PCI_V3_BASE + (unsigned int)(o)) -#define v3_readw(o) (__raw_readw(PHYS_PCI_V3_BASE + (unsigned int)(o))) - -#define v3_writel(o, v) __raw_writel(v, PHYS_PCI_V3_BASE + (unsigned int)(o)) -#define v3_readl(o) (__raw_readl(PHYS_PCI_V3_BASE + (unsigned int)(o))) - -static unsigned long v3_open_config_window(pci_dev_t bdf, int offset) -{ - unsigned int address, mapaddress; - unsigned int busnr = PCI_BUS(bdf); - unsigned int devfn = PCI_FUNC(bdf); - - /* - * Trap out illegal values - */ - if (offset > 255) - BUG(); - if (busnr > 255) - BUG(); - if (devfn > 255) - BUG(); - - if (busnr == 0) { - /* - * Linux calls the thing U-Boot calls "DEV" "SLOT" - * instead, but it's the same 5 bits - */ - int slot = PCI_DEV(bdf); - - /* - * local bus segment so need a type 0 config cycle - * - * build the PCI configuration "address" with one-hot in - * A31-A11 - * - * mapaddress: - * 3:1 = config cycle (101) - * 0 = PCI A1 & A0 are 0 (0) - */ - address = PCI_FUNC(bdf) << 8; - mapaddress = V3_LB_MAP_TYPE_CONFIG; - - if (slot > 12) - /* - * high order bits are handled by the MAP register - */ - mapaddress |= 1 << (slot - 5); - else - /* - * low order bits handled directly in the address - */ - address |= 1 << (slot + 11); - } else { - /* - * not the local bus segment so need a type 1 config cycle - * - * address: - * 23:16 = bus number - * 15:11 = slot number (7:3 of devfn) - * 10:8 = func number (2:0 of devfn) - * - * mapaddress: - * 3:1 = config cycle (101) - * 0 = PCI A1 & A0 from host bus (1) - */ - mapaddress = V3_LB_MAP_TYPE_CONFIG | V3_LB_MAP_AD_LOW_EN; - address = (busnr << 16) | (devfn << 8); - } - - /* - * Set up base0 to see all 512Mbytes of memory space (not - * prefetchable), this frees up base1 for re-use by - * configuration memory - */ - v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) | - V3_LB_BASE_ADR_SIZE_512MB | V3_LB_BASE_ENABLE); - - /* - * Set up base1/map1 to point into configuration space. - */ - v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_CONFIG_BASE) | - V3_LB_BASE_ADR_SIZE_16MB | V3_LB_BASE_ENABLE); - v3_writew(V3_LB_MAP1, mapaddress); - - return PHYS_PCI_CONFIG_BASE + address + offset; -} - -static void v3_close_config_window(void) -{ - /* - * Reassign base1 for use by prefetchable PCI memory - */ - v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE + SZ_256M) | - V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH | - V3_LB_BASE_ENABLE); - v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(PCI_BUS_PREMEM_START) | - V3_LB_MAP_TYPE_MEM_MULTIPLE); - - /* - * And shrink base0 back to a 256M window (NOTE: MAP0 already correct) - */ - v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) | - V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE); -} - -static int pci_integrator_read_byte(struct pci_controller *hose, pci_dev_t bdf, - int offset, unsigned char *val) -{ - unsigned long addr; - - addr = v3_open_config_window(bdf, offset); - *val = __raw_readb(addr); - v3_close_config_window(); - return 0; -} - -static int pci_integrator_read__word(struct pci_controller *hose, - pci_dev_t bdf, int offset, - unsigned short *val) -{ - unsigned long addr; - - addr = v3_open_config_window(bdf, offset); - *val = __raw_readw(addr); - v3_close_config_window(); - return 0; -} - -static int pci_integrator_read_dword(struct pci_controller *hose, - pci_dev_t bdf, int offset, - unsigned int *val) -{ - unsigned long addr; - - addr = v3_open_config_window(bdf, offset); - *val = __raw_readl(addr); - v3_close_config_window(); - return 0; -} - -static int pci_integrator_write_byte(struct pci_controller *hose, - pci_dev_t bdf, int offset, - unsigned char val) -{ - unsigned long addr; - - addr = v3_open_config_window(bdf, offset); - __raw_writeb((u8)val, addr); - __raw_readb(addr); - v3_close_config_window(); - return 0; -} - -static int pci_integrator_write_word(struct pci_controller *hose, - pci_dev_t bdf, int offset, - unsigned short val) -{ - unsigned long addr; - - addr = v3_open_config_window(bdf, offset); - __raw_writew((u8)val, addr); - __raw_readw(addr); - v3_close_config_window(); - return 0; -} - -static int pci_integrator_write_dword(struct pci_controller *hose, - pci_dev_t bdf, int offset, - unsigned int val) -{ - unsigned long addr; - - addr = v3_open_config_window(bdf, offset); - __raw_writel((u8)val, addr); - __raw_readl(addr); - v3_close_config_window(); - return 0; -} - -struct pci_controller integrator_hose = { -#ifndef CONFIG_PCI_PNP - config_table: pci_integrator_config_table, -#endif -}; - -void pci_init_board(void) -{ - struct pci_controller *hose = &integrator_hose; - u16 val; - - /* setting this register will take the V3 out of reset */ - __raw_writel(SC_PCI_PCIEN, SC_PCI); - - /* Wait for 230 ms (from spec) before accessing any V3 registers */ - mdelay(230); - - /* Now write the Base I/O Address Word to PHYS_PCI_V3_BASE + 0x6E */ - v3_writew(V3_LB_IO_BASE, (PHYS_PCI_V3_BASE >> 16)); - - /* Wait for the mailbox to settle */ - do { - v3_writeb(V3_MAIL_DATA, 0xAA); - v3_writeb(V3_MAIL_DATA + 4, 0x55); - } while (v3_readb(V3_MAIL_DATA) != 0xAA || - v3_readb(V3_MAIL_DATA + 4) != 0x55); - - /* Make sure that V3 register access is not locked, if it is, unlock it */ - if (v3_readw(V3_SYSTEM) & V3_SYSTEM_M_LOCK) - v3_writew(V3_SYSTEM, 0xA05F); - - /* - * Ensure that the slave accesses from PCI are disabled while we - * setup memory windows - */ - val = v3_readw(V3_PCI_CMD); - val &= ~(V3_COMMAND_M_MEM_EN | V3_COMMAND_M_IO_EN); - v3_writew(V3_PCI_CMD, val); - - /* Clear RST_OUT to 0; keep the PCI bus in reset until we've finished */ - val = v3_readw(V3_SYSTEM); - val &= ~V3_SYSTEM_M_RST_OUT; - v3_writew(V3_SYSTEM, val); - - /* Make all accesses from PCI space retry until we're ready for them */ - val = v3_readw(V3_PCI_CFG); - val |= V3_PCI_CFG_M_RETRY_EN; - v3_writew(V3_PCI_CFG, val); - - /* - * Set up any V3 PCI Configuration Registers that we absolutely have to. - * LB_CFG controls Local Bus protocol. - * Enable LocalBus byte strobes for READ accesses too. - * set bit 7 BE_IMODE and bit 6 BE_OMODE - */ - val = v3_readw(V3_LB_CFG); - val |= 0x0C0; - v3_writew(V3_LB_CFG, val); - - /* PCI_CMD controls overall PCI operation. Enable PCI bus master. */ - val = v3_readw(V3_PCI_CMD); - val |= V3_COMMAND_M_MASTER_EN; - v3_writew(V3_PCI_CMD, val); - - /* - * PCI_MAP0 controls where the PCI to CPU memory window is on - * Local Bus - */ - v3_writel(V3_PCI_MAP0, - (INTEGRATOR_BOOT_ROM_BASE) | (V3_PCI_MAP_M_ADR_SIZE_512MB | - V3_PCI_MAP_M_REG_EN | - V3_PCI_MAP_M_ENABLE)); - - /* PCI_BASE0 is the PCI address of the start of the window */ - v3_writel(V3_PCI_BASE0, INTEGRATOR_BOOT_ROM_BASE); - - /* PCI_MAP1 is LOCAL address of the start of the window */ - v3_writel(V3_PCI_MAP1, - (INTEGRATOR_HDR0_SDRAM_BASE) | (V3_PCI_MAP_M_ADR_SIZE_1GB | - V3_PCI_MAP_M_REG_EN | - V3_PCI_MAP_M_ENABLE)); - - /* PCI_BASE1 is the PCI address of the start of the window */ - v3_writel(V3_PCI_BASE1, INTEGRATOR_HDR0_SDRAM_BASE); - - /* - * Set up memory the windows from local bus memory into PCI - * configuration, I/O and Memory regions. - * PCI I/O, LB_BASE2 and LB_MAP2 are used exclusively for this. - */ - v3_writew(V3_LB_BASE2, - v3_addr_to_lb_map(PHYS_PCI_IO_BASE) | V3_LB_BASE_ENABLE); - v3_writew(V3_LB_MAP2, 0); - - /* PCI Configuration, use LB_BASE1/LB_MAP1. */ - - /* - * PCI Memory use LB_BASE0/LB_MAP0 and LB_BASE1/LB_MAP1 - * Map first 256Mbytes as non-prefetchable via BASE0/MAP0 - */ - v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) | - V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE); - v3_writew(V3_LB_MAP0, - v3_addr_to_lb_map(PCI_BUS_NONMEM_START) | V3_LB_MAP_TYPE_MEM); - - /* Map second 256 Mbytes as prefetchable via BASE1/MAP1 */ - v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE + SZ_256M) | - V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH | - V3_LB_BASE_ENABLE); - v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(PCI_BUS_PREMEM_START) | - V3_LB_MAP_TYPE_MEM_MULTIPLE); - - /* Dump PCI to local address space mappings */ - debug("LB_BASE0 = %08x\n", v3_readl(V3_LB_BASE0)); - debug("LB_MAP0 = %04x\n", v3_readw(V3_LB_MAP0)); - debug("LB_BASE1 = %08x\n", v3_readl(V3_LB_BASE1)); - debug("LB_MAP1 = %04x\n", v3_readw(V3_LB_MAP1)); - debug("LB_BASE2 = %04x\n", v3_readw(V3_LB_BASE2)); - debug("LB_MAP2 = %04x\n", v3_readw(V3_LB_MAP2)); - debug("LB_IO_BASE = %04x\n", v3_readw(V3_LB_IO_BASE)); - - /* - * Allow accesses to PCI Configuration space and set up A1, A0 for - * type 1 config cycles - */ - val = v3_readw(V3_PCI_CFG); - val &= ~(V3_PCI_CFG_M_RETRY_EN | V3_PCI_CFG_M_AD_LOW1); - val |= V3_PCI_CFG_M_AD_LOW0; - v3_writew(V3_PCI_CFG, val); - - /* now we can allow incoming PCI MEMORY accesses */ - val = v3_readw(V3_PCI_CMD); - val |= V3_COMMAND_M_MEM_EN; - v3_writew(V3_PCI_CMD, val); - - /* - * Set RST_OUT to take the PCI bus is out of reset, PCI devices can - * now initialise. - */ - val = v3_readw(V3_SYSTEM); - val |= V3_SYSTEM_M_RST_OUT; - v3_writew(V3_SYSTEM, val); - - /* Lock the V3 system register so that no one else can play with it */ - val = v3_readw(V3_SYSTEM); - val |= V3_SYSTEM_M_LOCK; - v3_writew(V3_SYSTEM, val); - - /* - * Configure and register the PCI hose - */ - hose->first_busno = 0; - hose->last_busno = 0xff; - - /* System memory space, window 0 256 MB non-prefetchable */ - pci_set_region(hose->regions + 0, - PCI_BUS_NONMEM_START, PHYS_PCI_MEM_BASE, - SZ_256M, - PCI_REGION_MEM); - - /* System memory space, window 1 256 MB prefetchable */ - pci_set_region(hose->regions + 1, - PCI_BUS_PREMEM_START, PHYS_PCI_MEM_BASE + SZ_256M, - SZ_256M, - PCI_REGION_MEM | - PCI_REGION_PREFETCH); - - /* PCI I/O space */ - pci_set_region(hose->regions + 2, - 0x00000000, PHYS_PCI_IO_BASE, 0x01000000, - PCI_REGION_IO); - - /* PCI Memory - config space */ - pci_set_region(hose->regions + 3, - 0x00000000, PHYS_PCI_CONFIG_BASE, 0x01000000, - PCI_REGION_MEM); - /* PCI V3 regs */ - pci_set_region(hose->regions + 4, - 0x00000000, PHYS_PCI_V3_BASE, 0x01000000, - PCI_REGION_MEM); - - hose->region_count = 5; - - pci_set_ops(hose, - pci_integrator_read_byte, - pci_integrator_read__word, - pci_integrator_read_dword, - pci_integrator_write_byte, - pci_integrator_write_word, - pci_integrator_write_dword); - - pci_register_hose(hose); - - pciauto_config_init(hose); - pciauto_config_device(hose, 0); - - hose->last_busno = pci_hose_scan(hose); -} diff --git a/board/armltd/integrator/pci_v3.h b/board/armltd/integrator/pci_v3.h deleted file mode 100644 index 8d09e6966db2..000000000000 --- a/board/armltd/integrator/pci_v3.h +++ /dev/null @@ -1,187 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * arch/arm/include/asm/hardware/pci_v3.h - * - * Internal header file PCI V3 chip - * - * Copyright (C) ARM Limited - * Copyright (C) 2000-2001 Deep Blue Solutions Ltd. - */ -#ifndef ASM_ARM_HARDWARE_PCI_V3_H -#define ASM_ARM_HARDWARE_PCI_V3_H - -/* ------------------------------------------------------------------------------- - * V3 Local Bus to PCI Bridge definitions - * ------------------------------------------------------------------------------- - * Registers (these are taken from page 129 of the EPC User's Manual Rev 1.04 - * All V3 register names are prefaced by V3_ to avoid clashing with any other - * PCI definitions. Their names match the user's manual. - * - * I'm assuming that I20 is disabled. - * - */ -#define V3_PCI_VENDOR 0x00000000 -#define V3_PCI_DEVICE 0x00000002 -#define V3_PCI_CMD 0x00000004 -#define V3_PCI_STAT 0x00000006 -#define V3_PCI_CC_REV 0x00000008 -#define V3_PCI_HDR_CFG 0x0000000C -#define V3_PCI_IO_BASE 0x00000010 -#define V3_PCI_BASE0 0x00000014 -#define V3_PCI_BASE1 0x00000018 -#define V3_PCI_SUB_VENDOR 0x0000002C -#define V3_PCI_SUB_ID 0x0000002E -#define V3_PCI_ROM 0x00000030 -#define V3_PCI_BPARAM 0x0000003C -#define V3_PCI_MAP0 0x00000040 -#define V3_PCI_MAP1 0x00000044 -#define V3_PCI_INT_STAT 0x00000048 -#define V3_PCI_INT_CFG 0x0000004C -#define V3_LB_BASE0 0x00000054 -#define V3_LB_BASE1 0x00000058 -#define V3_LB_MAP0 0x0000005E -#define V3_LB_MAP1 0x00000062 -#define V3_LB_BASE2 0x00000064 -#define V3_LB_MAP2 0x00000066 -#define V3_LB_SIZE 0x00000068 -#define V3_LB_IO_BASE 0x0000006E -#define V3_FIFO_CFG 0x00000070 -#define V3_FIFO_PRIORITY 0x00000072 -#define V3_FIFO_STAT 0x00000074 -#define V3_LB_ISTAT 0x00000076 -#define V3_LB_IMASK 0x00000077 -#define V3_SYSTEM 0x00000078 -#define V3_LB_CFG 0x0000007A -#define V3_PCI_CFG 0x0000007C -#define V3_DMA_PCI_ADR0 0x00000080 -#define V3_DMA_PCI_ADR1 0x00000090 -#define V3_DMA_LOCAL_ADR0 0x00000084 -#define V3_DMA_LOCAL_ADR1 0x00000094 -#define V3_DMA_LENGTH0 0x00000088 -#define V3_DMA_LENGTH1 0x00000098 -#define V3_DMA_CSR0 0x0000008B -#define V3_DMA_CSR1 0x0000009B -#define V3_DMA_CTLB_ADR0 0x0000008C -#define V3_DMA_CTLB_ADR1 0x0000009C -#define V3_DMA_DELAY 0x000000E0 -#define V3_MAIL_DATA 0x000000C0 -#define V3_PCI_MAIL_IEWR 0x000000D0 -#define V3_PCI_MAIL_IERD 0x000000D2 -#define V3_LB_MAIL_IEWR 0x000000D4 -#define V3_LB_MAIL_IERD 0x000000D6 -#define V3_MAIL_WR_STAT 0x000000D8 -#define V3_MAIL_RD_STAT 0x000000DA -#define V3_QBA_MAP 0x000000DC - -/* PCI COMMAND REGISTER bits - */ -#define V3_COMMAND_M_FBB_EN (1 << 9) -#define V3_COMMAND_M_SERR_EN (1 << 8) -#define V3_COMMAND_M_PAR_EN (1 << 6) -#define V3_COMMAND_M_MASTER_EN (1 << 2) -#define V3_COMMAND_M_MEM_EN (1 << 1) -#define V3_COMMAND_M_IO_EN (1 << 0) - -/* SYSTEM REGISTER bits - */ -#define V3_SYSTEM_M_RST_OUT (1 << 15) -#define V3_SYSTEM_M_LOCK (1 << 14) - -/* PCI_CFG bits - */ -#define V3_PCI_CFG_M_I2O_EN (1 << 15) -#define V3_PCI_CFG_M_IO_REG_DIS (1 << 14) -#define V3_PCI_CFG_M_IO_DIS (1 << 13) -#define V3_PCI_CFG_M_EN3V (1 << 12) -#define V3_PCI_CFG_M_RETRY_EN (1 << 10) -#define V3_PCI_CFG_M_AD_LOW1 (1 << 9) -#define V3_PCI_CFG_M_AD_LOW0 (1 << 8) - -/* PCI_BASE register bits (PCI -> Local Bus) - */ -#define V3_PCI_BASE_M_ADR_BASE 0xFFF00000 -#define V3_PCI_BASE_M_ADR_BASEL 0x000FFF00 -#define V3_PCI_BASE_M_PREFETCH (1 << 3) -#define V3_PCI_BASE_M_TYPE (3 << 1) -#define V3_PCI_BASE_M_IO (1 << 0) - -/* PCI MAP register bits (PCI -> Local bus) - */ -#define V3_PCI_MAP_M_MAP_ADR 0xFFF00000 -#define V3_PCI_MAP_M_RD_POST_INH (1 << 15) -#define V3_PCI_MAP_M_ROM_SIZE (3 << 10) -#define V3_PCI_MAP_M_SWAP (3 << 8) -#define V3_PCI_MAP_M_ADR_SIZE 0x000000F0 -#define V3_PCI_MAP_M_REG_EN (1 << 1) -#define V3_PCI_MAP_M_ENABLE (1 << 0) - -#define V3_PCI_MAP_M_ADR_SIZE_1MB (0 << 4) -#define V3_PCI_MAP_M_ADR_SIZE_2MB (1 << 4) -#define V3_PCI_MAP_M_ADR_SIZE_4MB (2 << 4) -#define V3_PCI_MAP_M_ADR_SIZE_8MB (3 << 4) -#define V3_PCI_MAP_M_ADR_SIZE_16MB (4 << 4) -#define V3_PCI_MAP_M_ADR_SIZE_32MB (5 << 4) -#define V3_PCI_MAP_M_ADR_SIZE_64MB (6 << 4) -#define V3_PCI_MAP_M_ADR_SIZE_128MB (7 << 4) -#define V3_PCI_MAP_M_ADR_SIZE_256MB (8 << 4) -#define V3_PCI_MAP_M_ADR_SIZE_512MB (9 << 4) -#define V3_PCI_MAP_M_ADR_SIZE_1GB (10 << 4) -#define V3_PCI_MAP_M_ADR_SIZE_2GB (11 << 4) - -/* - * LB_BASE0,1 register bits (Local bus -> PCI) - */ -#define V3_LB_BASE_ADR_BASE 0xfff00000 -#define V3_LB_BASE_SWAP (3 << 8) -#define V3_LB_BASE_ADR_SIZE (15 << 4) -#define V3_LB_BASE_PREFETCH (1 << 3) -#define V3_LB_BASE_ENABLE (1 << 0) - -#define V3_LB_BASE_ADR_SIZE_1MB (0 << 4) -#define V3_LB_BASE_ADR_SIZE_2MB (1 << 4) -#define V3_LB_BASE_ADR_SIZE_4MB (2 << 4) -#define V3_LB_BASE_ADR_SIZE_8MB (3 << 4) -#define V3_LB_BASE_ADR_SIZE_16MB (4 << 4) -#define V3_LB_BASE_ADR_SIZE_32MB (5 << 4) -#define V3_LB_BASE_ADR_SIZE_64MB (6 << 4) -#define V3_LB_BASE_ADR_SIZE_128MB (7 << 4) -#define V3_LB_BASE_ADR_SIZE_256MB (8 << 4) -#define V3_LB_BASE_ADR_SIZE_512MB (9 << 4) -#define V3_LB_BASE_ADR_SIZE_1GB (10 << 4) -#define V3_LB_BASE_ADR_SIZE_2GB (11 << 4) - -#define v3_addr_to_lb_base(a) ((a) & V3_LB_BASE_ADR_BASE) - -/* - * LB_MAP0,1 register bits (Local bus -> PCI) - */ -#define V3_LB_MAP_MAP_ADR 0xfff0 -#define V3_LB_MAP_TYPE (7 << 1) -#define V3_LB_MAP_AD_LOW_EN (1 << 0) - -#define V3_LB_MAP_TYPE_IACK (0 << 1) -#define V3_LB_MAP_TYPE_IO (1 << 1) -#define V3_LB_MAP_TYPE_MEM (3 << 1) -#define V3_LB_MAP_TYPE_CONFIG (5 << 1) -#define V3_LB_MAP_TYPE_MEM_MULTIPLE (6 << 1) - -/* PCI MAP register bits (PCI -> Local bus) */ -#define v3_addr_to_lb_map(a) (((a) >> 16) & V3_LB_MAP_MAP_ADR) - -/* - * LB_BASE2 register bits (Local bus -> PCI IO) - */ -#define V3_LB_BASE2_ADR_BASE 0xff00 -#define V3_LB_BASE2_SWAP (3 << 6) -#define V3_LB_BASE2_ENABLE (1 << 0) - -#define v3_addr_to_lb_base2(a) (((a) >> 16) & V3_LB_BASE2_ADR_BASE) - -/* - * LB_MAP2 register bits (Local bus -> PCI IO) - */ -#define V3_LB_MAP2_MAP_ADR 0xff00 - -#define v3_addr_to_lb_map2(a) (((a) >> 16) & V3_LB_MAP2_MAP_ADR) - -#endif diff --git a/configs/integratorap_cm720t_defconfig b/configs/integratorap_cm720t_defconfig index 5d28135a8220..378bf936d737 100644 --- a/configs/integratorap_cm720t_defconfig +++ b/configs/integratorap_cm720t_defconfig @@ -16,7 +16,6 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Integrator-AP # " CONFIG_CMD_IMLS=y CONFIG_CMD_ARMFLASH=y -CONFIG_CMD_PCI=y # CONFIG_CMD_SETEXPR is not set CONFIG_SYS_RELOC_GD_ENV_ADDR=y # CONFIG_MMC is not set @@ -24,8 +23,5 @@ CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y -CONFIG_EEPRO100=y -CONFIG_TULIP=y -CONFIG_PCI=y CONFIG_BAUDRATE=38400 CONFIG_OF_LIBFDT=y diff --git a/configs/integratorap_cm920t_defconfig b/configs/integratorap_cm920t_defconfig index 0e914e91ebed..4ec2961a4ecb 100644 --- a/configs/integratorap_cm920t_defconfig +++ b/configs/integratorap_cm920t_defconfig @@ -16,7 +16,6 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Integrator-AP # " CONFIG_CMD_IMLS=y CONFIG_CMD_ARMFLASH=y -CONFIG_CMD_PCI=y # CONFIG_CMD_SETEXPR is not set CONFIG_SYS_RELOC_GD_ENV_ADDR=y # CONFIG_MMC is not set @@ -24,8 +23,5 @@ CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y -CONFIG_EEPRO100=y -CONFIG_TULIP=y -CONFIG_PCI=y CONFIG_BAUDRATE=38400 CONFIG_OF_LIBFDT=y diff --git a/configs/integratorap_cm926ejs_defconfig b/configs/integratorap_cm926ejs_defconfig index d28bc0f976cf..012d346500f5 100644 --- a/configs/integratorap_cm926ejs_defconfig +++ b/configs/integratorap_cm926ejs_defconfig @@ -16,7 +16,6 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Integrator-AP # " CONFIG_CMD_IMLS=y CONFIG_CMD_ARMFLASH=y -CONFIG_CMD_PCI=y # CONFIG_CMD_SETEXPR is not set CONFIG_SYS_RELOC_GD_ENV_ADDR=y # CONFIG_MMC is not set @@ -24,8 +23,5 @@ CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y -CONFIG_EEPRO100=y -CONFIG_TULIP=y -CONFIG_PCI=y CONFIG_BAUDRATE=38400 CONFIG_OF_LIBFDT=y diff --git a/configs/integratorap_cm946es_defconfig b/configs/integratorap_cm946es_defconfig index ae44f01ff50d..1868c7024f0f 100644 --- a/configs/integratorap_cm946es_defconfig +++ b/configs/integratorap_cm946es_defconfig @@ -16,7 +16,6 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Integrator-AP # " CONFIG_CMD_IMLS=y CONFIG_CMD_ARMFLASH=y -CONFIG_CMD_PCI=y # CONFIG_CMD_SETEXPR is not set CONFIG_SYS_RELOC_GD_ENV_ADDR=y # CONFIG_MMC is not set @@ -24,8 +23,5 @@ CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y -CONFIG_EEPRO100=y -CONFIG_TULIP=y -CONFIG_PCI=y CONFIG_BAUDRATE=38400 CONFIG_OF_LIBFDT=y -- 2.31.1

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[PATCH] mpc8379erdb: enable DM_USB DM_PCI DM_ETH
by sinan＠writeme.com 07 Jul '21

07 Jul '21

From: Sinan Akman <sinan(a)writeme.com> Signed-off-by: Sinan Akman <sinan(a)writeme.com> --- arch/powerpc/cpu/mpc83xx/pci.c | 2 ++ arch/powerpc/dts/mpc8379erdb.dts | 52 +++++++++++++++++++++++++++++++ board/freescale/mpc837xerdb/mpc837xerdb.c | 11 ++++++- configs/MPC837XERDB_defconfig | 18 +++++------ 4 files changed, 73 insertions(+), 10 deletions(-) diff --git a/arch/powerpc/cpu/mpc83xx/pci.c b/arch/powerpc/cpu/mpc83xx/pci.c index 5c289d0022..507ab3417b 100644 --- a/arch/powerpc/cpu/mpc83xx/pci.c +++ b/arch/powerpc/cpu/mpc83xx/pci.c @@ -27,6 +27,7 @@ DECLARE_GLOBAL_DATA_PTR; static struct pci_controller pci_hose[MAX_BUSES]; static int pci_num_buses; +#if !defined(CONFIG_DM_PCI) static void pci_init_bus(int bus, struct pci_region *reg) { volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; @@ -184,6 +185,7 @@ void mpc83xx_pcislave_unlock(int bus) hose->last_busno = pci_hose_scan(hose); } #endif +#endif /* CONFIG_DM_PCI */ #if defined(CONFIG_OF_LIBFDT) void ft_pci_setup(void *blob, struct bd_info *bd) diff --git a/arch/powerpc/dts/mpc8379erdb.dts b/arch/powerpc/dts/mpc8379erdb.dts index b1881b161c..2e7c8f103c 100644 --- a/arch/powerpc/dts/mpc8379erdb.dts +++ b/arch/powerpc/dts/mpc8379erdb.dts @@ -69,6 +69,58 @@ device_type = "ipic"; }; + usb@23000 { + compatible = "fsl-usb2-dr"; + reg = <0x23000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&ipic>; + interrupts = <38 0x8>; + phy_type = "ulpi"; + }; + + enet0: ethernet@24000 { + #address-cells = <1>; + #size-cells = <1>; + cell-index = <0>; + device_type = "network"; + model = "eTSEC"; + compatible = "fsl,etsec2"; + reg = <0x24000 0x1000>; + ranges = <0x0 0x24000 0x1000>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <32 0x8 33 0x8 34 0x8>; + phy-connection-type = "mii"; + interrupt-parent = <&ipic>; + fixed-link = <1 0 1000 0 0>; + phy-handle = <&phy>; + fsl,magic-packet; + + mdio@520 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,etsec2-mdio"; + reg = <0x520 0x20>; + + phy: ethernet-phy@2 { + interrupt-parent = <&ipic>; + interrupts = <17 0x8>; + reg = <0x2>; + device_type = "ethernet-phy"; + }; + }; + }; + + pci0: pci@e0008300 { + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + reg = <0x0 0xe0008300 0x0 0x00000fff>; + compatible = "fsl,mpc837x-pci"; + clock-frequency = <0>; + }; + }; }; diff --git a/board/freescale/mpc837xerdb/mpc837xerdb.c b/board/freescale/mpc837xerdb/mpc837xerdb.c index 624e92ef9c..66b3d9a465 100644 --- a/board/freescale/mpc837xerdb/mpc837xerdb.c +++ b/board/freescale/mpc837xerdb/mpc837xerdb.c @@ -176,7 +176,7 @@ int board_early_init_f(void) } #ifdef CONFIG_FSL_ESDHC -#if !(CONFIG_IS_ENABLED(DM_MMC)) +#if !(CONFIG_IS_ENABLED(DM_MMC) || CONFIG_IS_ENABLED(DM_USB)) int board_mmc_init(struct bd_info *bd) { struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR; @@ -217,6 +217,15 @@ int misc_init_r(void) return rc; } +int board_late_init(void) +{ + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; +#ifdef CONFIG_USB + clrsetbits_be32(&immap->sysconf.sicrl, SICRL_USB_A, 0x40000000); +#endif + return 0; +} + #if defined(CONFIG_OF_BOARD_SETUP) int ft_board_setup(void *blob, struct bd_info *bd) diff --git a/configs/MPC837XERDB_defconfig b/configs/MPC837XERDB_defconfig index 63ce36d533..b6161ca072 100644 --- a/configs/MPC837XERDB_defconfig +++ b/configs/MPC837XERDB_defconfig @@ -147,7 +147,9 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PCIE" CONFIG_BOOTDELAY=6 +CONFIG_BOARD_LATE_INIT=y CONFIG_MISC_INIT_R=y +CONFIG_PCI_INIT_R=y CONFIG_HUSH_PARSER=y CONFIG_CMD_IMLS=y CONFIG_CMD_I2C=y @@ -173,16 +175,14 @@ CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y +CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y +CONFIG_DM_ETH_PHY=y +CONFIG_RGMII=y +CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_PCI=y CONFIG_SYS_NS16550=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y -- 2.14.5

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