May 2021 - U-Boot

Re: [TF-A] Proposal: TF-A to adopt hand-off blocks (HOBs) for information passing between boot stages
by François Ozog 06 May '21

06 May '21

Hi here is the meeting recording: https://linaro-org.zoom.us/rec/share/zjfHeMIumkJhirLCVQYTHR6ftaqyWvF_0klgQn… Passcode: IPn+5q%z I am really sorry about the confusion related to the meeting time. I have now understood: the Collaborate portal uses a specific calendar which is tied to US/Chicago timezone while the actual Google Calendar is tied to Central Europe timezone. I am going to drop the Collaborate portal and use a shared Google calendar (it should be visible on the trusted-substrate.org page). I'll try to summarize what I learnt and highlight my view on what can be next steps in a future mail. Cheers FF On Thu, 8 Apr 2021 at 13:56, Manish Pandey2 via TF-A < tf-a(a)lists.trustedfirmware.org> wrote: > Hi, > > From TF-A project point of view, we prefer to use existing mechanism to > pass parameters across boot stages using linked list of tagged elements (as > suggested by Julius). It has support for both generic and SiP-specific > tags. Having said that, it does not stop partners to introduce new > mechanisms suitable for their usecase in platform port initially and later > move to generic code if its suitable for other platforms. > > To start with, Ampere can introduce a platform specific implementation of > memory tag(speed/NUMA topology etc) which can be evaluated and discussed > for generalization in future. The tag will be populated in BL2 stage and > can be forwarded to further stages(and to BL33) by passing the head of list > pointer in one of the registers. Initially any register can be used but > going forward a standardization will be needed. > > The U-boot bloblist mentioned by Simon is conceptually similar to what > TF-A is using, if there is consensus of using bloblist/taglist then TF-A > tag list may be enhanced to take best of both the implementations. > > One of the potential problems of having structure used in different > projects is maintainability, this can be avoided by having a single copy of > these structures in TF-A (kept inside "include/export" which intended to be > used by other projects.) > > Regarding usage of either UUID or tag, I echo the sentiments of Simon and > Julius to keep it simple and use tag values. > > Looking forward to having further discussions on zoom call today. > > Thanks > Manish P > > ------------------------------ > *From:* TF-A <tf-a-bounces(a)lists.trustedfirmware.org> on behalf of Julius > Werner via TF-A <tf-a(a)lists.trustedfirmware.org> > *Sent:* 25 March 2021 02:43 > *To:* Simon Glass <sjg(a)chromium.org> > *Cc:* Harb Abdulhamid OS <abdulhamid(a)os.amperecomputing.com>; Boot > Architecture Mailman List <boot-architecture(a)lists.linaro.org>; > tf-a(a)lists.trustedfirmware.org <tf-a(a)lists.trustedfirmware.org>; U-Boot > Mailing List <u-boot(a)lists.denx.de>; Paul Isaac's <paul.isaacs(a)linaro.org>; > Ron Minnich <rminnich(a)google.com> > *Subject:* Re: [TF-A] Proposal: TF-A to adopt hand-off blocks (HOBs) for > information passing between boot stages > > Just want to point out that TF-A currently already supports a (very > simple) mechanism like this: > > > https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/… > > https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/… > > https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/… > > It's just a linked list of tagged elements. The tag space is split into > TF-A-wide generic tags and SiP-specific tags (with plenty of room to spare > if more areas need to be defined -- a 64-bit tag can fit a lot). This is > currently being used by some platforms that run coreboot in place of > BL1/BL2, to pass information from coreboot (BL2) to BL31. > > I would echo Simon's sentiment of keeping this as simple as possible and > avoiding complicated and bloated data structures with UUIDs. You usually > want to parse something like this as early as possible in the passed-to > firmware stage, particularly if the structure encodes information about the > debug console (like it does for the platforms I mentioned above). For > example, in BL31 this basically means doing it right after moving from > assembly to C in bl31_early_platform_setup2() to get the console up before > running anything else. At that point in the BL31 initialization, the MMU > and caches are disabled, so data accesses are pretty expensive and you > don't want to spend a lot of parsing effort or calculate complicated > checksums or the like. You just want something extremely simple where you > ideally have to touch every data word only once. > > On Wed, Mar 24, 2021 at 5:06 PM Simon Glass via TF-A < > tf-a(a)lists.trustedfirmware.org> wrote: > > Hi Harb, > > On Wed, 24 Mar 2021 at 11:39, Harb Abdulhamid OS < > abdulhamid(a)os.amperecomputing.com> wrote: > > Hello Folks, > > Appreciate the feedback and replies on this. Glad to see that there is > interest in this topic. 😊 > > > > I try to address the comments/feedback from Francois and Simon below…. > > > > @François Ozog <francois.ozog(a)linaro.org> – happy to discuss this on a > zoom call. I will make that time slot work, and will be available to > attend April 8, 4pm CT. > > > > Note that I’m using the term “HOB” here more generically, as there are > typically vendor specific structures beyond the resource descriptor HOB, > which provides only a small subset of the information that needs to be > passed between the boot phases. > > > > The whole point here is to provide mechanism to develop firmware that we > can build ARM Server SoC’s that support **any** BL33 payload (e.g. EDK2, > AptioV, CoreBoot, and maybe even directly boot strapping LinuxBoot at some > point). In other-words, we are trying to come up with a TF-A that would > be completely agnostic to the implementation of BL33 (i.e. BL33 is built > completely independently by a separate entity – e.g. an ODM/OEM). > > > > Keep in mind, in the server/datacenter market segment we are not building > vertically integrated systems with a single entity compiling > firmware/software stacks like most folks in TF-A have become use to. There > are two categories of higher level firmware code blobs in the > server/datacenter model: > > 1. “SoC” or “silicon” firmware – in TF-A this may map to BL1, BL2, > BL31, and **possibly** one or more BL32 instances > 2. “Platform” or “board” firmware – in TF-A this may map to BL33 and * > *possibly** one or more BL32 instances. > > > > Even the platform firmware stack could be further fragmented by having > multiple entities involved in delivering the entire firmware stack: IBVs, > ODMs, OEMs, CSPs, and possibly even device vendor code. > > > > To support a broad range of platform designs with a broad range of memory > devices, we need a crisp and clear contract between the SoC firmware that > initializes memory (e.g. BL2) and how that platform boot firmware (e.g. > BL33) gathers information about what memory that was initialized, at what > speeds, NUMA topology, and many other relevant information that needs to be > known and comprehended by the platform firmware and eventually by the > platform software. > > > > I understand the versatility of DT, but I see two major problems with DT: > > - DT requires more complicated parsing to get properties, and even > more complex to dynamically set properties – this HOB structures may need > to be generated in boot phases where DDR is not available, and therefore we > will be extremely memory constrained. > - DT is probably overkill for this purpose – We really just want a > list of pointers to simple C structures that code cast (e.g. JEDEC SPD data > blob) > > > > I think that we should not mix the efforts around DT/ACPI specs with what > we are doing here, because those specs and concepts were developed for a > completely different purpose (i.e. abstractions needed for OS / RTOS > software, and not necessarily suitable for firmware-to-firmware hand-offs). > > > > Frankly, I would personally push back pretty hard on defining SMC’s for > something that should be one way information passing. Every SMC we add is > another attack vector to the secure world and an increased burden on the > folks that have to do security auditing and threat analysis. I see no > benefit in exposing these boot/HOB/BOB structures at run-time via SMC > calls. > > > > Please do let me know if you disagree and why. Look forward to discussing > on this thread or on the call. > > > > @Simon Glass <sjg(a)chromium.org> - Thanks for the pointer to bloblist. > I briefly reviewed and it seems like a good baseline for what we may be > looking for. > > > > That being said, I would say that there is some benefit in having some > kind of unique identifiers (e.g. UUID or some unique signature) so that we > can tie standardized data structures (based on some future TBD specs) to a > particular ID. For example, if the TPM driver in BL33 is looking for the > TPM structure in the HOB/BOB list, and may not care about the other data > blobs. The driver needs a way to identify and locate the blob it cares > about. > > > The tag is intended to serve that purpose, although perhaps it should > switch from an auto-allocating enum to one with explicit values for each > entry and a range for 'local' use. > > > > I guess we can achieve this with the tag, but the problem with tag when > you have eco-system with a lot of parties doing parallel development, you > can end up with tag collisions and folks fighting about who has rights to > what tag values. We would need some official process for folks to register > tags for whatever new structures we define, or maybe some tag range for > vendor specific structures. This comes with a lot of pain and > bureaucracy. On the other hand, UUID has been a proven way to make it easy > to just define your own blobs with **either** standard or vendor specific > structures without worry of ID collisions between vendors. > > > True. I think the pain is overstated, though. In this case I think we > actually want something that can be shared between projects and orgs, so > some amount of coordination could be considered a benefit. It could just be > a github pull request. I find the UUID unfriendly and not just to code size > and eyesight! Trying to discover what GUIDs mean or are valid is quite > tricky. E.g. see this code: > > #define FSP_HOB_RESOURCE_OWNER_TSEG_GUID \ > EFI_GUID(0xd038747c, 0xd00c, 0x4980, \ > 0xb3, 0x19, 0x49, 0x01, 0x99, 0xa4, 0x7d, 0x55) > (etc.) > > static struct guid_name { > efi_guid_t guid; > const char *name; > } guid_name[] = { > { FSP_HOB_RESOURCE_OWNER_TSEG_GUID, "TSEG" }, > { FSP_HOB_RESOURCE_OWNER_FSP_GUID, "FSP" }, > { FSP_HOB_RESOURCE_OWNER_SMM_PEI_SMRAM_GUID, "SMM PEI SMRAM" }, > { FSP_NON_VOLATILE_STORAGE_HOB_GUID, "NVS" }, > { FSP_VARIABLE_NV_DATA_HOB_GUID, "Variable NVS" }, > { FSP_GRAPHICS_INFO_HOB_GUID, "Graphics info" }, > { FSP_HOB_RESOURCE_OWNER_PCD_DATABASE_GUID1, "PCD database ea" }, > { FSP_HOB_RESOURCE_OWNER_PCD_DATABASE_GUID2, "PCD database 9b" }, > (never figured out what those two are) > > { FSP_HOB_RESOURCE_OWNER_PEIM_DXE_GUID, "PEIM Init DXE" }, > { FSP_HOB_RESOURCE_OWNER_ALLOC_STACK_GUID, "Alloc stack" }, > { FSP_HOB_RESOURCE_OWNER_SMBIOS_MEMORY_GUID, "SMBIOS memory" }, > { {}, "zero-guid" }, > {} > }; > > static const char *guid_to_name(const efi_guid_t *guid) > { > struct guid_name *entry; > > for (entry = guid_name; entry->name; entry++) { > if (!guidcmp(guid, &entry->guid)) > return entry->name; > } > > return NULL; > } > > Believe it or not it took a fair bit of effort to find just that small > list, with nearly every one in a separate doc, from memory. > > > > We can probably debate whether there is any value in GUID/UUID or not > during the call… but again, boblist seems like a reasonable starting point > as an alternative to HOB. > > > Indeed. There is certainly value in both approaches. > > Regards, > Simon > > > > > Thanks, > > --Harb > > > > *From:* François Ozog <francois.ozog(a)linaro.org> > *Sent:* Tuesday, March 23, 2021 10:00 AM > *To:* François Ozog <francois.ozog(a)linaro.org>; Ron Minnich < > rminnich(a)google.com>; Paul Isaac's <paul.isaacs(a)linaro.org> > *Cc:* Simon Glass <sjg(a)chromium.org>; Harb Abdulhamid OS < > abdulhamid(a)os.amperecomputing.com>; Boot Architecture Mailman List < > boot-architecture(a)lists.linaro.org>; tf-a(a)lists.trustedfirmware.org > *Subject:* Re: [TF-A] Proposal: TF-A to adopt hand-off blocks (HOBs) for > information passing between boot stages > > > > +Ron Minnich <rminnich(a)google.com> +Paul Isaac's <paul.isaacs(a)linaro.org> > > > > Adding Ron and Paul because I think this interface should be also > benefiting LinuxBoot efforts. > > > > On Tue, 23 Mar 2021 at 11:17, François Ozog via TF-A < > tf-a(a)lists.trustedfirmware.org> wrote: > > Hi, > > > > I propose we cover the topic at the next Trusted Substrate > <https://collaborate.linaro.org/display/TS/Trusted+Substrate+Home> zoom > call <https://linaro-org.zoom.us/j/94563644892> on April 8th 4pm CET. > > > > The agenda: > > ABI between non-secure firmware and the rest of firmware (EL3, S-EL1, > S-EL2, SCP) to adapt hardware description to some runtime conditions. > > runtime conditions here relates to DRAM size and topology detection, > secure DRAM memory carvings, PSCI and SCMI interface publishing. > > > > For additional background on existing metadata: UEFI Platform > Initialization Specification Version 1.7 > <https://uefi.org/sites/default/files/resources/PI_Spec_1_7_final_Jan_2019.p…> > , 5.5 Resource Descriptor HOB > > Out of the ResourceType we care about is EFI_RESOURCE_SYSTEM_MEMORY. > > This HOB lacks memory NUMA attachment or something that could be related > to fill SRAT table for ACPI or relevant DT proximity domains. > > HOB is not consistent accros platforms: some platforms (Arm) lists memory > from the booting NUMA node, other platforms (x86) lists all memory from all > NUMA nodes. (At least this is the case on the two platforms I tested). > > > > There are two proposals to use memory structures from SPL/BLx up to the > handover function (as defined in the Device Tree technical report > <https://docs.google.com/document/d/1CLkhLRaz_zcCq44DLGmPZQFPbYHOC6nzPowaL0X…>) > which can be U-boot (BL33 or just U-Boot in case of SPL/U-Boot scheme) or > EDK2. > > I would propose we also discuss possibility of FF-A interface to actually > query information or request actions to be done (this is a model actually > used in some SoCs with proprietary SMC calls). > > > > Requirements (to be validated): > > - ACPI and DT hardware descriptions. > > - agnostic to boot framework (SPL/U-Boot, TF-A/U-Boot, TF-A/EDK2) > > - agnostic to boot framework (SPL/U-Boot, TF-A/U-Boot, TF-A/EDK2, > TF-A/LinuxBoot) > > - at least allows complete DRAM description and "persistent" usage > (reserved areas for secure world or other usages) > > - support secure world device assignment > > > > Cheers > > > > FF > > > > > > On Mon, 22 Mar 2021 at 19:56, Simon Glass <sjg(a)chromium.org> wrote: > > Hi, > > Can I suggest using bloblist for this instead? It is lightweight, > easier to parse, doesn't have GUIDs and is already used within U-Boot > for passing info between SPL/U-Boot, etc. > > Docs here: > https://github.com/u-boot/u-boot/blob/master/doc/README.bloblist > Header file describes the format: > https://github.com/u-boot/u-boot/blob/master/include/bloblist.h > > Full set of unit tests: > https://github.com/u-boot/u-boot/blob/master/test/bloblist.c > > Regards, > Simon > > On Mon, 22 Mar 2021 at 23:58, François Ozog <francois.ozog(a)linaro.org> > wrote: > > > > +Boot Architecture Mailman List <boot-architecture(a)lists.linaro.org> > > > > standardization is very much welcomed here and need to accommodate a very > > diverse set of situations. > > For example, TEE OS may need to pass memory reservations to BL33 or > > "capture" a device for the secure world. > > > > I have observed a number of architectures: > > 1) pass information from BLx to BLy in the form of a specific object > > 2) BLx called by BLy by a platform specific SMC to get information > > 3) BLx called by BLy by a platform specific SMC to perform Device Tree > > fixups > > > > I also imagined a standardized "broadcast" FF-A call so that any firmware > > element can either provide information or "do something". > > > > My understanding of your proposal is about standardizing on architecture > 1) > > with the HOB format. > > > > The advantage of the HOB is simplicity but it may be difficult to > implement > > schemes such as pruning a DT because device assignment in the secure > world. > > > > In any case, it looks feasible to have TF-A and OP-TEE complement the > list > > of HOBs to pass information downstream (the bootflow). > > > > It would be good to start with building the comprehensive list of > > information that need to be conveyed between firmware elements: > > > > information. | authoritative entity | reporting entity | information > > exchanged: > > dram | TFA | TFA | > > <format to be detailed, NUMA topology to build the SRAT table or DT > > equivalent?> > > PSCI | SCP | TFA? | > > SCMI | SCP or TEE-OS | TFA? TEE-OS?| > > secure SRAM | TFA. | TFA. | > > secure DRAM | TFA? TEE-OS? | TFA? TEE-OS? | > > other? | | > > | > > > > Cheers > > > > FF > > > > > > On Mon, 22 Mar 2021 at 09:34, Harb Abdulhamid OS via TF-A < > > tf-a(a)lists.trustedfirmware.org> wrote: > > > > > Hello Folks, > > > > > > > > > > > > I'm emailing to start an open discussion about the adoption of a > concept > > > known as "hand-off blocks" or HOB to become a part of the TF-A Firmware > > > Framework Architecture (FFA). This is something that is a pretty major > > > pain point when it comes to the adoption of TF-A in ARM Server SoC’s > > > designed to enable a broad range of highly configurable datacenter > > > platforms. > > > > > > > > > > > > > > > > > > What is a HOB (Background)? > > > > > > --------------------------- > > > > > > UEFI PI spec describes a particular definition for how HOB may be used > for > > > transitioning between the PEI and DXE boot phases, which is a good > > > reference point for this discussion, but not necessarily the exact > solution > > > appropriate for TF-A. > > > > > > > > > > > > A HOB is simply a dynamically generated data structure passed in > between > > > two boot phases. This is information that was obtained through > discovery > > > and needs to be passed forward to the next boot phase *once*, with no > API > > > needed to call back (e.g. no call back into previous firmware phase is > > > needed to fetch this information at run-time - it is simply passed one > time > > > during boot). > > > > > > > > > > > > There may be one or more HOBs passed in between boot phases. If there > are > > > more than one HOB that needs to be passed, this can be in a form of a > "HOB > > > table", which (for example) could be a UUID indexed array of pointers > to > > > HOB structures, used to locate a HOB of interest (based on UUID). In > such > > > cases, instead of passing a single HOB, the boot phases may rely on > passing > > > the pointer to the HOB table. > > > > > > > > > > > > This has been extremely useful concept to employ on highly configurable > > > systems that must rely on flexible discovery mechanisms to initialize > and > > > boot the system. This is especially helpful when you have multiple > > > > > > > > > > > > > > > > > > Why do we need HOBs in TF-A?: > > > > > > ----------------------------- > > > > > > It is desirable that EL3 firmware (e.g. TF-A) built for ARM Server SoC > in > > > a way that is SoC specific *but* platform agnostic. This means that a > > > single ARM SoC that a SiP may deliver to customers may provide a single > > > TF-A binary (e.g. BL1, BL2, BL31) that could be used to support a broad > > > range of platform designs and configurations in order to boot a > platform > > > specific firmware (e.g. BL33 and possibly even BL32 code). In order to > > > achieve this, the platform configuration must be *discovered* instead > of > > > statically compiled as it is today in TF-A via device tree based > > > enumeration. The mechanisms of discovery may differ broadly depending > on > > > the relevant industry standard, or in some cases may have rely on SiP > > > specific discovery flows. > > > > > > > > > > > > For example: On server systems that support a broad range DIMM memory > > > population/topologies, all the necessary information required to boot > is > > > fully discovered via standard JEDEC Serial Presence Detect (SPD) over > an > > > I2C bus. Leveraging the SPD bus, may platform variants could be > supported > > > with a single TF-A binary. Not only is this information required to > > > initialize memory in early boot phases (e.g. BL2), the subsequent boot > > > phases will also need this SPD info to construct a system physical > address > > > map and properly initialize the MMU based on the memory present, and > where > > > the memory may be present. Subsequent boot phases (e.g. BL33 / UEFI) > may > > > need to generate standard firmware tables to the operating systems, > such as > > > SMBIOS tables describing DIMM topology and various ACPI tables (e.g. > SLIT, > > > SRAT, even NFIT if NVDIMM's are present). > > > > > > > > > > > > In short, it all starts with a standardized or vendor specific > discovery > > > flow in an early boot stage (e.g. BL1/BL2), followed by the passing of > > > information to the next boot stages (e.g. BL31/BL32/BL33). > > > > > > > > > > > > Today, every HOB may be a vendor specific structure, but in the future > > > there may be benefit of defining standard HOBs. This may be useful for > > > memory discovery, passing the system physical address map, enabling TPM > > > measured boot, and potentially many other common HOB use-cases. > > > > > > > > > > > > It would be extremely beneficial to the datacenter market segment if > the > > > TF-A community would adopt this concept of information passing between > all > > > boot phases as opposed to rely solely on device tree enumeration. > This is > > > not intended to replace device tree, rather intended as an alternative > way > > > to describe the info that must be discovered and dynamically generated. > > > > > > > > > > > > > > > > > > Conclusion: > > > > > > ----------- > > > > > > We are proposing that the TF-A community begin pursuing the adoption of > > > HOBs as a mechanism used for information exchange between each boot > stage > > > (e.g. BL1->BL2, BL2->BL31, BL31->BL32, and BL31->BL33)? Longer term we > > > want to explore standardizing some HOB structures for the BL33 phase > (e.g. > > > UEFI HOB structures), but initially would like to agree on this being a > > > useful mechanism used to pass information between each boot stage. > > > > > > > > > > > > Thanks, > > > > > > --Harb > > > > > > > > > > > > > > > > > > > > > -- > > > TF-A mailing list > > > TF-A(a)lists.trustedfirmware.org > > > https://lists.trustedfirmware.org/mailman/listinfo/tf-a > > > > > > > > > -- > > François-Frédéric Ozog | *Director Linaro Edge & Fog Computing Group* > > T: +33.67221.6485 > > francois.ozog(a)linaro.org | Skype: ffozog > > _______________________________________________ > > boot-architecture mailing list > > boot-architecture(a)lists.linaro.org > > https://lists.linaro.org/mailman/listinfo/boot-architecture > > > > > -- > > *François-Frédéric Ozog* | *Director Linaro Edge & Fog Computing Group* > > T: +33.67221.6485 > francois.ozog(a)linaro.org | Skype: ffozog > > > > -- > TF-A mailing list > TF-A(a)lists.trustedfirmware.org > https://lists.trustedfirmware.org/mailman/listinfo/tf-a > > > > > -- > > *François-Frédéric Ozog* | *Director Linaro Edge & Fog Computing Group* > > T: +33.67221.6485 > francois.ozog(a)linaro.org | Skype: ffozog > > > > -- > TF-A mailing list > TF-A(a)lists.trustedfirmware.org > https://lists.trustedfirmware.org/mailman/listinfo/tf-a > > -- > TF-A mailing list > TF-A(a)lists.trustedfirmware.org > https://lists.trustedfirmware.org/mailman/listinfo/tf-a > -- François-Frédéric Ozog | *Director Linaro Edge & Fog Computing Group* T: +33.67221.6485 francois.ozog(a)linaro.org | Skype: ffozog

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[RESEND PATCH v1] psci: rename psci_features function
by Igor Opaniuk 05 May '21

05 May '21

From: Igor Opaniuk <igor.opaniuk(a)foundries.io> s/psci_features/psci_features_req/g for the case when both ARCH_SUPPORT_PSCI=y and ARM_PSCI_FW=y, that leads to these compilation issues: drivers/firmware/psci.c:69:12: error: conflicting types for 'psci_features' 69 | static int psci_features(u32 psci_func_id) | ^~~~~~~~~~~~~ In file included from drivers/firmware/psci.c:23: ./arch/arm/include/asm/system.h:548:5: note: previous declaration of 'psci_features' was here 548 | s32 psci_features(u32 function_id, u32 psci_fid); | ^~~~~~~~~~~~~ Signed-off-by: Igor Opaniuk <igor.opaniuk(a)foundries.io> Reported-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- drivers/firmware/psci.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/firmware/psci.c b/drivers/firmware/psci.c index be57552aba..f1841a1835 100644 --- a/drivers/firmware/psci.c +++ b/drivers/firmware/psci.c @@ -66,7 +66,7 @@ unsigned long __efi_runtime invoke_psci_fn return res.a0; } -static int psci_features(u32 psci_func_id) +static int psci_features_req(u32 psci_func_id) { return invoke_psci_fn(PSCI_1_0_FN_PSCI_FEATURES, psci_func_id, 0, 0); @@ -85,7 +85,7 @@ static bool psci_is_system_reset2_supported(void) ver = psci_0_2_get_version(); if (PSCI_VERSION_MAJOR(ver) >= 1) { - ret = psci_features(PSCI_FN_NATIVE(1_1, SYSTEM_RESET2)); + ret = psci_features_req(PSCI_FN_NATIVE(1_1, SYSTEM_RESET2)); if (ret != PSCI_RET_NOT_SUPPORTED) return true; -- 2.25.1

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[PATCH v1] psci: rename psci_features function
by Igor Opaniuk 05 May '21

05 May '21

From: Igor Opaniuk <igor.opaniuk(a)foundries.io> s/psci_features/psci_features_req/g for the case when both ARCH_SUPPORT_PSCI=y and ARM_PSCI_FW=y, that leads to these compilation issues: drivers/firmware/psci.c:69:12: error: conflicting types for 'psci_features' 69 | static int psci_features(u32 psci_func_id) | ^~~~~~~~~~~~~ In file included from drivers/firmware/psci.c:23: ./arch/arm/include/asm/system.h:548:5: note: previous declaration of 'psci_features' was here 548 | s32 psci_features(u32 function_id, u32 psci_fid); | ^~~~~~~~~~~~~ Signed-off-by: Igor Opaniuk <igor.opaniuk(a)foundries.io> --- drivers/firmware/psci.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/firmware/psci.c b/drivers/firmware/psci.c index be57552aba..f1841a1835 100644 --- a/drivers/firmware/psci.c +++ b/drivers/firmware/psci.c @@ -66,7 +66,7 @@ unsigned long __efi_runtime invoke_psci_fn return res.a0; } -static int psci_features(u32 psci_func_id) +static int psci_features_req(u32 psci_func_id) { return invoke_psci_fn(PSCI_1_0_FN_PSCI_FEATURES, psci_func_id, 0, 0); @@ -85,7 +85,7 @@ static bool psci_is_system_reset2_supported(void) ver = psci_0_2_get_version(); if (PSCI_VERSION_MAJOR(ver) >= 1) { - ret = psci_features(PSCI_FN_NATIVE(1_1, SYSTEM_RESET2)); + ret = psci_features_req(PSCI_FN_NATIVE(1_1, SYSTEM_RESET2)); if (ret != PSCI_RET_NOT_SUPPORTED) return true; -- 2.25.1

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[PATCH] cmd: mvebu: Rename rx_training to mvebu_comphy_rx_training
by Stefan Roese 05 May '21

05 May '21

Rename the misleading cmd "rx_training" to "mvebu_comphy_rx_training" to avoid confusion and mixup with DDR3/4 training. This makes it clear, that this command is platform specific and handles the COMPHY RX training. Also depend this cmd on ARMADA_8K and not TARGET_MVEBU_ARMADA_8K to make is available for OcteonTX2 CN913x. Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Pali Rohár <pali(a)kernel.org> Cc: Marek Behun <marek.behun(a)nic.cz> Cc: Kostya Porotchkin <kostap(a)marvell.com> Cc: Nadav Haklai <nadavh(a)marvell.com> --- cmd/mvebu/Kconfig | 9 ++++----- cmd/mvebu/Makefile | 2 +- cmd/mvebu/{rx_training.c => comphy_rx_training.c} | 10 +++++----- 3 files changed, 10 insertions(+), 11 deletions(-) rename cmd/mvebu/{rx_training.c => comphy_rx_training.c} (74%) diff --git a/cmd/mvebu/Kconfig b/cmd/mvebu/Kconfig index f0e4f884d703..7c42c75afbe2 100644 --- a/cmd/mvebu/Kconfig +++ b/cmd/mvebu/Kconfig @@ -49,11 +49,10 @@ config MVEBU_UBOOT_DFLT_NAME This option should contain a default file name to be used with MVEBU "bubt" command if the source file name is omitted -config CMD_MVEBU_RX_TRAINING - bool "rx_training" - depends on TARGET_MVEBU_ARMADA_8K - default n +config CMD_MVEBU_COMPHY_RX_TRAINING + bool "mvebu_comphy_rx_training" + depends on ARMADA_8K help - Perform RX training sequence + Perform COMPHY RX training sequence endmenu diff --git a/cmd/mvebu/Makefile b/cmd/mvebu/Makefile index 79299b0814f4..ca96ad01d911 100644 --- a/cmd/mvebu/Makefile +++ b/cmd/mvebu/Makefile @@ -5,4 +5,4 @@ # https://spdx.org/licenses obj-$(CONFIG_CMD_MVEBU_BUBT) += bubt.o -obj-$(CONFIG_CMD_MVEBU_RX_TRAINING) += rx_training.o +obj-$(CONFIG_CMD_MVEBU_COMPHY_RX_TRAINING) += comphy_rx_training.o diff --git a/cmd/mvebu/rx_training.c b/cmd/mvebu/comphy_rx_training.c similarity index 74% rename from cmd/mvebu/rx_training.c rename to cmd/mvebu/comphy_rx_training.c index 4bae7653aca3..0798decfae13 100644 --- a/cmd/mvebu/rx_training.c +++ b/cmd/mvebu/comphy_rx_training.c @@ -13,8 +13,8 @@ #include <dm/device-internal.h> #include <mvebu/comphy.h> -int rx_training_cmd(struct cmd_tbl *cmdtp, int flag, int argc, - char * const argv[]) +int mvebu_comphy_rx_training_cmd(struct cmd_tbl *cmdtp, int flag, int argc, + char * const argv[]) { struct udevice *dev; struct uclass *uc; @@ -51,7 +51,7 @@ int rx_training_cmd(struct cmd_tbl *cmdtp, int flag, int argc, } U_BOOT_CMD( - rx_training, 3, 0, rx_training_cmd, - "rx_training <cp id> <comphy id>\n", - "\n\tRun RX training sequence, the user must state CP index (0/1) and comphy ID (0/5)" + mvebu_comphy_rx_training, 3, 0, mvebu_comphy_rx_training_cmd, + "mvebu_comphy_rx_training <cp id> <comphy id>\n", + "\n\tRun COMPHY RX training sequence, the user must state CP index (0/1) and comphy ID (0/5)" ); -- 2.31.1

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[PATCH v4 0/5] psci: add support for SYSTEM_RESET2 and PSCI_FEATURES
by Igor Opaniuk 05 May '21

05 May '21

From: Igor Opaniuk <igor.opaniuk(a)foundries.io> 1. Adds support for: * PSCI_FEATURES, introduced in PSCI 1.0. This provides API that allows discovering whether a specific PSCI function is implemented and its features. * SYSTEM_RESET2, introduced in PSCI 1.1, which extends existing SYSTEM_RESET. It provides support for vendor-specific resets, providing reset_type as an additional param. 2. PSCI sysreset driver is refactored to use new API. 3. do_reset cmd is extended, optional param added for providing type of reset CI: https://dev.azure.com/igoropaniuk/u-boot/_build/results?buildId=23&view=res… Changes in v4: - Fix htmldoc build issue Changes in v3: - Drop RFC tag - Add usage doc for reset cmd - Reimplement param handling for reset cmd - Droped updates in reset usage string Changes in v2: - do_reset cmd updates Igor Opaniuk (5): psci: add v1.0/v1.1 definitions from Linux psci: add features/reset2 support sysreset: psci: use psci driver exported functions sysreset: provide type of reset in do_reset cmd doc: usage: add usage details for reset cmd cmd/boot.c | 2 +- doc/usage/index.rst | 1 + doc/usage/reset.rst | 26 ++++++++++++ drivers/firmware/psci.c | 68 ++++++++++++++++++++++++++++++ drivers/sysreset/sysreset-uclass.c | 11 ++++- drivers/sysreset/sysreset_psci.c | 8 +--- include/linux/psci.h | 31 ++++++++++++++ 7 files changed, 139 insertions(+), 8 deletions(-) create mode 100644 doc/usage/reset.rst -- 2.25.1

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[PATCH v4 0/6] nable ECDSA FIT verification for stm32mp
by Alexandru Gagniuc 05 May '21

05 May '21

This series is Part II of the ECDSA saga. It applies on top of [1]: * [PATCH v7 00/11] Add support for ECDSA image signing Changes since v3: - Remove unused ecdsa_check_key() function Changes since v2: - Spell out "elliptic curve" in Kconfig (Although RSA isn't spelled out) Changes since v1: - Add test to make sure the UCLASS is enabled - Fix check against wrong sig_len in ecdsa_romapi.c - s/U_BOOT_DEVICE/U_BOOT_DRVINFO/ - Use "if(!ret)" instead of "if (ret == 0)" - Use uclass_first_device_err() instead of uclass_first_device() - Make sure #includes are correctly alphabetized Alexandru Gagniuc (6): dm: crypto: Define UCLASS API for ECDSA signature verification lib: ecdsa: Add skeleton to implement ecdsa verification in u-boot lib: ecdsa: Implement signature verification for crypto_algo API arm: stm32mp1: Implement ECDSA signature verification Kconfig: FIT_SIGNATURE should not select RSA_VERIFY test: dm: Add test for ECDSA UCLASS support arch/arm/mach-stm32mp/Kconfig | 9 ++ arch/arm/mach-stm32mp/Makefile | 1 + arch/arm/mach-stm32mp/ecdsa_romapi.c | 102 +++++++++++++++++++++ common/Kconfig.boot | 8 +- configs/sandbox_defconfig | 2 + include/crypto/ecdsa-uclass.h | 39 ++++++++ include/dm/uclass-id.h | 1 + include/image.h | 10 +-- include/u-boot/rsa.h | 2 +- lib/Kconfig | 1 + lib/Makefile | 1 + lib/ecdsa/Kconfig | 23 +++++ lib/ecdsa/Makefile | 1 + lib/ecdsa/ecdsa-verify.c | 128 +++++++++++++++++++++++++++ test/dm/Makefile | 1 + test/dm/ecdsa.c | 38 ++++++++ 16 files changed, 357 insertions(+), 10 deletions(-) create mode 100644 arch/arm/mach-stm32mp/ecdsa_romapi.c create mode 100644 include/crypto/ecdsa-uclass.h create mode 100644 lib/ecdsa/Kconfig create mode 100644 lib/ecdsa/Makefile create mode 100644 lib/ecdsa/ecdsa-verify.c create mode 100644 test/dm/ecdsa.c -- 2.26.3

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[PATCH] common: fdt_support: Observe index in fdt_getprop_u32_default_node()
by Andre Przywara 05 May '21

05 May '21

fdt_getprop_u32_default_node() promises to take the "cell" number into account when returning the value of a property array. However it actually misses out on this, always returning the first cell only instead. This was so far not a problem, since every user always asks for cell 0. Observe the index value when accessing the property, and also fix the parameter names to the more commonly used propname, offset and index names, to improve readability of the function. Signed-off-by: Andre Przywara <andre.przywara(a)arm.com> --- common/fdt_support.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/common/fdt_support.c b/common/fdt_support.c index e624bbdf404..8dc45483f79 100644 --- a/common/fdt_support.c +++ b/common/fdt_support.c @@ -26,31 +26,31 @@ DECLARE_GLOBAL_DATA_PTR; * fdt_getprop_u32_default_node - Return a node's property or a default * * @fdt: ptr to device tree - * @off: offset of node - * @cell: cell offset in property - * @prop: property name + * @offset: offset of node + * @index: cell offset in property + * @propname: property name * @dflt: default value if the property isn't found * * Convenience function to return a node's property or a default value if * the property doesn't exist. */ -u32 fdt_getprop_u32_default_node(const void *fdt, int off, int cell, - const char *prop, const u32 dflt) +u32 fdt_getprop_u32_default_node(const void *fdt, int offset, int index, + const char *propname, const u32 dflt) { const fdt32_t *val; int len; - val = fdt_getprop(fdt, off, prop, &len); + val = fdt_getprop(fdt, offset, propname, &len); /* Check if property exists */ if (!val) return dflt; /* Check if property is long enough */ - if (len < ((cell + 1) * sizeof(uint32_t))) + if (len < ((index + 1) * sizeof(uint32_t))) return dflt; - return fdt32_to_cpu(*val); + return fdt32_to_cpu(val[index]); } /** -- 2.17.5

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[U-Boot] [PATCH] Marvell 88EXXXX Switch/PHY init support
by sajad momeni 05 May '21

05 May '21

Hello Can send the Marvell 88E61XXX Switch driver And file thanks

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[PATCH v1 00/23] phy: marvell: Sync Armada 3k/7k/8k SERDES code with Marvell version
by Stefan Roese 05 May '21

05 May '21

This patchset adds the missing SERDES patches from the Marvell U-Boot SDK U-Boot version. This is done in preparation for the integration of the Octeon TX2 CN913x support, which uses the updated version of this code. Thanks, Stefan Christine Gharzuzi (1): phy: marvell: fix handling of unconnected comphy Grzegorz Jaszczyk (8): phy: marvell: cp110: let the firmware configure comphy for RXAUI phy: marvell: cp110: let the firmware configure comphy for USB phy: marvell: cp110: let the firmware perform training for XFI phy: marvell: cp110: remove both phy and pipe selector configuration phy: marvell: cp110: clean up driver after it was moved to atf phy: marvell: allow to initialize up to 6 USB ports phy: marvell: fix pll initialization for second utmi port phy: marvell: utmi: update utmi config which fixes usb2.0 instability Igal Liberman (11): phy: marvell: rename comphy related definitions to COMPHY_XX phy: marvell: add missing speed during info prints phy: marvell: cp110: utmi: update analog parameters according to latest ETP phy: marvell: fix several minor bugs in comphy_probe phy: marvell: save comphy_map_data priv structure phy: marvell: add RX training command phy: marvell: enable comphy info prints for all devices phy: marvell: pass sgmii id to firmware phy: marvell: cp110: mark u-boot power-off calls phy: marvell: add support for SFI1 doc: dt-bindings: add Marvell comphy binding Marcin Wojtas (1): phy: marvell: cp110: remove unused definitions Omri Itach (1): phy: marvell: cp110: initialize only enabled UTMI units jinghua (1): phy: marvell: add comphy type PHY_TYPE_USB3 arch/arm/dts/armada-3720-db.dts | 8 +- arch/arm/dts/armada-3720-espressobin.dts | 12 +- arch/arm/dts/armada-3720-turris-mox.dts | 12 +- arch/arm/dts/armada-3720-uDPU.dts | 23 +- arch/arm/dts/armada-7040-db-nand.dts | 24 +- arch/arm/dts/armada-7040-db.dts | 23 +- arch/arm/dts/armada-8040-clearfog-gt-8k.dts | 32 +- arch/arm/dts/armada-8040-db.dts | 24 +- arch/arm/dts/armada-8040-mcbin.dts | 27 +- arch/arm/dts/armada-8040-puzzle-m801.dts | 32 +- arch/arm/dts/armada-cp110.dtsi | 36 +- arch/arm/dts/cn9130-crb-A.dts | 16 +- arch/arm/dts/cn9130-crb-B.dts | 16 +- board/CZ.NIC/turris_mox/turris_mox.c | 8 +- cmd/mvebu/Kconfig | 7 + cmd/mvebu/Makefile | 2 +- cmd/mvebu/rx_training.c | 57 ++ configs/mvebu_db_armada8k_defconfig | 1 + doc/device-tree-bindings/phy/mvebu_comphy.txt | 68 ++ drivers/phy/marvell/comphy_a3700.c | 70 +- drivers/phy/marvell/comphy_a3700.h | 1 - drivers/phy/marvell/comphy_core.c | 81 ++- drivers/phy/marvell/comphy_core.h | 67 +- drivers/phy/marvell/comphy_cp110.c | 621 ++++------------ drivers/phy/marvell/comphy_hpipe.h | 660 ------------------ drivers/phy/marvell/comphy_mux.c | 11 +- drivers/phy/marvell/utmi_phy.h | 24 +- include/dt-bindings/comphy/comphy_data.h | 80 +-- include/mvebu/comphy.h | 2 +- 29 files changed, 591 insertions(+), 1454 deletions(-) create mode 100644 cmd/mvebu/rx_training.c create mode 100644 doc/device-tree-bindings/phy/mvebu_comphy.txt delete mode 100644 drivers/phy/marvell/comphy_hpipe.h -- 2.31.0

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[PATCH V2] ARM: imx6: Update dhelectronics/dh_imx6/MAINTAINERS file
by Christoph Niedermaier 05 May '21

05 May '21

Adding new DH electronics mailing list and update list of maintainers. Signed-off-by: Christoph Niedermaier <cniedermaier(a)dh-electronics.com> --- V2: Correct message tag and update list of maintainers --- board/dhelectronics/dh_imx6/MAINTAINERS | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/board/dhelectronics/dh_imx6/MAINTAINERS b/board/dhelectronics/dh_imx6/MAINTAINERS index ab4e16bd5d..8f9b5ff2dc 100644 --- a/board/dhelectronics/dh_imx6/MAINTAINERS +++ b/board/dhelectronics/dh_imx6/MAINTAINERS @@ -1,6 +1,7 @@ DH_IMX6 BOARD M: Andreas Geisreiter <ageisreiter(a)dh-electronics.de> -M: Ludwig Zenz <lzenz(a)dh-electronics.de> +M: Christoph Niedermaier <cniedermaier(a)dh-electronics.com> +L: u-boot(a)dh-electronics.com S: Maintained F: board/dhelectronics/dh_imx6/ F: include/configs/dh_imx6.h -- 2.11.0

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