May 2021 - U-Boot

Re: [PATCH] riscv: Split SiFive CLINT support between SPL and U-Boot proper
by Rick Chen 18 May '21

18 May '21

> From: Bin Meng <bmeng.cn(a)gmail.com> > Sent: Tuesday, May 11, 2021 8:04 PM > To: Rick Jian-Zhi Chen(陳建志) <rick(a)andestech.com>; Sean Anderson <seanga2(a)gmail.com>; u-boot(a)lists.denx.de > Cc: Anup Patel <anup.patel(a)wdc.com>; Bin Meng <bmeng.cn(a)gmail.com> > Subject: [PATCH] riscv: Split SiFive CLINT support between SPL and U-Boot proper > > At present there is only one Kconfig option CONFIG_SIFIVE_CLINT to control the enabling of SiFive CLINT support in both SPL (M-mode) and U-Boot proper (S-mode). So for a typical SPL config that the SiFive CLINT driver is enabled in both SPL and U-Boot proper, that means the S-mode U-Boot tries to access the memory-mapped CLINT registers directly, instead of the normal 'rdtime' instruction. > > This was not a problem before, as the hardware does not forbid the access from S-mode. However this becomes an issue now with OpenSBI commit 8b569803475e ("lib: utils/sys: Add CLINT memregion in the root domain") that the SiFive CLINT register space is protected by PMP for M-mode access only. U-Boot proper does not boot any more with the latest OpenSBI, that access exceptions are fired forever from U-Boot when trying to read the timer value via the SiFive CLINT driver in U-Boot. > > To solve this, we need to split current SiFive CLINT support between SPL and U-Boot proper, using 2 separate Kconfig options. > > Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> > --- > > arch/riscv/Kconfig | 9 ++++++++- > arch/riscv/cpu/fu540/Kconfig | 2 +- > arch/riscv/cpu/generic/Kconfig | 3 ++- > arch/riscv/include/asm/global_data.h | 2 +- > arch/riscv/lib/Makefile | 2 +- > drivers/timer/Makefile | 2 +- > 6 files changed, 14 insertions(+), 6 deletions(-) Reviewed-by: Rick Chen <rick(a)andestech.com>

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[PATCH 1/2] riscv: Fix memmove and optimise memcpy when misalign
by Bin Meng 18 May '21

18 May '21

At present U-Boot SPL fails to boot on SiFive Unleashed board, due to a load address misaligned exception happens when loading the FIT image in spl_load_simple_fit(). The exception happens in memmove() which is called by fdt_splice_(). Commit 8f0dc4cfd106 introduces an assembly version of memmove but it does take misalignment into account (it checks if length is a multiple of machine word size but pointers need also be aligned). As a result it will generate misaligned load/store for the majority of cases and causes significant performance regression on hardware that traps misaligned load/store and emulate them using firmware. The current behaviour of memcpy is that it checks if both src and dest pointers are co-aligned (aka congruent modular SZ_REG). If aligned, it will copy data word-by-word after first aligning pointers to word boundary. If src and dst are not co-aligned, however, byte-wise copy will be performed. This patch was taken from the Linux kernel patch [1], which has not been applied at the time being. It fixes the memmove and optimises memcpy for misaligned cases. It will first align destination pointer to word-boundary regardless whether src and dest are co-aligned or not. If they indeed are, then wordwise copy is performed. If they are not co-aligned, then it will load two adjacent words from src and use shifts to assemble a full machine word. Some additional assembly level micro-optimisation is also performed to ensure more instructions can be compressed (e.g. prefer a0 to t6). With this patch, U-Boot boots again on SiFive Unleashed board. [1] https://patchwork.kernel.org/project/linux-riscv/patch/20210216225555.4976-… Fixes: 8f0dc4cfd106 ("riscv: assembler versions of memcpy, memmove, memset") Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- arch/riscv/lib/memcpy.S | 223 ++++++++++++++++++++++++--------------- arch/riscv/lib/memmove.S | 176 ++++++++++++++++++++---------- 2 files changed, 257 insertions(+), 142 deletions(-) diff --git a/arch/riscv/lib/memcpy.S b/arch/riscv/lib/memcpy.S index 51ab716253..00672c19ad 100644 --- a/arch/riscv/lib/memcpy.S +++ b/arch/riscv/lib/memcpy.S @@ -9,100 +9,151 @@ /* void *memcpy(void *, const void *, size_t) */ ENTRY(__memcpy) WEAK(memcpy) - move t6, a0 /* Preserve return value */ + /* Save for return value */ + mv t6, a0 - /* Defer to byte-oriented copy for small sizes */ - sltiu a3, a2, 128 - bnez a3, 4f - /* Use word-oriented copy only if low-order bits match */ - andi a3, t6, SZREG-1 - andi a4, a1, SZREG-1 - bne a3, a4, 4f + /* + * Register allocation for code below: + * a0 - start of uncopied dst + * a1 - start of uncopied src + * t0 - end of uncopied dst + */ + add t0, a0, a2 - beqz a3, 2f /* Skip if already aligned */ /* - * Round to nearest double word-aligned address - * greater than or equal to start address + * Use bytewise copy if too small. + * + * This threshold must be at least 2*SZREG to ensure at least one + * wordwise copy is performed. It is chosen to be 16 because it will + * save at least 7 iterations of bytewise copy, which pays off the + * fixed overhead. */ - andi a3, a1, ~(SZREG-1) - addi a3, a3, SZREG - /* Handle initial misalignment */ - sub a4, a3, a1 + li a3, 16 + bltu a2, a3, .Lbyte_copy_tail + + /* + * Bytewise copy first to align a0 to word boundary. + */ + addi a2, a0, SZREG-1 + andi a2, a2, ~(SZREG-1) + beq a0, a2, 2f 1: - lb a5, 0(a1) - addi a1, a1, 1 - sb a5, 0(t6) - addi t6, t6, 1 - bltu a1, a3, 1b - sub a2, a2, a4 /* Update count */ + lb a5, 0(a1) + addi a1, a1, 1 + sb a5, 0(a0) + addi a0, a0, 1 + bne a0, a2, 1b +2: + + /* + * Now a0 is word-aligned. If a1 is also word aligned, we could perform + * aligned word-wise copy. Otherwise we need to perform misaligned + * word-wise copy. + */ + andi a3, a1, SZREG-1 + bnez a3, .Lmisaligned_word_copy + /* Unrolled wordwise copy */ + addi t0, t0, -(16*SZREG-1) + bgeu a0, t0, 2f +1: + REG_L a2, 0(a1) + REG_L a3, SZREG(a1) + REG_L a4, 2*SZREG(a1) + REG_L a5, 3*SZREG(a1) + REG_L a6, 4*SZREG(a1) + REG_L a7, 5*SZREG(a1) + REG_L t1, 6*SZREG(a1) + REG_L t2, 7*SZREG(a1) + REG_L t3, 8*SZREG(a1) + REG_L t4, 9*SZREG(a1) + REG_L t5, 10*SZREG(a1) + REG_S a2, 0(a0) + REG_S a3, SZREG(a0) + REG_S a4, 2*SZREG(a0) + REG_S a5, 3*SZREG(a0) + REG_S a6, 4*SZREG(a0) + REG_S a7, 5*SZREG(a0) + REG_S t1, 6*SZREG(a0) + REG_S t2, 7*SZREG(a0) + REG_S t3, 8*SZREG(a0) + REG_S t4, 9*SZREG(a0) + REG_S t5, 10*SZREG(a0) + REG_L a2, 11*SZREG(a1) + REG_L a3, 12*SZREG(a1) + REG_L a4, 13*SZREG(a1) + REG_L a5, 14*SZREG(a1) + REG_L a6, 15*SZREG(a1) + addi a1, a1, 16*SZREG + REG_S a2, 11*SZREG(a0) + REG_S a3, 12*SZREG(a0) + REG_S a4, 13*SZREG(a0) + REG_S a5, 14*SZREG(a0) + REG_S a6, 15*SZREG(a0) + addi a0, a0, 16*SZREG + bltu a0, t0, 1b 2: - andi a4, a2, ~((16*SZREG)-1) - beqz a4, 4f - add a3, a1, a4 -3: - REG_L a4, 0(a1) - REG_L a5, SZREG(a1) - REG_L a6, 2*SZREG(a1) - REG_L a7, 3*SZREG(a1) - REG_L t0, 4*SZREG(a1) - REG_L t1, 5*SZREG(a1) - REG_L t2, 6*SZREG(a1) - REG_L t3, 7*SZREG(a1) - REG_L t4, 8*SZREG(a1) - REG_L t5, 9*SZREG(a1) - REG_S a4, 0(t6) - REG_S a5, SZREG(t6) - REG_S a6, 2*SZREG(t6) - REG_S a7, 3*SZREG(t6) - REG_S t0, 4*SZREG(t6) - REG_S t1, 5*SZREG(t6) - REG_S t2, 6*SZREG(t6) - REG_S t3, 7*SZREG(t6) - REG_S t4, 8*SZREG(t6) - REG_S t5, 9*SZREG(t6) - REG_L a4, 10*SZREG(a1) - REG_L a5, 11*SZREG(a1) - REG_L a6, 12*SZREG(a1) - REG_L a7, 13*SZREG(a1) - REG_L t0, 14*SZREG(a1) - REG_L t1, 15*SZREG(a1) - addi a1, a1, 16*SZREG - REG_S a4, 10*SZREG(t6) - REG_S a5, 11*SZREG(t6) - REG_S a6, 12*SZREG(t6) - REG_S a7, 13*SZREG(t6) - REG_S t0, 14*SZREG(t6) - REG_S t1, 15*SZREG(t6) - addi t6, t6, 16*SZREG - bltu a1, a3, 3b - andi a2, a2, (16*SZREG)-1 /* Update count */ - -4: - /* Handle trailing misalignment */ - beqz a2, 6f - add a3, a1, a2 - - /* Use word-oriented copy if co-aligned to word boundary */ - or a5, a1, t6 - or a5, a5, a3 - andi a5, a5, 3 - bnez a5, 5f -7: - lw a4, 0(a1) - addi a1, a1, 4 - sw a4, 0(t6) - addi t6, t6, 4 - bltu a1, a3, 7b + /* Post-loop increment by 16*SZREG-1 and pre-loop decrement by SZREG-1 */ + addi t0, t0, 15*SZREG - ret + /* Wordwise copy */ + bgeu a0, t0, 2f +1: + REG_L a5, 0(a1) + addi a1, a1, SZREG + REG_S a5, 0(a0) + addi a0, a0, SZREG + bltu a0, t0, 1b +2: + addi t0, t0, SZREG-1 -5: - lb a4, 0(a1) - addi a1, a1, 1 - sb a4, 0(t6) - addi t6, t6, 1 - bltu a1, a3, 5b -6: +.Lbyte_copy_tail: + /* + * Bytewise copy anything left. + */ + beq a0, t0, 2f +1: + lb a5, 0(a1) + addi a1, a1, 1 + sb a5, 0(a0) + addi a0, a0, 1 + bne a0, t0, 1b +2: + + mv a0, t6 ret + +.Lmisaligned_word_copy: + /* + * Misaligned word-wise copy. + * For misaligned copy we still perform word-wise copy, but we need to + * use the value fetched from the previous iteration and do some shifts. + * This is safe because we wouldn't access more words than necessary. + */ + + /* Calculate shifts */ + slli t3, a3, 3 + sub t4, x0, t3 /* negate is okay as shift will only look at LSBs */ + + /* Load the initial value and align a1 */ + andi a1, a1, ~(SZREG-1) + REG_L a5, 0(a1) + + addi t0, t0, -(SZREG-1) + /* At least one iteration will be executed here, no check */ +1: + srl a4, a5, t3 + REG_L a5, SZREG(a1) + addi a1, a1, SZREG + sll a2, a5, t4 + or a2, a2, a4 + REG_S a2, 0(a0) + addi a0, a0, SZREG + bltu a0, t0, 1b + + /* Update pointers to correct value */ + addi t0, t0, SZREG-1 + add a1, a1, a3 + + j .Lbyte_copy_tail END(__memcpy) diff --git a/arch/riscv/lib/memmove.S b/arch/riscv/lib/memmove.S index 07d1d2152b..fbe6701dbe 100644 --- a/arch/riscv/lib/memmove.S +++ b/arch/riscv/lib/memmove.S @@ -5,60 +5,124 @@ ENTRY(__memmove) WEAK(memmove) - move t0, a0 - move t1, a1 - - beq a0, a1, exit_memcpy - beqz a2, exit_memcpy - srli t2, a2, 0x2 - - slt t3, a0, a1 - beqz t3, do_reverse - - andi a2, a2, 0x3 - li t4, 1 - beqz t2, byte_copy - -word_copy: - lw t3, 0(a1) - addi t2, t2, -1 - addi a1, a1, 4 - sw t3, 0(a0) - addi a0, a0, 4 - bnez t2, word_copy - beqz a2, exit_memcpy - j byte_copy - -do_reverse: - add a0, a0, a2 - add a1, a1, a2 - andi a2, a2, 0x3 - li t4, -1 - beqz t2, reverse_byte_copy - -reverse_word_copy: - addi a1, a1, -4 - addi t2, t2, -1 - lw t3, 0(a1) - addi a0, a0, -4 - sw t3, 0(a0) - bnez t2, reverse_word_copy - beqz a2, exit_memcpy - -reverse_byte_copy: - addi a0, a0, -1 - addi a1, a1, -1 - -byte_copy: - lb t3, 0(a1) - addi a2, a2, -1 - sb t3, 0(a0) - add a1, a1, t4 - add a0, a0, t4 - bnez a2, byte_copy - -exit_memcpy: - move a0, t0 - move a1, t1 - ret + /* + * Here we determine if forward copy is possible. Forward copy is + * preferred to backward copy as it is more cache friendly. + * + * If a0 >= a1, t0 gives their distance, if t0 >= a2 then we can + * copy forward. + * If a0 < a1, we can always copy forward. This will make t0 negative, + * so a *unsigned* comparison will always have t0 >= a2. + * + * For forward copy we just delegate the task to memcpy. + */ + sub t0, a0, a1 + bltu t0, a2, 1f + tail __memcpy +1: + + /* + * Register allocation for code below: + * a0 - end of uncopied dst + * a1 - end of uncopied src + * t0 - start of uncopied dst + */ + mv t0, a0 + add a0, a0, a2 + add a1, a1, a2 + + /* + * Use bytewise copy if too small. + * + * This threshold must be at least 2*SZREG to ensure at least one + * wordwise copy is performed. It is chosen to be 16 because it will + * save at least 7 iterations of bytewise copy, which pays off the + * fixed overhead. + */ + li a3, 16 + bltu a2, a3, .Lbyte_copy_tail + + /* + * Bytewise copy first to align t0 to word boundary. + */ + andi a2, a0, ~(SZREG-1) + beq a0, a2, 2f +1: + addi a1, a1, -1 + lb a5, 0(a1) + addi a0, a0, -1 + sb a5, 0(a0) + bne a0, a2, 1b +2: + + /* + * Now a0 is word-aligned. If a1 is also word aligned, we could perform + * aligned word-wise copy. Otherwise we need to perform misaligned + * word-wise copy. + */ + andi a3, a1, SZREG-1 + bnez a3, .Lmisaligned_word_copy + + /* Wordwise copy */ + addi t0, t0, SZREG-1 + bleu a0, t0, 2f +1: + addi a1, a1, -SZREG + REG_L a5, 0(a1) + addi a0, a0, -SZREG + REG_S a5, 0(a0) + bgtu a0, t0, 1b +2: + addi t0, t0, -(SZREG-1) + +.Lbyte_copy_tail: + /* + * Bytewise copy anything left. + */ + beq a0, t0, 2f +1: + addi a1, a1, -1 + lb a5, 0(a1) + addi a0, a0, -1 + sb a5, 0(a0) + bne a0, t0, 1b +2: + + mv a0, t0 + ret + +.Lmisaligned_word_copy: + /* + * Misaligned word-wise copy. + * For misaligned copy we still perform word-wise copy, but we need to + * use the value fetched from the previous iteration and do some shifts. + * This is safe because we wouldn't access more words than necessary. + */ + + /* Calculate shifts */ + slli t3, a3, 3 + sub t4, x0, t3 /* negate is okay as shift will only look at LSBs */ + + /* Load the initial value and align a1 */ + andi a1, a1, ~(SZREG-1) + REG_L a5, 0(a1) + + addi t0, t0, SZREG-1 + /* At least one iteration will be executed here, no check */ +1: + sll a4, a5, t4 + addi a1, a1, -SZREG + REG_L a5, 0(a1) + srl a2, a5, t3 + or a2, a2, a4 + addi a0, a0, -SZREG + REG_S a2, 0(a0) + bgtu a0, t0, 1b + + /* Update pointers to correct value */ + addi t0, t0, -(SZREG-1) + add a1, a1, a3 + + j .Lbyte_copy_tail + END(__memmove) -- 2.25.1

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Please pull u-boot-marvell/master v2
by Stefan Roese 17 May '21

17 May '21

please pull the next batch of Marvell Armada related patches. Here the summary log: ---------------------------------------------------------------- - Add base support for Marvell OcteonTX2 CN9130 DB (mostly done by Kostya) - Sync Armada 8k MMU setup with Marvell version (misc Marvell authors) - spi: kirkwood: Some fixes especially for baudrate generation (misc Marvell authors) - mvebu: x530: Reduce SPL image size (Stefan) - Rename "rx_training" to "mvebu_comphy_rx_training" (Stefan) ---------------------------------------------------------------- Here the Azure build without any issues: https://dev.azure.com/sr0718/u-boot/_build/results?buildId=89&view=results I've dropped the mvpp2 ethernet driver sync with the PHY header extension as it introduces some issues on xilinx_versal_virt which need to be investigated. Thanks, Stefan The following changes since commit e644dfbb1786a4a3308b068e1f61cd9e2dfac237: configs: Resync with savedefconfig (2021-05-15 08:10:13 -0400) are available in the Git repository at: git@source.denx.de:u-boot/custodians/u-boot-marvell.git for you to fetch changes up to e1c55dfc7b59e8e49fc400290b3bea8066b74de1: arm: octeontx2: Add Octeon TX2 CN913x DB support (2021-05-16 06:48:45 +0200) ---------------------------------------------------------------- Grzegorz Jaszczyk (4): spi: kirkwood: prevent limiting speed to 0 arm64: mvebu: do not map firmware RT service region arm64: mvebu: a8k: move firmware related definitions to fw info arm64: mvebu: extend the mmio region Ken Ma (1): spi: kirkwood: support extended baud rates Konstantin Porotchkin (2): arm: octeontx2: Add dtsi/dts files for Octeon TX2 CN913x DB arm: octeontx2: Add Octeon TX2 CN913x DB support Marcin Wojtas (2): spi: kirkwood: prevent configuring speed exceeding max controller freq pcie: designware: mvebu: do not configure ATU for IO when not used Stefan Roese (2): mvebu: x530: Reduce SPL image size cmd: mvebu: Rename rx_training to mvebu_comphy_rx_training jinghua (1): arm64: mvebu: a8k: align memory regions arch/arm/dts/Makefile | 6 + arch/arm/dts/cn9130-db-A.dts | 55 ++++ arch/arm/dts/cn9130-db-B.dts | 51 ++++ arch/arm/dts/cn9130-db-dev-info.dtsi | 44 +++ arch/arm/dts/cn9130-db.dtsi | 316 ++++++++++++++++++++++ arch/arm/dts/cn9131-db-A.dts | 54 ++++ arch/arm/dts/cn9131-db-B.dts | 69 +++++ arch/arm/dts/cn9131-db.dtsi | 166 ++++++++++++ arch/arm/dts/cn9132-db-A.dts | 13 + arch/arm/dts/cn9132-db-B.dts | 13 + arch/arm/dts/cn9132-db.dtsi | 217 +++++++++++++++ arch/arm/mach-mvebu/armada8k/cpu.c | 70 ++--- arch/arm/mach-mvebu/include/mach/fw_info.h | 18 ++ board/Marvell/octeontx2_cn913x/MAINTAINERS | 1 + board/Marvell/octeontx2_cn913x/README | 24 ++ cmd/mvebu/Kconfig | 9 +- cmd/mvebu/Makefile | 2 +- cmd/mvebu/{rx_training.c => comphy_rx_training.c} | 10 +- configs/mvebu_db_cn9130_defconfig | 89 ++++++ configs/x530_defconfig | 2 +- drivers/pci/pcie_dw_mvebu.c | 37 ++- drivers/spi/kirkwood_spi.c | 67 ++++- 22 files changed, 1250 insertions(+), 83 deletions(-) create mode 100644 arch/arm/dts/cn9130-db-A.dts create mode 100644 arch/arm/dts/cn9130-db-B.dts create mode 100644 arch/arm/dts/cn9130-db-dev-info.dtsi create mode 100644 arch/arm/dts/cn9130-db.dtsi create mode 100644 arch/arm/dts/cn9131-db-A.dts create mode 100644 arch/arm/dts/cn9131-db-B.dts create mode 100644 arch/arm/dts/cn9131-db.dtsi create mode 100644 arch/arm/dts/cn9132-db-A.dts create mode 100644 arch/arm/dts/cn9132-db-B.dts create mode 100644 arch/arm/dts/cn9132-db.dtsi create mode 100644 arch/arm/mach-mvebu/include/mach/fw_info.h create mode 100644 board/Marvell/octeontx2_cn913x/README rename cmd/mvebu/{rx_training.c => comphy_rx_training.c} (74%) create mode 100644 configs/mvebu_db_cn9130_defconfig

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[PULL] u-boot-usb/master
by Marek Vasut 17 May '21

17 May '21

The following changes since commit e644dfbb1786a4a3308b068e1f61cd9e2dfac237: configs: Resync with savedefconfig (2021-05-15 08:10:13 -0400) are available in the Git repository at: git://source.denx.de/u-boot-usb.git master for you to fetch changes up to a5f9be1ed5a5e3a89478edd2f544e667046cd5ea: usb: dwc3-generic: Disable host driver definition if gadget only (2021-05-16 19:01:45 +0200) ---------------------------------------------------------------- Andre Przywara (1): usb: musb-new: Extend and move Allwinner quirk into Kconfig Kunihiko Hayashi (1): usb: dwc3-generic: Disable host driver definition if gadget only drivers/usb/dwc3/dwc3-generic.c | 3 ++- drivers/usb/musb-new/Kconfig | 10 ++++++++++ drivers/usb/musb-new/musb_regs.h | 3 +-- 3 files changed, 13 insertions(+), 3 deletions(-)

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[PATCH] imx: Add SeeedStudio NPI-IMX6ULL Support
by Navin Sankar Velliangiri 17 May '21

17 May '21

From: NavinSankar Velliangiri <navin(a)linumiz.com> CPU: Freescale i.MX6ULL rev1.1 792 MHz (running at 396 MHz) CPU: Industrial temperature grade (-40C to 105C) at 49C Reset cause: POR Model: Seeed NPi iMX6ULL Dev Board with NAND Board: Seeed NPi i.MX6ULL Dev Board DRAM: 512 MiB NAND: 512 MiB MMC: FSL_SDHC: 0 In: serial@2020000 Out: serial@2020000 Err: serial@2020000 Net: FEC0 Working: - Eth0 - MMC/SD - NAND - UART 1 - USB host Signed-off-by: NavinSankar Velliangiri <navin(a)linumiz.com> --- arch/arm/Kconfig | 1 + arch/arm/dts/Makefile | 1 + .../imx6ull-seeed-npi-imx6ull-dev-board.dts | 19 ++ .../dts/imx6ull-seeed-npi-imx6ull-u-boot.dtsi | 24 ++ arch/arm/dts/imx6ull-seeed-npi-imx6ull.dtsi | 271 ++++++++++++++++++ arch/arm/mach-imx/mx6/Kconfig | 11 + board/seeed/npi_imx6ull/Kconfig | 12 + board/seeed/npi_imx6ull/MAINTAINERS | 9 + board/seeed/npi_imx6ull/Makefile | 4 + board/seeed/npi_imx6ull/README | 61 ++++ board/seeed/npi_imx6ull/npi_imx6ull.c | 114 ++++++++ board/seeed/npi_imx6ull/spl.c | 205 +++++++++++++ configs/seeed_npi_imx6ull_defconfig | 80 ++++++ include/configs/npi_imx6ull.h | 96 +++++++ 14 files changed, 908 insertions(+) create mode 100644 arch/arm/dts/imx6ull-seeed-npi-imx6ull-dev-board.dts create mode 100644 arch/arm/dts/imx6ull-seeed-npi-imx6ull-u-boot.dtsi create mode 100644 arch/arm/dts/imx6ull-seeed-npi-imx6ull.dtsi create mode 100644 board/seeed/npi_imx6ull/Kconfig create mode 100644 board/seeed/npi_imx6ull/MAINTAINERS create mode 100644 board/seeed/npi_imx6ull/Makefile create mode 100644 board/seeed/npi_imx6ull/README create mode 100644 board/seeed/npi_imx6ull/npi_imx6ull.c create mode 100644 board/seeed/npi_imx6ull/spl.c create mode 100644 configs/seeed_npi_imx6ull_defconfig create mode 100644 include/configs/npi_imx6ull.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 31d687ea01..3c46f3ff39 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -2008,6 +2008,7 @@ source "board/hisilicon/poplar/Kconfig" source "board/isee/igep003x/Kconfig" source "board/kontron/sl28/Kconfig" source "board/myir/mys_6ulx/Kconfig" +source "board/seeed/npi_imx6ull/Kconfig" source "board/spear/spear300/Kconfig" source "board/spear/spear310/Kconfig" source "board/spear/spear320/Kconfig" diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index aec5020a0f..6cbaafcc73 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -798,6 +798,7 @@ dtb-$(CONFIG_MX6ULL) += \ imx6ull-14x14-evk.dtb \ imx6ull-colibri.dtb \ imx6ull-myir-mys-6ulx-eval.dtb \ + imx6ull-seeed-npi-imx6ull-dev-board.dtb \ imx6ull-phytec-segin-ff-rdk-emmc.dtb \ imx6ull-dart-6ul.dtb \ imx6ull-somlabs-visionsom.dtb \ diff --git a/arch/arm/dts/imx6ull-seeed-npi-imx6ull-dev-board.dts b/arch/arm/dts/imx6ull-seeed-npi-imx6ull-dev-board.dts new file mode 100644 index 0000000000..d08071a026 --- /dev/null +++ b/arch/arm/dts/imx6ull-seeed-npi-imx6ull-dev-board.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2021 Linumiz + * Author: NavinSankar Velliangiri <navin(a)linumiz.com> + */ + +/dts-v1/; +#include "imx6ull.dtsi" +#include "imx6ull-seeed-npi-imx6ull.dtsi" +#include "imx6ull-seeed-npi-imx6ull-u-boot.dtsi" + +/ { + model = "Seeed NPi iMX6ULL Dev Board with NAND"; + compatible = "seeed, imx6ull-seeed-npi-imx6ull", "fsl,imx6ull"; +}; + +&gpmi { + status = "okay"; +}; diff --git a/arch/arm/dts/imx6ull-seeed-npi-imx6ull-u-boot.dtsi b/arch/arm/dts/imx6ull-seeed-npi-imx6ull-u-boot.dtsi new file mode 100644 index 0000000000..262f8be360 --- /dev/null +++ b/arch/arm/dts/imx6ull-seeed-npi-imx6ull-u-boot.dtsi @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2021 Linumiz + * Author: NavinSankar Velliangiri <navin(a)linumiz.com> + */ + +&pinctrl_uart1 { + u-boot,dm-pre-reloc; +}; + +&gpmi { + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; + +&usdhc1 { + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; + +&usdhc2 { + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/imx6ull-seeed-npi-imx6ull.dtsi b/arch/arm/dts/imx6ull-seeed-npi-imx6ull.dtsi new file mode 100644 index 0000000000..04be7a4d9f --- /dev/null +++ b/arch/arm/dts/imx6ull-seeed-npi-imx6ull.dtsi @@ -0,0 +1,271 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2021 Linumiz + * Author: NavinSankar Velliangiri <navin(a)linumiz.com> + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/pwm/pwm.h> + +/ { + model = "Seeed NPi-iMX6ULL Dev Board"; + compatible = "fsl,imx6ull"; + + chosen { + stdout-path = &uart1; + }; + + leds { + compatible = "gpio-leds"; + + user-led { + label = "User"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpios>; + gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + nand-on-flash-bbt; + status = "disabled"; +}; + +&uart1 { + pinctrl-name = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + no-1-8-v; + keep-power-in-suspend; + wakeup-source; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + bus-width = <8>; + non-removable; + keep-power-in-suspend; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-handle = <&ethphy0>; + status = "okay"; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + phy-mode = "rmii"; + phy-handle = <&ethphy1>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <2>; + micrel,led-mode = <1>; + clocks = <&clks IMX6UL_CLK_ENET_REF>; + clock-names = "rmii-ref"; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + micrel,led-mode = <1>; + clocks = <&clks IMX6UL_CLK_ENET2_REF>; + clock-names = "rmii-ref"; + }; + }; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1_id>; + dr_mode = "otg"; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpios>; + + pinctrl_uart1: uart1grp { + fsl,pin = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_usb_otg1_id: usbotg1idgrp { + fsl,pin = < + MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 + >; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6UL_PAD_NAND_DQS__RAWNAND_DQS 0x0b0b1 + MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x0b0b1 + MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0b0b1 + MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x0b0b1 + MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000 + MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0b0b1 + MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B 0x0b0b1 + MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0b0b1 + MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x0b0b1 + MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0b0b1 + MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0b0b1 + MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0b0b1 + MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x0b0b1 + MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0b0b1 + MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0b0b1 + MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0b0b1 + MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x0b0b1 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 + >; + }; + + pinctrl_gpios: gpiosgrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0b0b0 + >; + }; +}; diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index 9450e6a683..c313698423 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -453,6 +453,17 @@ config TARGET_NITROGEN6X imply USB_ETHER_SMSC95XX imply USB_HOST_ETHER +config TARGET_NPI_IMX6ULL + bool "Seeed NPI-IMX6ULL" + depends on MX6ULL + select DM + select DM_ETH + select DM_MMC + select DM_GPIO + select DM_SERIAL + select DM_THERMAL + select SUPPORT_SPL + config TARGET_OPOS6ULDEV bool "Armadeus OPOS6ULDev board" depends on MX6UL diff --git a/board/seeed/npi_imx6ull/Kconfig b/board/seeed/npi_imx6ull/Kconfig new file mode 100644 index 0000000000..5e298299a3 --- /dev/null +++ b/board/seeed/npi_imx6ull/Kconfig @@ -0,0 +1,12 @@ +if TARGET_NPI_IMX6ULL + +config SYS_BOARD + default "npi_imx6ull" + +config SYS_VENDOR + default "seeed" + +config SYS_CONFIG_NAME + default "npi_imx6ull" + +endif diff --git a/board/seeed/npi_imx6ull/MAINTAINERS b/board/seeed/npi_imx6ull/MAINTAINERS new file mode 100644 index 0000000000..8eb66d8839 --- /dev/null +++ b/board/seeed/npi_imx6ull/MAINTAINERS @@ -0,0 +1,9 @@ +NPI_IMX6ULL BOARD +M: NavinSankar Velliangiri <navin(a)linumiz.com> +S: Maintained +F: arch/arm/dts/imx6ull-seeed-npi-imx6ull-dev-board.dts +F: arch/arm/dts/imx6ull-seeed-npi-imx6ull-u-boot.dtsi +F: arch/arm/dts/imx6ull-seeed-npi-imx6ull.dtsi +F: board/seeed/npi-imx6ull/ +F: configs/seeed_npi_imx6ull_defconfig +F: include/configs/npi_imx6ull.h diff --git a/board/seeed/npi_imx6ull/Makefile b/board/seeed/npi_imx6ull/Makefile new file mode 100644 index 0000000000..93ea413517 --- /dev/null +++ b/board/seeed/npi_imx6ull/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-y := npi_imx6ull.o +obj-$(CONFIG_SPL_BUILD) += spl.o diff --git a/board/seeed/npi_imx6ull/README b/board/seeed/npi_imx6ull/README new file mode 100644 index 0000000000..01d218a9bc --- /dev/null +++ b/board/seeed/npi_imx6ull/README @@ -0,0 +1,61 @@ +How to use U-BOOT on SeeedStudio NPI-IMX6ULL Single Board Computer +------------------------------------------------------------------ + +- Configure and build U-Boot for NPI-IMX6ULL: + + $ export ARCH=arm + $ export CROSS_COMPILE=arm-none-linux-gnueabihf- + $ make seeed_npi_imx6ull_defconfig + $ make + +This will generate SPL and u-boot-dtb.img images. + +Boot from MMC/SD: +- The SPL and u-boot-dtb.img images need to be flashed into the micro SD card: + + $ sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync + $ sudo dd if=u-boot-dtb.img of=/dev/mmcblk0 bs=1k seek=69; sync + +- Boot mode settings: + + Boot switch position: SW1 -> 0 + SW2 -> 1 + SW3 -> 0 + SW4 -> 0 + SW5 -> 1 + SW6 -> 0 + SW7 -> 0 + SW8 -> 1 + +Boot from NAND: +- Boot the board using SD/MMC or Serial download and load the SPL into memory +either from SD/MMC or TFTP. + +Default MTD layout is 512k(spl),1m(uboot),1m(uboot-dup),-(ubi) + +Flash SPL to NAND from SD/MMC, + + $ ext4load mmc 0:2 $loadaddr SPL + $ nand erase.part spl + $ nandbcb init $loadaddr 0x0 $filesize + +Flash u-boot image to NAND from SD/MMC, + + $ ext4load mmc 0:2 $loadaddr u-boot-dtb.img + $ nand erase.part uboot + $ nand write $loadaddr uboot $filesize + +- Boot mode settings: + + Boot switch position: SW1 -> 0 + SW2 -> 1 + SW3 -> 1 + SW4 -> 0 + SW5 -> 0 + SW6 -> 1 + SW7 -> 0 + SW8 -> 0 + +- Connect the Serial cable to UART0 and the PC for the console. + +- Reset the board using reset button and U-Boot should boot from NAND. diff --git a/board/seeed/npi_imx6ull/npi_imx6ull.c b/board/seeed/npi_imx6ull/npi_imx6ull.c new file mode 100644 index 0000000000..06bb94484b --- /dev/null +++ b/board/seeed/npi_imx6ull/npi_imx6ull.c @@ -0,0 +1,114 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2021 Linumiz + * Author: NavinSankar Velliangiri <navin(a)linumiz.com> + */ + +#include <init.h> +#include <asm/arch/clock.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/iomux.h> +#include <asm/arch/mx6-pins.h> +#include <asm/arch/sys_proto.h> +#include <asm/mach-imx/iomux-v3.h> +#include <asm/mach-imx/mxc_i2c.h> +#include <fsl_esdhc_imx.h> +#include <linux/bitops.h> +#include <miiphy.h> +#include <net.h> +#include <netdev.h> +#include <usb.h> +#include <usb/ehci-ci.h> + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + gd->ram_size = imx_ddr_size(); + + return 0; +} + +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | \ + PAD_CTL_HYS) + +static iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); +} + +int board_early_init_f(void) +{ + setup_iomux_uart(); + + return 0; +} + +#ifdef CONFIG_FEC_MXC + +static int setup_fec(int fec_id) +{ + struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + int ret; + + if (fec_id == 0) { + /* + * Use 50MHz anatop loopback REF_CLK1 for ENET1, + * clear gpr1[13], set gpr1[17]. + */ + clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, + IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK); + } else { + /* + * Use 50MHz anatop loopbak REF_CLK2 for ENET2, + * clear gpr1[14], set gpr1[18]. + */ + clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, + IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK); + } + + ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ); + if (ret) + return ret; + + enable_enet_clk(1); + + return 0; +} + +int board_phy_config(struct phy_device *phydev) +{ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} +#endif + +int board_init(void) +{ + /* Address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + +#ifdef CONFIG_FEC_MXC + setup_fec(CONFIG_FEC_ENET_DEV); +#endif + + return 0; +} + +int checkboard(void) +{ + printf("Board: Seeed NPi i.MX6ULL Dev Board\n"); + + return 0; +} diff --git a/board/seeed/npi_imx6ull/spl.c b/board/seeed/npi_imx6ull/spl.c new file mode 100644 index 0000000000..1bfef54576 --- /dev/null +++ b/board/seeed/npi_imx6ull/spl.c @@ -0,0 +1,205 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2021 Linumiz + * Author: NavinSankar Velliangiri <navin(a)linumiz.com> + */ + +#include <common.h> +#include <init.h> +#include <spl.h> +#include <asm/arch/clock.h> +#include <asm/io.h> +#include <asm/arch/mx6-ddr.h> +#include <asm/arch/mx6-pins.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/sys_proto.h> +#include <fsl_esdhc_imx.h> + +/* Configuration for Micron MT41K256M16TW-107 32M x 16 x 8 -> 512MiB */ + +static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = { + .grp_addds = 0x00000030, + .grp_ddrmode_ctl = 0x00020000, + .grp_b0ds = 0x00000030, + .grp_ctlds = 0x00000030, + .grp_b1ds = 0x00000030, + .grp_ddrpke = 0x00000000, + .grp_ddrmode = 0x00020000, + .grp_ddr_type = 0x000c0000, +}; + +static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = { + .dram_dqm0 = 0x00000030, + .dram_dqm1 = 0x00000030, + .dram_ras = 0x00000030, + .dram_cas = 0x00000030, + .dram_odt0 = 0x00000030, + .dram_odt1 = 0x00000030, + .dram_sdba2 = 0x00000000, + .dram_sdclk_0 = 0x00000030, + .dram_sdqs0 = 0x00000030, + .dram_sdqs1 = 0x00000030, + .dram_reset = 0x00000030, +}; + +static struct mx6_mmdc_calibration mx6_mmcd_calib = { + .p0_mpwldectrl0 = 0x00000000, + .p0_mpdgctrl0 = 0x41480148, + .p0_mprddlctl = 0x40403E42, + .p0_mpwrdlctl = 0x40405852, +}; + +struct mx6_ddr_sysinfo ddr_sysinfo = { + .dsize = 0, /* Bus size = 16bit */ + .cs_density = 32, + .ncs = 1, + .cs1_mirror = 0, + .rtt_wr = 1, + .rtt_nom = 1, + .walat = 1, /* Write additional latency */ + .ralat = 5, /* Read additional latency */ + .mif3_mode = 3, /* Command prediction working mode */ + .bi_on = 1, /* Bank interleaving enabled */ + .pd_fast_exit = 1, + .sde_to_rst = 0x10, + .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ + .ddr_type = DDR_TYPE_DDR3, + .refsel = 1, /* Refresh cycles at 32KHz */ + .refr = 7, /* 8 refresh commands per refresh cycle */ +}; + +static struct mx6_ddr3_cfg mem_ddr = { + .mem_speed = 1600, + .density = 4, + .width = 16, + .banks = 8, + .rowaddr = 15, + .coladdr = 10, + .pagesz = 2, + .trcd = 1375, + .trcmin = 4875, + .trasmin = 3500, +}; + +static void ccgr_init(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + writel(0xFFFFFFFF, &ccm->CCGR0); + writel(0xFFFFFFFF, &ccm->CCGR1); + writel(0xFFFFFFFF, &ccm->CCGR2); + writel(0xFFFFFFFF, &ccm->CCGR3); + writel(0xFFFFFFFF, &ccm->CCGR4); + writel(0xFFFFFFFF, &ccm->CCGR5); + writel(0xFFFFFFFF, &ccm->CCGR6); +} + +static void spl_dram_init(void) +{ + mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); + mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr); +} + +#ifdef CONFIG_FSL_ESDHC_IMX + +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | \ + PAD_CTL_HYS) + +static iomux_v3_cfg_t const usdhc1_pads[] = { + MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_UART1_RTS_B__USDHC1_CD_B | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +#ifndef CONFIG_NAND_MXS +static iomux_v3_cfg_t const usdhc2_pads[] = { + MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; +#endif + +static struct fsl_esdhc_cfg usdhc_cfg[] = { + { + .esdhc_base = USDHC1_BASE_ADDR, + .max_bus_width = 4, + }, +#ifndef CONFIG_NAND_MXS + { + .esdhc_base = USDHC2_BASE_ADDR, + .max_bus_width = 8, + }, +#endif +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + return 1; +} + +int board_mmc_init(struct bd_info *bis) +{ + int i, ret; + + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + SETUP_IOMUX_PADS(usdhc1_pads); + usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + break; +#ifndef CONFIG_NAND_MXS + case 1: + SETUP_IOMUX_PADS(usdhc2_pads); + usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + break; +#endif + default: + printf("Warning - USDHC%d controller not supporting\n", + i + 1); + return 0; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) { + printf("Warning: failed to initialize mmc dev %d\n", i); + return ret; + } + } + + return 0; +} + +#endif /* CONFIG_FSL_ESDHC_IMX */ + +void board_init_f(ulong dummy) +{ + ccgr_init(); + + /* Setup AIPS and disable watchdog */ + arch_cpu_init(); + + /* Setup iomux and fec */ + board_early_init_f(); + + /* Setup GP timer */ + timer_init(); + + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); + + /* DDR initialization */ + spl_dram_init(); +} diff --git a/configs/seeed_npi_imx6ull_defconfig b/configs/seeed_npi_imx6ull_defconfig new file mode 100644 index 0000000000..6503cabbd0 --- /dev/null +++ b/configs/seeed_npi_imx6ull_defconfig @@ -0,0 +1,80 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SYS_TEXT_BASE=0x87800000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=8 +CONFIG_ENV_SIZE=0x4000 +CONFIG_MX6ULL=y +CONFIG_TARGET_NPI_IMX6ULL=y +CONFIG_SPL_TEXT_BASE=0x908000 +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ull-seeed-npi-imx6ull-dev-board" +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" +CONFIG_BOOTDELAY=3 +# CONFIG_USE_BOOTCOMMAND is not set +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_DMA=y +CONFIG_SPL_NAND_SUPPORT=y +CONFIG_SPL_USB_HOST_SUPPORT=y +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x90000000 +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_GPT=y +# CONFIG_RANDOM_UUID is not set +# CONFIG_CMD_I2C is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_CMD_USB=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand" +CONFIG_MTDPARTS_DEFAULT="gpmi-nand:512k(spl),1m(uboot),1m(uboot-dup),-(ubi)" +CONFIG_SYS_NAND_USE_FLASH_BBT=y +CONFIG_CMD_UBI=y +# CONFIG_ISO_PARTITION is not set +CONFIG_OF_CONTROL=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +# CONFIG_DM_I2C_GPIO is not set +# CONFIG_SYS_I2C_MXC is not set +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_RAW_NAND=y +CONFIG_NAND_MXS=y +CONFIG_NAND_MXS_DT=y +CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y +CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000 +CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND=0x180000 +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ8XXX=y +CONFIG_DM_ETH=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_PMIC=y +CONFIG_NET_RANDOM_ETHADDR=y +# CONFIG_SPL_PMIC_CHILDREN is not set +CONFIG_MMC=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_OFFSET=0x3c00000 +CONFIG_MXC_UART=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_GADGET=y +CONFIG_SMBIOS_MANUFACTURER="Seeed" diff --git a/include/configs/npi_imx6ull.h b/include/configs/npi_imx6ull.h new file mode 100644 index 0000000000..97ba4bc794 --- /dev/null +++ b/include/configs/npi_imx6ull.h @@ -0,0 +1,96 @@ +/* SPDX-License-Identifier: GPL-2.0+ + * + * Copyright (c) 2021 Linumiz + * Author: NavinSankar Velliangiri <navin(a)linumiz.com> + */ + +#ifndef _NPI_IMX6ULL_H +#define _NPI_IMX6ULL_H + +#include <linux/sizes.h> +#include "mx6_common.h" + +/* SPL options */ +#include "imx6_spl.h" + +#define CONFIG_SYS_FSL_USDHC_NUM 1 + +/* Size of malloc() poll */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (2 << 20)) + +/* Console configs */ +#define CONFIG_MXC_UART_BASE UART1_BASE + +/* MMC Configs */ +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR + +#define CONFIG_NETMASK 255.255.255.0 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_HZ 1000 + +/* Physical Memory Map */ +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* environment settings */ +#if defined(CONFIG_ENV_IS_IN_MMC) +#define CONFIG_SYS_MMC_ENV_DEV 0 +#elif defined(CONFIG_ENV_IS_IN_NAND) +#undef CONFIG_ENV_SIZE +#define CONFIG_ENV_SECT_SIZE (128 << 10) +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE +#endif + +/* NAND */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 + +/* USB Configs */ +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 + +#ifdef CONFIG_CMD_NET +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x1 +#define CONFIG_FEC_XCV_TYPE RMII +#define CONFIG_ETHPRIME "eth0" +#endif + +#define CONFIG_IMX_THERMAL + +#define CONFIG_FEC_ENET_DEV 1 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "console=ttymxc0,115200n8\0" \ + "image=zImage\0" \ + "fdtfile=imx6ull-seeed-npi-dev-board.dtb\0" \ + "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ + "fdt_addr_r=0x82000000\0" \ + "kernel_addr_r=0x81000000\0" \ + "pxefile_addr_r=0x87100000\0" \ + "ramdisk_addr_r=0x82100000\0" \ + "scriptaddr=0x87000000\0" \ + "root=/dev/mmcblk0p2 rootwait\0" \ + BOOTENV + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(UBIFS, ubifs, 0) \ + func(PXE, pxe, na) \ + func(DHCP, dhcp, na) + +#include <config_distro_bootcmd.h> + +#endif /* _NPI_IMX6ULL_H */ -- 2.31.1

2 1

[PATCH v2 00/28] fs/squashfs: fix memory leaks and introduce exists() function
by Richard Genoud 17 May '21

17 May '21

This patch series fix several memory leaks, some use of dangling pointers (leading to cpu freeze) and finally introduce the exists() function for squashfs. This function enable testing the existence of a file, which is mandatory for using the distro_bootcmd Those fixes have been cut into several patches to be easier to review Changes since v1: - patch 5: *dir = *file = NULL; is split in 2 lines - For consistency, sqfs_frag_lookup is modified to use a single "goto out" ( cf https://lists.denx.de/pipermail/u-boot/2020-October/429645.html ) - more memory leak fixes in sqfs_get_abs_path, sqfs_read and sqfs_probe - a missing error check typo in sqfs_get_abs_path - some missing reseting ctxt.sblk to NULL to prevent double free - reset cur_dev/cur_part_info to NULL when they are freed - return value of sqfs_decompressor_init() wasn't used - use "len" in sqfs_read to prevent writing beyond buffer - prevent reading with an offset since it doesn't work - prevent reading fragmented files since it doesn't work Richard Genoud (28): fs/squashfs: fix board hang-up when calling .exists() fs/squashfs: sqfs_opendir: fix some memory leaks and dangling pointers fs/squashfs: sqfs_opendir: simplify error handling fs/squashfs: sqfs_closedir: fix memory leak fs/squashfs: sqfs_split_path: fix memory leak and dangling pointers fs/squashfs: sqfs_read_directory_table: fix memory leak fs/squashfs: sqfs_search_dir: fix dangling pointer fs/squashfs: sqfs_search_dir: fix memory leaks fs/squashfs: sqfs_read_inode_table: fix dangling pointer fs/squashfs: sqfs_concat_tokens: check if malloc succeeds fs/squashfs: sqfs_size: fix dangling pointer dirs->entry fs/squashfs: sqfs_size: remove useless sqfs_closedir() fs/squashfs: sqfs_read: fix dangling pointer dirs->entry fs/squashfs: sqfs_read: remove useless sqfs_closedir() fs/squashfs: sqfs_read: fix memory leak fs/squashfs: sqfs_read: fix another memory leak fs/squashfs: sqfs_frag_lookup: simplify error handling fs/squashfs: sqfs_get_abs_path: fix error check fs/squashfs: sqfs_get_abs_path: fix possible memory leak on error fs/squashfs: sqfs_read: fix memory leak on finfo.blk_sizes fs/squashfs: sqfs_probe: fix possible memory leak on error fs/squashfs: sqfs_close/sqfs_read_sblk: set ctxt.sblk to NULL after free fs/squashfs: sqfs_probe: reset cur_dev/cur_part_info to NULL on error fs/squashfs: sqfs_probe: use sqfs_decompressor_init() return value fs/squashfs: sqfs_read: don't write beyond buffer size fs/squashfs: sqfs_read: remove buggy offset functionality fs/squashfs: sqfs_read: fragmented files are not supported fs/squashfs: implement exists() function fs/fs.c | 7 + fs/squashfs/sqfs.c | 399 +++++++++++++++++++++++++++++++-------------- include/squashfs.h | 1 + 3 files changed, 286 insertions(+), 121 deletions(-)

4 81

Unable to boot u-boot image from nand storage imx6ull.
by Navin Sankar 17 May '21

17 May '21

Hello all, Ported uboot to seeed studio based imx6ull <https://www.seeedstudio.com/NPi-i-MX6ULL-Dev-Board-Industrial-Grade-Linux-S…> board. NAND Part Number - mt29f4g08abaeawp NAND Size - 512 MBytes Both the SPL and U-BOOT image boot successfully from SD card. While with nand flash, SPL boot's fine. But SPL didn't boot the u-boot from nand flash. => mtdparts device nand0 <gpmi-nand>, # parts = 4 #: name size offset mask_flags 0: spl 0x00080000 0x00000000 0 1: uboot 0x00100000 0x00080000 0 2: uboot-dup 0x00100000 0x00180000 0 3: ubi 0x1fd80000 0x00280000 0 active partition: nand0,0 - (spl) 0x00080000 @ 0x00000000 defaults: mtdids : nand0=gpmi-nand mtdparts: gpmi-nand:512k(spl),1m(uboot),1m(uboot-dup),-(ubi) And I flashed the SPL and u-boot image from SD card. Here is flashing result, Initially erased the nand chip => nand erase.chip NAND erase.chip: device 0 whole chip Skipping bad block at 0x1ff00000 Skipping bad block at 0x1ff40000 Skipping bad block at 0x1ff80000 Skipping bad block at 0x1ffc0000 OK Then flashed the SPL => ext4load mmc 0:1 $loadaddr SPL 35840 bytes read in 4 ms (8.5 MiB/s) => nand erase.part spl NAND erase.part: device 0 offset 0x0, size 0x80000 Erasing at 0x40000 -- 100% complete. OK => nandbcb init $loadaddr 0x0 $filesize device 0 offset 0x0, size 0x8c00 Skipping bad block at 0x1ff00000 Skipping bad block at 0x1ff40000 Skipping bad block at 0x1ff80000 Skipping bad block at 0x1ffc0000 Write firmware0 @0x200000 offset, 0x9000 bytes written: OK Write firmware1 @0x10100000 offset, 0x9000 bytes written: OK NAND FCB write to 0x400 offset 0x0 written: OK NAND FCB write to 0x400 offset 0x40000 written: OK NAND FCB write to 0x400 offset 0x80000 written: OK NAND FCB write to 0x400 offset 0xc0000 written: OK NAND DBBT write to 0x100000 offset 0x1000 written: OK DBBT data write to 0x104000 offset 0x1000 written: OK NAND DBBT write to 0x140000 offset 0x1000 written: OK DBBT data write to 0x144000 offset 0x1000 written: OK NAND DBBT write to 0x180000 offset 0x1000 written: OK DBBT data write to 0x184000 offset 0x1000 written: OK NAND DBBT write to 0x1c0000 offset 0x1000 written: OK DBBT data write to 0x1c4000 offset 0x1000 written: OK Afterwards flashed the uboot image, => ext4load mmc 0:1 $loadaddr u-boot-dtb.img 624580 bytes read in 29 ms (20.5 MiB/s) => nand erase.part uboot NAND erase.part: device 0 offset 0x80000, size 0x100000 Erasing at 0x140000 -- 100% complete. OK => nand erase.part uboot-dup NAND erase.part: device 0 offset 0x180000, size 0x100000 Erasing at 0x240000 -- 100% complete. OK => nand write $loadaddr uboot $filesize NAND write: device 0 offset 0x80000, size 0x987c4 624580 bytes written: OK Everything work's fine, but it didn't boot the u-boot image from nand storage. U-Boot SPL 2021.07-rc1-02889-gf6058bbb94-dirty (May 01 2021 - 14:12:55 +0530) Trying to boot from NAND Any hint? -- Thanks and Regards, Navin Sankar N V,

2 4

[PATCH v5 00/10] Add support for extension boards detection and DT overlays application
by Kory Maincent 17 May '21

17 May '21

This series of patches aims at proposing a generic U-Boot mechanism to detect extension boards connected to the HW platform, and apply the appropriate Device Tree overlays depending on the detected extension boards. Indeed, numerous popular platforms, such as the BeagleBone or the RaspberryPi, feature some kind of extension board mechanism. These extension boards are often discoverable through some kind of EEPROM (connected on I2C, 1-wire, etc.) and require Device Tree overlays to be applied at the U-Boot level to provide a complete HW description to the Linux kernel. However, currently this logic is usually implemented ad-hoc in downstream forks of U-Boot. This series proposes to bring a HW-agnostic and generic solution to this problem to upstream U-Boot. The series shows that it is generic enough by implementing its usage for 2 different families of HW platforms and expansion boards: - The BeagleBone Black and BeagleBone AI, that use extension boards where the EEPROM describing the extension boards is connected over I2C. - The CHIP, that uses extension boards where the EEPROM describing the extension boards is connected over 1-wire. The patch series implements a new command called "extension", with two sub-commands: - "extension scan" to detect available extension boards - "extension list" will simply list the detected extension boards - "extension apply" will allow to apply the Device Tree overlays corresponding to one extension board or to all expansion boards Note that the name "extension" has been chosen to not refer to any particular board-specific terminology for extension boards ("cape" for BeagleBone, "DIP" for CHIP, "hat" for RaspberryPi, etc.). However, we welcome suggestions of other names and are definitely willing to use a different naming. The "extension apply" command requires two environment variables to be defined so that it knows how to apply DT overlays. This is described in more details in PATCH 1. This generic code requires board-specific code for the detection and enumeration of extension boards. This is simply implemented in the form of a board-specific extension_board_scan() function, which fills in a list of detected extension boards. In detail: - PATCH 1 move fdt_valid function to fdt_support file - PATCH 2 implements the generic command and logic - PATCH 3 implements the python test for the "extension" command - PATCH 4 implements the board-specific code for the BeagleBone platforms - PATCH 5 enables the mechanism for the BeagleBone AI - PATCH 6 review the detection mechanism of one-wire devices - PATCH 7 and 8 enable the mechanism for the CHIP - PATCH 9 and 10 enable the mechanism for the BeagleBone Black Thanks in advance for your review and feedback Change since v1: - remove the one wire devicetree description of the CHIP board - rewrite the detection of w1 to makes it automatic and not devicetree dependent - replace Kconfig CHIP board target by Kconfig CHIP_DIP_SCAN simple option - rewrite doc to rST syntax - make few syntax update Change since v2: - review the detection of w1 to makes it compatible with automatic detection alongside the devicetree description detection - update the patch separation between the mechanism for the CHIP and the configuration activation Change since v3: - Update commit messages on the extension command patch - Remove a test on CMD_EXTENSION in the chip.c file. Change since v4: - Rebase on master Kory Maincent (10): fdt_support: move fdt_valid from cmd_fdt.c to fdt_support.c cmd: add support for a new "extension" command pytest: add sandbox test for "extension" command ti/common: add support for extension_scan_board function am57xx: add support for cape detect functionality w1: replace dt detection by automatic detection arm: sunxi: add support for DIP detection to CHIP board configs: CHIP: add support for DIP detect functionality arm: am335x: add support for i2c2 bus am335x: add support for cape detect functionality arch/Kconfig | 2 + arch/arm/mach-omap2/am33xx/Kconfig | 1 + arch/arm/mach-omap2/am33xx/clock_am33xx.c | 1 + arch/arm/mach-omap2/omap5/Kconfig | 1 + arch/arm/mach-sunxi/Kconfig | 9 ++ arch/sandbox/dts/Makefile | 1 + arch/sandbox/dts/overlay0.dts | 9 ++ arch/sandbox/dts/overlay1.dts | 9 ++ board/sandbox/sandbox.c | 23 +++ board/sunxi/Makefile | 1 + board/sunxi/chip.c | 100 +++++++++++++ board/ti/am335x/board.c | 3 + board/ti/am335x/board.h | 1 + board/ti/am335x/mux.c | 15 ++ board/ti/am57xx/board.c | 1 + board/ti/common/Kconfig | 6 + board/ti/common/Makefile | 1 + board/ti/common/cape_detect.c | 96 +++++++++++++ board/ti/common/cape_detect.h | 28 ++++ cmd/Kconfig | 12 ++ cmd/Makefile | 1 + cmd/extension_board.c | 167 ++++++++++++++++++++++ cmd/fdt.c | 49 ------- common/fdt_support.c | 46 ++++++ configs/CHIP_defconfig | 1 + doc/usage/extension.rst | 111 ++++++++++++++ drivers/w1-eeprom/ds24xxx.c | 7 + drivers/w1-eeprom/ds2502.c | 6 + drivers/w1-eeprom/w1-eeprom-uclass.c | 31 ---- drivers/w1/w1-uclass.c | 76 +++++++++- include/extension_board.h | 31 ++++ include/fdt_support.h | 2 + include/w1-eeprom.h | 2 - include/w1.h | 17 +++ test/py/tests/test_extension.py | 52 +++++++ 35 files changed, 835 insertions(+), 84 deletions(-) create mode 100644 arch/sandbox/dts/overlay0.dts create mode 100644 arch/sandbox/dts/overlay1.dts create mode 100644 board/sunxi/chip.c create mode 100644 board/ti/common/cape_detect.c create mode 100644 board/ti/common/cape_detect.h create mode 100644 cmd/extension_board.c create mode 100644 doc/usage/extension.rst create mode 100644 include/extension_board.h create mode 100644 test/py/tests/test_extension.py -- 2.17.1

5 26

[PATCH] phy: add nxp tja1103 phy driver
by Radu Pirea (NXP OSS) 17 May '21

17 May '21

Add nxp tja1103 phy driver. Signed-off-by: Radu Pirea (NXP OSS) <radu-nicolae.pirea(a)oss.nxp.com> --- MAINTAINERS | 5 + drivers/net/phy/Kconfig | 6 + drivers/net/phy/Makefile | 1 + drivers/net/phy/nxp-c45-tja11xx.c | 348 ++++++++++++++++++++++++++++++ drivers/net/phy/phy.c | 3 + include/phy.h | 5 + 6 files changed, 368 insertions(+) create mode 100644 drivers/net/phy/nxp-c45-tja11xx.c diff --git a/MAINTAINERS b/MAINTAINERS index 20092cb367..737ba3b162 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -910,6 +910,11 @@ S: Maintained T: git https://source.denx.de/u-boot/custodians/u-boot-nios.git F: arch/nios2/ +NXP C45 TJA11XX PHY DRIVER +M: Radu Pirea <radu-nicolae.pirea(a)oss.nxp.com> +S: Maintained +F: drivers/net/phy/nxp-c45-tja11xx.c + ONENAND #M: Lukasz Majewski <l.majewski(a)majess.pl> S: Orphaned (Since 2017-01) diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index 070ffa82cb..405bf76753 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -197,6 +197,12 @@ config PHY_MSCC config PHY_NATSEMI bool "National Semiconductor Ethernet PHYs support" +config PHY_NXP_C45_TJA11XX + tristate "NXP C45 TJA11XX PHYs" + help + Enable support for NXP C45 TJA11XX PHYs. + Currently supports only the TJA1103 PHY. + config PHY_REALTEK bool "Realtek Ethernet PHYs support" diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile index e967f82201..218b8c7669 100644 --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile @@ -23,6 +23,7 @@ obj-$(CONFIG_PHY_MICREL_KSZ8XXX) += micrel_ksz8xxx.o obj-$(CONFIG_PHY_MICREL_KSZ90X1) += micrel_ksz90x1.o obj-$(CONFIG_PHY_MESON_GXL) += meson-gxl.o obj-$(CONFIG_PHY_NATSEMI) += natsemi.o +obj-$(CONFIG_PHY_NXP_C45_TJA11XX) += nxp-c45-tja11xx.o obj-$(CONFIG_PHY_REALTEK) += realtek.o obj-$(CONFIG_PHY_SMSC) += smsc.o obj-$(CONFIG_PHY_TERANETICS) += teranetics.o diff --git a/drivers/net/phy/nxp-c45-tja11xx.c b/drivers/net/phy/nxp-c45-tja11xx.c new file mode 100644 index 0000000000..f86e31f0d9 --- /dev/null +++ b/drivers/net/phy/nxp-c45-tja11xx.c @@ -0,0 +1,348 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * NXP C45 PHY driver + * + * Copyright 2021 NXP + * Author: Radu Pirea <radu-nicolae.pirea(a)oss.nxp.com> + */ +#include <common.h> +#include <dm.h> +#include <dm/devres.h> +#include <linux/delay.h> +#include <linux/math64.h> +#include <linux/mdio.h> +#include <phy.h> + +#define PHY_ID_TJA_1103 0x001BB010 + +#define VEND1_DEVICE_CONTROL 0x0040 +#define DEVICE_CONTROL_RESET BIT(15) +#define DEVICE_CONTROL_CONFIG_GLOBAL_EN BIT(14) +#define DEVICE_CONTROL_CONFIG_ALL_EN BIT(13) + +#define VEND1_PORT_CONTROL 0x8040 +#define PORT_CONTROL_EN BIT(14) + +#define VEND1_PHY_CONTROL 0x8100 +#define PHY_CONFIG_EN BIT(14) +#define PHY_START_OP BIT(0) + +#define VEND1_PHY_CONFIG 0x8108 +#define PHY_CONFIG_AUTO BIT(0) + +#define VEND1_PORT_INFRA_CONTROL 0xAC00 +#define PORT_INFRA_CONTROL_EN BIT(14) + +#define VEND1_RXID 0xAFCC +#define VEND1_TXID 0xAFCD +#define ID_ENABLE BIT(15) + +#define VEND1_ABILITIES 0xAFC4 +#define RGMII_ID_ABILITY BIT(15) +#define RGMII_ABILITY BIT(14) +#define RMII_ABILITY BIT(10) +#define REVMII_ABILITY BIT(9) +#define MII_ABILITY BIT(8) +#define SGMII_ABILITY BIT(0) + +#define VEND1_MII_BASIC_CONFIG 0xAFC6 +#define MII_BASIC_CONFIG_REV BIT(8) +#define MII_BASIC_CONFIG_SGMII 0x9 +#define MII_BASIC_CONFIG_RGMII 0x7 +#define MII_BASIC_CONFIG_RMII 0x5 +#define MII_BASIC_CONFIG_MII 0x4 + +#define RGMII_PERIOD_PS 8000U +#define PS_PER_DEGREE div_u64(RGMII_PERIOD_PS, 360) +#define MIN_ID_PS 1644U +#define MAX_ID_PS 2260U +#define DEFAULT_ID_PS 2000U + +#define RESET_DELAY_MS 25 +#define CONF_EN_DELAY_US 450 + +struct nxp_c45_phy { + u32 tx_delay; + u32 rx_delay; +}; + +static int nxp_c45_soft_reset(struct phy_device *phydev) +{ + int tries = 10, ret; + + ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_DEVICE_CONTROL, + DEVICE_CONTROL_RESET); + if (ret) + return ret; + + do { + ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, + VEND1_DEVICE_CONTROL); + if (!(ret & DEVICE_CONTROL_RESET)) + return 0; + mdelay(RESET_DELAY_MS); + } while (tries--); + + return -EIO; +} + +static int nxp_c45_start_op(struct phy_device *phydev) +{ + return phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_PHY_CONTROL, + PHY_START_OP); +} + +static int nxp_c45_config_enable(struct phy_device *phydev) +{ + phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_DEVICE_CONTROL, + DEVICE_CONTROL_CONFIG_GLOBAL_EN | + DEVICE_CONTROL_CONFIG_ALL_EN); + udelay(CONF_EN_DELAY_US); + + phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_PORT_CONTROL, + PORT_CONTROL_EN); + phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_PHY_CONTROL, + PHY_CONFIG_EN); + phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_PORT_INFRA_CONTROL, + PORT_INFRA_CONTROL_EN); + + return 0; +} + +static u64 nxp_c45_get_phase_shift(u64 phase_offset_raw) +{ + /* The delay in degree phase is 73.8 + phase_offset_raw * 0.9. + * To avoid floating point operations we'll multiply by 10 + * and get 1 decimal point precision. + */ + phase_offset_raw *= 10; + phase_offset_raw -= 738; + return div_u64(phase_offset_raw, 9); +} + +static void nxp_c45_disable_delays(struct phy_device *phydev) +{ + phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_TXID, 0); + phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_RXID, 0); +} + +static int nxp_c45_check_delay(struct phy_device *phydev, u32 delay) +{ + if (delay < MIN_ID_PS) { + pr_err("%s: delay value smaller than %u\n", + phydev->drv->name, MIN_ID_PS); + return -EINVAL; + } + + if (delay > MAX_ID_PS) { + pr_err("%s: delay value higher than %u\n", + phydev->drv->name, MAX_ID_PS); + return -EINVAL; + } + + return 0; +} + +static int nxp_c45_get_delays(struct phy_device *phydev) +{ + struct nxp_c45_phy *priv = phydev->priv; + int ret; + + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || + phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) { + ret = dev_read_u32(phydev->dev, "tx-internal-delay-ps", + &priv->tx_delay); + if (ret) + priv->tx_delay = DEFAULT_ID_PS; + + ret = nxp_c45_check_delay(phydev, priv->tx_delay); + if (ret) { + pr_err("%s: tx-internal-delay-ps invalid value\n", + phydev->drv->name); + return ret; + } + } + + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || + phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) { + ret = dev_read_u32(phydev->dev, "rx-internal-delay-ps", + &priv->rx_delay); + if (ret) + priv->rx_delay = DEFAULT_ID_PS; + + ret = nxp_c45_check_delay(phydev, priv->rx_delay); + if (ret) { + pr_err("%s: rx-internal-delay-ps invalid value\n", + phydev->drv->name); + return ret; + } + } + + return 0; +} + +static void nxp_c45_set_delays(struct phy_device *phydev) +{ + struct nxp_c45_phy *priv = phydev->priv; + u64 tx_delay = priv->tx_delay; + u64 rx_delay = priv->rx_delay; + u64 degree; + + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || + phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) { + degree = div_u64(tx_delay, PS_PER_DEGREE); + phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_TXID, + ID_ENABLE | nxp_c45_get_phase_shift(degree)); + } else { + phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_TXID, 0); + } + + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || + phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) { + degree = div_u64(rx_delay, PS_PER_DEGREE); + phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_RXID, + ID_ENABLE | nxp_c45_get_phase_shift(degree)); + } else { + phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_RXID, 0); + } +} + +static int nxp_c45_set_phy_mode(struct phy_device *phydev) +{ + int ret; + + ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_ABILITIES); + pr_debug("%s: Clause 45 managed PHY abilities 0x%x\n", + phydev->drv->name, ret); + + switch (phydev->interface) { + case PHY_INTERFACE_MODE_RGMII: + if (!(ret & RGMII_ABILITY)) { + pr_err("%s: rgmii mode not supported\n", + phydev->drv->name); + return -EINVAL; + } + phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG, + MII_BASIC_CONFIG_RGMII); + nxp_c45_disable_delays(phydev); + break; + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + if (!(ret & RGMII_ID_ABILITY)) { + pr_err("%s: rgmii-id, rgmii-txid, rgmii-rxid modes are not supported\n", + phydev->drv->name); + return -EINVAL; + } + phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG, + MII_BASIC_CONFIG_RGMII); + ret = nxp_c45_get_delays(phydev); + if (ret) + return ret; + + nxp_c45_set_delays(phydev); + break; + case PHY_INTERFACE_MODE_MII: + if (!(ret & MII_ABILITY)) { + pr_err("%s: mii mode not supported\n", + phydev->drv->name); + return -EINVAL; + } + phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG, + MII_BASIC_CONFIG_MII); + break; + case PHY_INTERFACE_MODE_RMII: + if (!(ret & RMII_ABILITY)) { + pr_err("%s: rmii mode not supported\n", + phydev->drv->name); + return -EINVAL; + } + phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG, + MII_BASIC_CONFIG_RMII); + break; + case PHY_INTERFACE_MODE_SGMII: + if (!(ret & SGMII_ABILITY)) { + pr_err("%s: sgmii mode not supported\n", + phydev->drv->name); + return -EINVAL; + } + phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG, + MII_BASIC_CONFIG_SGMII); + break; + case PHY_INTERFACE_MODE_INTERNAL: + break; + default: + return -EINVAL; + } + + return 0; +} + +static int nxp_c45_config(struct phy_device *phydev) +{ + int ret; + + ret = nxp_c45_soft_reset(phydev); + if (ret) + return ret; + + ret = nxp_c45_config_enable(phydev); + if (ret) { + pr_err("%s: Failed to enable config\n", phydev->drv->name); + return ret; + } + + phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_PHY_CONFIG, + PHY_CONFIG_AUTO); + + ret = nxp_c45_set_phy_mode(phydev); + if (ret) { + pr_err("%s: Failed to set phy mode\n", phydev->drv->name); + return ret; + } + + phydev->autoneg = AUTONEG_DISABLE; + + return nxp_c45_start_op(phydev); +} + +static int nxp_c45_startup(struct phy_device *phydev) +{ + u32 reg; + + reg = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_STAT1); + phydev->link = !!(reg & MDIO_STAT1_LSTATUS); + phydev->speed = SPEED_100; + phydev->duplex = DUPLEX_FULL; + return 0; +} + +static int nxp_c45_probe(struct phy_device *phydev) +{ + struct nxp_c45_phy *priv; + + priv = devm_kzalloc(phydev->priv, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + phydev->priv = priv; + + return 0; +} + +static struct phy_driver nxp_tja11xx = { + .name = "NXP C45 TJA1103", + .uid = PHY_ID_TJA_1103, + .mask = 0xfffff0, + .features = PHY_100BT1_FEATURES, + .probe = &nxp_c45_probe, + .config = &nxp_c45_config, + .startup = &nxp_c45_startup, + .shutdown = &genphy_shutdown, +}; + +int phy_nxp_tja11xx_init(void) +{ + phy_register(&nxp_tja11xx); + return 0; +} diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index ed197fa46d..69acb69460 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -529,6 +529,9 @@ int phy_init(void) #ifdef CONFIG_PHY_NATSEMI phy_natsemi_init(); #endif +#ifdef CONFIG_NXP_C45_TJA11XX_PHY + phy_nxp_tja11xx_init(); +#endif #ifdef CONFIG_PHY_REALTEK phy_realtek_init(); #endif diff --git a/include/phy.h b/include/phy.h index 2754421ed4..6b928636b6 100644 --- a/include/phy.h +++ b/include/phy.h @@ -51,6 +51,10 @@ struct udevice; PHY_100BT_FEATURES | \ PHY_DEFAULT_FEATURES) +#define PHY_100BT1_FEATURES (SUPPORTED_TP | \ + SUPPORTED_MII | \ + SUPPORTED_100baseT_Full) + #define PHY_GBIT_FEATURES (PHY_BASIC_FEATURES | \ PHY_1000BT_FEATURES) @@ -523,6 +527,7 @@ int phy_micrel_ksz8xxx_init(void); int phy_micrel_ksz90x1_init(void); int phy_meson_gxl_init(void); int phy_natsemi_init(void); +int phy_nxp_tja11xx_init(void); int phy_realtek_init(void); int phy_smsc_init(void); int phy_teranetics_init(void); -- 2.31.1

1 0

[PATCH] mtd: spi: add XT25F128B flash support
by Neil Armstrong 17 May '21

17 May '21

This adds the XTX Technology Inc. flash producer Kconfig entry to enable support for the 128Mbit XT25F128B NOR SPI flash. Signed-off-by: Neil Armstrong <narmstrong(a)baylibre.com> --- drivers/mtd/spi/Kconfig | 6 ++++++ drivers/mtd/spi/spi-nor-ids.c | 4 ++++ 2 files changed, 10 insertions(+) diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig index f8db8e5213..512b57f0db 100644 --- a/drivers/mtd/spi/Kconfig +++ b/drivers/mtd/spi/Kconfig @@ -162,6 +162,12 @@ config SPI_FLASH_XMC Add support for various XMC (Wuhan Xinxin Semiconductor Manufacturing Corp.) SPI flash chips (XM25xxx) +config SPI_FLASH_XTX + bool "XTX SPI flash support" + help + Add support for various XTX (XTX Technology Limited) + SPI flash chips (XT25xxx) + endif config SPI_FLASH_USE_4K_SECTORS diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 2b57797954..e995a9eca7 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -336,6 +336,10 @@ const struct flash_info spi_nor_ids[] = { /* XMC (Wuhan Xinxin Semiconductor Manufacturing Corp.) */ { INFO("XM25QH64A", 0x207017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("XM25QH128A", 0x207018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, +#endif +#ifdef CONFIG_SPI_FLASH_XTX + /* XTX (XTX Technology Inc.) */ + { INFO("XT25F128B", 0x0b4018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, #endif { }, }; -- 2.25.1

2 1