May 2021 - U-Boot

[PATCH v2 00/18] image: Reduce #ifdef abuse in image code
by Alexandru Gagniuc 24 May '21

24 May '21

This is a combination of select patches from Simon's series: "image: Reduce #ifdefs and ad-hoc defines in image code" and alternative solutions I proposed in: "image: Reduce the abuse of #ifdefs in image-sig.c" After syncing with Simon, we agree that this is a reasonable base for further work in #ifdef reduction. Rather than describing changes from Simon's series or mine, we present this series de novo. Most patches are already peer-reviewed. Changes since v1: - Place fit_common.o under CONFIG_FIT, not CONFIG_FIT_SIGNATURE Alexandru Gagniuc (10): common: Move host-only logic in image-sig.c to separate file common: image-sig.c: Remove host-specific logic and #ifdefs image: Add support for placing crypto_algo in linker lists image: rsa: Move verification algorithm to a linker list image: image-sig.c: Remove crypto_algos array lib: ecdsa: Remove #ifdefs from ecdsa.h lib: rsa: Remove #ifdefs from rsa.h image: Eliminate IMAGE_ENABLE_VERIFY macro image: Eliminate IMAGE_ENABLE_VERIFY_ECDSA macro image: Add support for relocating crypto_algos in linker lists Simon Glass (8): image: Shorten FIT_ENABLE_SHAxxx_SUPPORT image: Rename SPL_SHAxxx_SUPPORT to SPL_FIT_SHAxxx image: Rename CONFIG_FIT_ENABLE_RSASSA_PSS_SUPPORT Kconfig: Rename SPL_CRC32_SUPPORT to SPL_CRC32 Kconfig: Rename SPL_MD5_SUPPORT to SPL_MD5 image: Drop IMAGE_ENABLE_SHA1 image: Drop IMAGE_ENABLE_SHAxxx image: Drop IMAGE_ENABLE_BEST_MATCH common/Kconfig.boot | 8 +- common/image-fit.c | 10 +- common/image-sig.c | 75 +++--------- common/spl/Kconfig | 14 +-- configs/axm_defconfig | 2 +- configs/bcm963158_ram_defconfig | 2 +- configs/chromebit_mickey_defconfig | 2 +- configs/chromebook_jerry_defconfig | 2 +- configs/chromebook_minnie_defconfig | 2 +- configs/chromebook_speedy_defconfig | 2 +- configs/evb-px30_defconfig | 2 +- configs/firefly-px30_defconfig | 2 +- configs/imxrt1020-evk_defconfig | 2 +- configs/imxrt1050-evk_defconfig | 2 +- configs/mt8516_pumpkin_defconfig | 2 +- configs/odroid-go2_defconfig | 2 +- configs/px30-core-ctouch2-px30_defconfig | 2 +- configs/px30-core-edimm2.2-px30_defconfig | 2 +- configs/sandbox_defconfig | 2 +- configs/socfpga_agilex_atf_defconfig | 2 +- configs/socfpga_agilex_vab_defconfig | 2 +- configs/socfpga_stratix10_atf_defconfig | 2 +- configs/taurus_defconfig | 2 +- include/image.h | 59 ++-------- include/u-boot/ecdsa.h | 25 ---- include/u-boot/rsa.h | 51 +-------- lib/rsa/rsa-sign.c | 4 +- lib/rsa/rsa-verify.c | 18 ++- tools/Makefile | 2 +- tools/image-sig-host.c | 133 ++++++++++++++++++++++ 30 files changed, 218 insertions(+), 219 deletions(-) create mode 100644 tools/image-sig-host.c -- 2.31.1

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[Contributor call] Request for agenda items
by Simon Glass 24 May '21

24 May '21

Hi, If you plan to join tomorrow and want to add a topic, please do so at [1]. For now the main topic is to talk about VPL, the Verifying Program Loader, a proposed new phase of U-Boot. Regards, Simon [1] https://bit.ly/3bFvwA1 or https://docs.google.com/document/d/1YBOMsbM19uSFyoJWnt7-PsOLBaevzQUgV-hiR88…

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[PATCH 0/4] efi_loader: simplify efidebug implementation
by Heinrich Schuchardt 24 May '21

24 May '21

This series contains several patches reducing the code size of the efidebug command implementation. Heinrich Schuchardt (4): efi_loader: simplify show_efi_boot_opt_data() efi_loader: simplify show_efi_boot_order() efi_loader: use efi_create_indexed_name() efi_loader: simplify accessing variables cmd/efidebug.c | 96 +++++++++++++++++--------------------------------- 1 file changed, 33 insertions(+), 63 deletions(-) -- 2.30.2

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[PATCH v11 0/8] Add FU740 chip and HiFive Unmatched board support
by Green Wan 24 May '21

24 May '21

This patch set is to add SiFive fu740 chip and HiFive Unmatched board support. Patches are split into several parts: - [PATCH v11 1/8] support for fu740 cpu - [PATCH v11 2/8] support for fu740 clk driver - [PATCH v11 3/8] rename and support for fu740 ram driver - [PATCH v11 4/8] add pcie driver - [PATCH v11 5/8] dts for SiFive fu740 - [PATCH v11 6/8] dts for SiFive Unmatched board - [PATCH v11 7/8] add Unmatched board support - [PATCH v11 8/8] clear feature disable CSR Description - For fu740 cpu support, reuse most of fu540 cpu. - For prci driver, add one abstract layer to separate fu540 and fu740. Move orignal fu540 code to separate files. - For pcie driver, it depends on gpio, prci, clk and reset drivers to do init&reset works. Also based on pcie_dw_common.c - Align with Linux DT file. Tests and patch checks - Able to boot both unmatched and unleashed boards. - PCIe tests . M.2 NVMe SSD . e1000 compatibale ethernet adapter (ping&tftpboot) . pci-to-usb adapter(usb mass storage) - checkpatch is performed. To keep code derived from other boards the same. Changlogs - v11 . squash 'binman change' patch into [PATH v11 6/8] and [PATCH v11 7/8] - v10 . on top of 2 patchset below, http://patchwork.ozlabs.org/project/uboot/patch/20210511120412.25065-1-bmen… http://patchwork.ozlabs.org/project/uboot/list/?series=242992 . appends patch 'clear feature disable CSRs' and 'binman change for unmatched' - v9 . applied http://patchwork.ozlabs.org/project/uboot/patch/20210511120412.25065-1-bmen… . append clear feature disable CSR patch to the last - v8 . Add #include <asm/global_data.h> back to sifive_clint.c in [PATCH v8 1/7] . Remove unused CLK_SIFIVE_FU540_PRCI from Kconfig [PATCH v8 2/8] and remove CONFIG_CLK_SIFIVE_PRCI=y from unleashed config in [PATCH v8 7/7] . Remove ECAM compatible string to align with Linux pcie driver and add Reviewed-by to [PATCH v8 4/7] . Drop last patch [PATCH v7 8/8] for drivers/net/macb.c and use the same compatible string, 'sifive,fu540-c000-gem', to align with Linux driver. - v7 . Rebase to latest master branch . Moved dts for fu740 patch [v6 1/7] to [v7 5/8] and seperate dts of Unmatched board from [v6 6/7] into [v7 6/8] . Applied PCIe refactoring patch to base on the common code in pcie_dw_common.c - v6 . Remove redundant DT string for 1.2GHz CPU clock and squash to [1/7] - v5 . Fix unleashed build error in patch [6/8] . Append one more set for 1.2GHz CPU speed . Add "#include <asm/global_data.h>" back to sifive_ddr.c . Add Reviewed-by to [4/8] and [7/8] - v4 . fixed incorrect file name in ./board/sifive/unmatched/Makefile . fixed link in doc/board/sifive/index.rst, passed 'make htmldocs' - v3 . Rebase to unleashed rename v2 patch . Rename doc/board/sifive/unmatched.rst board/sifive/unmatched/unmatched.c . Fix tail whitespace . Add 'git mv' info to ram driver and merge patch back to one . Add comment to macb driver for PLL hardware quirk . Add reviewed-by to patch [6/7] . Add 'gpio-poweroff' node for upcoming opensbi integration - v2 . Rebase to unleashed rename patch . remove unnessaary fu540 changes . split ram driver patch into 2 to keep 'git mv' info . use a shorter name for unmatched support . Remove redundant&incorrect temperature-sensor in DT . Remove unnecessary USB EHCI & OHCI from defconfig . Revised fu740 doc . Fixed year of copyright . Add reviewed-by received in v1 patch Green Wan (8): riscv: cpu: fu740: Add support for cpu fu740 drivers: clk: add fu740 support drivers: ram: sifive: rename fu540_ddr and add fu740 support drivers: pci: add pcie support for fu740 riscv: dts: add fu740 support riscv: dts: add SiFive Unmatched board support board: sifive: add HiFive Unmatched board support riscv: cpu: fu740: clear feature disable CSR arch/riscv/Kconfig | 5 + arch/riscv/cpu/fu540/Kconfig | 2 +- arch/riscv/cpu/fu740/Kconfig | 37 + arch/riscv/cpu/fu740/Makefile | 12 + arch/riscv/cpu/fu740/cache.c | 55 + arch/riscv/cpu/fu740/cpu.c | 22 + arch/riscv/cpu/fu740/dram.c | 38 + arch/riscv/cpu/fu740/spl.c | 38 + arch/riscv/dts/Makefile | 1 + arch/riscv/dts/fu740-c000-u-boot.dtsi | 105 ++ arch/riscv/dts/fu740-c000.dtsi | 329 ++++ .../dts/fu740-hifive-unmatched-a00-ddr.dtsi | 1489 +++++++++++++++++ .../dts/hifive-unmatched-a00-u-boot.dtsi | 41 + arch/riscv/dts/hifive-unmatched-a00.dts | 259 +++ arch/riscv/include/asm/arch-fu740/cache.h | 14 + arch/riscv/include/asm/arch-fu740/clk.h | 14 + arch/riscv/include/asm/arch-fu740/gpio.h | 38 + arch/riscv/include/asm/arch-fu740/reset.h | 13 + arch/riscv/include/asm/arch-fu740/spl.h | 14 + board/sifive/unleashed/Kconfig | 1 + board/sifive/unmatched/Kconfig | 51 + board/sifive/unmatched/MAINTAINERS | 9 + board/sifive/unmatched/Makefile | 9 + board/sifive/unmatched/spl.c | 85 + board/sifive/unmatched/unmatched.c | 24 + common/spl/Kconfig | 4 +- configs/sifive_unmatched_defconfig | 54 + doc/board/sifive/index.rst | 1 + doc/board/sifive/unmatched.rst | 536 ++++++ drivers/clk/sifive/Kconfig | 8 +- drivers/clk/sifive/Makefile | 4 +- drivers/clk/sifive/fu540-prci.c | 769 +-------- drivers/clk/sifive/fu540-prci.h | 22 + drivers/clk/sifive/fu740-prci.c | 158 ++ drivers/clk/sifive/fu740-prci.h | 22 + drivers/clk/sifive/sifive-prci.c | 733 ++++++++ drivers/clk/sifive/sifive-prci.h | 323 ++++ drivers/pci/Kconfig | 10 + drivers/pci/Makefile | 1 + drivers/pci/pcie_dw_sifive.c | 507 ++++++ drivers/ram/sifive/Kconfig | 8 +- drivers/ram/sifive/Makefile | 2 +- .../ram/sifive/{fu540_ddr.c => sifive_ddr.c} | 89 +- drivers/reset/Kconfig | 2 +- include/configs/sifive-unmatched.h | 85 + include/dt-bindings/clock/sifive-fu740-prci.h | 25 + include/dt-bindings/reset/sifive-fu740-prci.h | 19 + 47 files changed, 5281 insertions(+), 806 deletions(-) create mode 100644 arch/riscv/cpu/fu740/Kconfig create mode 100644 arch/riscv/cpu/fu740/Makefile create mode 100644 arch/riscv/cpu/fu740/cache.c create mode 100644 arch/riscv/cpu/fu740/cpu.c create mode 100644 arch/riscv/cpu/fu740/dram.c create mode 100644 arch/riscv/cpu/fu740/spl.c create mode 100644 arch/riscv/dts/fu740-c000-u-boot.dtsi create mode 100644 arch/riscv/dts/fu740-c000.dtsi create mode 100644 arch/riscv/dts/fu740-hifive-unmatched-a00-ddr.dtsi create mode 100644 arch/riscv/dts/hifive-unmatched-a00-u-boot.dtsi create mode 100644 arch/riscv/dts/hifive-unmatched-a00.dts create mode 100644 arch/riscv/include/asm/arch-fu740/cache.h create mode 100644 arch/riscv/include/asm/arch-fu740/clk.h create mode 100644 arch/riscv/include/asm/arch-fu740/gpio.h create mode 100644 arch/riscv/include/asm/arch-fu740/reset.h create mode 100644 arch/riscv/include/asm/arch-fu740/spl.h create mode 100644 board/sifive/unmatched/Kconfig create mode 100644 board/sifive/unmatched/MAINTAINERS create mode 100644 board/sifive/unmatched/Makefile create mode 100644 board/sifive/unmatched/spl.c create mode 100644 board/sifive/unmatched/unmatched.c create mode 100644 configs/sifive_unmatched_defconfig create mode 100644 doc/board/sifive/unmatched.rst create mode 100644 drivers/clk/sifive/fu540-prci.h create mode 100644 drivers/clk/sifive/fu740-prci.c create mode 100644 drivers/clk/sifive/fu740-prci.h create mode 100644 drivers/clk/sifive/sifive-prci.c create mode 100644 drivers/clk/sifive/sifive-prci.h create mode 100644 drivers/pci/pcie_dw_sifive.c rename drivers/ram/sifive/{fu540_ddr.c => sifive_ddr.c} (81%) create mode 100644 include/configs/sifive-unmatched.h create mode 100644 include/dt-bindings/clock/sifive-fu740-prci.h create mode 100644 include/dt-bindings/reset/sifive-fu740-prci.h -- 2.31.0

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[PULL] u-boot-sh/master
by Marek Vasut 23 May '21

23 May '21

The following changes since commit 27c2236f8acfa311eed2c8f8d210824fadd25483: Merge tag 'xilinx-for-v2021.07-rc3' of https://source.denx.de/u-boot/custodians/u-boot-microblaze (2021-05-19 11:50:25 -0400) are available in the Git repository at: git://source.denx.de/u-boot-sh.git master for you to fetch changes up to 6fc323c1ae7312db4e04891b83bbe60f3b68c56b: pinctrl: renesas: Implement unlock register masks (2021-05-21 15:00:17 +0200) ---------------------------------------------------------------- Hai Pham (6): clk: renesas: Fix incorrect return RPC clk_get_rate clk: renesas: Fix Realtime Module Stop Control Register offsets clk: renesas: Add support for RPCD2 clock clk: renesas: Pass struct cpg_mssr_info to renesas_clk_endisable() clk: renesas: Introduce enum clk_reg_layout clk: renesas: Add register pointers into struct cpg_mssr_info Marek Vasut (10): clk: renesas: Synchronize RZ/G2 tables with Linux 5.12 clk: renesas: Synchronize R-Car Gen2 tables with Linux 5.12 clk: renesas: Synchronize R-Car Gen3 tables with Linux 5.12 clk: renesas: Reinstate RPC clock on R-Car D3/E3 clk: renesas: Make reset controller modemr register offset configurable clk: renesas: Deduplicate gen3_clk_get_rate64() PLL handling gpio: renesas: Pass struct udevice to rcar_gpio_set_direction() pinctrl: renesas: Deduplicate Kconfig pinctrl: renesas: Fix R-Car Gen2 help text pinctrl: renesas: Implement unlock register masks drivers/clk/renesas/clk-rcar-gen2.c | 6 ++--- drivers/clk/renesas/clk-rcar-gen3.c | 120 ++++++++++++++++++++++++++++++++++++++++++++++++------------------------------------ drivers/clk/renesas/r8a774a1-cpg-mssr.c | 15 +++++++---- drivers/clk/renesas/r8a774b1-cpg-mssr.c | 9 +++++++ drivers/clk/renesas/r8a774c0-cpg-mssr.c | 10 +++++++ drivers/clk/renesas/r8a774e1-cpg-mssr.c | 1 + drivers/clk/renesas/r8a7790-cpg-mssr.c | 5 ++-- drivers/clk/renesas/r8a7791-cpg-mssr.c | 3 ++- drivers/clk/renesas/r8a7792-cpg-mssr.c | 3 ++- drivers/clk/renesas/r8a7794-cpg-mssr.c | 3 ++- drivers/clk/renesas/r8a7795-cpg-mssr.c | 59 +++++++++++++++++++++++------------------ drivers/clk/renesas/r8a7796-cpg-mssr.c | 59 +++++++++++++++++++++++++---------------- drivers/clk/renesas/r8a77965-cpg-mssr.c | 59 +++++++++++++++++++++++++---------------- drivers/clk/renesas/r8a77970-cpg-mssr.c | 133 ++++++++++++++++++++++++++++++++++++++++++++++++--------------------------------------------- drivers/clk/renesas/r8a77980-cpg-mssr.c | 1 + drivers/clk/renesas/r8a77990-cpg-mssr.c | 43 ++++++++++++++++++++---------- drivers/clk/renesas/r8a77995-cpg-mssr.c | 22 +++++++++++++--- drivers/clk/renesas/rcar-gen2-cpg.h | 7 +++-- drivers/clk/renesas/rcar-gen3-cpg.h | 19 +++++++++----- drivers/clk/renesas/renesas-cpg-mssr.c | 52 +++++------------------------------- drivers/clk/renesas/renesas-cpg-mssr.h | 62 ++++++++++++++++++++++++++++++++++++++++++- drivers/gpio/gpio-rcar.c | 13 +++++---- drivers/pinctrl/renesas/Kconfig | 84 +++++++---------------------------------------------------- drivers/pinctrl/renesas/pfc.c | 39 ++++++++++++++------------- drivers/pinctrl/renesas/sh_pfc.h | 2 +- 25 files changed, 452 insertions(+), 377 deletions(-)

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[PATCH 0/2] arm: imx8m: add support for Advantech RSB-3720
by Ying-Chun Liu 23 May '21

23 May '21

From: "Ying-Chun Liu (PaulLiu)" <paul.liu(a)linaro.org> Add initial support for Advantech RSB-3720 board. The initial support includes: - MMC - eMMC - I2C - FEC - Serial console Ying-Chun Liu (PaulLiu) (2): arm: dts: add imx8mp-rsb3720-a1 dts file arm: imx8m: add support for Advantech RSB-3720 arch/arm/dts/Makefile | 3 + arch/arm/dts/imx8mp-rsb3720-a1-u-boot.dtsi | 257 +++ arch/arm/dts/imx8mp-rsb3720-a1.dts | 539 +++++ arch/arm/mach-imx/imx8m/Kconfig | 15 + board/freescale/imx8mp_rsb3720a1/Kconfig | 14 + board/freescale/imx8mp_rsb3720a1/MAINTAINERS | 7 + board/freescale/imx8mp_rsb3720a1/Makefile | 24 + .../imx8mp_rsb3720a1/imx8mp_rsb3720a1.c | 391 ++++ .../imx8mp_rsb3720a1/imximage-8mp-lpddr4.cfg | 11 + .../lpddr4_timing_rsb3720a1_4G.c | 1848 ++++++++++++++++ .../lpddr4_timing_rsb3720a1_6G.c | 1875 +++++++++++++++++ board/freescale/imx8mp_rsb3720a1/spl.c | 270 +++ configs/imx8mp_rsb3720a1_4G_defconfig | 158 ++ configs/imx8mp_rsb3720a1_6G_defconfig | 159 ++ include/configs/imx8mp_rsb3720.h | 273 +++ 15 files changed, 5844 insertions(+) create mode 100644 arch/arm/dts/imx8mp-rsb3720-a1-u-boot.dtsi create mode 100644 arch/arm/dts/imx8mp-rsb3720-a1.dts create mode 100644 board/freescale/imx8mp_rsb3720a1/Kconfig create mode 100644 board/freescale/imx8mp_rsb3720a1/MAINTAINERS create mode 100644 board/freescale/imx8mp_rsb3720a1/Makefile create mode 100644 board/freescale/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c create mode 100644 board/freescale/imx8mp_rsb3720a1/imximage-8mp-lpddr4.cfg create mode 100644 board/freescale/imx8mp_rsb3720a1/lpddr4_timing_rsb3720a1_4G.c create mode 100644 board/freescale/imx8mp_rsb3720a1/lpddr4_timing_rsb3720a1_6G.c create mode 100644 board/freescale/imx8mp_rsb3720a1/spl.c create mode 100644 configs/imx8mp_rsb3720a1_4G_defconfig create mode 100644 configs/imx8mp_rsb3720a1_6G_defconfig create mode 100644 include/configs/imx8mp_rsb3720.h -- 2.30.2

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[PATCH 1/2] watchdog: add gpio watchdog driver
by Rasmus Villemoes 22 May '21

22 May '21

A rather common kind of external watchdog circuit is one that is kept alive by toggling a gpio. Add a driver for handling such a watchdog. The compatible string is probably a little odd as it has nothing to do with linux per se - however, I chose that to make .dts snippets reusable between device trees used with U-Boot and linux, and this is the (only) compatible string that linux' corresponding driver and DT binding accepts. I have asked whether one should/could add "wdt-gpio" to that binding, but the answer was no: https://lore.kernel.org/lkml/CAL_JsqKEGaFpiFV_oAtE+S_bnHkg4qry+bhx2EDs=NSbV… If someone feels strongly about this, I can certainly remove the "linux," part from the string - it probably wouldn't the only place where one can't reuse a DT snippet as-is between linux and U-Boot. Signed-off-by: Rasmus Villemoes <rasmus.villemoes(a)prevas.dk> --- .../watchdog/gpio-wdt.txt | 15 ++++++ drivers/watchdog/Kconfig | 7 +++ drivers/watchdog/Makefile | 1 + drivers/watchdog/gpio_wdt.c | 51 +++++++++++++++++++ 4 files changed, 74 insertions(+) create mode 100644 doc/device-tree-bindings/watchdog/gpio-wdt.txt create mode 100644 drivers/watchdog/gpio_wdt.c diff --git a/doc/device-tree-bindings/watchdog/gpio-wdt.txt b/doc/device-tree-bindings/watchdog/gpio-wdt.txt new file mode 100644 index 0000000000..2283b7ba6e --- /dev/null +++ b/doc/device-tree-bindings/watchdog/gpio-wdt.txt @@ -0,0 +1,15 @@ +GPIO watchdog timer + +Describes a simple watchdog timer which is reset by toggling a gpio. + +Required properties: + +- compatible: must be "linux,wdt-gpio" +- gpios: gpio to toggle when wdt driver reset method is called + +Example: + + gpio-wdt { + gpios = <&gpio0 1 0>; + compatible = "linux,wdt-gpio"; + }; diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index f0ff2612a6..2cf378db29 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -147,6 +147,13 @@ config WDT_CORTINA This driver support all CPU ISAs supported by Cortina Access CAxxxx SoCs. +config WDT_GPIO + bool "External gpio watchdog support" + depends on WDT + depends on DM_GPIO + help + Support for external watchdog fed by toggling a gpio. + config WDT_MPC8xx bool "MPC8xx watchdog timer support" depends on WDT && MPC8xx diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index 5c7ef593fe..f14415bb8e 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -25,6 +25,7 @@ obj-$(CONFIG_WDT_BOOKE) += booke_wdt.o obj-$(CONFIG_WDT_CORTINA) += cortina_wdt.o obj-$(CONFIG_WDT_ORION) += orion_wdt.o obj-$(CONFIG_WDT_CDNS) += cdns_wdt.o +obj-$(CONFIG_WDT_GPIO) += gpio_wdt.o obj-$(CONFIG_WDT_MPC8xx) += mpc8xx_wdt.o obj-$(CONFIG_WDT_MT7620) += mt7620_wdt.o obj-$(CONFIG_WDT_MT7621) += mt7621_wdt.o diff --git a/drivers/watchdog/gpio_wdt.c b/drivers/watchdog/gpio_wdt.c new file mode 100644 index 0000000000..9dba9c254e --- /dev/null +++ b/drivers/watchdog/gpio_wdt.c @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include <common.h> +#include <dm.h> +#include <dm/device_compat.h> +#include <wdt.h> +#include <asm/gpio.h> + +struct gpio_wdt_priv { + struct gpio_desc gpio; + int state; +}; + +static int gpio_wdt_reset(struct udevice *dev) +{ + struct gpio_wdt_priv *priv = dev_get_priv(dev); + + priv->state = !priv->state; + return dm_gpio_set_value(&priv->gpio, priv->state); +} + +static int dm_probe(struct udevice *dev) +{ + struct gpio_wdt_priv *priv = dev_get_priv(dev); + int ret; + + ret = gpio_request_by_name(dev, "gpios", 0, &priv->gpio, GPIOD_IS_OUT); + if (ret < 0) { + dev_err(dev, "Request for wdt gpio failed: %d\n", ret); + return ret; + } + return gpio_wdt_reset(dev); +} + +static const struct wdt_ops gpio_wdt_ops = { + .reset = gpio_wdt_reset, +}; + +static const struct udevice_id gpio_wdt_ids[] = { + { .compatible = "linux,wdt-gpio" }, + {} +}; + +U_BOOT_DRIVER(wdt_gpio) = { + .name = "wdt_gpio", + .id = UCLASS_WDT, + .of_match = gpio_wdt_ids, + .ops = &gpio_wdt_ops, + .probe = dm_probe, + .priv_auto = sizeof(struct gpio_wdt_priv), +}; -- 2.29.2

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[PATCH v4, 1/2] driver: watchdog: reset watchdog in designware_wdt_stop() function
by Meng.Li＠windriver.com 22 May '21

22 May '21

From: MengLi <meng.li(a)windriver.com> In uboot command line environment, watchdog is not able to be stopped with below commands: SOCFPGA_STRATIX10 # wdt dev watchdog@ffd00200 SOCFPGA_STRATIX10 # wdt stop Refer to watchdog driver in linux kernel, it is also need to reset watchdog after disable it so that the disable action takes effect. Signed-off-by: Meng Li <Meng.Li(a)windriver.com> Reviewed-by: Stefan Roese <sr(a)denx.de> --- v4: Remove the unauthorized signature. v3: Add the resets to designware_wdt_priv and initialize it in probe(). v2: Change "#if CONFIG_IS_ENABLED(DM_RESET)" into "if (CONFIG_IS_ENABLED(DM_RESET)) {", and define the variable into if condition sentence. --- drivers/watchdog/designware_wdt.c | 31 +++++++++++++++++++++---------- 1 file changed, 21 insertions(+), 10 deletions(-) diff --git a/drivers/watchdog/designware_wdt.c b/drivers/watchdog/designware_wdt.c index 12f09a7a39..cdf6b5709b 100644 --- a/drivers/watchdog/designware_wdt.c +++ b/drivers/watchdog/designware_wdt.c @@ -23,6 +23,7 @@ struct designware_wdt_priv { void __iomem *base; unsigned int clk_khz; + struct reset_ctl_bulk *resets; }; /* @@ -96,6 +97,18 @@ static int designware_wdt_stop(struct udevice *dev) designware_wdt_reset(dev); writel(0, priv->base + DW_WDT_CR); + if (CONFIG_IS_ENABLED(DM_RESET)) { + int ret; + + ret = reset_assert_bulk(priv->resets); + if (ret) + return ret; + + ret = reset_deassert_bulk(priv->resets); + if (ret) + return ret; + } + return 0; } @@ -143,13 +143,11 @@ static int designware_wdt_probe(struct udevice *dev) #endif if (CONFIG_IS_ENABLED(DM_RESET)) { - struct reset_ctl_bulk resets; - - ret = reset_get_bulk(dev, &resets); + ret = reset_get_bulk(dev, priv->resets); if (ret) goto err; - ret = reset_deassert_bulk(&resets); + ret = reset_deassert_bulk((priv->resets); if (ret) goto err; } -- 2.17.1

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[PATCH 1/3] pci: pcie_dw_rockchip: Fixed the below compilation error
by Anand Moon 21 May '21

21 May '21

Use the Error values that may be returned by PCI functions Added the error macro from linux/include/linux/pci.h drivers/pci/pcie_dw_rockchip.c: In function 'rk_pcie_read': drivers/pci/pcie_dw_rockchip.c:70:10: error: 'PCIBIOS_UNSUPPORTED' undeclared (first use in this function) 70 | return PCIBIOS_UNSUPPORTED; | ^~~~~~~~~~~~~~~~~~~ drivers/pci/pcie_dw_rockchip.c: In function 'rk_pcie_write': drivers/pci/pcie_dw_rockchip.c:90:10: error: 'PCIBIOS_UNSUPPORTED' undeclared (first use in this function) 90 | return PCIBIOS_UNSUPPORTED; | ^~~~~~~~~~~~~~~~~~~ Cc: Neil Armstrong <narmstrong(a)baylibre.com> Cc: Kever Yang <kever.yang(a)rock-chips.com> Signed-off-by: Anand Moon <linux.amoon(a)gmail.com> --- drivers/pci/pcie_dw_common.h | 9 +++++++++ drivers/pci/pcie_dw_rockchip.c | 4 ++-- 2 files changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/pci/pcie_dw_common.h b/drivers/pci/pcie_dw_common.h index 6b701645af..ba5feb5b51 100644 --- a/drivers/pci/pcie_dw_common.h +++ b/drivers/pci/pcie_dw_common.h @@ -90,6 +90,15 @@ #define PCIE_MISC_CONTROL_1_OFF 0x8bc #define PCIE_DBI_RO_WR_EN BIT(0) +/* Error values that may be returned by PCI functions */ +#define PCIBIOS_SUCCESSFUL 0x00 +#define PCIBIOS_FUNC_NOT_SUPPORTED 0x81 +#define PCIBIOS_BAD_VENDOR_ID 0x83 +#define PCIBIOS_DEVICE_NOT_FOUND 0x86 +#define PCIBIOS_BAD_REGISTER_NUMBER 0x87 +#define PCIBIOS_SET_FAILED 0x88 +#define PCIBIOS_BUFFER_TOO_SMALL 0x89 + /* Parameters for the waiting for iATU enabled routine */ #define LINK_WAIT_MAX_IATU_RETRIES 5 #define LINK_WAIT_IATU 10000 diff --git a/drivers/pci/pcie_dw_rockchip.c b/drivers/pci/pcie_dw_rockchip.c index bc22af4230..9702b40019 100644 --- a/drivers/pci/pcie_dw_rockchip.c +++ b/drivers/pci/pcie_dw_rockchip.c @@ -67,7 +67,7 @@ static int rk_pcie_read(void __iomem *addr, int size, u32 *val) { if ((uintptr_t)addr & (size - 1)) { *val = 0; - return PCIBIOS_UNSUPPORTED; + return PCIBIOS_BAD_REGISTER_NUMBER; } if (size == 4) { @@ -87,7 +87,7 @@ static int rk_pcie_read(void __iomem *addr, int size, u32 *val) static int rk_pcie_write(void __iomem *addr, int size, u32 val) { if ((uintptr_t)addr & (size - 1)) - return PCIBIOS_UNSUPPORTED; + return PCIBIOS_BAD_REGISTER_NUMBER; if (size == 4) writel(val, addr); -- 2.31.1

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[PATCH] configs: sama7g5ek: increase bootm len
by Eugen Hristev 21 May '21

21 May '21

Increase the BOOTM_LEN to 32M . This would allow a bigger kernel image to be booted, for example the multi_v7_defconfig. Loading Kernel Image Image too large: increase CONFIG_SYS_BOOTM_LEN Must RESET board to recover resetting ... Signed-off-by: Eugen Hristev <eugen.hristev(a)microchip.com> --- include/configs/sama7g5ek.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/sama7g5ek.h b/include/configs/sama7g5ek.h index ef3bfa36fd..96db82e9d4 100644 --- a/include/configs/sama7g5ek.h +++ b/include/configs/sama7g5ek.h @@ -11,7 +11,7 @@ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 #define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */ - +#define CONFIG_SYS_BOOTM_LEN SZ_32M /* SDRAM */ #define CONFIG_SYS_SDRAM_BASE 0x60000000 #define CONFIG_SYS_SDRAM_SIZE 0x20000000 -- 2.25.1

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