May 2021 - U-Boot

Weirdness of ofnode_get_addr_size()
by Jan Kiszka 04 May '21

04 May '21

Hi, I'm trying to make some sense of ofnode_get_addr_size() in order to fix [1] properly. First, the documentation if this functions says "This does no address translation". But the node-pointer path happily calls of_translate_address(), as the result of a6a45cd32539. For not offset-bases path, it calls fdtdec_get_addr_size() which does no translation. Related to [1]: The node-pointer path cleanly calls of_n_addr/size_cells() in order to retrieve the configured number of cells. But the offset-based path simply calls fdtdec_get_addr_size() which assumes that the number of cells is derived from the physical address width of that platform. So, what is that functions actually supposed to do? Jan [1] https://www.mail-archive.com/u-boot@lists.denx.de/msg405446.html

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[PATCH] pinctrl: mscc: fix multiple definitions
by Daniel Schwierzeck 04 May '21

04 May '21

gcc-11 complains about multiple definitions: /opt/gcc-11.0.20210426-nolibc/mips-linux/bin/mips-linux-ld.bfd: drivers/pinctrl/mscc/pinctrl-ocelot.o:drivers/pinctrl/mscc/mscc-common.h:64: multiple definition of `mscc_pinctrl_ops'; drivers/pinctrl/mscc/mscc-common.o:drivers/pinctrl/mscc/mscc-common.h:64: first defined here /opt/gcc-11.0.20210426-nolibc/mips-linux/bin/mips-linux-ld.bfd: drivers/pinctrl/mscc/pinctrl-ocelot.o:drivers/pinctrl/mscc/mscc-common.h:66: multiple definition of `mscc_gpio_ops'; drivers/pinctrl/mscc/mscc-common.o:drivers/pinctrl/mscc/mscc-common.h:66: first defined here mscc_pinctrl_ops and mscc_gpio_ops are instantiated in mscc-common.c and just referenced by SoC specific pinctrl drivers. Annotate the exports in mscc-common.h with `extern` to avoid creating new instances when including mscc-common.h. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck(a)gmail.com> --- drivers/pinctrl/mscc/mscc-common.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/mscc/mscc-common.h b/drivers/pinctrl/mscc/mscc-common.h index 3c5c1faf84..9eb1321f89 100644 --- a/drivers/pinctrl/mscc/mscc-common.h +++ b/drivers/pinctrl/mscc/mscc-common.h @@ -61,6 +61,6 @@ int mscc_pinctrl_probe(struct udevice *dev, int num_func, const struct mscc_pin_data *mscc_pins, int num_pins, char * const *function_names, const unsigned long *mscc_gpios); -const struct pinctrl_ops mscc_pinctrl_ops; -const struct dm_gpio_ops mscc_gpio_ops; +extern const struct pinctrl_ops mscc_pinctrl_ops; +extern const struct dm_gpio_ops mscc_gpio_ops; -- 2.31.1

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[PATCH v1 0/6] common: Introduce crypt-style password support
by Steffen Jaeckel 04 May '21

04 May '21

This patchset introduces support for crypt-style passwords to unlock the console in autoboot mode. The implementation of crypt-sha256 and crypt-sha512 originate from libxcrypt at https://github.com/besser82/libxcrypt.git Version v4.4.17 Git commit hash 6b110bc I didn't re-format those two files to make diffing to the original versions from libxcrypt easier, which leads to a huge load of checkpatch.pl warnings&errors. Please advise on whether they should be re-formatted or can be kept as is. The remaining warnings from checkpatch.pl are intentional resp. open for discussion. Cheers, Steffen Changes in v1: Added unit-tests of crypt_compare() Wrapped crypt functions to encapsulate errno Steffen Jaeckel (6): lib: add crypt subsystem lib: wrap crypt API to hide errno usage common: integrate crypt-based passwords common: Rename macro appropriately cmd: allow disabling of timeout for password entry configs: add new values to bcm963158 defconfig cmd/Kconfig | 8 + common/Kconfig.boot | 23 ++- common/autoboot.c | 109 ++++++++-- configs/bcm963158_ram_defconfig | 8 + include/crypt.h | 14 ++ lib/Kconfig | 1 + lib/Makefile | 1 + lib/crypt/Kconfig | 29 +++ lib/crypt/Makefile | 10 + lib/crypt/alg-sha256.h | 11 + lib/crypt/alg-sha512.h | 11 + lib/crypt/crypt-port.h | 30 +++ lib/crypt/crypt-sha256.c | 334 ++++++++++++++++++++++++++++++ lib/crypt/crypt-sha512.c | 349 ++++++++++++++++++++++++++++++++ lib/crypt/crypt.c | 76 +++++++ test/Kconfig | 9 + test/lib/Makefile | 1 + test/lib/test_crypt.c | 64 ++++++ 18 files changed, 1068 insertions(+), 20 deletions(-) create mode 100644 include/crypt.h create mode 100644 lib/crypt/Kconfig create mode 100644 lib/crypt/Makefile create mode 100644 lib/crypt/alg-sha256.h create mode 100644 lib/crypt/alg-sha512.h create mode 100644 lib/crypt/crypt-port.h create mode 100644 lib/crypt/crypt-sha256.c create mode 100644 lib/crypt/crypt-sha512.c create mode 100644 lib/crypt/crypt.c create mode 100644 test/lib/test_crypt.c -- 2.31.1

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Re: [PATCH v2] cmd: gpt: Add option to write GPT partitions to environment variable
by Heinrich Schuchardt 04 May '21

04 May '21

On 5/3/21 9:29 PM, Farhan Ali wrote: > Hi Heinrich, > > I was wondering if there are any other changes necessary? Nothing on my side. The patch was reviewed by Simon and now is is assigned to Tom. https://patchwork.ozlabs.org/project/uboot/patch/20210226181733.19307-1-far… He should be able to tell you why it wasn't merged yet. Best regards Heinrich > > Thanks > > Farhan > > On Thu, Mar 4, 2021 at 8:08 PM Simon Glass <sjg(a)chromium.org > <mailto:sjg@chromium.org>> wrote: > > On Fri, 26 Feb 2021 at 13:17, Farhan Ali <farhan.ali(a)broadcom.com > <mailto:farhan.ali@broadcom.com>> wrote: > > > > This change would enhance the existing 'gpt read' command to allow > > (optionally) writing of the read GPT partitions to an environment > > variable in the UBOOT partitions layout format. This would allow users > > to easily change the overall partition settings by editing said > variable > > and then using the variable in the 'gpt write' and 'gpt verify' > commands. > > > > Signed-off-by: Farhan Ali <farhan.ali(a)broadcom.com > <mailto:farhan.ali@broadcom.com>> > > Cc: Simon Glass <sjg(a)chromium.org <mailto:sjg@chromium.org>> > > Cc: Heinrich Schuchardt <xypron.glpk(a)gmx.de > <mailto:xypron.glpk@gmx.de>> > > Cc: Corneliu Doban <cdoban(a)broadcom.com <mailto:cdoban@broadcom.com>> > > Cc: Rayagonda Kokatanur <rayagonda.kokatanur(a)broadcom.com > <mailto:rayagonda.kokatanur@broadcom.com>> > > Cc: Rasmus Villemoes <rasmus.villemoes(a)prevas.dk > <mailto:rasmus.villemoes@prevas.dk>> > > > > --- > > Changes for v2: > > - Checked for argv[4] existence before calling do_get_gpt_info > > - Added missing update to doc/README.gpt > > --- > > cmd/gpt.c | 46 ++++++++++++++++++++++++++++++++++++++-------- > > doc/README.gpt | 17 +++++++++++++++++ > > 2 files changed, 55 insertions(+), 8 deletions(-) > > > > Reviewed-by: Simon Glass <sjg(a)chromium.org <mailto:sjg@chromium.org>> >

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[PATCH] arm: dts: stm32mp157c-odyssey-som: enable the RNG1
by Grzegorz Szymaszek 04 May '21

04 May '21

Enable the true random number generator. It can be used, for example, to generate partition UUIDs when partitioning with the gpt command. The generator is already enabled in the device trees of several other STM32MP1‐based boards, like DKx or DHCOM. Signed-off-by: Grzegorz Szymaszek <gszymaszek(a)short.pl> Cc: Patrice Chotard <patrice.chotard(a)foss.st.com> Cc: Patrick Delaunay <patrick.delaunay(a)foss.st.com> --- arch/arm/dts/stm32mp157c-odyssey-som.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/dts/stm32mp157c-odyssey-som.dtsi b/arch/arm/dts/stm32mp157c-odyssey-som.dtsi index 83ff2e7ce1..e367a311c4 100644 --- a/arch/arm/dts/stm32mp157c-odyssey-som.dtsi +++ b/arch/arm/dts/stm32mp157c-odyssey-som.dtsi @@ -258,6 +258,10 @@ status = "okay"; }; +&rng1 { + status = "okay"; +}; + &sdmmc2 { pinctrl-names = "default", "opendrain", "sleep"; pinctrl-0 = <&sdmmc2_b4_pins_a>; -- 2.30.2

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[PATCH v3 0/7] arm: cache: cp15: don't map reserved region with no-map property
by Patrick Delaunay 04 May '21

04 May '21

Hi, It it the v3 serie of [1]. This v3 serie is rebased on top of v2021.07-rc1 with integrated previous series: - [2] for stm32mp parts and added dram_bank_mmu_setup - [3] for LMB impacts On STM32MP15x platform we can use OP-TEE, loaded in DDR in a region protected by a firewall. This region is reserved in device with "no-map" property. Sometime the platform boot failed in U-Boot on a Cortex A7 access to this region (depending of the binary and the issue can change with compiler version or with code alignment), then the firewall raise an error, for example: E/TC:0 tzc_it_handler:19 TZC permission failure E/TC:0 dump_fail_filter:420 Permission violation on filter 0 E/TC:0 dump_fail_filter:425 Violation @0xde5c6bf0, non-secure privileged read, AXI ID 5c0 E/TC:0 Panic After investigation, the forbidden access is a speculative request performed by the Cortex A7 because all the DDR is mapped as MEMORY with CACHEABLE property. The issue is solved only when the region reserved by OP-TEE is no more mapped in U-Boot as it is already done in Linux kernel. Tested on DK2 board with OP-TEE 3.12 / TF-A 2.4: With hard-coded address for OP-TEE reserved memory, the error doesn't occur. void dram_bank_mmu_setup(int bank) { .... for (i = start >> MMU_SECTION_SHIFT; i < (start >> MMU_SECTION_SHIFT) + (size >> MMU_SECTION_SHIFT); i++) { option = DCACHE_DEFAULT_OPTION; if (i >= 0xde0) option = INVALID_ENTRY; set_section_dcache(i, option); } } Just by modifying the test on 0xde0 to 0xdf0, the OP-TEE memory protected by firewall is mapped cacheable and the error occurs. I think that can be a general issue for ARM architecture: the no-map tag in device should be respected by U-Boot. But I don't propose a generic solution in arm/lib/cache-cp15.c:dram_bank_mmu_setup() because the device tree parsing done in lmb_init_and_reserve() take a long time when it is executed without data cache. => the previous path 7/7 of v2 series is dropped to avoid performance issue on other ARM target. To avoid this issue on stm32mp32mp platform, this V3 series moves the lmb initialization in enable_caches() and the lmb variable becomes a static struct. This v3 series is composed by 7 patches - 1..3/7: preliminary steps to support flags in library in lmb (as it is done in memblock.c in Linux) - 4/7: unitary test on the added feature in lmb lib - 5/7: save the no-map flags in lmb when the device tree is parsed - 6/7: solve issue for the size of cacheable area in pre-reloc case - 7/7: update the stm32mp mmu support See also [4] which handle same speculative access on armv8 for area with Executable attribute. [1] http://patchwork.ozlabs.org/project/uboot/list/?series=228543&state=* [2] http://patchwork.ozlabs.org/project/uboot/list/?series=228202&state=* [3] http://patchwork.ozlabs.org/project/uboot/list/?series=227570&state=* [4] http://patchwork.ozlabs.org/project/uboot/patch/20200903000106.5016-1-marek… Regards Patrick Changes in v3: - NEW: solve performance issue as relocated DT is not marked cacheable - call lmb_init_and_reserve when data cache is activated in enable_caches() - drop v2 patch "arm: cache: cp15: don't map the reserved region with no-map property" Changes in v2: - remove unnecessary comments in lmb.h - rebase on latest lmb patches - NEW: update in stm32mp specific MMU setup functions Patrick Delaunay (7): lmb: Add support of flags for no-map properties lmb: add lmb_is_reserved_flags lmb: add lmb_dump_region() function test: lmb: add test for lmb_reserve_flags image-fdt: save no-map parameter of reserve-memory stm32mp: Increase the reserved memory in board_get_usable_ram_top stm32mp: don't map the reserved region with no-map property arch/arm/mach-stm32mp/cpu.c | 17 +++++- arch/arm/mach-stm32mp/dram_init.c | 3 +- common/image-fdt.c | 23 +++++--- include/lmb.h | 21 +++++++ lib/lmb.c | 94 ++++++++++++++++++++++--------- test/lib/lmb.c | 89 +++++++++++++++++++++++++++++ 6 files changed, 209 insertions(+), 38 deletions(-) -- 2.17.1

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[PATCH v4 00/10] Add support for extension boards detection and DT overlays application
by Kory Maincent 04 May '21

04 May '21

This series of patches aims at proposing a generic U-Boot mechanism to detect extension boards connected to the HW platform, and apply the appropriate Device Tree overlays depending on the detected extension boards. Indeed, numerous popular platforms, such as the BeagleBone or the RaspberryPi, feature some kind of extension board mechanism. These extension boards are often discoverable through some kind of EEPROM (connected on I2C, 1-wire, etc.) and require Device Tree overlays to be applied at the U-Boot level to provide a complete HW description to the Linux kernel. However, currently this logic is usually implemented ad-hoc in downstream forks of U-Boot. This series proposes to bring a HW-agnostic and generic solution to this problem to upstream U-Boot. The series shows that it is generic enough by implementing its usage for 2 different families of HW platforms and expansion boards: - The BeagleBone Black and BeagleBone AI, that use extension boards where the EEPROM describing the extension boards is connected over I2C. - The CHIP, that uses extension boards where the EEPROM describing the extension boards is connected over 1-wire. The patch series implements a new command called "extension", with two sub-commands: - "extension scan" to detect available extension boards - "extension list" will simply list the detected extension boards - "extension apply" will allow to apply the Device Tree overlays corresponding to one extension board or to all expansion boards Note that the name "extension" has been chosen to not refer to any particular board-specific terminology for extension boards ("cape" for BeagleBone, "DIP" for CHIP, "hat" for RaspberryPi, etc.). However, we welcome suggestions of other names and are definitely willing to use a different naming. The "extension apply" command requires two environment variables to be defined so that it knows how to apply DT overlays. This is described in more details in PATCH 1. This generic code requires board-specific code for the detection and enumeration of extension boards. This is simply implemented in the form of a board-specific extension_board_scan() function, which fills in a list of detected extension boards. In detail: - PATCH 1 move fdt_valid function to fdt_support file - PATCH 2 implements the generic command and logic - PATCH 3 implements the python test for the "extension" command - PATCH 4 implements the board-specific code for the BeagleBone platforms - PATCH 5 enables the mechanism for the BeagleBone AI - PATCH 6 review the detection mechanism of one-wire devices - PATCH 7 and 8 enable the mechanism for the CHIP - PATCH 9 and 10 enable the mechanism for the BeagleBone Black Thanks in advance for your review and feedback Change since v1: - remove the one wire devicetree description of the CHIP board - rewrite the detection of w1 to makes it automatic and not devicetree dependent - replace Kconfig CHIP board target by Kconfig CHIP_DIP_SCAN simple option - rewrite doc to rST syntax - make few syntax update Change since v2: - review the detection of w1 to makes it compatible with automatic detection alongside the devicetree description detection - update the patch separation between the mechanism for the CHIP and the configuration activation Change since v3: - Update commit messages on the extension command patch - Remove a test on CMD_EXTENSION in the chip.c file. Kory Maincent (10): fdt_support: move fdt_valid from cmd_fdt.c to fdt_support.c cmd: add support for a new "extension" command pytest: add sandbox test for "extension" command ti/common: add support for extension_scan_board function am57xx: add support for cape detect functionality w1: replace dt detection by automatic detection arm: sunxi: add support for DIP detection to CHIP board configs: CHIP: add support for DIP detect functionality arm: am335x: add support for i2c2 bus am335x: add support for cape detect functionality arch/Kconfig | 2 + arch/arm/mach-omap2/am33xx/Kconfig | 1 + arch/arm/mach-omap2/am33xx/clock_am33xx.c | 1 + arch/arm/mach-omap2/omap5/Kconfig | 1 + arch/arm/mach-sunxi/Kconfig | 9 ++ arch/sandbox/dts/Makefile | 1 + arch/sandbox/dts/overlay0.dts | 9 ++ arch/sandbox/dts/overlay1.dts | 9 ++ board/sandbox/sandbox.c | 23 +++ board/sunxi/Makefile | 1 + board/sunxi/chip.c | 100 +++++++++++++ board/ti/am335x/board.c | 3 + board/ti/am335x/board.h | 1 + board/ti/am335x/mux.c | 15 ++ board/ti/am57xx/board.c | 1 + board/ti/common/Kconfig | 6 + board/ti/common/Makefile | 1 + board/ti/common/cape_detect.c | 96 +++++++++++++ board/ti/common/cape_detect.h | 28 ++++ cmd/Kconfig | 12 ++ cmd/Makefile | 1 + cmd/extension_board.c | 167 ++++++++++++++++++++++ cmd/fdt.c | 49 ------- common/fdt_support.c | 46 ++++++ configs/CHIP_defconfig | 1 + doc/usage/extension.rst | 111 ++++++++++++++ drivers/w1-eeprom/ds24xxx.c | 7 + drivers/w1-eeprom/ds2502.c | 6 + drivers/w1-eeprom/w1-eeprom-uclass.c | 31 ---- drivers/w1/w1-uclass.c | 76 +++++++++- include/extension_board.h | 31 ++++ include/fdt_support.h | 2 + include/w1-eeprom.h | 2 - include/w1.h | 17 +++ test/py/tests/test_extension.py | 52 +++++++ 35 files changed, 835 insertions(+), 84 deletions(-) create mode 100644 arch/sandbox/dts/overlay0.dts create mode 100644 arch/sandbox/dts/overlay1.dts create mode 100644 board/sunxi/chip.c create mode 100644 board/ti/common/cape_detect.c create mode 100644 board/ti/common/cape_detect.h create mode 100644 cmd/extension_board.c create mode 100644 doc/usage/extension.rst create mode 100644 include/extension_board.h create mode 100644 test/py/tests/test_extension.py -- 2.17.1

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squashfs tests flaky?
by Pratyush Yadav 04 May '21

04 May '21

Hi, I am playing around with the U-Boot CI, mostly to make sure my patches don't break things. To that end I created a fork of u-boot on GitLab and started the CI pipeline on the current master (8ddaf94358). I see on the official repo the job passes [0]. But on my fork, the job fails due to squashfs failures [1]. Both jobs are using the same commit. I looked at the failure logs and it seems to be because of some I/O errors but I'm not sure what exactly is going on. [0] https://source.denx.de/u-boot/u-boot/-/jobs/263093 [1] https://gitlab.com/prati0100/uboot/-/jobs/1234264642 -- Regards, Pratyush Yadav Texas Instruments Inc.

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Re: [PATCH v7 2/8] drivers: clk: add fu740 support
by Dimitri John Ledkov 04 May '21

04 May '21

(resending to the list after subscribing) Hi, On Thu, Apr 22, 2021 at 10:15 AM Green Wan <green.wan(a)sifive.com> wrote: > > Add fu740 support. One abstract layer is added for supporting > multiple chips such as fu540 and fu740. > > Signed-off-by: Green Wan <green.wan(a)sifive.com> > --- > drivers/clk/sifive/Kconfig | 8 +- > drivers/clk/sifive/Makefile | 4 +- > drivers/clk/sifive/fu540-prci.c | 769 +------------------------------ > drivers/clk/sifive/fu540-prci.h | 22 + > drivers/clk/sifive/fu740-prci.c | 158 +++++++ > drivers/clk/sifive/fu740-prci.h | 22 + > drivers/clk/sifive/sifive-prci.c | 733 +++++++++++++++++++++++++++++ > drivers/clk/sifive/sifive-prci.h | 323 +++++++++++++ > 8 files changed, 1286 insertions(+), 753 deletions(-) > create mode 100644 drivers/clk/sifive/fu540-prci.h > create mode 100644 drivers/clk/sifive/fu740-prci.c > create mode 100644 drivers/clk/sifive/fu740-prci.h > create mode 100644 drivers/clk/sifive/sifive-prci.c > create mode 100644 drivers/clk/sifive/sifive-prci.h > > diff --git a/drivers/clk/sifive/Kconfig b/drivers/clk/sifive/Kconfig > index c4d0a1f9b1..20fc004b59 100644 > --- a/drivers/clk/sifive/Kconfig > +++ b/drivers/clk/sifive/Kconfig > @@ -6,11 +6,11 @@ config CLK_SIFIVE > help > SoC drivers for SiFive Linux-capable SoCs. > > -config CLK_SIFIVE_FU540_PRCI > - bool "PRCI driver for SiFive FU540 SoCs" > +config CLK_SIFIVE_PRCI > + bool "PRCI driver for SiFive SoCs" > depends on CLK_SIFIVE Since the above is done in this patch, I would expect to remove all references to the CLK_SIFIVE_FU540_PRCI config option at the same time. Specifically: $ git grep CLK_SIFIVE_FU540_PRCI arch/riscv/cpu/fu540/Kconfig: imply CLK_SIFIVE_FU540_PRCI drivers/reset/Kconfig: depends on DM_RESET && CLK_SIFIVE_FU540_PRCI && TARGET_SIFIVE_UNLEASHED If above references were fixed, it remove the need to manually add "CONFIG_CLK_SIFIVE_PRCI=y" to unleashed config in the "board: sifive: add HiFive Unmatched board support" patch. Leaving left over references to the removed config options is confusing, and makes the patch not self contained. > select CLK_ANALOGBITS_WRPLL_CLN28HPC > help > Supports the Power Reset Clock interface (PRCI) IP block found in > - FU540 SoCs. If this kernel is meant to run on a SiFive FU540 SoC, > - enable this driver. > + FU540/FU740 SoCs. If this kernel is meant to run on a SiFive FU540/ > + FU740 SoCs, enable this driver. > diff --git a/drivers/clk/sifive/Makefile b/drivers/clk/sifive/Makefile > index b224279afb..51348b1ddc 100644 > --- a/drivers/clk/sifive/Makefile > +++ b/drivers/clk/sifive/Makefile > @@ -1,3 +1,5 @@ > # SPDX-License-Identifier: GPL-2.0+ > > -obj-$(CONFIG_CLK_SIFIVE_FU540_PRCI) += fu540-prci.o > +obj-y += sifive-prci.o > + > +obj-$(CONFIG_CLK_SIFIVE_PRCI) += fu540-prci.o fu740-prci.o > diff --git a/drivers/clk/sifive/fu540-prci.c b/drivers/clk/sifive/fu540-prci.c > index b3882d0b77..ceb2c6fab0 100644 > --- a/drivers/clk/sifive/fu540-prci.c > +++ b/drivers/clk/sifive/fu540-prci.c > @@ -5,6 +5,8 @@ > * Copyright (C) 2018 SiFive, Inc. > * Wesley Terpstra > * Paul Walmsley > + * Zong Li > + * Pragnesh Patel > * > * This program is free software; you can redistribute it and/or modify > * it under the terms of the GNU General Public License version 2 as > @@ -15,632 +17,48 @@ > * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > * GNU General Public License for more details. > * > - * The FU540 PRCI implements clock and reset control for the SiFive > - * FU540-C000 chip. This driver assumes that it has sole control > - * over all PRCI resources. > - * > - * This driver is based on the PRCI driver written by Wesley Terpstra. > - * > - * Refer, commit 999529edf517ed75b56659d456d221b2ee56bb60 of: > - * https://github.com/riscv/riscv-linux > - * > * References: > * - SiFive FU540-C000 manual v1p0, Chapter 7 "Clocking and Reset" > */ > > -#include <common.h> > -#include <clk-uclass.h> > -#include <clk.h> > -#include <div64.h> > -#include <dm.h> > -#include <dm/device.h> > -#include <dm/device_compat.h> > -#include <dm/uclass.h> > #include <dt-bindings/clock/sifive-fu540-prci.h> > -#include <dt-bindings/reset/sifive-fu540-prci.h> > -#include <errno.h> > -#include <reset-uclass.h> > -#include <asm/io.h> > -#include <asm/arch/reset.h> > -#include <linux/delay.h> > -#include <linux/err.h> > -#include <linux/math64.h> > -#include <linux/clk/analogbits-wrpll-cln28hpc.h> > - > -/* > - * EXPECTED_CLK_PARENT_COUNT: how many parent clocks this driver expects: > - * hfclk and rtcclk > - */ > -#define EXPECTED_CLK_PARENT_COUNT 2 > - > -/* > - * Register offsets and bitmasks > - */ > - > -/* COREPLLCFG0 */ > -#define PRCI_COREPLLCFG0_OFFSET 0x4 > -#define PRCI_COREPLLCFG0_DIVR_SHIFT 0 > -#define PRCI_COREPLLCFG0_DIVR_MASK (0x3f << PRCI_COREPLLCFG0_DIVR_SHIFT) > -#define PRCI_COREPLLCFG0_DIVF_SHIFT 6 > -#define PRCI_COREPLLCFG0_DIVF_MASK (0x1ff << PRCI_COREPLLCFG0_DIVF_SHIFT) > -#define PRCI_COREPLLCFG0_DIVQ_SHIFT 15 > -#define PRCI_COREPLLCFG0_DIVQ_MASK (0x7 << PRCI_COREPLLCFG0_DIVQ_SHIFT) > -#define PRCI_COREPLLCFG0_RANGE_SHIFT 18 > -#define PRCI_COREPLLCFG0_RANGE_MASK (0x7 << PRCI_COREPLLCFG0_RANGE_SHIFT) > -#define PRCI_COREPLLCFG0_BYPASS_SHIFT 24 > -#define PRCI_COREPLLCFG0_BYPASS_MASK (0x1 << PRCI_COREPLLCFG0_BYPASS_SHIFT) > -#define PRCI_COREPLLCFG0_FSE_SHIFT 25 > -#define PRCI_COREPLLCFG0_FSE_MASK (0x1 << PRCI_COREPLLCFG0_FSE_SHIFT) > -#define PRCI_COREPLLCFG0_LOCK_SHIFT 31 > -#define PRCI_COREPLLCFG0_LOCK_MASK (0x1 << PRCI_COREPLLCFG0_LOCK_SHIFT) > - > -/* COREPLLCFG1 */ > -#define PRCI_COREPLLCFG1_OFFSET 0x8 > -#define PRCI_COREPLLCFG1_CKE_SHIFT 31 > -#define PRCI_COREPLLCFG1_CKE_MASK (0x1 << PRCI_COREPLLCFG1_CKE_SHIFT) > - > -/* DDRPLLCFG0 */ > -#define PRCI_DDRPLLCFG0_OFFSET 0xc > -#define PRCI_DDRPLLCFG0_DIVR_SHIFT 0 > -#define PRCI_DDRPLLCFG0_DIVR_MASK (0x3f << PRCI_DDRPLLCFG0_DIVR_SHIFT) > -#define PRCI_DDRPLLCFG0_DIVF_SHIFT 6 > -#define PRCI_DDRPLLCFG0_DIVF_MASK (0x1ff << PRCI_DDRPLLCFG0_DIVF_SHIFT) > -#define PRCI_DDRPLLCFG0_DIVQ_SHIFT 15 > -#define PRCI_DDRPLLCFG0_DIVQ_MASK (0x7 << PRCI_DDRPLLCFG0_DIVQ_SHIFT) > -#define PRCI_DDRPLLCFG0_RANGE_SHIFT 18 > -#define PRCI_DDRPLLCFG0_RANGE_MASK (0x7 << PRCI_DDRPLLCFG0_RANGE_SHIFT) > -#define PRCI_DDRPLLCFG0_BYPASS_SHIFT 24 > -#define PRCI_DDRPLLCFG0_BYPASS_MASK (0x1 << PRCI_DDRPLLCFG0_BYPASS_SHIFT) > -#define PRCI_DDRPLLCFG0_FSE_SHIFT 25 > -#define PRCI_DDRPLLCFG0_FSE_MASK (0x1 << PRCI_DDRPLLCFG0_FSE_SHIFT) > -#define PRCI_DDRPLLCFG0_LOCK_SHIFT 31 > -#define PRCI_DDRPLLCFG0_LOCK_MASK (0x1 << PRCI_DDRPLLCFG0_LOCK_SHIFT) > - > -/* DDRPLLCFG1 */ > -#define PRCI_DDRPLLCFG1_OFFSET 0x10 > -#define PRCI_DDRPLLCFG1_CKE_SHIFT 31 > -#define PRCI_DDRPLLCFG1_CKE_MASK (0x1 << PRCI_DDRPLLCFG1_CKE_SHIFT) > - > -/* GEMGXLPLLCFG0 */ > -#define PRCI_GEMGXLPLLCFG0_OFFSET 0x1c > -#define PRCI_GEMGXLPLLCFG0_DIVR_SHIFT 0 > -#define PRCI_GEMGXLPLLCFG0_DIVR_MASK \ > - (0x3f << PRCI_GEMGXLPLLCFG0_DIVR_SHIFT) > -#define PRCI_GEMGXLPLLCFG0_DIVF_SHIFT 6 > -#define PRCI_GEMGXLPLLCFG0_DIVF_MASK \ > - (0x1ff << PRCI_GEMGXLPLLCFG0_DIVF_SHIFT) > -#define PRCI_GEMGXLPLLCFG0_DIVQ_SHIFT 15 > -#define PRCI_GEMGXLPLLCFG0_DIVQ_MASK (0x7 << PRCI_GEMGXLPLLCFG0_DIVQ_SHIFT) > -#define PRCI_GEMGXLPLLCFG0_RANGE_SHIFT 18 > -#define PRCI_GEMGXLPLLCFG0_RANGE_MASK \ > - (0x7 << PRCI_GEMGXLPLLCFG0_RANGE_SHIFT) > -#define PRCI_GEMGXLPLLCFG0_BYPASS_SHIFT 24 > -#define PRCI_GEMGXLPLLCFG0_BYPASS_MASK \ > - (0x1 << PRCI_GEMGXLPLLCFG0_BYPASS_SHIFT) > -#define PRCI_GEMGXLPLLCFG0_FSE_SHIFT 25 > -#define PRCI_GEMGXLPLLCFG0_FSE_MASK \ > - (0x1 << PRCI_GEMGXLPLLCFG0_FSE_SHIFT) > -#define PRCI_GEMGXLPLLCFG0_LOCK_SHIFT 31 > -#define PRCI_GEMGXLPLLCFG0_LOCK_MASK (0x1 << PRCI_GEMGXLPLLCFG0_LOCK_SHIFT) > - > -/* GEMGXLPLLCFG1 */ > -#define PRCI_GEMGXLPLLCFG1_OFFSET 0x20 > -#define PRCI_GEMGXLPLLCFG1_CKE_SHIFT 31 > -#define PRCI_GEMGXLPLLCFG1_CKE_MASK (0x1 << PRCI_GEMGXLPLLCFG1_CKE_SHIFT) > - > -/* CORECLKSEL */ > -#define PRCI_CORECLKSEL_OFFSET 0x24 > -#define PRCI_CORECLKSEL_CORECLKSEL_SHIFT 0 > -#define PRCI_CORECLKSEL_CORECLKSEL_MASK \ > - (0x1 << PRCI_CORECLKSEL_CORECLKSEL_SHIFT) > - > -/* DEVICESRESETREG */ > -#define PRCI_DEVICESRESETREG_OFFSET 0x28 > -#define PRCI_DEVICERESETCNT 5 > - > -#define PRCI_DEVICESRESETREG_DDR_CTRL_RST_N_MASK \ > - (0x1 << PRCI_RST_DDR_CTRL_N) > -#define PRCI_DEVICESRESETREG_DDR_AXI_RST_N_MASK \ > - (0x1 << PRCI_RST_DDR_AXI_N) > -#define PRCI_DEVICESRESETREG_DDR_AHB_RST_N_MASK \ > - (0x1 << PRCI_RST_DDR_AHB_N) > -#define PRCI_DEVICESRESETREG_DDR_PHY_RST_N_MASK \ > - (0x1 << PRCI_RST_DDR_PHY_N) > -#define PRCI_DEVICESRESETREG_GEMGXL_RST_N_MASK \ > - (0x1 << PRCI_RST_GEMGXL_N) > - > -/* CLKMUXSTATUSREG */ > -#define PRCI_CLKMUXSTATUSREG_OFFSET 0x2c > -#define PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_SHIFT 1 > -#define PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_MASK \ > - (0x1 << PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_SHIFT) > - > -/* PROCMONCFG */ > -#define PRCI_PROCMONCFG_OFFSET 0xF0 > -#define PRCI_PROCMONCFG_CORE_CLOCK_SHIFT 24 > -#define PRCI_PROCMONCFG_CORE_CLOCK_MASK \ > - (0x1 << PRCI_PROCMONCFG_CORE_CLOCK_SHIFT) > - > -/* > - * Private structures > - */ > - > -/** > - * struct __prci_data - per-device-instance data > - * @va: base virtual address of the PRCI IP block > - * @parent: parent clk instance > - * > - * PRCI per-device instance data > - */ > -struct __prci_data { > - void *va; > - struct clk parent_hfclk; > - struct clk parent_rtcclk; > -}; > - > -/** > - * struct __prci_wrpll_data - WRPLL configuration and integration data > - * @c: WRPLL current configuration record > - * @enable_bypass: fn ptr to code to bypass the WRPLL (if applicable; else NULL) > - * @disable_bypass: fn ptr to code to not bypass the WRPLL (or NULL) > - * @cfg0_offs: WRPLL CFG0 register offset (in bytes) from the PRCI base address > - * @cfg1_offs: WRPLL CFG1 register offset (in bytes) from the PRCI base address > - * @release_reset: fn ptr to code to release clock reset > - * > - * @enable_bypass and @disable_bypass are used for WRPLL instances > - * that contain a separate external glitchless clock mux downstream > - * from the PLL. The WRPLL internal bypass mux is not glitchless. > - */ > -struct __prci_wrpll_data { > - struct wrpll_cfg c; > - void (*enable_bypass)(struct __prci_data *pd); > - void (*disable_bypass)(struct __prci_data *pd); > - u8 cfg0_offs; > - u8 cfg1_offs; > - void (*release_reset)(struct __prci_data *pd); > -}; > - > -struct __prci_clock; > - > -/* struct __prci_clock_ops - clock operations */ > -struct __prci_clock_ops { > - int (*set_rate)(struct __prci_clock *pc, > - unsigned long rate, > - unsigned long parent_rate); > - unsigned long (*round_rate)(struct __prci_clock *pc, > - unsigned long rate, > - unsigned long *parent_rate); > - unsigned long (*recalc_rate)(struct __prci_clock *pc, > - unsigned long parent_rate); > - int (*enable_clk)(struct __prci_clock *pc, bool enable); > -}; > - > -/** > - * struct __prci_clock - describes a clock device managed by PRCI > - * @name: user-readable clock name string - should match the manual > - * @parent_name: parent name for this clock > - * @ops: struct __prci_clock_ops for control > - * @pwd: WRPLL-specific data, associated with this clock (if not NULL) > - * @pd: PRCI-specific data associated with this clock (if not NULL) > - * > - * PRCI clock data. Used by the PRCI driver to register PRCI-provided > - * clocks to the Linux clock infrastructure. > - */ > -struct __prci_clock { > - const char *name; > - const char *parent_name; > - const struct __prci_clock_ops *ops; > - struct __prci_wrpll_data *pwd; > - struct __prci_data *pd; > -}; > - > -/* > - * Private functions > - */ > - > -/** > - * __prci_readl() - read from a PRCI register > - * @pd: PRCI context > - * @offs: register offset to read from (in bytes, from PRCI base address) > - * > - * Read the register located at offset @offs from the base virtual > - * address of the PRCI register target described by @pd, and return > - * the value to the caller. > - * > - * Context: Any context. > - * > - * Return: the contents of the register described by @pd and @offs. > - */ > -static u32 __prci_readl(struct __prci_data *pd, u32 offs) > -{ > - return readl(pd->va + offs); > -} > - > -static void __prci_writel(u32 v, u32 offs, struct __prci_data *pd) > -{ > - writel(v, pd->va + offs); > -} > - > -/* WRPLL-related private functions */ > - > -/** > - * __prci_wrpll_unpack() - unpack WRPLL configuration registers into parameters > - * @c: ptr to a struct wrpll_cfg record to write config into > - * @r: value read from the PRCI PLL configuration register > - * > - * Given a value @r read from an FU540 PRCI PLL configuration register, > - * split it into fields and populate it into the WRPLL configuration record > - * pointed to by @c. > - * > - * The COREPLLCFG0 macros are used below, but the other *PLLCFG0 macros > - * have the same register layout. > - * > - * Context: Any context. > - */ > -static void __prci_wrpll_unpack(struct wrpll_cfg *c, u32 r) > -{ > - u32 v; > - > - v = r & PRCI_COREPLLCFG0_DIVR_MASK; > - v >>= PRCI_COREPLLCFG0_DIVR_SHIFT; > - c->divr = v; > - > - v = r & PRCI_COREPLLCFG0_DIVF_MASK; > - v >>= PRCI_COREPLLCFG0_DIVF_SHIFT; > - c->divf = v; > - > - v = r & PRCI_COREPLLCFG0_DIVQ_MASK; > - v >>= PRCI_COREPLLCFG0_DIVQ_SHIFT; > - c->divq = v; > - > - v = r & PRCI_COREPLLCFG0_RANGE_MASK; > - v >>= PRCI_COREPLLCFG0_RANGE_SHIFT; > - c->range = v; > - > - c->flags &= (WRPLL_FLAGS_INT_FEEDBACK_MASK | > - WRPLL_FLAGS_EXT_FEEDBACK_MASK); > - > - /* external feedback mode not supported */ > - c->flags |= WRPLL_FLAGS_INT_FEEDBACK_MASK; > -} > - > -/** > - * __prci_wrpll_pack() - pack PLL configuration parameters into a register value > - * @c: pointer to a struct wrpll_cfg record containing the PLL's cfg > - * > - * Using a set of WRPLL configuration values pointed to by @c, > - * assemble a PRCI PLL configuration register value, and return it to > - * the caller. > - * > - * Context: Any context. Caller must ensure that the contents of the > - * record pointed to by @c do not change during the execution > - * of this function. > - * > - * Returns: a value suitable for writing into a PRCI PLL configuration > - * register > - */ > -static u32 __prci_wrpll_pack(const struct wrpll_cfg *c) > -{ > - u32 r = 0; > - > - r |= c->divr << PRCI_COREPLLCFG0_DIVR_SHIFT; > - r |= c->divf << PRCI_COREPLLCFG0_DIVF_SHIFT; > - r |= c->divq << PRCI_COREPLLCFG0_DIVQ_SHIFT; > - r |= c->range << PRCI_COREPLLCFG0_RANGE_SHIFT; > - > - /* external feedback mode not supported */ > - r |= PRCI_COREPLLCFG0_FSE_MASK; > - > - return r; > -} > - > -/** > - * __prci_wrpll_read_cfg0() - read the WRPLL configuration from the PRCI > - * @pd: PRCI context > - * @pwd: PRCI WRPLL metadata > - * > - * Read the current configuration of the PLL identified by @pwd from > - * the PRCI identified by @pd, and store it into the local configuration > - * cache in @pwd. > - * > - * Context: Any context. Caller must prevent the records pointed to by > - * @pd and @pwd from changing during execution. > - */ > -static void __prci_wrpll_read_cfg0(struct __prci_data *pd, > - struct __prci_wrpll_data *pwd) > -{ > - __prci_wrpll_unpack(&pwd->c, __prci_readl(pd, pwd->cfg0_offs)); > -} > - > -/** > - * __prci_wrpll_write_cfg0() - write WRPLL configuration into the PRCI > - * @pd: PRCI context > - * @pwd: PRCI WRPLL metadata > - * @c: WRPLL configuration record to write > - * > - * Write the WRPLL configuration described by @c into the WRPLL > - * configuration register identified by @pwd in the PRCI instance > - * described by @c. Make a cached copy of the WRPLL's current > - * configuration so it can be used by other code. > - * > - * Context: Any context. Caller must prevent the records pointed to by > - * @pd and @pwd from changing during execution. > - */ > -static void __prci_wrpll_write_cfg0(struct __prci_data *pd, > - struct __prci_wrpll_data *pwd, > - struct wrpll_cfg *c) > -{ > - __prci_writel(__prci_wrpll_pack(c), pwd->cfg0_offs, pd); > - > - memcpy(&pwd->c, c, sizeof(*c)); > -} > - > -/** > - * __prci_wrpll_write_cfg1() - write Clock enable/disable configuration > - * into the PRCI > - * @pd: PRCI context > - * @pwd: PRCI WRPLL metadata > - * @enable: Clock enable or disable value > - */ > -static void __prci_wrpll_write_cfg1(struct __prci_data *pd, > - struct __prci_wrpll_data *pwd, > - u32 enable) > -{ > - __prci_writel(enable, pwd->cfg1_offs, pd); > -} > - > -/* Core clock mux control */ > - > -/** > - * __prci_coreclksel_use_hfclk() - switch the CORECLK mux to output HFCLK > - * @pd: struct __prci_data * for the PRCI containing the CORECLK mux reg > - * > - * Switch the CORECLK mux to the HFCLK input source; return once complete. > - * > - * Context: Any context. Caller must prevent concurrent changes to the > - * PRCI_CORECLKSEL_OFFSET register. > - */ > -static void __prci_coreclksel_use_hfclk(struct __prci_data *pd) > -{ > - u32 r; > - > - r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET); > - r |= PRCI_CORECLKSEL_CORECLKSEL_MASK; > - __prci_writel(r, PRCI_CORECLKSEL_OFFSET, pd); > - > - r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET); /* barrier */ > -} > - > -/** > - * __prci_coreclksel_use_corepll() - switch the CORECLK mux to output COREPLL > - * @pd: struct __prci_data * for the PRCI containing the CORECLK mux reg > - * > - * Switch the CORECLK mux to the PLL output clock; return once complete. > - * > - * Context: Any context. Caller must prevent concurrent changes to the > - * PRCI_CORECLKSEL_OFFSET register. > - */ > -static void __prci_coreclksel_use_corepll(struct __prci_data *pd) > -{ > - u32 r; > - > - r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET); > - r &= ~PRCI_CORECLKSEL_CORECLKSEL_MASK; > - __prci_writel(r, PRCI_CORECLKSEL_OFFSET, pd); > - > - r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET); /* barrier */ > -} > - > -static unsigned long sifive_fu540_prci_wrpll_recalc_rate( > - struct __prci_clock *pc, > - unsigned long parent_rate) > -{ > - struct __prci_wrpll_data *pwd = pc->pwd; > > - return wrpll_calc_output_rate(&pwd->c, parent_rate); > -} > - > -static unsigned long sifive_fu540_prci_wrpll_round_rate( > - struct __prci_clock *pc, > - unsigned long rate, > - unsigned long *parent_rate) > -{ > - struct __prci_wrpll_data *pwd = pc->pwd; > - struct wrpll_cfg c; > - > - memcpy(&c, &pwd->c, sizeof(c)); > - > - wrpll_configure_for_rate(&c, rate, *parent_rate); > - > - return wrpll_calc_output_rate(&c, *parent_rate); > -} > - > -static int sifive_fu540_prci_wrpll_set_rate(struct __prci_clock *pc, > - unsigned long rate, > - unsigned long parent_rate) > -{ > - struct __prci_wrpll_data *pwd = pc->pwd; > - struct __prci_data *pd = pc->pd; > - int r; > - > - r = wrpll_configure_for_rate(&pwd->c, rate, parent_rate); > - if (r) > - return r; > - > - if (pwd->enable_bypass) > - pwd->enable_bypass(pd); > - > - __prci_wrpll_write_cfg0(pd, pwd, &pwd->c); > - > - udelay(wrpll_calc_max_lock_us(&pwd->c)); > - > - if (pwd->disable_bypass) > - pwd->disable_bypass(pd); > - > - return 0; > -} > - > -static int sifive_fu540_prci_clock_enable(struct __prci_clock *pc, bool enable) > -{ > - struct __prci_wrpll_data *pwd = pc->pwd; > - struct __prci_data *pd = pc->pd; > - > - if (enable) { > - __prci_wrpll_write_cfg1(pd, pwd, PRCI_COREPLLCFG1_CKE_MASK); > - > - if (pwd->release_reset) > - pwd->release_reset(pd); > - } else { > - u32 r; > - > - r = __prci_readl(pd, pwd->cfg1_offs); > - r &= ~PRCI_COREPLLCFG1_CKE_MASK; > - > - __prci_wrpll_write_cfg1(pd, pwd, r); > - } > - > - return 0; > -} > - > -static const struct __prci_clock_ops sifive_fu540_prci_wrpll_clk_ops = { > - .set_rate = sifive_fu540_prci_wrpll_set_rate, > - .round_rate = sifive_fu540_prci_wrpll_round_rate, > - .recalc_rate = sifive_fu540_prci_wrpll_recalc_rate, > - .enable_clk = sifive_fu540_prci_clock_enable, > -}; > - > -/* TLCLKSEL clock integration */ > - > -static unsigned long sifive_fu540_prci_tlclksel_recalc_rate( > - struct __prci_clock *pc, > - unsigned long parent_rate) > -{ > - struct __prci_data *pd = pc->pd; > - u32 v; > - u8 div; > - > - v = __prci_readl(pd, PRCI_CLKMUXSTATUSREG_OFFSET); > - v &= PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_MASK; > - div = v ? 1 : 2; > - > - return div_u64(parent_rate, div); > -} > - > -static const struct __prci_clock_ops sifive_fu540_prci_tlclksel_clk_ops = { > - .recalc_rate = sifive_fu540_prci_tlclksel_recalc_rate, > -}; > - > -static int __prci_consumer_reset(const char *rst_name, bool trigger) > -{ > - struct udevice *dev; > - struct reset_ctl rst_sig; > - int ret; > - > - ret = uclass_get_device_by_driver(UCLASS_RESET, > - DM_DRIVER_GET(sifive_reset), > - &dev); > - if (ret) { > - dev_err(dev, "Reset driver not found: %d\n", ret); > - return ret; > - } > - > - ret = reset_get_by_name(dev, rst_name, &rst_sig); > - if (ret) { > - dev_err(dev, "failed to get %s reset\n", rst_name); > - return ret; > - } > - > - if (reset_valid(&rst_sig)) { > - if (trigger) > - ret = reset_deassert(&rst_sig); > - else > - ret = reset_assert(&rst_sig); > - if (ret) { > - dev_err(dev, "failed to trigger reset id = %ld\n", > - rst_sig.id); > - return ret; > - } > - } > - > - return ret; > -} > - > -/** > - * __prci_ddr_release_reset() - Release DDR reset > - * @pd: struct __prci_data * for the PRCI containing the DDRCLK mux reg > - * > - */ > -static void __prci_ddr_release_reset(struct __prci_data *pd) > -{ > - /* Release DDR ctrl reset */ > - __prci_consumer_reset("ddr_ctrl", true); > - > - /* HACK to get the '1 full controller clock cycle'. */ > - asm volatile ("fence"); > - > - /* Release DDR AXI reset */ > - __prci_consumer_reset("ddr_axi", true); > - > - /* Release DDR AHB reset */ > - __prci_consumer_reset("ddr_ahb", true); > - > - /* Release DDR PHY reset */ > - __prci_consumer_reset("ddr_phy", true); > - > - /* HACK to get the '1 full controller clock cycle'. */ > - asm volatile ("fence"); > - > - /* > - * These take like 16 cycles to actually propagate. We can't go sending > - * stuff before they come out of reset. So wait. > - */ > - for (int i = 0; i < 256; i++) > - asm volatile ("nop"); > -} > - > -/** > - * __prci_ethernet_release_reset() - Release ethernet reset > - * @pd: struct __prci_data * for the PRCI containing the Ethernet CLK mux reg > - * > - */ > -static void __prci_ethernet_release_reset(struct __prci_data *pd) > -{ > - /* Release GEMGXL reset */ > - __prci_consumer_reset("gemgxl_reset", true); > - > - /* Procmon => core clock */ > - __prci_writel(PRCI_PROCMONCFG_CORE_CLOCK_MASK, PRCI_PROCMONCFG_OFFSET, > - pd); > -} > - > -/* > - * PRCI integration data for each WRPLL instance > - */ > +#include "sifive-prci.h" > > +/* PRCI integration data for each WRPLL instance */ > static struct __prci_wrpll_data __prci_corepll_data = { > .cfg0_offs = PRCI_COREPLLCFG0_OFFSET, > .cfg1_offs = PRCI_COREPLLCFG1_OFFSET, > - .enable_bypass = __prci_coreclksel_use_hfclk, > - .disable_bypass = __prci_coreclksel_use_corepll, > + .enable_bypass = sifive_prci_coreclksel_use_hfclk, > + .disable_bypass = sifive_prci_coreclksel_use_corepll, > }; > > static struct __prci_wrpll_data __prci_ddrpll_data = { > .cfg0_offs = PRCI_DDRPLLCFG0_OFFSET, > .cfg1_offs = PRCI_DDRPLLCFG1_OFFSET, > - .release_reset = __prci_ddr_release_reset, > + .release_reset = sifive_prci_ddr_release_reset, > }; > > static struct __prci_wrpll_data __prci_gemgxlpll_data = { > .cfg0_offs = PRCI_GEMGXLPLLCFG0_OFFSET, > .cfg1_offs = PRCI_GEMGXLPLLCFG1_OFFSET, > - .release_reset = __prci_ethernet_release_reset, > + .release_reset = sifive_prci_ethernet_release_reset, > }; > > -/* > - * List of clock controls provided by the PRCI > - */ > +/* Linux clock framework integration */ > +static const struct __prci_clock_ops sifive_fu540_prci_wrpll_clk_ops = { > + .set_rate = sifive_prci_wrpll_set_rate, > + .round_rate = sifive_prci_wrpll_round_rate, > + .recalc_rate = sifive_prci_wrpll_recalc_rate, > + .enable_clk = sifive_prci_clock_enable, > +}; > > -static struct __prci_clock __prci_init_clocks[] = { > +static const struct __prci_clock_ops sifive_fu540_prci_tlclksel_clk_ops = { > + .recalc_rate = sifive_prci_tlclksel_recalc_rate, > +}; > + > +/* List of clock controls provided by the PRCI */ > +struct __prci_clock __prci_init_clocks_fu540[] = { > [PRCI_CLK_COREPLL] = { > .name = "corepll", > .parent_name = "hfclk", > @@ -665,148 +83,3 @@ static struct __prci_clock __prci_init_clocks[] = { > .ops = &sifive_fu540_prci_tlclksel_clk_ops, > }, > }; > - > -static ulong sifive_fu540_prci_parent_rate(struct __prci_clock *pc) > -{ > - ulong parent_rate; > - struct __prci_clock *p; > - > - if (strcmp(pc->parent_name, "corepll") == 0) { > - p = &__prci_init_clocks[PRCI_CLK_COREPLL]; > - if (!p->pd || !p->ops->recalc_rate) > - return -ENXIO; > - > - return p->ops->recalc_rate(p, sifive_fu540_prci_parent_rate(p)); > - } > - > - if (strcmp(pc->parent_name, "rtcclk") == 0) > - parent_rate = clk_get_rate(&pc->pd->parent_rtcclk); > - else > - parent_rate = clk_get_rate(&pc->pd->parent_hfclk); > - > - return parent_rate; > -} > - > -static ulong sifive_fu540_prci_get_rate(struct clk *clk) > -{ > - struct __prci_clock *pc; > - > - if (ARRAY_SIZE(__prci_init_clocks) <= clk->id) > - return -ENXIO; > - > - pc = &__prci_init_clocks[clk->id]; > - if (!pc->pd || !pc->ops->recalc_rate) > - return -ENXIO; > - > - return pc->ops->recalc_rate(pc, sifive_fu540_prci_parent_rate(pc)); > -} > - > -static ulong sifive_fu540_prci_set_rate(struct clk *clk, ulong rate) > -{ > - int err; > - struct __prci_clock *pc; > - > - if (ARRAY_SIZE(__prci_init_clocks) <= clk->id) > - return -ENXIO; > - > - pc = &__prci_init_clocks[clk->id]; > - if (!pc->pd || !pc->ops->set_rate) > - return -ENXIO; > - > - err = pc->ops->set_rate(pc, rate, sifive_fu540_prci_parent_rate(pc)); > - if (err) > - return err; > - > - return rate; > -} > - > -static int sifive_fu540_prci_enable(struct clk *clk) > -{ > - struct __prci_clock *pc; > - int ret = 0; > - > - if (ARRAY_SIZE(__prci_init_clocks) <= clk->id) > - return -ENXIO; > - > - pc = &__prci_init_clocks[clk->id]; > - if (!pc->pd) > - return -ENXIO; > - > - if (pc->ops->enable_clk) > - ret = pc->ops->enable_clk(pc, 1); > - > - return ret; > -} > - > -static int sifive_fu540_prci_disable(struct clk *clk) > -{ > - struct __prci_clock *pc; > - int ret = 0; > - > - if (ARRAY_SIZE(__prci_init_clocks) <= clk->id) > - return -ENXIO; > - > - pc = &__prci_init_clocks[clk->id]; > - if (!pc->pd) > - return -ENXIO; > - > - if (pc->ops->enable_clk) > - ret = pc->ops->enable_clk(pc, 0); > - > - return ret; > -} > - > -static int sifive_fu540_prci_probe(struct udevice *dev) > -{ > - int i, err; > - struct __prci_clock *pc; > - struct __prci_data *pd = dev_get_priv(dev); > - > - pd->va = (void *)dev_read_addr(dev); > - if (IS_ERR(pd->va)) > - return PTR_ERR(pd->va); > - > - err = clk_get_by_index(dev, 0, &pd->parent_hfclk); > - if (err) > - return err; > - > - err = clk_get_by_index(dev, 1, &pd->parent_rtcclk); > - if (err) > - return err; > - > - for (i = 0; i < ARRAY_SIZE(__prci_init_clocks); ++i) { > - pc = &__prci_init_clocks[i]; > - pc->pd = pd; > - if (pc->pwd) > - __prci_wrpll_read_cfg0(pd, pc->pwd); > - } > - > - return 0; > -} > - > -static struct clk_ops sifive_fu540_prci_ops = { > - .set_rate = sifive_fu540_prci_set_rate, > - .get_rate = sifive_fu540_prci_get_rate, > - .enable = sifive_fu540_prci_enable, > - .disable = sifive_fu540_prci_disable, > -}; > - > -static int sifive_fu540_clk_bind(struct udevice *dev) > -{ > - return sifive_reset_bind(dev, PRCI_DEVICERESETCNT); > -} > - > -static const struct udevice_id sifive_fu540_prci_ids[] = { > - { .compatible = "sifive,fu540-c000-prci" }, > - { } > -}; > - > -U_BOOT_DRIVER(sifive_fu540_prci) = { > - .name = "sifive-fu540-prci", > - .id = UCLASS_CLK, > - .of_match = sifive_fu540_prci_ids, > - .probe = sifive_fu540_prci_probe, > - .ops = &sifive_fu540_prci_ops, > - .priv_auto = sizeof(struct __prci_data), > - .bind = sifive_fu540_clk_bind, > -}; > diff --git a/drivers/clk/sifive/fu540-prci.h b/drivers/clk/sifive/fu540-prci.h > new file mode 100644 > index 0000000000..113301107d > --- /dev/null > +++ b/drivers/clk/sifive/fu540-prci.h > @@ -0,0 +1,22 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * Copyright (C) 2020-2021 SiFive, Inc. > + * Zong Li > + * Pragnesh Patel > + */ > + > +#ifndef __SIFIVE_CLK_FU540_PRCI_H > +#define __SIFIVE_CLK_FU540_PRCI_H > + > +#include "sifive-prci.h" > + > +#define NUM_CLOCK_FU540 4 > + > +extern struct __prci_clock __prci_init_clocks_fu540[NUM_CLOCK_FU540]; > + > +static const struct prci_clk_desc prci_clk_fu540 = { > + .clks = __prci_init_clocks_fu540, > + .num_clks = ARRAY_SIZE(__prci_init_clocks_fu540), > +}; > + > +#endif /* __SIFIVE_CLK_FU540_PRCI_H */ > diff --git a/drivers/clk/sifive/fu740-prci.c b/drivers/clk/sifive/fu740-prci.c > new file mode 100644 > index 0000000000..9a642c1c99 > --- /dev/null > +++ b/drivers/clk/sifive/fu740-prci.c > @@ -0,0 +1,158 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (C) 2018-2021 SiFive, Inc. > + * Wesley Terpstra > + * Paul Walmsley > + * Zong Li > + * Pragnesh Patel > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + */ > + > +#include <dt-bindings/clock/sifive-fu740-prci.h> > +#include "sifive-prci.h" > +#include <asm/io.h> > + > +int sifive_prci_fu740_pciauxclk_enable(struct __prci_clock *pc, bool enable) > +{ > + struct __prci_wrpll_data *pwd = pc->pwd; > + struct __prci_data *pd = pc->pd; > + u32 v; > + > + if (pwd->cfg1_offs != PRCI_PCIEAUXCFG1_OFFSET) > + return -EINVAL; > + > + v = readl(pd->va + pwd->cfg1_offs); > + v = enable ? (v | PRCI_PCIEAUXCFG1_MASK) : (v & ~PRCI_PCIEAUXCFG1_MASK); > + writel(v, pd->va + pwd->cfg1_offs); > + > + return 0; > +} > + > +/* PRCI integration data for each WRPLL instance */ > +static struct __prci_wrpll_data __prci_corepll_data = { > + .cfg0_offs = PRCI_COREPLLCFG0_OFFSET, > + .cfg1_offs = PRCI_COREPLLCFG1_OFFSET, > + .enable_bypass = sifive_prci_coreclksel_use_hfclk, > + .disable_bypass = sifive_prci_coreclksel_use_final_corepll, > +}; > + > +static struct __prci_wrpll_data __prci_ddrpll_data = { > + .cfg0_offs = PRCI_DDRPLLCFG0_OFFSET, > + .cfg1_offs = PRCI_DDRPLLCFG1_OFFSET, > + .release_reset = sifive_prci_ddr_release_reset, > +}; > + > +static struct __prci_wrpll_data __prci_gemgxlpll_data = { > + .cfg0_offs = PRCI_GEMGXLPLLCFG0_OFFSET, > + .cfg1_offs = PRCI_GEMGXLPLLCFG1_OFFSET, > + .release_reset = sifive_prci_ethernet_release_reset, > +}; > + > +static struct __prci_wrpll_data __prci_dvfscorepll_data = { > + .cfg0_offs = PRCI_DVFSCOREPLLCFG0_OFFSET, > + .cfg1_offs = PRCI_DVFSCOREPLLCFG1_OFFSET, > + .enable_bypass = sifive_prci_corepllsel_use_corepll, > + .disable_bypass = sifive_prci_corepllsel_use_dvfscorepll, > +}; > + > +static struct __prci_wrpll_data __prci_hfpclkpll_data = { > + .cfg0_offs = PRCI_HFPCLKPLLCFG0_OFFSET, > + .cfg1_offs = PRCI_HFPCLKPLLCFG1_OFFSET, > + .enable_bypass = sifive_prci_hfpclkpllsel_use_hfclk, > + .disable_bypass = sifive_prci_hfpclkpllsel_use_hfpclkpll, > +}; > + > +static struct __prci_wrpll_data __prci_cltxpll_data = { > + .cfg0_offs = PRCI_CLTXPLLCFG0_OFFSET, > + .cfg1_offs = PRCI_CLTXPLLCFG1_OFFSET, > + .release_reset = sifive_prci_cltx_release_reset, > +}; > + > +static struct __prci_wrpll_data __prci_pcieaux_data = { > + .cfg1_offs = PRCI_PCIEAUXCFG1_OFFSET, > +}; > + > +/* Linux clock framework integration */ > + > +static const struct __prci_clock_ops sifive_fu740_prci_wrpll_clk_ops = { > + .set_rate = sifive_prci_wrpll_set_rate, > + .round_rate = sifive_prci_wrpll_round_rate, > + .recalc_rate = sifive_prci_wrpll_recalc_rate, > + .enable_clk = sifive_prci_clock_enable, > +}; > + > +static const struct __prci_clock_ops sifive_fu740_prci_tlclksel_clk_ops = { > + .recalc_rate = sifive_prci_tlclksel_recalc_rate, > +}; > + > +static const struct __prci_clock_ops sifive_fu740_prci_hfpclkplldiv_clk_ops = { > + .recalc_rate = sifive_prci_hfpclkplldiv_recalc_rate, > +}; > + > +static const struct __prci_clock_ops sifive_fu740_prci_pcieaux_clk_ops = { > + .enable_clk = sifive_prci_fu740_pciauxclk_enable, > +}; > + > +/* List of clock controls provided by the PRCI */ > +struct __prci_clock __prci_init_clocks_fu740[] = { > + [PRCI_CLK_COREPLL] = { > + .name = "corepll", > + .parent_name = "hfclk", > + .ops = &sifive_fu740_prci_wrpll_clk_ops, > + .pwd = &__prci_corepll_data, > + }, > + [PRCI_CLK_DDRPLL] = { > + .name = "ddrpll", > + .parent_name = "hfclk", > + .ops = &sifive_fu740_prci_wrpll_clk_ops, > + .pwd = &__prci_ddrpll_data, > + }, > + [PRCI_CLK_GEMGXLPLL] = { > + .name = "gemgxlpll", > + .parent_name = "hfclk", > + .ops = &sifive_fu740_prci_wrpll_clk_ops, > + .pwd = &__prci_gemgxlpll_data, > + }, > + [PRCI_CLK_DVFSCOREPLL] = { > + .name = "dvfscorepll", > + .parent_name = "hfclk", > + .ops = &sifive_fu740_prci_wrpll_clk_ops, > + .pwd = &__prci_dvfscorepll_data, > + }, > + [PRCI_CLK_HFPCLKPLL] = { > + .name = "hfpclkpll", > + .parent_name = "hfclk", > + .ops = &sifive_fu740_prci_wrpll_clk_ops, > + .pwd = &__prci_hfpclkpll_data, > + }, > + [PRCI_CLK_CLTXPLL] = { > + .name = "cltxpll", > + .parent_name = "hfclk", > + .ops = &sifive_fu740_prci_wrpll_clk_ops, > + .pwd = &__prci_cltxpll_data, > + }, > + [PRCI_CLK_TLCLK] = { > + .name = "tlclk", > + .parent_name = "corepll", > + .ops = &sifive_fu740_prci_tlclksel_clk_ops, > + }, > + [PRCI_CLK_PCLK] = { > + .name = "pclk", > + .parent_name = "hfpclkpll", > + .ops = &sifive_fu740_prci_hfpclkplldiv_clk_ops, > + }, > + [PRCI_CLK_PCIEAUX] { > + .name = "pciaux", > + .parent_name = "", > + .ops = &sifive_fu740_prci_pcieaux_clk_ops, > + .pwd = &__prci_pcieaux_data, > + } > +}; > diff --git a/drivers/clk/sifive/fu740-prci.h b/drivers/clk/sifive/fu740-prci.h > new file mode 100644 > index 0000000000..b74f078906 > --- /dev/null > +++ b/drivers/clk/sifive/fu740-prci.h > @@ -0,0 +1,22 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * Copyright (C) 2020-2021 SiFive, Inc. > + * Zong Li > + * Pragnesh Patel > + */ > + > +#ifndef __SIFIVE_CLK_FU740_PRCI_H > +#define __SIFIVE_CLK_FU740_PRCI_H > + > +#include "sifive-prci.h" > + > +#define NUM_CLOCK_FU740 9 > + > +extern struct __prci_clock __prci_init_clocks_fu740[NUM_CLOCK_FU740]; > + > +static const struct prci_clk_desc prci_clk_fu740 = { > + .clks = __prci_init_clocks_fu740, > + .num_clks = ARRAY_SIZE(__prci_init_clocks_fu740), > +}; > + > +#endif /* __SIFIVE_CLK_FU740_PRCI_H */ > diff --git a/drivers/clk/sifive/sifive-prci.c b/drivers/clk/sifive/sifive-prci.c > new file mode 100644 > index 0000000000..cd1acb9442 > --- /dev/null > +++ b/drivers/clk/sifive/sifive-prci.c > @@ -0,0 +1,733 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (C) 2018-2021 SiFive, Inc. > + * Wesley Terpstra > + * Paul Walmsley > + * Zong Li > + * Pragnesh Patel > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * The PRCI implements clock and reset control for the SiFive chip. > + * This driver assumes that it has sole control over all PRCI resources. > + * > + * This driver is based on the PRCI driver written by Wesley Terpstra: > + * https://github.com/riscv/riscv-linux/commit/999529edf517ed75b56659d456d221b… > + */ > + > +#include <common.h> > +#include <clk-uclass.h> > +#include <clk.h> > +#include <dm.h> > +#include <dm/device_compat.h> > +#include <reset.h> > +#include <asm/io.h> > +#include <asm/arch/reset.h> > +#include <linux/delay.h> > +#include <linux/math64.h> > +#include <dt-bindings/clock/sifive-fu740-prci.h> > + > +#include "fu540-prci.h" > +#include "fu740-prci.h" > + > +/* > + * Private functions > + */ > + > +/** > + * __prci_readl() - read from a PRCI register > + * @pd: PRCI context > + * @offs: register offset to read from (in bytes, from PRCI base address) > + * > + * Read the register located at offset @offs from the base virtual > + * address of the PRCI register target described by @pd, and return > + * the value to the caller. > + * > + * Context: Any context. > + * > + * Return: the contents of the register described by @pd and @offs. > + */ > +static u32 __prci_readl(struct __prci_data *pd, u32 offs) > +{ > + return readl(pd->va + offs); > +} > + > +static void __prci_writel(u32 v, u32 offs, struct __prci_data *pd) > +{ > + writel(v, pd->va + offs); > +} > + > +/* WRPLL-related private functions */ > + > +/** > + * __prci_wrpll_unpack() - unpack WRPLL configuration registers into parameters > + * @c: ptr to a struct wrpll_cfg record to write config into > + * @r: value read from the PRCI PLL configuration register > + * > + * Given a value @r read from an FU540 PRCI PLL configuration register, > + * split it into fields and populate it into the WRPLL configuration record > + * pointed to by @c. > + * > + * The COREPLLCFG0 macros are used below, but the other *PLLCFG0 macros > + * have the same register layout. > + * > + * Context: Any context. > + */ > +static void __prci_wrpll_unpack(struct wrpll_cfg *c, u32 r) > +{ > + u32 v; > + > + v = r & PRCI_COREPLLCFG0_DIVR_MASK; > + v >>= PRCI_COREPLLCFG0_DIVR_SHIFT; > + c->divr = v; > + > + v = r & PRCI_COREPLLCFG0_DIVF_MASK; > + v >>= PRCI_COREPLLCFG0_DIVF_SHIFT; > + c->divf = v; > + > + v = r & PRCI_COREPLLCFG0_DIVQ_MASK; > + v >>= PRCI_COREPLLCFG0_DIVQ_SHIFT; > + c->divq = v; > + > + v = r & PRCI_COREPLLCFG0_RANGE_MASK; > + v >>= PRCI_COREPLLCFG0_RANGE_SHIFT; > + c->range = v; > + > + c->flags &= (WRPLL_FLAGS_INT_FEEDBACK_MASK | > + WRPLL_FLAGS_EXT_FEEDBACK_MASK); > + > + /* external feedback mode not supported */ > + c->flags |= WRPLL_FLAGS_INT_FEEDBACK_MASK; > +} > + > +/** > + * __prci_wrpll_pack() - pack PLL configuration parameters into a register value > + * @c: pointer to a struct wrpll_cfg record containing the PLL's cfg > + * > + * Using a set of WRPLL configuration values pointed to by @c, > + * assemble a PRCI PLL configuration register value, and return it to > + * the caller. > + * > + * Context: Any context. Caller must ensure that the contents of the > + * record pointed to by @c do not change during the execution > + * of this function. > + * > + * Returns: a value suitable for writing into a PRCI PLL configuration > + * register > + */ > +static u32 __prci_wrpll_pack(const struct wrpll_cfg *c) > +{ > + u32 r = 0; > + > + r |= c->divr << PRCI_COREPLLCFG0_DIVR_SHIFT; > + r |= c->divf << PRCI_COREPLLCFG0_DIVF_SHIFT; > + r |= c->divq << PRCI_COREPLLCFG0_DIVQ_SHIFT; > + r |= c->range << PRCI_COREPLLCFG0_RANGE_SHIFT; > + > + /* external feedback mode not supported */ > + r |= PRCI_COREPLLCFG0_FSE_MASK; > + > + return r; > +} > + > +/** > + * __prci_wrpll_read_cfg0() - read the WRPLL configuration from the PRCI > + * @pd: PRCI context > + * @pwd: PRCI WRPLL metadata > + * > + * Read the current configuration of the PLL identified by @pwd from > + * the PRCI identified by @pd, and store it into the local configuration > + * cache in @pwd. > + * > + * Context: Any context. Caller must prevent the records pointed to by > + * @pd and @pwd from changing during execution. > + */ > +static void __prci_wrpll_read_cfg0(struct __prci_data *pd, > + struct __prci_wrpll_data *pwd) > +{ > + __prci_wrpll_unpack(&pwd->c, __prci_readl(pd, pwd->cfg0_offs)); > +} > + > +/** > + * __prci_wrpll_write_cfg0() - write WRPLL configuration into the PRCI > + * @pd: PRCI context > + * @pwd: PRCI WRPLL metadata > + * @c: WRPLL configuration record to write > + * > + * Write the WRPLL configuration described by @c into the WRPLL > + * configuration register identified by @pwd in the PRCI instance > + * described by @c. Make a cached copy of the WRPLL's current > + * configuration so it can be used by other code. > + * > + * Context: Any context. Caller must prevent the records pointed to by > + * @pd and @pwd from changing during execution. > + */ > +static void __prci_wrpll_write_cfg0(struct __prci_data *pd, > + struct __prci_wrpll_data *pwd, > + struct wrpll_cfg *c) > +{ > + __prci_writel(__prci_wrpll_pack(c), pwd->cfg0_offs, pd); > + > + memcpy(&pwd->c, c, sizeof(*c)); > +} > + > +/** > + * __prci_wrpll_write_cfg1() - write Clock enable/disable configuration > + * into the PRCI > + * @pd: PRCI context > + * @pwd: PRCI WRPLL metadata > + * @enable: Clock enable or disable value > + */ > +static void __prci_wrpll_write_cfg1(struct __prci_data *pd, > + struct __prci_wrpll_data *pwd, > + u32 enable) > +{ > + __prci_writel(enable, pwd->cfg1_offs, pd); > +} > + > +unsigned long sifive_prci_wrpll_recalc_rate(struct __prci_clock *pc, > + unsigned long parent_rate) > +{ > + struct __prci_wrpll_data *pwd = pc->pwd; > + > + return wrpll_calc_output_rate(&pwd->c, parent_rate); > +} > + > +unsigned long sifive_prci_wrpll_round_rate(struct __prci_clock *pc, > + unsigned long rate, > + unsigned long *parent_rate) > +{ > + struct __prci_wrpll_data *pwd = pc->pwd; > + struct wrpll_cfg c; > + > + memcpy(&c, &pwd->c, sizeof(c)); > + > + wrpll_configure_for_rate(&c, rate, *parent_rate); > + > + return wrpll_calc_output_rate(&c, *parent_rate); > +} > + > +int sifive_prci_wrpll_set_rate(struct __prci_clock *pc, > + unsigned long rate, > + unsigned long parent_rate) > +{ > + struct __prci_wrpll_data *pwd = pc->pwd; > + struct __prci_data *pd = pc->pd; > + int r; > + > + r = wrpll_configure_for_rate(&pwd->c, rate, parent_rate); > + if (r) > + return r; > + > + if (pwd->enable_bypass) > + pwd->enable_bypass(pd); > + > + __prci_wrpll_write_cfg0(pd, pwd, &pwd->c); > + > + udelay(wrpll_calc_max_lock_us(&pwd->c)); > + > + return 0; > +} > + > +int sifive_prci_clock_enable(struct __prci_clock *pc, bool enable) > +{ > + struct __prci_wrpll_data *pwd = pc->pwd; > + struct __prci_data *pd = pc->pd; > + > + if (enable) { > + __prci_wrpll_write_cfg1(pd, pwd, PRCI_COREPLLCFG1_CKE_MASK); > + > + if (pwd->disable_bypass) > + pwd->disable_bypass(pd); > + > + if (pwd->release_reset) > + pwd->release_reset(pd); > + } else { > + u32 r; > + > + if (pwd->enable_bypass) > + pwd->enable_bypass(pd); > + > + r = __prci_readl(pd, pwd->cfg1_offs); > + r &= ~PRCI_COREPLLCFG1_CKE_MASK; > + > + __prci_wrpll_write_cfg1(pd, pwd, r); > + } > + > + return 0; > +} > + > +/* TLCLKSEL clock integration */ > + > +unsigned long sifive_prci_tlclksel_recalc_rate(struct __prci_clock *pc, > + unsigned long parent_rate) > +{ > + struct __prci_data *pd = pc->pd; > + u32 v; > + u8 div; > + > + v = __prci_readl(pd, PRCI_CLKMUXSTATUSREG_OFFSET); > + v &= PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_MASK; > + div = v ? 1 : 2; > + > + return div_u64(parent_rate, div); > +} > + > +/* HFPCLK clock integration */ > + > +unsigned long sifive_prci_hfpclkplldiv_recalc_rate(struct __prci_clock *pc, > + unsigned long parent_rate) > +{ > + struct __prci_data *pd = pc->pd; > + u32 div = __prci_readl(pd, PRCI_HFPCLKPLLDIV_OFFSET); > + > + return div_u64(parent_rate, div + 2); > +} > + > +/** > + * sifive_prci_coreclksel_use_final_corepll() - switch the CORECLK mux to output > + * FINAL_COREPLL > + * @pd: struct __prci_data * for the PRCI containing the CORECLK mux reg > + * > + * Switch the CORECLK mux to the final COREPLL output clock; return once > + * complete. > + * > + * Context: Any context. Caller must prevent concurrent changes to the > + * PRCI_CORECLKSEL_OFFSET register. > + */ > +void sifive_prci_coreclksel_use_final_corepll(struct __prci_data *pd) > +{ > + u32 r; > + > + r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET); > + r &= ~PRCI_CORECLKSEL_CORECLKSEL_MASK; > + __prci_writel(r, PRCI_CORECLKSEL_OFFSET, pd); > + > + r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET); /* barrier */ > +} > + > +/** > + * sifive_prci_corepllsel_use_dvfscorepll() - switch the COREPLL mux to > + * output DVFS_COREPLL > + * @pd: struct __prci_data * for the PRCI containing the COREPLL mux reg > + * > + * Switch the COREPLL mux to the DVFSCOREPLL output clock; return once complete. > + * > + * Context: Any context. Caller must prevent concurrent changes to the > + * PRCI_COREPLLSEL_OFFSET register. > + */ > +void sifive_prci_corepllsel_use_dvfscorepll(struct __prci_data *pd) > +{ > + u32 r; > + > + r = __prci_readl(pd, PRCI_COREPLLSEL_OFFSET); > + r |= PRCI_COREPLLSEL_COREPLLSEL_MASK; > + __prci_writel(r, PRCI_COREPLLSEL_OFFSET, pd); > + > + r = __prci_readl(pd, PRCI_COREPLLSEL_OFFSET); /* barrier */ > +} > + > +/** > + * sifive_prci_corepllsel_use_corepll() - switch the COREPLL mux to > + * output COREPLL > + * @pd: struct __prci_data * for the PRCI containing the COREPLL mux reg > + * > + * Switch the COREPLL mux to the COREPLL output clock; return once complete. > + * > + * Context: Any context. Caller must prevent concurrent changes to the > + * PRCI_COREPLLSEL_OFFSET register. > + */ > +void sifive_prci_corepllsel_use_corepll(struct __prci_data *pd) > +{ > + u32 r; > + > + r = __prci_readl(pd, PRCI_COREPLLSEL_OFFSET); > + r &= ~PRCI_COREPLLSEL_COREPLLSEL_MASK; > + __prci_writel(r, PRCI_COREPLLSEL_OFFSET, pd); > + > + r = __prci_readl(pd, PRCI_COREPLLSEL_OFFSET); /* barrier */ > +} > + > +/** > + * sifive_prci_hfpclkpllsel_use_hfclk() - switch the HFPCLKPLL mux to > + * output HFCLK > + * @pd: struct __prci_data * for the PRCI containing the HFPCLKPLL mux reg > + * > + * Switch the HFPCLKPLL mux to the HFCLK input source; return once complete. > + * > + * Context: Any context. Caller must prevent concurrent changes to the > + * PRCI_HFPCLKPLLSEL_OFFSET register. > + */ > +void sifive_prci_hfpclkpllsel_use_hfclk(struct __prci_data *pd) > +{ > + u32 r; > + > + r = __prci_readl(pd, PRCI_HFPCLKPLLSEL_OFFSET); > + r |= PRCI_HFPCLKPLLSEL_HFPCLKPLLSEL_MASK; > + __prci_writel(r, PRCI_HFPCLKPLLSEL_OFFSET, pd); > + > + r = __prci_readl(pd, PRCI_HFPCLKPLLSEL_OFFSET); /* barrier */ > +} > + > +/** > + * sifive_prci_hfpclkpllsel_use_hfpclkpll() - switch the HFPCLKPLL mux to > + * output HFPCLKPLL > + * @pd: struct __prci_data * for the PRCI containing the HFPCLKPLL mux reg > + * > + * Switch the HFPCLKPLL mux to the HFPCLKPLL output clock; return once complete. > + * > + * Context: Any context. Caller must prevent concurrent changes to the > + * PRCI_HFPCLKPLLSEL_OFFSET register. > + */ > +void sifive_prci_hfpclkpllsel_use_hfpclkpll(struct __prci_data *pd) > +{ > + u32 r; > + > + r = __prci_readl(pd, PRCI_HFPCLKPLLSEL_OFFSET); > + r &= ~PRCI_HFPCLKPLLSEL_HFPCLKPLLSEL_MASK; > + __prci_writel(r, PRCI_HFPCLKPLLSEL_OFFSET, pd); > + > + r = __prci_readl(pd, PRCI_HFPCLKPLLSEL_OFFSET); /* barrier */ > +} > + > +static int __prci_consumer_reset(const char *rst_name, bool trigger) > +{ > + struct udevice *dev; > + struct reset_ctl rst_sig; > + int ret; > + > + ret = uclass_get_device_by_driver(UCLASS_RESET, > + DM_DRIVER_GET(sifive_reset), > + &dev); > + if (ret) { > + dev_err(dev, "Reset driver not found: %d\n", ret); > + return ret; > + } > + > + ret = reset_get_by_name(dev, rst_name, &rst_sig); > + if (ret) { > + dev_err(dev, "failed to get %s reset\n", rst_name); > + return ret; > + } > + > + if (reset_valid(&rst_sig)) { > + if (trigger) > + ret = reset_deassert(&rst_sig); > + else > + ret = reset_assert(&rst_sig); > + if (ret) { > + dev_err(dev, "failed to trigger reset id = %ld\n", > + rst_sig.id); > + return ret; > + } > + } > + > + return ret; > +} > + > +/** > + * sifive_prci_ddr_release_reset() - Release DDR reset > + * @pd: struct __prci_data * for the PRCI containing the DDRCLK mux reg > + * > + */ > +void sifive_prci_ddr_release_reset(struct __prci_data *pd) > +{ > + /* Release DDR ctrl reset */ > + __prci_consumer_reset("ddr_ctrl", true); > + > + /* HACK to get the '1 full controller clock cycle'. */ > + asm volatile ("fence"); > + > + /* Release DDR AXI reset */ > + __prci_consumer_reset("ddr_axi", true); > + > + /* Release DDR AHB reset */ > + __prci_consumer_reset("ddr_ahb", true); > + > + /* Release DDR PHY reset */ > + __prci_consumer_reset("ddr_phy", true); > + > + /* HACK to get the '1 full controller clock cycle'. */ > + asm volatile ("fence"); > + > + /* > + * These take like 16 cycles to actually propagate. We can't go sending > + * stuff before they come out of reset. So wait. > + */ > + for (int i = 0; i < 256; i++) > + asm volatile ("nop"); > +} > + > +/** > + * sifive_prci_ethernet_release_reset() - Release ethernet reset > + * @pd: struct __prci_data * for the PRCI containing the Ethernet CLK mux reg > + * > + */ > +void sifive_prci_ethernet_release_reset(struct __prci_data *pd) > +{ > + /* Release GEMGXL reset */ > + __prci_consumer_reset("gemgxl_reset", true); > + > + /* Procmon => core clock */ > + __prci_writel(PRCI_PROCMONCFG_CORE_CLOCK_MASK, PRCI_PROCMONCFG_OFFSET, > + pd); > + > + /* Release Chiplink reset */ > + __prci_consumer_reset("cltx_reset", true); > +} > + > +/** > + * sifive_prci_cltx_release_reset() - Release cltx reset > + * @pd: struct __prci_data * for the PRCI containing the Ethernet CLK mux reg > + * > + */ > +void sifive_prci_cltx_release_reset(struct __prci_data *pd) > +{ > + /* Release CLTX reset */ > + __prci_consumer_reset("cltx_reset", true); > +} > + > +/* Core clock mux control */ > + > +/** > + * sifive_prci_coreclksel_use_hfclk() - switch the CORECLK mux to output HFCLK > + * @pd: struct __prci_data * for the PRCI containing the CORECLK mux reg > + * > + * Switch the CORECLK mux to the HFCLK input source; return once complete. > + * > + * Context: Any context. Caller must prevent concurrent changes to the > + * PRCI_CORECLKSEL_OFFSET register. > + */ > +void sifive_prci_coreclksel_use_hfclk(struct __prci_data *pd) > +{ > + u32 r; > + > + r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET); > + r |= PRCI_CORECLKSEL_CORECLKSEL_MASK; > + __prci_writel(r, PRCI_CORECLKSEL_OFFSET, pd); > + > + r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET); /* barrier */ > +} > + > +/** > + * sifive_prci_coreclksel_use_corepll() - switch the CORECLK mux to output COREPLL > + * @pd: struct __prci_data * for the PRCI containing the CORECLK mux reg > + * > + * Switch the CORECLK mux to the PLL output clock; return once complete. > + * > + * Context: Any context. Caller must prevent concurrent changes to the > + * PRCI_CORECLKSEL_OFFSET register. > + */ > +void sifive_prci_coreclksel_use_corepll(struct __prci_data *pd) > +{ > + u32 r; > + > + r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET); > + r &= ~PRCI_CORECLKSEL_CORECLKSEL_MASK; > + __prci_writel(r, PRCI_CORECLKSEL_OFFSET, pd); > + > + r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET); /* barrier */ > +} > + > +static ulong sifive_prci_parent_rate(struct __prci_clock *pc, struct prci_clk_desc *data) > +{ > + ulong parent_rate; > + ulong i; > + struct __prci_clock *p; > + > + if (strcmp(pc->parent_name, "corepll") == 0 || > + strcmp(pc->parent_name, "hfpclkpll") == 0) { > + for (i = 0; i < data->num_clks; i++) { > + if (strcmp(pc->parent_name, data->clks[i].name) == 0) > + break; > + } > + > + if (i >= data->num_clks) > + return -ENXIO; > + > + p = &data->clks[i]; > + if (!p->pd || !p->ops->recalc_rate) > + return -ENXIO; > + > + return p->ops->recalc_rate(p, sifive_prci_parent_rate(p, data)); > + } > + > + if (strcmp(pc->parent_name, "rtcclk") == 0) > + parent_rate = clk_get_rate(&pc->pd->parent_rtcclk); > + else > + parent_rate = clk_get_rate(&pc->pd->parent_hfclk); > + > + return parent_rate; > +} > + > +static ulong sifive_prci_get_rate(struct clk *clk) > +{ > + struct __prci_clock *pc; > + struct prci_clk_desc *data = > + (struct prci_clk_desc *)dev_get_driver_data(clk->dev); > + > + if (data->num_clks <= clk->id) > + return -ENXIO; > + > + pc = &data->clks[clk->id]; > + if (!pc->pd || !pc->ops->recalc_rate) > + return -ENXIO; > + > + return pc->ops->recalc_rate(pc, sifive_prci_parent_rate(pc, data)); > +} > + > +static ulong sifive_prci_set_rate(struct clk *clk, ulong rate) > +{ > + int err; > + struct __prci_clock *pc; > + struct prci_clk_desc *data = > + (struct prci_clk_desc *)dev_get_driver_data(clk->dev); > + > + if (data->num_clks <= clk->id) > + return -ENXIO; > + > + pc = &data->clks[clk->id]; > + if (!pc->pd || !pc->ops->set_rate) > + return -ENXIO; > + > + err = pc->ops->set_rate(pc, rate, sifive_prci_parent_rate(pc, data)); > + if (err) > + return err; > + > + return rate; > +} > + > +static int sifive_prci_enable(struct clk *clk) > +{ > + struct __prci_clock *pc; > + int ret = 0; > + struct prci_clk_desc *data = > + (struct prci_clk_desc *)dev_get_driver_data(clk->dev); > + > + if (data->num_clks <= clk->id) > + return -ENXIO; > + > + pc = &data->clks[clk->id]; > + if (!pc->pd) > + return -ENXIO; > + > + if (pc->ops->enable_clk) > + ret = pc->ops->enable_clk(pc, 1); > + > + return ret; > +} > + > +static int sifive_prci_disable(struct clk *clk) > +{ > + struct __prci_clock *pc; > + int ret = 0; > + struct prci_clk_desc *data = > + (struct prci_clk_desc *)dev_get_driver_data(clk->dev); > + > + if (data->num_clks <= clk->id) > + return -ENXIO; > + > + pc = &data->clks[clk->id]; > + if (!pc->pd) > + return -ENXIO; > + > + if (pc->ops->enable_clk) > + ret = pc->ops->enable_clk(pc, 0); > + > + return ret; > +} > + > +static int sifive_prci_probe(struct udevice *dev) > +{ > + int i, err; > + struct __prci_clock *pc; > + struct __prci_data *pd = dev_get_priv(dev); > + > + struct prci_clk_desc *data = > + (struct prci_clk_desc *)dev_get_driver_data(dev); > + > + pd->va = (void *)dev_read_addr(dev); > + if (IS_ERR(pd->va)) > + return PTR_ERR(pd->va); > + > + err = clk_get_by_index(dev, 0, &pd->parent_hfclk); > + if (err) > + return err; > + > + err = clk_get_by_index(dev, 1, &pd->parent_rtcclk); > + if (err) > + return err; > + > + for (i = 0; i < data->num_clks; ++i) { > + pc = &data->clks[i]; > + pc->pd = pd; > + if (pc->pwd) > + __prci_wrpll_read_cfg0(pd, pc->pwd); > + } > + > + if (IS_ENABLED(CONFIG_SPL_BUILD)) { > + if (device_is_compatible(dev, "sifive,fu740-c000-prci")) { > + u32 prci_pll_reg; > + unsigned long parent_rate; > + > + prci_pll_reg = readl(pd->va + PRCI_PRCIPLL_OFFSET); > + > + if (prci_pll_reg & PRCI_PRCIPLL_HFPCLKPLL) { > + /* > + * Only initialize the HFPCLK PLL. In this > + * case the design uses hfpclk to drive > + * Chiplink > + */ > + pc = &data->clks[PRCI_CLK_HFPCLKPLL]; > + parent_rate = sifive_prci_parent_rate(pc, data); > + sifive_prci_wrpll_set_rate(pc, 260000000, > + parent_rate); > + pc->ops->enable_clk(pc, 1); > + } else if (prci_pll_reg & PRCI_PRCIPLL_CLTXPLL) { > + /* CLTX pll init */ > + pc = &data->clks[PRCI_CLK_CLTXPLL]; > + parent_rate = sifive_prci_parent_rate(pc, data); > + sifive_prci_wrpll_set_rate(pc, 260000000, > + parent_rate); > + pc->ops->enable_clk(pc, 1); > + } > + } > + } > + > + return 0; > +} > + > +static struct clk_ops sifive_prci_ops = { > + .set_rate = sifive_prci_set_rate, > + .get_rate = sifive_prci_get_rate, > + .enable = sifive_prci_enable, > + .disable = sifive_prci_disable, > +}; > + > +static int sifive_clk_bind(struct udevice *dev) > +{ > + return sifive_reset_bind(dev, PRCI_DEVICERESETCNT); > +} > + > +static const struct udevice_id sifive_prci_ids[] = { > + { .compatible = "sifive,fu540-c000-prci", .data = (ulong)&prci_clk_fu540 }, > + { .compatible = "sifive,fu740-c000-prci", .data = (ulong)&prci_clk_fu740 }, > + { } > +}; > + > +U_BOOT_DRIVER(sifive_prci) = { > + .name = "sifive-prci", > + .id = UCLASS_CLK, > + .of_match = sifive_prci_ids, > + .probe = sifive_prci_probe, > + .ops = &sifive_prci_ops, > + .priv_auto = sizeof(struct __prci_data), > + .bind = sifive_clk_bind, > +}; > diff --git a/drivers/clk/sifive/sifive-prci.h b/drivers/clk/sifive/sifive-prci.h > new file mode 100644 > index 0000000000..5ce33d6184 > --- /dev/null > +++ b/drivers/clk/sifive/sifive-prci.h > @@ -0,0 +1,323 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * Copyright (C) 2020-2021 SiFive, Inc. > + * Wesley Terpstra > + * Paul Walmsley > + * Zong Li > + * Pragnesh Patel > + */ > + > +#ifndef __SIFIVE_CLK_SIFIVE_PRCI_H > +#define __SIFIVE_CLK_SIFIVE_PRCI_H > + > +#include <clk.h> > +#include <linux/clk/analogbits-wrpll-cln28hpc.h> > + > +/* > + * EXPECTED_CLK_PARENT_COUNT: how many parent clocks this driver expects: > + * hfclk and rtcclk > + */ > +#define EXPECTED_CLK_PARENT_COUNT 2 > + > +/* > + * Register offsets and bitmasks > + */ > + > +/* COREPLLCFG0 */ > +#define PRCI_COREPLLCFG0_OFFSET 0x4 > +#define PRCI_COREPLLCFG0_DIVR_SHIFT 0 > +#define PRCI_COREPLLCFG0_DIVR_MASK (0x3f << PRCI_COREPLLCFG0_DIVR_SHIFT) > +#define PRCI_COREPLLCFG0_DIVF_SHIFT 6 > +#define PRCI_COREPLLCFG0_DIVF_MASK (0x1ff << PRCI_COREPLLCFG0_DIVF_SHIFT) > +#define PRCI_COREPLLCFG0_DIVQ_SHIFT 15 > +#define PRCI_COREPLLCFG0_DIVQ_MASK (0x7 << PRCI_COREPLLCFG0_DIVQ_SHIFT) > +#define PRCI_COREPLLCFG0_RANGE_SHIFT 18 > +#define PRCI_COREPLLCFG0_RANGE_MASK (0x7 << PRCI_COREPLLCFG0_RANGE_SHIFT) > +#define PRCI_COREPLLCFG0_BYPASS_SHIFT 24 > +#define PRCI_COREPLLCFG0_BYPASS_MASK (0x1 << PRCI_COREPLLCFG0_BYPASS_SHIFT) > +#define PRCI_COREPLLCFG0_FSE_SHIFT 25 > +#define PRCI_COREPLLCFG0_FSE_MASK (0x1 << PRCI_COREPLLCFG0_FSE_SHIFT) > +#define PRCI_COREPLLCFG0_LOCK_SHIFT 31 > +#define PRCI_COREPLLCFG0_LOCK_MASK (0x1 << PRCI_COREPLLCFG0_LOCK_SHIFT) > + > +/* COREPLLCFG1 */ > +#define PRCI_COREPLLCFG1_OFFSET 0x8 > +#define PRCI_COREPLLCFG1_CKE_SHIFT 31 > +#define PRCI_COREPLLCFG1_CKE_MASK (0x1 << PRCI_COREPLLCFG1_CKE_SHIFT) > + > +/* DDRPLLCFG0 */ > +#define PRCI_DDRPLLCFG0_OFFSET 0xc > +#define PRCI_DDRPLLCFG0_DIVR_SHIFT 0 > +#define PRCI_DDRPLLCFG0_DIVR_MASK (0x3f << PRCI_DDRPLLCFG0_DIVR_SHIFT) > +#define PRCI_DDRPLLCFG0_DIVF_SHIFT 6 > +#define PRCI_DDRPLLCFG0_DIVF_MASK (0x1ff << PRCI_DDRPLLCFG0_DIVF_SHIFT) > +#define PRCI_DDRPLLCFG0_DIVQ_SHIFT 15 > +#define PRCI_DDRPLLCFG0_DIVQ_MASK (0x7 << PRCI_DDRPLLCFG0_DIVQ_SHIFT) > +#define PRCI_DDRPLLCFG0_RANGE_SHIFT 18 > +#define PRCI_DDRPLLCFG0_RANGE_MASK (0x7 << PRCI_DDRPLLCFG0_RANGE_SHIFT) > +#define PRCI_DDRPLLCFG0_BYPASS_SHIFT 24 > +#define PRCI_DDRPLLCFG0_BYPASS_MASK (0x1 << PRCI_DDRPLLCFG0_BYPASS_SHIFT) > +#define PRCI_DDRPLLCFG0_FSE_SHIFT 25 > +#define PRCI_DDRPLLCFG0_FSE_MASK (0x1 << PRCI_DDRPLLCFG0_FSE_SHIFT) > +#define PRCI_DDRPLLCFG0_LOCK_SHIFT 31 > +#define PRCI_DDRPLLCFG0_LOCK_MASK (0x1 << PRCI_DDRPLLCFG0_LOCK_SHIFT) > + > +/* DDRPLLCFG1 */ > +#define PRCI_DDRPLLCFG1_OFFSET 0x10 > +#define PRCI_DDRPLLCFG1_CKE_SHIFT 31 > +#define PRCI_DDRPLLCFG1_CKE_MASK (0x1 << PRCI_DDRPLLCFG1_CKE_SHIFT) > + > +/* PCIEAUXCFG1 */ > +#define PRCI_PCIEAUXCFG1_OFFSET 0x14 > +#define PRCI_PCIEAUXCFG1_SHIFT 0 > +#define PRCI_PCIEAUXCFG1_MASK (0x1 << PRCI_PCIEAUXCFG1_SHIFT) > + > +/* GEMGXLPLLCFG0 */ > +#define PRCI_GEMGXLPLLCFG0_OFFSET 0x1c > +#define PRCI_GEMGXLPLLCFG0_DIVR_SHIFT 0 > +#define PRCI_GEMGXLPLLCFG0_DIVR_MASK \ > + (0x3f << PRCI_GEMGXLPLLCFG0_DIVR_SHIFT) > +#define PRCI_GEMGXLPLLCFG0_DIVF_SHIFT 6 > +#define PRCI_GEMGXLPLLCFG0_DIVF_MASK \ > + (0x1ff << PRCI_GEMGXLPLLCFG0_DIVF_SHIFT) > +#define PRCI_GEMGXLPLLCFG0_DIVQ_SHIFT 15 > +#define PRCI_GEMGXLPLLCFG0_DIVQ_MASK (0x7 << PRCI_GEMGXLPLLCFG0_DIVQ_SHIFT) > +#define PRCI_GEMGXLPLLCFG0_RANGE_SHIFT 18 > +#define PRCI_GEMGXLPLLCFG0_RANGE_MASK \ > + (0x7 << PRCI_GEMGXLPLLCFG0_RANGE_SHIFT) > +#define PRCI_GEMGXLPLLCFG0_BYPASS_SHIFT 24 > +#define PRCI_GEMGXLPLLCFG0_BYPASS_MASK \ > + (0x1 << PRCI_GEMGXLPLLCFG0_BYPASS_SHIFT) > +#define PRCI_GEMGXLPLLCFG0_FSE_SHIFT 25 > +#define PRCI_GEMGXLPLLCFG0_FSE_MASK \ > + (0x1 << PRCI_GEMGXLPLLCFG0_FSE_SHIFT) > +#define PRCI_GEMGXLPLLCFG0_LOCK_SHIFT 31 > +#define PRCI_GEMGXLPLLCFG0_LOCK_MASK (0x1 << PRCI_GEMGXLPLLCFG0_LOCK_SHIFT) > + > +/* GEMGXLPLLCFG1 */ > +#define PRCI_GEMGXLPLLCFG1_OFFSET 0x20 > +#define PRCI_GEMGXLPLLCFG1_CKE_SHIFT 31 > +#define PRCI_GEMGXLPLLCFG1_CKE_MASK (0x1 << PRCI_GEMGXLPLLCFG1_CKE_SHIFT) > + > +/* CORECLKSEL */ > +#define PRCI_CORECLKSEL_OFFSET 0x24 > +#define PRCI_CORECLKSEL_CORECLKSEL_SHIFT 0 > +#define PRCI_CORECLKSEL_CORECLKSEL_MASK \ > + (0x1 << PRCI_CORECLKSEL_CORECLKSEL_SHIFT) > + > +/* DEVICESRESETREG */ > +#define PRCI_DEVICESRESETREG_OFFSET 0x28 > +#define PRCI_DEVICERESETCNT 6 > + > +/* CLKMUXSTATUSREG */ > +#define PRCI_CLKMUXSTATUSREG_OFFSET 0x2c > +#define PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_SHIFT 1 > +#define PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_MASK \ > + (0x1 << PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_SHIFT) > + > +/* CLTXPLLCFG0 */ > +#define PRCI_CLTXPLLCFG0_OFFSET 0x30 > +#define PRCI_CLTXPLLCFG0_DIVR_SHIFT 0 > +#define PRCI_CLTXPLLCFG0_DIVR_MASK (0x3f << PRCI_CLTXPLLCFG0_DIVR_SHIFT) > +#define PRCI_CLTXPLLCFG0_DIVF_SHIFT 6 > +#define PRCI_CLTXPLLCFG0_DIVF_MASK (0x1ff << PRCI_CLTXPLLCFG0_DIVF_SHIFT) > +#define PRCI_CLTXPLLCFG0_DIVQ_SHIFT 15 > +#define PRCI_CLTXPLLCFG0_DIVQ_MASK (0x7 << PRCI_CLTXPLLCFG0_DIVQ_SHIFT) > +#define PRCI_CLTXPLLCFG0_RANGE_SHIFT 18 > +#define PRCI_CLTXPLLCFG0_RANGE_MASK (0x7 << PRCI_CLTXPLLCFG0_RANGE_SHIFT) > +#define PRCI_CLTXPLLCFG0_BYPASS_SHIFT 24 > +#define PRCI_CLTXPLLCFG0_BYPASS_MASK (0x1 << PRCI_CLTXPLLCFG0_BYPASS_SHIFT) > +#define PRCI_CLTXPLLCFG0_FSE_SHIFT 25 > +#define PRCI_CLTXPLLCFG0_FSE_MASK (0x1 << PRCI_CLTXPLLCFG0_FSE_SHIFT) > +#define PRCI_CLTXPLLCFG0_LOCK_SHIFT 31 > +#define PRCI_CLTXPLLCFG0_LOCK_MASK (0x1 << PRCI_CLTXPLLCFG0_LOCK_SHIFT) > + > +/* CLTXPLLCFG1 */ > +#define PRCI_CLTXPLLCFG1_OFFSET 0x34 > +#define PRCI_CLTXPLLCFG1_CKE_SHIFT 24 > +#define PRCI_CLTXPLLCFG1_CKE_MASK (0x1 << PRCI_CLTXPLLCFG1_CKE_SHIFT) > + > +/* DVFSCOREPLLCFG0 */ > +#define PRCI_DVFSCOREPLLCFG0_OFFSET 0x38 > + > +/* DVFSCOREPLLCFG1 */ > +#define PRCI_DVFSCOREPLLCFG1_OFFSET 0x3c > +#define PRCI_DVFSCOREPLLCFG1_CKE_SHIFT 24 > +#define PRCI_DVFSCOREPLLCFG1_CKE_MASK (0x1 << PRCI_DVFSCOREPLLCFG1_CKE_SHIFT) > + > +/* COREPLLSEL */ > +#define PRCI_COREPLLSEL_OFFSET 0x40 > +#define PRCI_COREPLLSEL_COREPLLSEL_SHIFT 0 > +#define PRCI_COREPLLSEL_COREPLLSEL_MASK \ > + (0x1 << PRCI_COREPLLSEL_COREPLLSEL_SHIFT) > + > +/* HFPCLKPLLCFG0 */ > +#define PRCI_HFPCLKPLLCFG0_OFFSET 0x50 > +#define PRCI_HFPCLKPLL_CFG0_DIVR_SHIFT 0 > +#define PRCI_HFPCLKPLL_CFG0_DIVR_MASK \ > + (0x3f << PRCI_HFPCLKPLLCFG0_DIVR_SHIFT) > +#define PRCI_HFPCLKPLL_CFG0_DIVF_SHIFT 6 > +#define PRCI_HFPCLKPLL_CFG0_DIVF_MASK \ > + (0x1ff << PRCI_HFPCLKPLLCFG0_DIVF_SHIFT) > +#define PRCI_HFPCLKPLL_CFG0_DIVQ_SHIFT 15 > +#define PRCI_HFPCLKPLL_CFG0_DIVQ_MASK \ > + (0x7 << PRCI_HFPCLKPLLCFG0_DIVQ_SHIFT) > +#define PRCI_HFPCLKPLL_CFG0_RANGE_SHIFT 18 > +#define PRCI_HFPCLKPLL_CFG0_RANGE_MASK \ > + (0x7 << PRCI_HFPCLKPLLCFG0_RANGE_SHIFT) > +#define PRCI_HFPCLKPLL_CFG0_BYPASS_SHIFT 24 > +#define PRCI_HFPCLKPLL_CFG0_BYPASS_MASK \ > + (0x1 << PRCI_HFPCLKPLLCFG0_BYPASS_SHIFT) > +#define PRCI_HFPCLKPLL_CFG0_FSE_SHIFT 25 > +#define PRCI_HFPCLKPLL_CFG0_FSE_MASK \ > + (0x1 << PRCI_HFPCLKPLLCFG0_FSE_SHIFT) > +#define PRCI_HFPCLKPLL_CFG0_LOCK_SHIFT 31 > +#define PRCI_HFPCLKPLL_CFG0_LOCK_MASK \ > + (0x1 << PRCI_HFPCLKPLLCFG0_LOCK_SHIFT) > + > +/* HFPCLKPLLCFG1 */ > +#define PRCI_HFPCLKPLLCFG1_OFFSET 0x54 > +#define PRCI_HFPCLKPLLCFG1_CKE_SHIFT 24 > +#define PRCI_HFPCLKPLLCFG1_CKE_MASK \ > + (0x1 << PRCI_HFPCLKPLLCFG1_CKE_SHIFT) > + > +/* HFPCLKPLLSEL */ > +#define PRCI_HFPCLKPLLSEL_OFFSET 0x58 > +#define PRCI_HFPCLKPLLSEL_HFPCLKPLLSEL_SHIFT 0 > +#define PRCI_HFPCLKPLLSEL_HFPCLKPLLSEL_MASK \ > + (0x1 << PRCI_HFPCLKPLLSEL_HFPCLKPLLSEL_SHIFT) > + > +/* HFPCLKPLLDIV */ > +#define PRCI_HFPCLKPLLDIV_OFFSET 0x5c > + > +/* PRCIPLL */ > +#define PRCI_PRCIPLL_OFFSET 0xe0 > + > +#define PRCI_PRCIPLL_CLTXPLL (0x1 << 0) > +#define PRCI_PRCIPLL_GEMGXLPLL (0x1 << 1) > +#define PRCI_PRCIPLL_DDRPLL (0x1 << 2) > +#define PRCI_PRCIPLL_HFPCLKPLL (0x1 << 3) > +#define PRCI_PRCIPLL_DVFSCOREPLL (0x1 << 4) > +#define PRCI_PRCIPLL_COREPLL (0x1 << 5) > + > +/* PROCMONCFG */ > +#define PRCI_PROCMONCFG_OFFSET 0xF0 > +#define PRCI_PROCMONCFG_CORE_CLOCK_SHIFT 24 > +#define PRCI_PROCMONCFG_CORE_CLOCK_MASK \ > + (0x1 << PRCI_PROCMONCFG_CORE_CLOCK_SHIFT) > + > +/* > + * Private structures > + */ > + > +/** > + * struct __prci_data - per-device-instance data > + * @va: base virtual address of the PRCI IP block > + * @parent: parent clk instance > + * > + * PRCI per-device instance data > + */ > +struct __prci_data { > + void *va; > + struct clk parent_hfclk; > + struct clk parent_rtcclk; > +}; > + > +/** > + * struct __prci_wrpll_data - WRPLL configuration and integration data > + * @c: WRPLL current configuration record > + * @enable_bypass: fn ptr to code to bypass the WRPLL (if applicable; else NULL) > + * @disable_bypass: fn ptr to code to not bypass the WRPLL (or NULL) > + * @cfg0_offs: WRPLL CFG0 register offset (in bytes) from the PRCI base address > + * @cfg1_offs: WRPLL CFG1 register offset (in bytes) from the PRCI base address > + * @release_reset: fn ptr to code to release clock reset > + * > + * @enable_bypass and @disable_bypass are used for WRPLL instances > + * that contain a separate external glitchless clock mux downstream > + * from the PLL. The WRPLL internal bypass mux is not glitchless. > + */ > +struct __prci_wrpll_data { > + struct wrpll_cfg c; > + void (*enable_bypass)(struct __prci_data *pd); > + void (*disable_bypass)(struct __prci_data *pd); > + u8 cfg0_offs; > + u8 cfg1_offs; > + void (*release_reset)(struct __prci_data *pd); > +}; > + > +/** > + * struct __prci_clock - describes a clock device managed by PRCI > + * @name: user-readable clock name string - should match the manual > + * @parent_name: parent name for this clock > + * @ops: struct __prci_clock_ops for control > + * @pwd: WRPLL-specific data, associated with this clock (if not NULL) > + * @pd: PRCI-specific data associated with this clock (if not NULL) > + * > + * PRCI clock data. Used by the PRCI driver to register PRCI-provided > + * clocks to the Linux clock infrastructure. > + */ > +struct __prci_clock { > + const char *name; > + const char *parent_name; > + const struct __prci_clock_ops *ops; > + struct __prci_wrpll_data *pwd; > + struct __prci_data *pd; > +}; > + > +/* struct __prci_clock_ops - clock operations */ > +struct __prci_clock_ops { > + int (*set_rate)(struct __prci_clock *pc, > + unsigned long rate, > + unsigned long parent_rate); > + unsigned long (*round_rate)(struct __prci_clock *pc, > + unsigned long rate, > + unsigned long *parent_rate); > + unsigned long (*recalc_rate)(struct __prci_clock *pc, > + unsigned long parent_rate); > + int (*enable_clk)(struct __prci_clock *pc, bool enable); > +}; > + > +/* > + * struct prci_clk_desc - describes the information of clocks of each SoCs > + * @clks: point to a array of __prci_clock > + * @num_clks: the number of element of clks > + */ > +struct prci_clk_desc { > + struct __prci_clock *clks; > + size_t num_clks; > +}; > + > +void sifive_prci_ethernet_release_reset(struct __prci_data *pd); > +void sifive_prci_ddr_release_reset(struct __prci_data *pd); > +void sifive_prci_cltx_release_reset(struct __prci_data *pd); > + > +/* Core clock mux control */ > +void sifive_prci_coreclksel_use_hfclk(struct __prci_data *pd); > +void sifive_prci_coreclksel_use_corepll(struct __prci_data *pd); > +void sifive_prci_coreclksel_use_final_corepll(struct __prci_data *pd); > +void sifive_prci_corepllsel_use_dvfscorepll(struct __prci_data *pd); > +void sifive_prci_corepllsel_use_corepll(struct __prci_data *pd); > +void sifive_prci_hfpclkpllsel_use_hfclk(struct __prci_data *pd); > +void sifive_prci_hfpclkpllsel_use_hfpclkpll(struct __prci_data *pd); > + > +unsigned long sifive_prci_wrpll_round_rate(struct __prci_clock *pc, > + unsigned long rate, > + unsigned long *parent_rate); > + > +/* Linux clock framework integration */ > +int sifive_prci_wrpll_set_rate(struct __prci_clock *pc, > + unsigned long rate, > + unsigned long parent_rate); > + > +unsigned long sifive_prci_wrpll_recalc_rate(struct __prci_clock *pc, > + unsigned long parent_rate); > + > +unsigned long sifive_prci_tlclksel_recalc_rate(struct __prci_clock *pc, > + unsigned long parent_rate); > + > +unsigned long sifive_prci_hfpclkplldiv_recalc_rate(struct __prci_clock *pc, > + unsigned long parent_rate); > + > +int sifive_prci_clock_enable(struct __prci_clock *pc, bool enable); > + > +#endif /* __SIFIVE_CLK_SIFIVE_PRCI_H */ > -- > 2.31.0 > -- Regards, Dimitri. -- Regards, Dimitri.

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Re: [PATCH v7 1/8] riscv: cpu: fu740: Add support for cpu fu740
by Dimitri John Ledkov 04 May '21

04 May '21

(resending to the list after subscribing) Hi, On Thu, Apr 22, 2021 at 10:14 AM Green Wan <green.wan(a)sifive.com> wrote: > > Add SiFive fu740 cpu to support RISC-V arch > > Signed-off-by: Green Wan <green.wan(a)sifive.com> > Reviewed-by: Bin Meng <bmeng.cn(a)gmail.com> > --- > arch/riscv/Kconfig | 1 + > arch/riscv/cpu/fu740/Kconfig | 37 +++++++++++++++ > arch/riscv/cpu/fu740/Makefile | 12 +++++ > arch/riscv/cpu/fu740/cache.c | 55 +++++++++++++++++++++++ > arch/riscv/cpu/fu740/cpu.c | 22 +++++++++ > arch/riscv/cpu/fu740/dram.c | 38 ++++++++++++++++ > arch/riscv/cpu/fu740/spl.c | 23 ++++++++++ > arch/riscv/include/asm/arch-fu740/cache.h | 14 ++++++ > arch/riscv/include/asm/arch-fu740/clk.h | 14 ++++++ > arch/riscv/include/asm/arch-fu740/gpio.h | 38 ++++++++++++++++ > arch/riscv/include/asm/arch-fu740/reset.h | 13 ++++++ > arch/riscv/include/asm/arch-fu740/spl.h | 14 ++++++ > arch/riscv/lib/sifive_clint.c | 1 - > 13 files changed, 281 insertions(+), 1 deletion(-) > create mode 100644 arch/riscv/cpu/fu740/Kconfig > create mode 100644 arch/riscv/cpu/fu740/Makefile > create mode 100644 arch/riscv/cpu/fu740/cache.c > create mode 100644 arch/riscv/cpu/fu740/cpu.c > create mode 100644 arch/riscv/cpu/fu740/dram.c > create mode 100644 arch/riscv/cpu/fu740/spl.c > create mode 100644 arch/riscv/include/asm/arch-fu740/cache.h > create mode 100644 arch/riscv/include/asm/arch-fu740/clk.h > create mode 100644 arch/riscv/include/asm/arch-fu740/gpio.h > create mode 100644 arch/riscv/include/asm/arch-fu740/reset.h > create mode 100644 arch/riscv/include/asm/arch-fu740/spl.h > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > index 3f221dccdb..4177253e44 100644 > --- a/arch/riscv/Kconfig > +++ b/arch/riscv/Kconfig > @@ -61,6 +61,7 @@ source "board/sipeed/maix/Kconfig" > # platform-specific options below > source "arch/riscv/cpu/ax25/Kconfig" > source "arch/riscv/cpu/fu540/Kconfig" > +source "arch/riscv/cpu/fu740/Kconfig" > source "arch/riscv/cpu/generic/Kconfig" > > # architecture-specific options below > diff --git a/arch/riscv/cpu/fu740/Kconfig b/arch/riscv/cpu/fu740/Kconfig > new file mode 100644 > index 0000000000..24788beab1 > --- /dev/null > +++ b/arch/riscv/cpu/fu740/Kconfig > @@ -0,0 +1,37 @@ > +# SPDX-License-Identifier: GPL-2.0+ > +# > +# Copyright (C) 2020-2021 SiFive, Inc > +# Pragnesh Patel <pragnesh.patel(a)sifive.com> > + > +config SIFIVE_FU740 > + bool > + select ARCH_EARLY_INIT_R > + select RAM > + select SPL_RAM if SPL > + imply CPU > + imply CPU_RISCV > + imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE) > + imply SIFIVE_CLINT if (RISCV_MMODE || SPL_RISCV_MMODE) > + imply CMD_CPU > + imply SPL_CPU > + imply SPL_OPENSBI > + imply SPL_LOAD_FIT > + imply SMP > + imply CLK_SIFIVE > + imply CLK_SIFIVE_PRCI > + imply SIFIVE_SERIAL > + imply MACB > + imply MII > + imply SPI > + imply SPI_SIFIVE > + imply MMC > + imply MMC_SPI > + imply MMC_BROKEN_CD > + imply CMD_MMC > + imply DM_GPIO > + imply SIFIVE_GPIO > + imply CMD_GPIO > + imply MISC > + imply SIFIVE_OTP > + imply DM_PWM > + imply PWM_SIFIVE > diff --git a/arch/riscv/cpu/fu740/Makefile b/arch/riscv/cpu/fu740/Makefile > new file mode 100644 > index 0000000000..5ef8ac18a7 > --- /dev/null > +++ b/arch/riscv/cpu/fu740/Makefile > @@ -0,0 +1,12 @@ > +# SPDX-License-Identifier: GPL-2.0+ > +# > +# Copyright (C) 2020-2021 SiFive, Inc > +# Pragnesh Patel <pragnesh.patel(a)sifive.com> > + > +ifeq ($(CONFIG_SPL_BUILD),y) > +obj-y += spl.o > +else > +obj-y += dram.o > +obj-y += cpu.o > +obj-y += cache.o > +endif > diff --git a/arch/riscv/cpu/fu740/cache.c b/arch/riscv/cpu/fu740/cache.c > new file mode 100644 > index 0000000000..680955c9e3 > --- /dev/null > +++ b/arch/riscv/cpu/fu740/cache.c > @@ -0,0 +1,55 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright (C) 2020-2021 SiFive, Inc > + * > + * Authors: > + * Pragnesh Patel <pragnesh.patel(a)sifive.com> > + */ > + > +#include <common.h> > +#include <asm/io.h> > +#include <linux/bitops.h> > +#include <asm/global_data.h> > + > +/* Register offsets */ > +#define L2_CACHE_CONFIG 0x000 > +#define L2_CACHE_ENABLE 0x008 > + > +#define MASK_NUM_WAYS GENMASK(15, 8) > +#define NUM_WAYS_SHIFT 8 > + > +DECLARE_GLOBAL_DATA_PTR; > + > +int cache_enable_ways(void) > +{ > + const void *blob = gd->fdt_blob; > + int node; > + fdt_addr_t base; > + u32 config; > + u32 ways; > + > + volatile u32 *enable; > + > + node = fdt_node_offset_by_compatible(blob, -1, > + "sifive,fu740-c000-ccache"); > + > + if (node < 0) > + return node; > + > + base = fdtdec_get_addr_size_auto_parent(blob, 0, node, "reg", 0, > + NULL, false); > + if (base == FDT_ADDR_T_NONE) > + return FDT_ADDR_T_NONE; > + > + config = readl((volatile u32 *)base + L2_CACHE_CONFIG); > + ways = (config & MASK_NUM_WAYS) >> NUM_WAYS_SHIFT; > + > + enable = (volatile u32 *)(base + L2_CACHE_ENABLE); > + > + /* memory barrier */ > + mb(); > + (*enable) = ways - 1; > + /* memory barrier */ > + mb(); > + return 0; > +} > diff --git a/arch/riscv/cpu/fu740/cpu.c b/arch/riscv/cpu/fu740/cpu.c > new file mode 100644 > index 0000000000..f13c18942f > --- /dev/null > +++ b/arch/riscv/cpu/fu740/cpu.c > @@ -0,0 +1,22 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright (C) 2018, Bin Meng <bmeng.cn(a)gmail.com> > + */ > + > +#include <irq_func.h> > +#include <asm/cache.h> > + > +/* > + * cleanup_before_linux() is called just before we call linux > + * it prepares the processor for linux > + * > + * we disable interrupt and caches. > + */ > +int cleanup_before_linux(void) > +{ > + disable_interrupts(); > + > + cache_flush(); > + > + return 0; > +} > diff --git a/arch/riscv/cpu/fu740/dram.c b/arch/riscv/cpu/fu740/dram.c > new file mode 100644 > index 0000000000..1dc77efeca > --- /dev/null > +++ b/arch/riscv/cpu/fu740/dram.c > @@ -0,0 +1,38 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright (C) 2018, Bin Meng <bmeng.cn(a)gmail.com> > + */ > + > +#include <common.h> > +#include <fdtdec.h> > +#include <init.h> > +#include <linux/sizes.h> > + > +DECLARE_GLOBAL_DATA_PTR; > + > +int dram_init(void) > +{ > + return fdtdec_setup_mem_size_base(); > +} > + > +int dram_init_banksize(void) > +{ > + return fdtdec_setup_memory_banksize(); > +} > + > +ulong board_get_usable_ram_top(ulong total_size) > +{ > +#ifdef CONFIG_64BIT > + /* > + * Ensure that we run from first 4GB so that all > + * addresses used by U-Boot are 32bit addresses. > + * > + * This in-turn ensures that 32bit DMA capable > + * devices work fine because DMA mapping APIs will > + * provide 32bit DMA addresses only. > + */ > + if (gd->ram_top > SZ_4G) > + return SZ_4G; > +#endif > + return gd->ram_top; > +} > diff --git a/arch/riscv/cpu/fu740/spl.c b/arch/riscv/cpu/fu740/spl.c > new file mode 100644 > index 0000000000..ea0b2283a2 > --- /dev/null > +++ b/arch/riscv/cpu/fu740/spl.c > @@ -0,0 +1,23 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright (C) 2020-201 SiFive, Inc > + * Pragnesh Patel <pragnesh.patel(a)sifive.com> > + */ > + > +#include <dm.h> > +#include <log.h> > + > +int spl_soc_init(void) > +{ > + int ret; > + struct udevice *dev; > + > + /* DDR init */ > + ret = uclass_get_device(UCLASS_RAM, 0, &dev); > + if (ret) { > + debug("DRAM init failed: %d\n", ret); > + return ret; > + } > + > + return 0; > +} > diff --git a/arch/riscv/include/asm/arch-fu740/cache.h b/arch/riscv/include/asm/arch-fu740/cache.h > new file mode 100644 > index 0000000000..7d4fe9942b > --- /dev/null > +++ b/arch/riscv/include/asm/arch-fu740/cache.h > @@ -0,0 +1,14 @@ > +/* SPDX-License-Identifier: GPL-2.0+ */ > +/* > + * Copyright (C) 2020-2021 SiFive, Inc. > + * > + * Authors: > + * Pragnesh Patel <pragnesh.patel(a)sifve.com> > + */ > + > +#ifndef _CACHE_SIFIVE_H > +#define _CACHE_SIFIVE_H > + > +int cache_enable_ways(void); > + > +#endif /* _CACHE_SIFIVE_H */ > diff --git a/arch/riscv/include/asm/arch-fu740/clk.h b/arch/riscv/include/asm/arch-fu740/clk.h > new file mode 100644 > index 0000000000..9f883616b2 > --- /dev/null > +++ b/arch/riscv/include/asm/arch-fu740/clk.h > @@ -0,0 +1,14 @@ > +/* SPDX-License-Identifier: GPL-2.0+ */ > +/* > + * Copyright (c) 2020-2021 SiFive Inc > + * > + * Authors: > + * Pragnesh Patel <pragnesh.patel(a)sifive.com> > + */ > + > +#ifndef __CLK_SIFIVE_H > +#define __CLK_SIFIVE_H > + > +/* Note: This is a placeholder header for driver compilation. */ > + > +#endif > diff --git a/arch/riscv/include/asm/arch-fu740/gpio.h b/arch/riscv/include/asm/arch-fu740/gpio.h > new file mode 100644 > index 0000000000..908e2e5563 > --- /dev/null > +++ b/arch/riscv/include/asm/arch-fu740/gpio.h > @@ -0,0 +1,38 @@ > +/* SPDX-License-Identifier: GPL-2.0+ */ > +/* > + * Copyright (C) 2020-2021 SiFive, Inc. > + */ > + > +#ifndef _GPIO_SIFIVE_H > +#define _GPIO_SIFIVE_H > + > +#define GPIO_INPUT_VAL 0x00 > +#define GPIO_INPUT_EN 0x04 > +#define GPIO_OUTPUT_EN 0x08 > +#define GPIO_OUTPUT_VAL 0x0C > +#define GPIO_RISE_IE 0x18 > +#define GPIO_RISE_IP 0x1C > +#define GPIO_FALL_IE 0x20 > +#define GPIO_FALL_IP 0x24 > +#define GPIO_HIGH_IE 0x28 > +#define GPIO_HIGH_IP 0x2C > +#define GPIO_LOW_IE 0x30 > +#define GPIO_LOW_IP 0x34 > +#define GPIO_OUTPUT_XOR 0x40 > + > +#define NR_GPIOS 16 > + > +enum gpio_state { > + LOW, > + HIGH > +}; > + > +/* Details about a GPIO bank */ > +struct sifive_gpio_plat { > + void *base; /* address of registers in physical memory */ > +}; > + > +#define SIFIVE_GENERIC_GPIO_NR(port, index) \ > + (((port) * NR_GPIOS) + ((index) & (NR_GPIOS - 1))) > + > +#endif /* _GPIO_SIFIVE_H */ > diff --git a/arch/riscv/include/asm/arch-fu740/reset.h b/arch/riscv/include/asm/arch-fu740/reset.h > new file mode 100644 > index 0000000000..538ef87410 > --- /dev/null > +++ b/arch/riscv/include/asm/arch-fu740/reset.h > @@ -0,0 +1,13 @@ > +/* SPDX-License-Identifier: GPL-2.0+ */ > +/* > + * Copyright (c) 2020-2021 SiFive, Inc. > + * > + * Author: Sagar Kadam <sagar.kadam(a)sifive.com> > + */ > + > +#ifndef __RESET_SIFIVE_H > +#define __RESET_SIFIVE_H > + > +int sifive_reset_bind(struct udevice *dev, ulong count); > + > +#endif > diff --git a/arch/riscv/include/asm/arch-fu740/spl.h b/arch/riscv/include/asm/arch-fu740/spl.h > new file mode 100644 > index 0000000000..15ad9e7c8b > --- /dev/null > +++ b/arch/riscv/include/asm/arch-fu740/spl.h > @@ -0,0 +1,14 @@ > +/* SPDX-License-Identifier: GPL-2.0+ */ > +/* > + * Copyright (C) 2020-2021 SiFive, Inc. > + * > + * Authors: > + * Pragnesh Patel <pragnesh.patel(a)sifve.com> > + */ > + > +#ifndef _SPL_SIFIVE_H > +#define _SPL_SIFIVE_H > + > +int spl_soc_init(void); > + > +#endif /* _SPL_SIFIVE_H */ > diff --git a/arch/riscv/lib/sifive_clint.c b/arch/riscv/lib/sifive_clint.c > index ab22395c55..cfa288a01a 100644 > --- a/arch/riscv/lib/sifive_clint.c > +++ b/arch/riscv/lib/sifive_clint.c > @@ -10,7 +10,6 @@ > > #include <common.h> > #include <dm.h> > -#include <asm/global_data.h> > #include <asm/io.h> > #include <asm/smp.h> > #include <linux/err.h> Why is this include being removed? As far as I can tell the file does use things from asm/global_data.h i.e. a little further down it does ... DECLARE_GLOBAL_DATA_PTR; ... gd->arch.clint Which come from asm/global_data.h header. Am I missing something? -- Regards, Dimitri. -- Regards, Dimitri.

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