May 2021 - U-Boot

[PATCH 0/8] sunxi: mmc: Fixes and speed increase
by Andre Przywara 04 Jul '21

04 Jul '21

While debugging some eMMC problem on the H616 SoC, I stumbled upon some weird code in the Allwinner MMC driver. Some closer inspection and some help from Ondrej later this series of fixes emerged: Some patches remove part of the #ifdef hell we needlessly had in the driver. A big chunk is around the "new timing mode", which all "newer" SoCs (since around 2015) have, and which requires some extra bit to be set. We didn't enable this mode for all SoCs, this is now fixed in patches 3-6. Patch 7 fixes a big performance problem we had due to using MMIO accesses for the actual data transfer, as opposed to DMA transfers used in Linux. Short from adding a lot of code to use DMA as well, we can actually halve the number of MMIO accesses on reads, effectively doubling the bus transfer performance. This helps the H6 a lot, but also improves the eMMC read performance. The final patch makes use of some generic MMC DT code, to parse generic DT properties. This allows us to remove sunxi specific code, but also adds support for "broken-cd" and more advanced MMC speed modes. Please have a look and test this code on as many boards as possible. While a performance increase is nice, we don't want to risk data integrity over this, so please try to verify that it still works for you. Cheers, Andre. P.S. Patches 5 and 6 use different approaches to differentiate between SoCs specific quirks: Patch 5/8 selects an explicit symbol from the SoC specific sections in our Kconfig file, while patch 6/8 compares the selected SoC type in the C code. Please let me know which approach is better, I can then use this for both patches (and in the future). Andre Przywara (8): mmc: sunxi: Avoid #ifdefs in delay and width setup mmc: sunxi: Fix warnings with CONFIG_PHYS_64BIT mmc: sunxi: Fix MMC clock parent selection mmc: sunxi: Cleanup "new timing mode" selection mmc: sunxi: Enable "new timing mode" on all new SoCs mmc: sunxi: Cleanup and fix self-calibration code mmc: sunxi: Increase MMIO FIFO read performance mmc: sunxi: Use mmc_of_parse() .../include/asm/arch-sunxi/clock_sun50i_h6.h | 2 +- arch/arm/include/asm/arch-sunxi/mmc.h | 1 + arch/arm/mach-sunxi/Kconfig | 3 + drivers/mmc/sunxi_mmc.c | 160 +++++++++++------- 4 files changed, 102 insertions(+), 64 deletions(-) -- 2.17.5

3 14

[PATCH] dm: core: fix no null pointer detection in ofnode_get_addr_size_index()
by chenguanqiao 04 Jul '21

04 Jul '21

From: Chen Guanqiao <chenguanqiao(a)kuaishou.com> Fixed a defect of a null pointer being discovered by Coverity Scan: CID 331544: Null pointer dereferences (REVERSE_INULL) Null-checking "size" suggests that it may be null, but it has already been dereferenced on all paths leading to the check. Signed-off-by: Chen Guanqiao <chenguanqiao(a)kuaishou.com> --- drivers/core/ofnode.c | 13 +++++++------ include/dm/ofnode.h | 2 +- 2 files changed, 8 insertions(+), 7 deletions(-) diff --git a/drivers/core/ofnode.c b/drivers/core/ofnode.c index 6c771e364f..554af95114 100644 --- a/drivers/core/ofnode.c +++ b/drivers/core/ofnode.c @@ -299,11 +299,10 @@ ofnode ofnode_get_by_phandle(uint phandle) return node; } -fdt_addr_t ofnode_get_addr_size_index(ofnode node, int index, fdt_size_t *size) +fdt_addr_t ofnode_get_addr_size_index(ofnode node, int index, fdt_size_t *psize) { int na, ns; - - *size = FDT_SIZE_T_NONE; + fdt_size_t size = FDT_SIZE_T_NONE; if (ofnode_is_np(node)) { const __be32 *prop_val; @@ -314,8 +313,7 @@ fdt_addr_t ofnode_get_addr_size_index(ofnode node, int index, fdt_size_t *size) &flags); if (!prop_val) return FDT_ADDR_T_NONE; - if (size) - *size = size64; + size = size64; ns = of_n_size_cells(ofnode_to_np(node)); @@ -330,9 +328,12 @@ fdt_addr_t ofnode_get_addr_size_index(ofnode node, int index, fdt_size_t *size) ns = ofnode_read_simple_size_cells(ofnode_get_parent(node)); return fdtdec_get_addr_size_fixed(gd->fdt_blob, ofnode_to_offset(node), "reg", - index, na, ns, size, true); + index, na, ns, psize, true); } + if (size) + *psize = size; + return FDT_ADDR_T_NONE; } diff --git a/include/dm/ofnode.h b/include/dm/ofnode.h index 8a69fd87da..e38d39dcf3 100644 --- a/include/dm/ofnode.h +++ b/include/dm/ofnode.h @@ -487,7 +487,7 @@ int ofnode_read_size(ofnode node, const char *propname); * @return address, or FDT_ADDR_T_NONE if not present or invalid */ phys_addr_t ofnode_get_addr_size_index(ofnode node, int index, - fdt_size_t *size); + fdt_size_t *psize); /** * ofnode_get_addr_index() - get an address from a node -- 2.27.0

2 2

[PATCH] fdtdec: fdtdec_get_aliases_highest_id: skip aliases to disabled nodes
by Tim Harvey 04 Jul '21

04 Jul '21

When looking for an alias with the highest id skip aliases for nodes that are disabled. Signed-off-by: Tim Harvey <tharvey(a)gateworks.com> --- lib/fdtdec.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 864589193b..d47195525a 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -546,6 +546,8 @@ int fdtdec_get_alias_highest_id(const void *blob, const char *base) if (*prop != '/' || prop[len - 1] || strncmp(name, base, base_len)) continue; + if (!fdtdec_get_is_enabled(blob, fdt_path_offset(blob, prop))) + continue; val = trailing_strtol(name); if (val > max) { -- 2.17.1

3 8

[PATCH v2 00/33] dm: Add dtoc implementation of device instantiation (part D)
by Simon Glass 04 Jul '21

04 Jul '21

By way of background, in May[1] and July[2] two 'tiny-dm' series were sent out, showing a possible way to reduce the overhead of driver model in SPL. The potential impact of that work was described in the cover letter[3]. While this was a successful demonstration, all but eliminating the overhead of driver model, it was not very practical, since it would have required substantial effort to adapt drivers used in SPL to what was effectively a parallel driver model. Instead, after much discussion [4], it was decided to try to use the tiny-dm methods to adapt the existing of-platdata infrastructure. This is considerably more work up front but should result in much less effort for maintainers, along with a single, more consistent driver model. Of the options mentioned in [3], the following are implemented (in dtoc only, not driver model) as part of this series (CS=reduces code size, DS=reduces data size): CS - drop driver_bind() and create devices (struct udevice) at build-time CS - allocate all device- and uclass-private data at build-time In addition the following was completed in an earlier series: CS / DS - Combine req_seq and seq and calculate the new value at build-time So this series updates dtoc to support generating devices and uclasses that are ready for use when SPL starts and don't need to be bound. This 'build-time' instantiation helps to reduce the code-size overhead of driver model in SPL. As part of this series, a new -i option is added to dtoc. This changes it to emit build-time-instantiated devices. Separate Kconfig options control instantiation and whether run-time binding is supported. Several corner cases have come up in making this work on sandbox_spl and chromebook_coral. It is possible that others will come up in the future, but it should be possible to adapt things to address these, based on the work here. This is part D of the overall effort. The final series includes the driver model implementation, as well as updating the documentation. To find out what the new generated files look like, see the last four patches of this series. It is available at u-boot-dm/prepd-working [1] http://patchwork.ozlabs.org/project/uboot/list/?series=179128&state=* [2] http://patchwork.ozlabs.org/project/uboot/list/?series=187295&state=* [3] https://lists.denx.de/pipermail/u-boot/2020-July/418433.html [4] http://patchwork.ozlabs.org/project/uboot/patch/20200525093539.1.Ibf2d19439… Changes in v2: - New patch - New patch - New patch - Drop patches previously applied - Update cover letter - Fix the naming for uclass_plat_name so it is different from uclass_priv - Tidy up tabbing to make the code output line up better - Add a summary to the top of the generated file Simon Glass (33): bootstage: Fix dependency for BOOTSTAGE_RECORD_COUNT dtoc: Scan drivers for available information dtoc: Save scan information across test runs dtoc: Ignore unwanted files when scanning for drivers dtoc: Collect priv/plat struct info from drivers dtoc: Support scanning of uclasses dtoc: Support scanning of structs in header files dtoc: Move test files into a test/ directory dtoc: Rename sandbox_i2c_test and sandbox_pmic_test dtoc: Add some extra properties to nodes dtoc: Make use of node properties dtoc: Process nodes to set up required properties dtoc: Track nodes which are actually used dtoc: Support tracking the phase of U-Boot Makefile: Pass the U-Boot phase to dtoc dtoc: Support headers needed for drivers dtoc: Process driver aliases along with drivers dtoc: Warn of duplicate drivers dtoc: Read aliases for uclasses dtoc: Detect drivers only at the start of start of line dtoc: Assign a sequence number to each node dtoc: Set up the uclasses that are used dtoc: Support processing the root node dtoc: Add an option for device instantiation dm: of-platadata: Add option for device instantiation dtoc: Add support for decl file dtoc: Don't generate platform data with instantiation sandbox: Make sandbox,emul more conventional sandbox: i2c: Rename driver names to work with of-platdata dtoc: Tidy up the list of supported phandle properties dtoc: Generate a summary in the dt-plat.c file dtoc: Generate uclass devices dtoc: Generate device instances arch/sandbox/dts/sandbox.dtsi | 6 +- arch/sandbox/dts/test.dts | 4 +- common/Kconfig.boot | 3 + common/bootstage.c | 2 +- doc/driver-model/of-plat.rst | 3 +- doc/driver-model/pci-info.rst | 1 + drivers/i2c/i2c-emul-uclass.c | 4 +- drivers/misc/test_drv.c | 11 +- drivers/rtc/i2c_rtc_emul.c | 2 +- dts/Kconfig | 23 +- include/dm/device.h | 34 + include/dm/test.h | 5 + scripts/Makefile.spl | 6 +- test/dm/test-fdt.c | 6 +- tools/dtoc/dtb_platdata.py | 620 +++++++++- tools/dtoc/dtoc_test_scan_drivers.cxx | 1 - tools/dtoc/main.py | 9 +- tools/dtoc/src_scan.py | 597 +++++++++- tools/dtoc/{ => test}/dtoc_test.dts | 0 tools/dtoc/{ => test}/dtoc_test_add_prop.dts | 0 tools/dtoc/{ => test}/dtoc_test_addr32.dts | 0 tools/dtoc/{ => test}/dtoc_test_addr32_64.dts | 0 tools/dtoc/{ => test}/dtoc_test_addr64.dts | 0 tools/dtoc/{ => test}/dtoc_test_addr64_32.dts | 0 tools/dtoc/test/dtoc_test_alias_bad.dts | 58 + tools/dtoc/test/dtoc_test_alias_bad_path.dts | 58 + tools/dtoc/test/dtoc_test_alias_bad_uc.dts | 58 + tools/dtoc/{ => test}/dtoc_test_aliases.dts | 0 tools/dtoc/{ => test}/dtoc_test_bad_reg.dts | 0 tools/dtoc/{ => test}/dtoc_test_bad_reg2.dts | 0 .../{ => test}/dtoc_test_driver_alias.dts | 0 tools/dtoc/{ => test}/dtoc_test_empty.dts | 0 tools/dtoc/test/dtoc_test_inst.dts | 58 + .../{ => test}/dtoc_test_invalid_driver.dts | 0 tools/dtoc/{ => test}/dtoc_test_phandle.dts | 0 .../dtoc/{ => test}/dtoc_test_phandle_bad.dts | 0 .../{ => test}/dtoc_test_phandle_bad2.dts | 0 .../{ => test}/dtoc_test_phandle_cd_gpios.dts | 0 .../{ => test}/dtoc_test_phandle_reorder.dts | 0 .../{ => test}/dtoc_test_phandle_single.dts | 0 tools/dtoc/test/dtoc_test_scan_drivers.cxx | 5 + tools/dtoc/{ => test}/dtoc_test_simple.dts | 4 +- tools/dtoc/test_dtoc.py | 1023 ++++++++++++++++- tools/dtoc/test_fdt.py | 31 +- tools/dtoc/test_src_scan.py | 397 ++++++- 45 files changed, 2847 insertions(+), 182 deletions(-) delete mode 100644 tools/dtoc/dtoc_test_scan_drivers.cxx rename tools/dtoc/{ => test}/dtoc_test.dts (100%) rename tools/dtoc/{ => test}/dtoc_test_add_prop.dts (100%) rename tools/dtoc/{ => test}/dtoc_test_addr32.dts (100%) rename tools/dtoc/{ => test}/dtoc_test_addr32_64.dts (100%) rename tools/dtoc/{ => test}/dtoc_test_addr64.dts (100%) rename tools/dtoc/{ => test}/dtoc_test_addr64_32.dts (100%) create mode 100644 tools/dtoc/test/dtoc_test_alias_bad.dts create mode 100644 tools/dtoc/test/dtoc_test_alias_bad_path.dts create mode 100644 tools/dtoc/test/dtoc_test_alias_bad_uc.dts rename tools/dtoc/{ => test}/dtoc_test_aliases.dts (100%) rename tools/dtoc/{ => test}/dtoc_test_bad_reg.dts (100%) rename tools/dtoc/{ => test}/dtoc_test_bad_reg2.dts (100%) rename tools/dtoc/{ => test}/dtoc_test_driver_alias.dts (100%) rename tools/dtoc/{ => test}/dtoc_test_empty.dts (100%) create mode 100644 tools/dtoc/test/dtoc_test_inst.dts rename tools/dtoc/{ => test}/dtoc_test_invalid_driver.dts (100%) rename tools/dtoc/{ => test}/dtoc_test_phandle.dts (100%) rename tools/dtoc/{ => test}/dtoc_test_phandle_bad.dts (100%) rename tools/dtoc/{ => test}/dtoc_test_phandle_bad2.dts (100%) rename tools/dtoc/{ => test}/dtoc_test_phandle_cd_gpios.dts (100%) rename tools/dtoc/{ => test}/dtoc_test_phandle_reorder.dts (100%) rename tools/dtoc/{ => test}/dtoc_test_phandle_single.dts (100%) create mode 100644 tools/dtoc/test/dtoc_test_scan_drivers.cxx rename tools/dtoc/{ => test}/dtoc_test_simple.dts (93%) -- 2.30.0.365.g02bc693789-goog

2 69

[PATCH 0/4] vpl: Introduce a verifying program loader
by Simon Glass 03 Jul '21

03 Jul '21

U-Boot provides a verified-boot feature based around FIT, but there is no standard way of implementing it for a board. At present the various required pieces must be built up separately, to produce a working implementation. In particular, there is no built-in support for selecting A/B boot or recovery mode. This series introduces VPL, a verified program loader. Its purpose is to run the verified-boot process and decide which SPL binary should be run. Adding VPL into the boot flow provides a standard way of implementing verified boot. So far, only the phase itself is added. More work is needed to add logic to the phase, based on continuing discussions about how best to standardise this feature. Simon Glass (4): doc: Convert SPL documentation to ReST doc: Expand SPL docs to explain the phase and config binman: Add VPL support Introduce Verifying Program Loader (VPL) common/Kconfig | 67 ++++++++ common/spl/Kconfig | 168 ++++++++++++++++++++- common/spl/spl.c | 25 ++- doc/develop/index.rst | 1 + doc/{README.SPL => develop/spl.rst} | 99 +++++++----- include/bootstage.h | 2 + include/linux/kconfig.h | 3 + include/spl.h | 20 ++- lib/Kconfig | 54 +++++++ scripts/Kbuild.include | 4 + scripts/Makefile.build | 4 + tools/binman/etype/u_boot_vpl.py | 42 ++++++ tools/binman/etype/u_boot_vpl_bss_pad.py | 44 ++++++ tools/binman/etype/u_boot_vpl_dtb.py | 28 ++++ tools/binman/etype/u_boot_vpl_expanded.py | 45 ++++++ tools/binman/etype/u_boot_vpl_nodtb.py | 42 ++++++ tools/binman/ftest.py | 110 +++++++++++--- tools/binman/state.py | 3 +- tools/binman/test/082_fdt_update_all.dts | 2 + tools/binman/test/201_u_boot_vpl.dts | 11 ++ tools/binman/test/202_u_boot_vpl_nodtb.dts | 13 ++ tools/binman/test/203_fdt_incl_vpl.dts | 13 ++ tools/binman/test/204_vpl_bss_pad.dts | 17 +++ 23 files changed, 748 insertions(+), 69 deletions(-) rename doc/{README.SPL => develop/spl.rst} (61%) create mode 100644 tools/binman/etype/u_boot_vpl.py create mode 100644 tools/binman/etype/u_boot_vpl_bss_pad.py create mode 100644 tools/binman/etype/u_boot_vpl_dtb.py create mode 100644 tools/binman/etype/u_boot_vpl_expanded.py create mode 100644 tools/binman/etype/u_boot_vpl_nodtb.py create mode 100644 tools/binman/test/201_u_boot_vpl.dts create mode 100644 tools/binman/test/202_u_boot_vpl_nodtb.dts create mode 100644 tools/binman/test/203_fdt_incl_vpl.dts create mode 100644 tools/binman/test/204_vpl_bss_pad.dts -- 2.31.1.607.g51e8a6a459-goog

2 8

[PATCH 1/3] usb: ehci-mx6: move mode set/detect to probe
by Tim Harvey 02 Jul '21

02 Jul '21

There is no need to set and/or detect mode in of_to_plat and accessing phy registers at that point before device power domain and clock are enabled will cause hangs on platforms such as IMX8M Mini. Move the mode set/detect from of_to_plat into the probe and remove the unnecessary of_to_plat. Signed-off-by: Tim Harvey <tharvey(a)gateworks.com> --- drivers/usb/host/ehci-mx6.c | 42 ++++++++++++++----------------------- 1 file changed, 16 insertions(+), 26 deletions(-) diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c index 06be9deaaa..c2dfe49012 100644 --- a/drivers/usb/host/ehci-mx6.c +++ b/drivers/usb/host/ehci-mx6.c @@ -539,28 +539,6 @@ static int ehci_usb_phy_mode(struct udevice *dev) return 0; } -static int ehci_usb_of_to_plat(struct udevice *dev) -{ - struct usb_plat *plat = dev_get_plat(dev); - enum usb_dr_mode dr_mode; - - dr_mode = usb_get_dr_mode(dev_ofnode(dev)); - - switch (dr_mode) { - case USB_DR_MODE_HOST: - plat->init_type = USB_INIT_HOST; - break; - case USB_DR_MODE_PERIPHERAL: - plat->init_type = USB_INIT_DEVICE; - break; - case USB_DR_MODE_OTG: - case USB_DR_MODE_UNKNOWN: - return ehci_usb_phy_mode(dev); - }; - - return 0; -} - static int mx6_parse_dt_addrs(struct udevice *dev) { #if !defined(CONFIG_PHY) @@ -623,7 +601,6 @@ static int ehci_usb_probe(struct udevice *dev) struct usb_plat *plat = dev_get_plat(dev); struct usb_ehci *ehci = dev_read_addr_ptr(dev); struct ehci_mx6_priv_data *priv = dev_get_priv(dev); - enum usb_init_type type = plat->init_type; struct ehci_hccr *hccr; struct ehci_hcor *hcor; int ret; @@ -641,7 +618,6 @@ static int ehci_usb_probe(struct udevice *dev) return ret; priv->ehci = ehci; - priv->init_type = type; #if CONFIG_IS_ENABLED(CLK) ret = clk_get_by_index(dev, 0, &priv->clk); @@ -657,6 +633,21 @@ static int ehci_usb_probe(struct udevice *dev) mdelay(1); #endif + switch (usb_get_dr_mode(dev_ofnode(dev))) { + case USB_DR_MODE_HOST: + plat->init_type = USB_INIT_HOST; + break; + case USB_DR_MODE_PERIPHERAL: + plat->init_type = USB_INIT_DEVICE; + break; + case USB_DR_MODE_OTG: + case USB_DR_MODE_UNKNOWN: + ret = ehci_usb_phy_mode(dev); + if (ret) + return ret; + }; + priv->init_type = plat->init_type; + #if CONFIG_IS_ENABLED(DM_REGULATOR) ret = device_get_supply_regulator(dev, "vbus-supply", &priv->vbus_supply); @@ -680,7 +671,7 @@ static int ehci_usb_probe(struct udevice *dev) #if CONFIG_IS_ENABLED(DM_REGULATOR) if (priv->vbus_supply) { ret = regulator_set_enable(priv->vbus_supply, - (type == USB_INIT_DEVICE) ? + (priv->init_type == USB_INIT_DEVICE) ? false : true); if (ret && ret != -ENOSYS) { printf("Error enabling VBUS supply (ret=%i)\n", ret); @@ -764,7 +755,6 @@ U_BOOT_DRIVER(usb_mx6) = { .name = "ehci_mx6", .id = UCLASS_USB, .of_match = mx6_usb_ids, - .of_to_plat = ehci_usb_of_to_plat, .probe = ehci_usb_probe, .remove = ehci_usb_remove, .ops = &ehci_usb_ops, -- 2.17.1

4 15

[PATCH] powerpc: fix regression in arch_initr_trap()
by Matt Merhar 01 Jul '21

01 Jul '21

The assembly output of the arch_initr_trap() function differed by a single byte after common.h was removed from traps.c: fff49a18 <arch_initr_trap>: fff49a18: 94 21 ff f0 stwu r1,-16(r1) fff49a1c: 7c 08 02 a6 mflr r0 fff49a20: 90 01 00 14 stw r0,20(r1) -fff49a24: 80 62 00 44 lwz r3,68(r2) +fff49a24: 80 62 00 38 lwz r3,56(r2) fff49a28: 4b ff 76 19 bl fff41040 <trap_init> fff49a2c: 80 01 00 14 lwz r0,20(r1) fff49a30: 38 60 00 00 li r3,0 fff49a34: 38 21 00 10 addi r1,r1,16 fff49a38: 7c 08 03 a6 mtlr r0 This was causing a consistent hard lockup during the MMC read / loading of the QoriQ FMan firmware on a P2041RDB board. Re-adding the header causes identical assembly to be emitted and allows the firmware loading and subsequent boot to succeed. Fixes: 401d1c4f5d ("common: Drop asm/global_data.h from common header") Signed-off-by: Matt Merhar <mattmerhar(a)protonmail.com> --- arch/powerpc/lib/traps.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/powerpc/lib/traps.c b/arch/powerpc/lib/traps.c index c7bce82a44..ab8ca269a5 100644 --- a/arch/powerpc/lib/traps.c +++ b/arch/powerpc/lib/traps.c @@ -4,6 +4,7 @@ * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. */ +#include <common.h> #include <init.h> #include <asm/global_data.h> -- 2.25.1

5 21

[PATCH v12 0/8] Add FU740 chip and HiFive Unmatched board support
by Green Wan 28 Jun '21

28 Jun '21

This patch set is to add SiFive fu740 chip and HiFive Unmatched board support. Patches are split into several parts: - [PATCH v12 1/8] support for fu740 cpu - [PATCH v12 2/8] support for fu740 clk driver - [PATCH v12 3/8] rename and support for fu740 ram driver - [PATCH v12 4/8] add pcie driver - [PATCH v12 5/8] dts for SiFive fu740 - [PATCH v12 6/8] dts for SiFive Unmatched board - [PATCH v12 7/8] add Unmatched board support - [PATCH v12 8/8] clear feature disable CSR Description - For fu740 cpu support, reuse most of fu540 cpu. - For prci driver, add one abstract layer to separate fu540 and fu740. Move orignal fu540 code to separate files. - For pcie driver, it depends on gpio, prci, clk and reset drivers to do init&reset works. Also based on pcie_dw_common.c - Align with Linux DT file. Tests and patch checks - Able to boot both unmatched and unleashed boards. - PCIe tests . M.2 NVMe SSD . e1000 compatibale ethernet adapter (ping&tftpboot) . pci-to-usb adapter(usb mass storage) - checkpatch is performed. To keep code derived from other boards the same. Changlogs - v12 . Remove fdt_high and initrd_high environment in [PATCH v11 7/8] to avoid fdt and initrd relocation are disabled. - v11 . squash 'binman change' patch into [PATH v11 6/8] and [PATCH v11 7/8] - v10 . on top of 2 patchset below, http://patchwork.ozlabs.org/project/uboot/patch/20210511120412.25065-1-bmen… http://patchwork.ozlabs.org/project/uboot/list/?series=242992 . appends patch 'clear feature disable CSRs' and 'binman change for unmatched' - v9 . applied http://patchwork.ozlabs.org/project/uboot/patch/20210511120412.25065-1-bmen… . append clear feature disable CSR patch to the last - v8 . Add #include <asm/global_data.h> back to sifive_clint.c in [PATCH v8 1/7] . Remove unused CLK_SIFIVE_FU540_PRCI from Kconfig [PATCH v8 2/8] and remove CONFIG_CLK_SIFIVE_PRCI=y from unleashed config in [PATCH v8 7/7] . Remove ECAM compatible string to align with Linux pcie driver and add Reviewed-by to [PATCH v8 4/7] . Drop last patch [PATCH v7 8/8] for drivers/net/macb.c and use the same compatible string, 'sifive,fu540-c000-gem', to align with Linux driver. - v7 . Rebase to latest master branch . Moved dts for fu740 patch [v6 1/7] to [v7 5/8] and seperate dts of Unmatched board from [v6 6/7] into [v7 6/8] . Applied PCIe refactoring patch to base on the common code in pcie_dw_common.c - v6 . Remove redundant DT string for 1.2GHz CPU clock and squash to [1/7] - v5 . Fix unleashed build error in patch [6/8] . Append one more set for 1.2GHz CPU speed . Add "#include <asm/global_data.h>" back to sifive_ddr.c . Add Reviewed-by to [4/8] and [7/8] - v4 . fixed incorrect file name in ./board/sifive/unmatched/Makefile . fixed link in doc/board/sifive/index.rst, passed 'make htmldocs' - v3 . Rebase to unleashed rename v2 patch . Rename doc/board/sifive/unmatched.rst board/sifive/unmatched/unmatched.c . Fix tail whitespace . Add 'git mv' info to ram driver and merge patch back to one . Add comment to macb driver for PLL hardware quirk . Add reviewed-by to patch [6/7] . Add 'gpio-poweroff' node for upcoming opensbi integration - v2 . Rebase to unleashed rename patch . remove unnessaary fu540 changes . split ram driver patch into 2 to keep 'git mv' info . use a shorter name for unmatched support . Remove redundant&incorrect temperature-sensor in DT . Remove unnecessary USB EHCI & OHCI from defconfig . Revised fu740 doc . Fixed year of copyright . Add reviewed-by received in v1 patch Green Wan (8): riscv: cpu: fu740: Add support for cpu fu740 drivers: clk: add fu740 support drivers: ram: sifive: rename fu540_ddr and add fu740 support drivers: pci: add pcie support for fu740 riscv: dts: add fu740 support riscv: dts: add SiFive Unmatched board support board: sifive: add HiFive Unmatched board support riscv: cpu: fu740: clear feature disable CSR arch/riscv/Kconfig | 5 + arch/riscv/cpu/fu540/Kconfig | 2 +- arch/riscv/cpu/fu740/Kconfig | 37 + arch/riscv/cpu/fu740/Makefile | 12 + arch/riscv/cpu/fu740/cache.c | 55 + arch/riscv/cpu/fu740/cpu.c | 22 + arch/riscv/cpu/fu740/dram.c | 38 + arch/riscv/cpu/fu740/spl.c | 38 + arch/riscv/dts/Makefile | 1 + arch/riscv/dts/fu740-c000-u-boot.dtsi | 105 ++ arch/riscv/dts/fu740-c000.dtsi | 329 ++++ .../dts/fu740-hifive-unmatched-a00-ddr.dtsi | 1489 +++++++++++++++++ .../dts/hifive-unmatched-a00-u-boot.dtsi | 41 + arch/riscv/dts/hifive-unmatched-a00.dts | 259 +++ arch/riscv/include/asm/arch-fu740/cache.h | 14 + arch/riscv/include/asm/arch-fu740/clk.h | 14 + arch/riscv/include/asm/arch-fu740/gpio.h | 38 + arch/riscv/include/asm/arch-fu740/reset.h | 13 + arch/riscv/include/asm/arch-fu740/spl.h | 14 + board/sifive/unleashed/Kconfig | 1 + board/sifive/unmatched/Kconfig | 51 + board/sifive/unmatched/MAINTAINERS | 9 + board/sifive/unmatched/Makefile | 9 + board/sifive/unmatched/spl.c | 85 + board/sifive/unmatched/unmatched.c | 24 + common/spl/Kconfig | 4 +- configs/sifive_unmatched_defconfig | 54 + doc/board/sifive/index.rst | 1 + doc/board/sifive/unmatched.rst | 536 ++++++ drivers/clk/sifive/Kconfig | 8 +- drivers/clk/sifive/Makefile | 4 +- drivers/clk/sifive/fu540-prci.c | 769 +-------- drivers/clk/sifive/fu540-prci.h | 22 + drivers/clk/sifive/fu740-prci.c | 158 ++ drivers/clk/sifive/fu740-prci.h | 22 + drivers/clk/sifive/sifive-prci.c | 733 ++++++++ drivers/clk/sifive/sifive-prci.h | 323 ++++ drivers/pci/Kconfig | 10 + drivers/pci/Makefile | 1 + drivers/pci/pcie_dw_sifive.c | 507 ++++++ drivers/ram/sifive/Kconfig | 8 +- drivers/ram/sifive/Makefile | 2 +- .../ram/sifive/{fu540_ddr.c => sifive_ddr.c} | 89 +- drivers/reset/Kconfig | 2 +- include/configs/sifive-unmatched.h | 83 + include/dt-bindings/clock/sifive-fu740-prci.h | 25 + include/dt-bindings/reset/sifive-fu740-prci.h | 19 + 47 files changed, 5279 insertions(+), 806 deletions(-) create mode 100644 arch/riscv/cpu/fu740/Kconfig create mode 100644 arch/riscv/cpu/fu740/Makefile create mode 100644 arch/riscv/cpu/fu740/cache.c create mode 100644 arch/riscv/cpu/fu740/cpu.c create mode 100644 arch/riscv/cpu/fu740/dram.c create mode 100644 arch/riscv/cpu/fu740/spl.c create mode 100644 arch/riscv/dts/fu740-c000-u-boot.dtsi create mode 100644 arch/riscv/dts/fu740-c000.dtsi create mode 100644 arch/riscv/dts/fu740-hifive-unmatched-a00-ddr.dtsi create mode 100644 arch/riscv/dts/hifive-unmatched-a00-u-boot.dtsi create mode 100644 arch/riscv/dts/hifive-unmatched-a00.dts create mode 100644 arch/riscv/include/asm/arch-fu740/cache.h create mode 100644 arch/riscv/include/asm/arch-fu740/clk.h create mode 100644 arch/riscv/include/asm/arch-fu740/gpio.h create mode 100644 arch/riscv/include/asm/arch-fu740/reset.h create mode 100644 arch/riscv/include/asm/arch-fu740/spl.h create mode 100644 board/sifive/unmatched/Kconfig create mode 100644 board/sifive/unmatched/MAINTAINERS create mode 100644 board/sifive/unmatched/Makefile create mode 100644 board/sifive/unmatched/spl.c create mode 100644 board/sifive/unmatched/unmatched.c create mode 100644 configs/sifive_unmatched_defconfig create mode 100644 doc/board/sifive/unmatched.rst create mode 100644 drivers/clk/sifive/fu540-prci.h create mode 100644 drivers/clk/sifive/fu740-prci.c create mode 100644 drivers/clk/sifive/fu740-prci.h create mode 100644 drivers/clk/sifive/sifive-prci.c create mode 100644 drivers/clk/sifive/sifive-prci.h create mode 100644 drivers/pci/pcie_dw_sifive.c rename drivers/ram/sifive/{fu540_ddr.c => sifive_ddr.c} (81%) create mode 100644 include/configs/sifive-unmatched.h create mode 100644 include/dt-bindings/clock/sifive-fu740-prci.h create mode 100644 include/dt-bindings/reset/sifive-fu740-prci.h -- 2.31.0

2 10

[PATCH u-boot-marvell] PLEASE TEST ddr: marvell: a38x: fix SPLIT_OUT_MIX state decision
by Marek Behún 28 Jun '21

28 Jun '21

From: motib <motib(a)marvell.com> In each pattern cycle the bus state can be changed. In order to avoid it, we need to switch back to the same bus state on each pattern cycle. Signed-off-by: motib <motib(a)marvell.com> Fixed code style, removed commented code, switched to use DEBUG macros instead of printf. Signed-off-by: Marek Behún <marek.behun(a)nic.cz> --- .../a38x/ddr3_training_centralization.c | 25 +++++++++++++++++++ .../marvell/a38x/ddr3_training_ip_engine.c | 8 ++++-- 2 files changed, 31 insertions(+), 2 deletions(-) diff --git a/drivers/ddr/marvell/a38x/ddr3_training_centralization.c b/drivers/ddr/marvell/a38x/ddr3_training_centralization.c index 648b37ef6f..a92760681e 100644 --- a/drivers/ddr/marvell/a38x/ddr3_training_centralization.c +++ b/drivers/ddr/marvell/a38x/ddr3_training_centralization.c @@ -24,6 +24,8 @@ u8 bus_start_window[NUM_OF_CENTRAL_TYPES][MAX_INTERFACE_NUM][MAX_BUS_NUM]; u8 centralization_state[MAX_INTERFACE_NUM][MAX_BUS_NUM]; static u8 ddr3_tip_special_rx_run_once_flag; +extern u8 byte_status[MAX_INTERFACE_NUM][MAX_BUS_NUM]; + static int ddr3_tip_centralization(u32 dev_num, u32 mode); /* @@ -110,6 +112,7 @@ static int ddr3_tip_centralization(u32 dev_num, u32 mode) (max_win_size - 1) + cons_tap; bus_start_window[mode][if_id][bus_id] = 0; centralization_result[if_id][bus_id] = 0; + byte_status[if_id][bus_id] = BYTE_NOT_DEFINED; } } @@ -166,6 +169,12 @@ static int ddr3_tip_centralization(u32 dev_num, u32 mode) result[search_dir_id][7])); } + DEBUG_CENTRALIZATION_ENGINE + (DEBUG_LEVEL_TRACE, + ("byte_status[%d][%d] = 0x%x\n", + if_id, + bus_id, + byte_status[if_id][bus_id])); for (bit_id = 0; bit_id < BUS_WIDTH_IN_BITS; bit_id++) { /* check if this code is valid for 2 edge, probably not :( */ @@ -174,11 +183,27 @@ static int ddr3_tip_centralization(u32 dev_num, u32 mode) [HWS_LOW2HIGH] [bit_id], EDGE_1); + if ((byte_status[if_id][bus_id] & BYTE_SPLIT_OUT_MIX) || + (byte_status[if_id][bus_id] & BYTE_HOMOGENEOUS_SPLIT_OUT)) { + if (cur_start_win[bit_id] >= 64) + cur_start_win[bit_id] -= 64; + else + cur_start_win[bit_id] = 0; + DEBUG_CENTRALIZATION_ENGINE + (DEBUG_LEVEL_TRACE, + ("--------------------------\n")); + } cur_end_win[bit_id] = GET_TAP_RESULT(result [HWS_HIGH2LOW] [bit_id], EDGE_1); + if (cur_end_win[bit_id] >= 64 && (byte_status[if_id][bus_id] & BYTE_SPLIT_OUT_MIX)) { + cur_end_win[bit_id] -= 64; + DEBUG_CENTRALIZATION_ENGINE + (DEBUG_LEVEL_TRACE, + ("++++++++++++++++++++++++++\n")); + } /* window length */ current_window[bit_id] = cur_end_win[bit_id] - diff --git a/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c b/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c index 5fd9a052fa..3d1fa1e74e 100644 --- a/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c +++ b/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c @@ -1174,7 +1174,6 @@ int ddr3_tip_ip_training_wrapper(u32 dev_num, enum hws_access_type access_type, /* zero the data base */ bit_bit_mask[sybphy_id] = 0; - byte_status[if_id][sybphy_id] = BYTE_NOT_DEFINED; for (bit_id = 0; bit_id < bit_end; bit_id++) { h2l_adll_value[sybphy_id][bit_id] = 64; l2h_adll_value[sybphy_id][bit_id] = 0; @@ -1276,6 +1275,7 @@ int ddr3_tip_ip_training_wrapper(u32 dev_num, enum hws_access_type access_type, l2h_if_train_res = ddr3_tip_get_buf_ptr(dev_num, HWS_LOW2HIGH, result_type, if_id); h2l_if_train_res = ddr3_tip_get_buf_ptr(dev_num, HWS_HIGH2LOW, result_type, if_id); /* search from middle to end */ + ddr3_tip_ip_training (dev_num, ACCESS_TYPE_UNICAST, if_id, ACCESS_TYPE_MULTICAST, @@ -1423,7 +1423,7 @@ int ddr3_tip_ip_training_wrapper(u32 dev_num, enum hws_access_type access_type, * the byte can be aligned. in this case add 64 to the the low ui bits aligning it * to the other ui bits */ - if (center_subphy_adll_window[sybphy_id] >= 32) { + if (center_subphy_adll_window[sybphy_id] >= 32 || bit_bit_mask[sybphy_id] != 0x0) { byte_status[if_id][sybphy_id] = BYTE_SPLIT_OUT_MIX; DEBUG_TRAINING_IP_ENGINE @@ -1432,8 +1432,12 @@ int ddr3_tip_ip_training_wrapper(u32 dev_num, enum hws_access_type access_type, if_id, sybphy_id, byte_status[if_id][sybphy_id])); for (bit_id = 0; bit_id < bit_end; bit_id++) { if (bit_state[sybphy_id * BUS_WIDTH_IN_BITS + bit_id] == BIT_LOW_UI) { + if (bit_bit_mask[sybphy_id] & (1 << bit_id)) + continue; l2h_if_train_res[sybphy_id * BUS_WIDTH_IN_BITS + bit_id] += 64; + l2h_adll_value[sybphy_id][bit_id] = l2h_if_train_res[sybphy_id * BUS_WIDTH_IN_BITS + bit_id]; h2l_if_train_res[sybphy_id * BUS_WIDTH_IN_BITS + bit_id] += 64; + h2l_adll_value[sybphy_id][bit_id] = h2l_if_train_res[sybphy_id * BUS_WIDTH_IN_BITS + bit_id]; } DEBUG_TRAINING_IP_ENGINE (DEBUG_LEVEL_TRACE, -- 2.26.2

5 6

[PATCH v9 00/28] mtd: spi-nor-core: add xSPI Octal DTR support
by Pratyush Yadav 25 Jun '21

25 Jun '21

Hi, This series adds support for octal DTR flashes in the SPI NOR framework, and then adds hooks for the Cypress S28HS512T and Micron MT35XU512ABA flashes. The Cadence QSPI controller driver is also updated to run in Octal DTR mode. Tested on TI J721E for MT35XU512ABA and J7200 for S28HS512T. Also tested on MT25QU512A for regressions. Changes in v9: - Fix a typo in patch 26 commit message. - Add Sean's Reviewed-by in patch 3. - Drop the 2-byte check from spi_mem_dtr_supports_op(). Instead, perform a even-byte length check on all 4 phases. Only do this when the buswidth of the phase is 8. - Make template ops in spi_nor_check_readop() and spi_nor_check_pp() have 2-byte data phase so they don't get rejected when 8D-8D-8D protocol is being used. Changes in v8: - Rebase on latest master, fixing merge conflicts. - Fix a regression related to address width that was discovered on Linux. - Port spi_mem_dtr_supports_op() from Linux and use it in Cadence qspi driver. - Do not set non-volatile Uniform Sector mode bit on S28HS512T. Instead use Takahiro's non-uniform erase patch to enable non-uniform erases. - Make sure spi_nor_write_reg() does not set data direction to out when there is no data to write, like in write enable. - Set buswidths to 0 before calling spi_nor_setup_op(), like how it is done in Linux. Changes in v7: - Port back changes requested on the Linux series. - Introduce the flag SPI_NOR_OCTAL_DTR_PP to indicate 8D page program support since it can't be detected from SFDP. - Re-order Profile 1.0 related defines by DWORD order. - Drop local variables addr_width and dummy in spi_nor_read_sr() spi_nor_read_fsr(). - Do not make having command opcode extension as a reserved field fatal. - Update doc comment for spi_nor_parse_profile1() and spi_nor_cypress_octal_dtr_enable() to add missing fields. - Move rdsr parameter parsing to where opcode is parsed because it is from the same DWORD. - Convert a comment in Profile 1.0 parsing from multi-line to one line. - Rename 'table' to 'dwords' in xSPI Profile 1.0 parsing. - Update spi_nor_check_readop() and spi_nor_check_pp() to use spi_nor_setup_op() so the buswidths are properly set up for DTR ops. - Do not set Uniform Sector bit on the Cypress S28HS512T flash if it is already set. It will avoid wearing out the non-volatile bit. - Enable DQS for Micron MT35XU512ABA. No reason not to. - Avoid enabling 4-byte addressing mode for all DTR ops instead of just Octal DTR ops. This is based on the assumption that DTR ops can only use 4-byte addressing. - Make spi_nor_set_fixups() static. - Add flag SPI_NOR_OCTAL_DTR_PP to both Cypress S28HS512T and Micron MT35XU512ABA. - Use values set up by spi-{rx,tx}-bus-width via device tree to determine if the controller supports the op or not. Gives more flexibility to choose protocol per-board. - Use tiny SPI NOR on x530 because of size constraints. Changes in v6: - Use "# CONFIG_SPI_FLASH_SMART_HWCAPS is not set" instead of "CONFIG_SPI_FLASH_SMART_HWCAPS=n" in x530_defconfig. Changes in v5: - Fix build breaking when CONFIG_SPL_SPI_FLASH_TINY is enabled because spi-nor-tiny did not have spi_nor_remove(). - The build was breaking in x530 because of SPL size too big. Fix it by the below changes. - Re-introduce old hwcaps selection logic and put the new one behind a config. This lets boards with size restrictions use the old logic which takes up less space. The code was getting hard to manage with the old code behind ifdefs. So, re-structure the old hwcaps selection logic and move it into one function: spi_nor_adjust_hwcaps(). This way, the common code just calls spi_nor_adjust_hwcaps(), but the old or new hwcaps selection is used based on the config option selected. - Put spi_nor_soft_reset() behind the config option SPI_NOR_SOFT_RESET. - Rename the config option used for soft resetting on boot to SPI_NOR_SOFT_RESET_ON_BOOT to make its intention clearer. - Put the fixup hooks of MT35XU512ABA and S28HS512T flashes behind config options to reduce code size on platforms that don't need them. - Introduce spi_nor_set_fixups(). Earlier, the fixup members of each flash was specified in spi-nor-ids.c. This meant they had to be declared as extern in sf_internal.h. But since spi-nor-tiny.c also uses it, and it doesn't have those fixups, they had to be put behind in an ifdef. The ".fixups = " assignment in spi-nor-ids.c also had to be put in an ifdef to account for spi-nor-tiny.c not having the fixup hooks. On top of this, the fixup of each flash is behind the flash's config. All this lead to a soup of ifdefs that wasn't easy to digest. So don't set the fixups in the common code. Instead, add a function in spi-nor-core.c that sets the fixups of each flash. This isn't ideal, but its the best compromise I could figure out. - Build were breaking with boards that use spi-mem-nodm.c because it doesn't have spi_mem_supports_op() which is needed for smart hwcaps selection. Add an equivalent to spi_mem_default_supports_op() there. - Replace uses of sizeof(op->cmd.opcode) with op->cmd.nbytes. - Do not set quad_enable to NULL if the value is set to reserved. Instead just print a warning and go on. quad_enable should be set to NULL in fixup hooks instead. Suggested on the Linux list. - Set dummy cycles for DTR mode in spi_nor_micron_octal_dtr_enable() instead of in the post sfdp hook. This keeps the flash functional in case Octal DTR mode is not selected. - Only use nor->rdsr_addr_nbytes and nor->rdsr_dummy when in Octal DTR mode. This makes sure the flash is functional in case Octal DTR is not selected. - Rebase on latest master and fix a small merge conflict. Changes in v4: - Fix BFPT parsing stopping too early for JESD216 rev B flashes. - Instead of just checking for spi_nor_get_protocol_width() in spi_nor_octal_dtr_enable(), make sure the protocol is SNOR_PROTO_8_8_8_DTR since get_protocol_width() only cares about data width. - Do not enable stateful X-X-X modes if the reset line is broken. - Instead of setting SNOR_READ_HWCAPS_8_8_8_DTR from Profile 1.0 table parsing, do it in spi_nor_info_init_params() instead based on the SPI_NOR_OCTAL_DTR_READ flag instead. - Set SNOR_HWCAPS_PP_8_8_8_DTR in s28hs post_sfdp hook since this capability is no longer set in Profile 1.0 parsing. - Rename spi_nor_cypress_octal_enable() to spi_nor_cypress_octal_dtr_enable(). - Instead of hard-coding 8D-8D-8D Fast Read dummy cycles to 20, find them out from the Profile 1.0 table. - Call post-bfpt fixup when exiting early because of JESD rev A. - Do not make an invalid Quad Enable BFPT field a fatal error. Silently ignore it by assuming no quad enable bit is present. - Set cmd.nbytes to 1 when using SPI_MEM_OP_CMD(). - Reject ops with more than 1 command byte in spi_mem_default_supports_op(). - Drop flag SPI_NOR_SOFT_RESET. Instead, discover soft reset capability via BFPT. - Add missing headers that were removed from common header. Changes in v3: - Read 2 bytes in Octal DTR mode when reading SR and FSR to avoid tripping up controllers. - Use op->data.nbytes as a measure of whether the data phase exists or not. This fixes data buswidth not being updadted for SR and FSR reads because they keep data buffer as NULL when calling spi_nor_setup_op(). - Add support for Micron mt35xu512aba to run in Octal DTR mode. Pratyush Yadav (27): spi: spi-mem: allow specifying whether an op is DTR or not spi: spi-mem: allow specifying a command's extension spi: spi-mem: export spi_mem_default_supports_op() spi: spi-mem: add spi_mem_dtr_supports_op() spi: cadence-qspi: Do not calibrate when device tree sets read delay spi: cadence-qspi: Add a small delay before indirect writes spi: cadence-qspi: Add support for octal DTR flashes arm: mvebu: x530: Use tiny SPI NOR mtd: spi-nor-core: Fix address width on flash chips > 16MB mtd: spi-nor-core: Add a ->setup() hook mtd: spi-nor-core: Move SFDP related declarations to top mtd: spi-nor-core: Introduce flash-specific fixup hooks mtd: spi-nor-core: Rework hwcaps selection mtd: spi-nor-core: Do not set data direction when there is no data mtd: spi-nor-core: Add support for DTR protocol mtd: spi-nor-core: prepare BFPT parsing for JESD216 rev D mtd: spi-nor-core: Get command opcode extension type from BFPT mtd: spi-nor-core: Parse xSPI Profile 1.0 table mtd: spi-nor-core: Prepare Read SR and FSR for Octal DTR mode mtd: spi-nor-core: Enable octal DTR mode when possible mtd: spi-nor-core: Do not make invalid quad enable fatal mtd: spi-nor-core: Detect Soft Reset sequence support from BFPT mtd: spi-nor-core: Perform a Soft Reset on shutdown mtd: spi-nor-core: Perform a Soft Reset on boot mtd: spi-nor-core: allow truncated erases mtd: spi-nor-core: Add support for Cypress Semper flash mtd: spi-nor-core: Allow using Micron mt35xu512aba in Octal DTR mode Takahiro Kuwano (1): mtd: spi-nor-core: Add non-uniform erase for Spansion/Cypress configs/x530_defconfig | 1 - drivers/mtd/spi/Kconfig | 42 + drivers/mtd/spi/sf_internal.h | 1 + drivers/mtd/spi/sf_probe.c | 8 + drivers/mtd/spi/spi-nor-core.c | 1447 ++++++++++++++++++++++++++------ drivers/mtd/spi/spi-nor-ids.c | 7 +- drivers/mtd/spi/spi-nor-tiny.c | 22 - drivers/spi/cadence_qspi.c | 69 +- drivers/spi/cadence_qspi.h | 16 +- drivers/spi/cadence_qspi_apb.c | 292 ++++++- drivers/spi/mtk_snfi_spi.c | 3 +- drivers/spi/spi-mem-nodm.c | 66 +- drivers/spi/spi-mem.c | 46 +- include/linux/mtd/spi-nor.h | 279 ++++-- include/spi-mem.h | 19 +- 15 files changed, 1923 insertions(+), 395 deletions(-) -- 2.30.0

2 35