April 2021 - U-Boot

[PATCH] net: sun8i-emac: Fix pinmux setup for Allwinner H5
by Andre Przywara 18 Apr '21

18 Apr '21

Commit eb5a2b671075 ("net: sun8i-emac: Determine pinmux based on SoC, not EMAC type") switched the pinmux setup over to look at CONFIG_MACH_SUN* symbols, to find the appropriate mux value. Unfortunately this patch missed to check for the H5, which is pin-compatible to the H3, but uses a different Kconfig symbol (because it has ARMv8 vs. ARMv7 cores). Replace the pure SUN8I_H3 symbol with the joint SUNXI_H3_H5 one, which is there to cover the peripherals common to both SoCs. Also explicitly list each supported SoC, and have an error message in the fallback case, to avoid those problems in the future. This fixes Ethernet support on all H5 boards. Signed-off-by: Andre Przywara <andre.przywara(a)arm.com> --- drivers/net/sun8i_emac.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c index a6cdda81a76..5a1b38bf80f 100644 --- a/drivers/net/sun8i_emac.c +++ b/drivers/net/sun8i_emac.c @@ -554,7 +554,7 @@ static int parse_phy_pins(struct udevice *dev) * The GPIO pinmux value is an integration choice, so depends on the * SoC, not the EMAC variant. */ - if (IS_ENABLED(CONFIG_MACH_SUN8I_H3)) + if (IS_ENABLED(CONFIG_MACH_SUNXI_H3_H5)) iomux = SUN8I_IOMUX_H3; else if (IS_ENABLED(CONFIG_MACH_SUN8I_R40)) iomux = SUN8I_IOMUX_R40; @@ -562,8 +562,12 @@ static int parse_phy_pins(struct udevice *dev) iomux = SUN8I_IOMUX_H6; else if (IS_ENABLED(CONFIG_MACH_SUN50I_H616)) iomux = SUN8I_IOMUX_H616; - else + else if (IS_ENABLED(CONFIG_MACH_SUN8I_A83T)) + iomux = SUN8I_IOMUX; + else if (IS_ENABLED(CONFIG_MACH_SUN50I)) iomux = SUN8I_IOMUX; + else + BUILD_BUG_ON_MSG(1, "missing pinmux value for Ethernet pins"); for (i = 0; ; i++) { int pin; -- 2.17.5

3 2

[PATCH 0/6] Allwinner H6 USB3 support
by Samuel Holland 17 Apr '21

17 Apr '21

This series adds clock, PHY, and XHCI driver support for the USB3 controller found in the Allwinner H6 SoC. Below is a log showing it functioning on the Orange Pi 3. Cheers, Samuel U-Boot 2021.04-rc1-00068-g6b8f4e0d060 (Jan 01 1970 - 00:00:00 +0000) Allwinner Technology CPU: Allwinner H6 (SUN50I) Model: OrangePi 3 DRAM: 2 GiB MMC: mmc@4020000: 0, mmc@4021000: 2, mmc@4022000: 1 Loading Environment from FAT... Unable to use mmc 1:0... In: serial@5000000 Out: serial@5000000 Err: serial@5000000 Net: No ethernet found. starting USB... Bus usb@5101000: USB EHCI 1.00 Bus usb@5101400: USB OHCI 1.0 Bus usb@5200000: Register 2000140 NbrPorts 2 Starting the controller USB XHCI 1.00 Bus usb@5311000: USB EHCI 1.00 Bus usb@5311400: USB OHCI 1.0 scanning bus usb@5101000 for devices... 1 USB Device(s) found scanning bus usb@5101400 for devices... 1 USB Device(s) found scanning bus usb@5200000 for devices... 4 USB Device(s) found scanning bus usb@5311000 for devices... 1 USB Device(s) found scanning bus usb@5311400 for devices... 1 USB Device(s) found scanning usb for storage devices... 1 Storage Device(s) found Hit any key to stop autoboot: 0 => usb tree USB device tree: 1 Hub (480 Mb/s, 0mA) u-boot EHCI Host Controller 1 Hub (12 Mb/s, 0mA) U-Boot Root Hub 1 Hub (5 Gb/s, 0mA) | U-Boot XHCI Host Controller | +-2 Hub (5 Gb/s, 0mA) | | GenesysLogic USB3.1 Hub | | | +-4 Mass Storage (5 Gb/s, 224mA) | 071044991D8D6A81 | +-3 Hub (480 Mb/s, 100mA) GenesysLogic USB2.1 Hub 1 Hub (480 Mb/s, 0mA) u-boot EHCI Host Controller 1 Hub (12 Mb/s, 0mA) U-Boot Root Hub Samuel Holland (6): clk: sunxi: Add a dummy clock driver for the RTC clk: sunxi: h6: Add XHCI clocks phy: sun50i-usb3: Add a driver for the H6 USB3 PHY usb: xhci-pci: Move reset logic out of XHCI core usb: xhci-dwc3: Add support for clocks/resets configs: Enable USB3 on Allwinner H6 boards configs/orangepi_3_defconfig | 5 + configs/pine_h64_defconfig | 5 + drivers/clk/sunxi/Makefile | 2 + drivers/clk/sunxi/clk_h6.c | 2 + drivers/clk/sunxi/clk_sun6i_rtc.c | 35 +++++ drivers/phy/allwinner/Kconfig | 8 ++ drivers/phy/allwinner/Makefile | 1 + drivers/phy/allwinner/phy-sun50i-usb3.c | 171 ++++++++++++++++++++++++ drivers/usb/host/xhci-dwc3.c | 56 ++++++++ drivers/usb/host/xhci-mem.c | 2 - drivers/usb/host/xhci-pci.c | 38 +++++- drivers/usb/host/xhci.c | 35 ----- include/usb/xhci.h | 2 - 13 files changed, 321 insertions(+), 41 deletions(-) create mode 100644 drivers/clk/sunxi/clk_sun6i_rtc.c create mode 100644 drivers/phy/allwinner/phy-sun50i-usb3.c -- 2.26.2

4 20

[PATCH UBoot] fs: btrfs: fix the false alert of decompression failure
by Qu Wenruo 17 Apr '21

17 Apr '21

There are some cases where decompressed sectors can have padding zeros. In kernel code, we have lines to address such situation: /* * btrfs_getblock is doing a zero on the tail of the page too, * but this will cover anything missing from the decompressed * data. */ if (bytes < destlen) memset(kaddr+bytes, 0, destlen-bytes); kunmap_local(kaddr); But not in U-boot code, thus we have some reports of U-boot failed to read compressed files in btrfs. Fix it by doing the same thing of the kernel. Reported-by: Matwey Kornilov <matwey.kornilov(a)gmail.com> Link: https://bugzilla.suse.com/show_bug.cgi?id=1183717 Fixes: a26a6bedafcf ("fs: btrfs: Introduce btrfs_read_extent_inline() and btrfs_read_extent_reg()") Signed-off-by: Qu Wenruo <wqu(a)suse.com> --- fs/btrfs/inode.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/fs/btrfs/inode.c b/fs/btrfs/inode.c index 019d532a1a4b..f780c53d5250 100644 --- a/fs/btrfs/inode.c +++ b/fs/btrfs/inode.c @@ -390,10 +390,16 @@ int btrfs_read_extent_inline(struct btrfs_path *path, csize); ret = btrfs_decompress(btrfs_file_extent_compression(leaf, fi), cbuf, csize, dbuf, dsize); - if (ret < 0 || ret != dsize) { + if (ret == (u32)-1) { ret = -EIO; goto out; } + /* + * The compressed part ends before sector boundary, the remaining needs + * to be zeroed out. + */ + if (ret < dsize) + memset(dbuf + ret, 0, dsize - ret); memcpy(dest, dbuf, dsize); ret = dsize; out: -- 2.31.1

1 0

[PATCH v1 0/2] cmd: bind: Fix driver binding
by Patrice Chotard 16 Apr '21

16 Apr '21

This series is fixing issues reported by Herbert Poetzl when trying to bind Ethernet gadget over USB on STM32MP1 platform. 2 issues have been found: - fix the bind command - add dwc2 bcdDevice in USB gadget controller Patrice Chotard (2): cmd: bind: Fix driver binding on a device usb: gadget: Add bcdDevice for the DWC2 USB Gadget Controller cmd/bind.c | 2 +- drivers/core/device.c | 2 +- drivers/core/lists.c | 11 ++++++++--- drivers/core/root.c | 2 +- drivers/misc/imx8/scu.c | 2 +- drivers/serial/serial-uclass.c | 2 +- drivers/timer/timer-uclass.c | 2 +- drivers/usb/gadget/gadget_chips.h | 8 ++++++++ include/dm/lists.h | 3 ++- test/dm/nop.c | 2 +- test/dm/test-fdt.c | 2 +- 11 files changed, 26 insertions(+), 12 deletions(-) -- 2.17.1

5 13

[PATCH v2] arm: dts: k3-j721e-main: Update the speed modes supported and their itap delay values for MMCSD subsystems
by Aswath Govindraju 16 Apr '21

16 Apr '21

According to latest errata of J721e [1], HS400 mode is not supported in MMCSD0 subsystem (i2024) and SDR104 mode is not supported in MMCSD1/2 subsystems (i2090). Therefore, replace mmc-hs400-1_8v with mmc-hs200-1_8v in MMCSD0 subsystem and add a sdhci mask to disable SDR104 speed mode. Also, update the itap delay values for all the MMCSD subsystems according the latest J721e data sheet[2] [1] - https://www.ti.com/lit/er/sprz455/sprz455.pdf [2] - https://www.ti.com/lit/ds/symlink/tda4vm.pdf Fixes: 70e167495ab2 ("arm: dts: k3-j721e: Sync Linux v5.11-rc6 dts into U-Boot") Signed-off-by: Aswath Govindraju <a-govindraju(a)ti.com> --- Changes since v1: - Corrected the fixes tag. arch/arm/dts/k3-j721e-main.dtsi | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-) diff --git a/arch/arm/dts/k3-j721e-main.dtsi b/arch/arm/dts/k3-j721e-main.dtsi index e47b6c0eb706..07b489679ed9 100644 --- a/arch/arm/dts/k3-j721e-main.dtsi +++ b/arch/arm/dts/k3-j721e-main.dtsi @@ -1078,13 +1078,12 @@ assigned-clocks = <&k3_clks 91 1>; assigned-clock-parents = <&k3_clks 91 2>; bus-width = <8>; - mmc-hs400-1_8v; + mmc-hs200-1_8v; mmc-ddr-1_8v; ti,otap-del-sel-legacy = <0xf>; ti,otap-del-sel-mmc-hs = <0xf>; ti,otap-del-sel-ddr52 = <0x5>; ti,otap-del-sel-hs200 = <0x6>; - ti,otap-del-sel-hs400 = <0x0>; ti,itap-del-sel-legacy = <0x10>; ti,itap-del-sel-mmc-hs = <0xa>; ti,itap-del-sel-ddr52 = <0x3>; @@ -1102,14 +1101,20 @@ assigned-clocks = <&k3_clks 92 0>; assigned-clock-parents = <&k3_clks 92 1>; ti,otap-del-sel-legacy = <0x0>; - ti,otap-del-sel-sd-hs = <0xf>; + ti,otap-del-sel-sd-hs = <0x0>; ti,otap-del-sel-sdr12 = <0xf>; ti,otap-del-sel-sdr25 = <0xf>; ti,otap-del-sel-sdr50 = <0xc>; ti,otap-del-sel-ddr50 = <0xc>; + ti,itap-del-sel-legacy = <0x0>; + ti,itap-del-sel-sd-hs = <0x0>; + ti,itap-del-sel-sdr12 = <0x0>; + ti,itap-del-sel-sdr25 = <0x0>; + ti,itap-del-sel-ddr50 = <0x2>; ti,trm-icp = <0x8>; ti,clkbuf-sel = <0x7>; dma-coherent; + sdhci-caps-mask = <0x2 0x0>; }; main_sdhci2: sdhci@4f98000 { @@ -1122,14 +1127,20 @@ assigned-clocks = <&k3_clks 93 0>; assigned-clock-parents = <&k3_clks 93 1>; ti,otap-del-sel-legacy = <0x0>; - ti,otap-del-sel-sd-hs = <0xf>; + ti,otap-del-sel-sd-hs = <0x0>; ti,otap-del-sel-sdr12 = <0xf>; ti,otap-del-sel-sdr25 = <0xf>; ti,otap-del-sel-sdr50 = <0xc>; ti,otap-del-sel-ddr50 = <0xc>; + ti,itap-del-sel-legacy = <0x0>; + ti,itap-del-sel-sd-hs = <0x0>; + ti,itap-del-sel-sdr12 = <0x0>; + ti,itap-del-sel-sdr25 = <0x0>; + ti,itap-del-sel-ddr50 = <0x2>; ti,trm-icp = <0x8>; ti,clkbuf-sel = <0x7>; dma-coherent; + sdhci-caps-mask = <0x2 0x0>; }; usbss0: cdns-usb@4104000 { -- 2.17.1

2 1

Re: [RFC PATCH v4 1/2] arch: riscv: cpu: Add callback to init each core
by Rick Chen 16 Apr '21

16 Apr '21

Hi Green, > From: Green Wan [mailto:green.wan@sifive.com] > Sent: Monday, April 12, 2021 10:33 AM > To: Sean Anderson > Cc: Rick Chen; Rick Jian-Zhi Chen(陳建志); Bin Meng; U-Boot Mailing List; Paul Walmsley; Pragnesh Patel; Simon Glass; Atish Patra; Leo Yu-Chi Liang(梁育齊); Brad Kim > Subject: Re: [RFC PATCH v4 1/2] arch: riscv: cpu: Add callback to init each core > > Hi Bin and Sean, > > While we keep the consistency of cache control discussion going, later > today I'd like to send the v5 patch which is not directly relevant to > cache control. I will prefer not to mix cache control issue into this patch. Like I said, this callback is a init for all harts before lottery. Thanks, Rick > > Regards, > Green > > On Sun, Apr 11, 2021 at 11:43 PM Sean Anderson <seanga2(a)gmail.com> wrote: > > > > On 4/9/21 12:05 PM, Green Wan wrote: > > > Hi folks, > > > > > > Correct me if I'm wrong, like Rick mentioned, i/dcache > > > enable/disable() is only called on the main hart. Right now the dummy > > > i/dcache enable/disable are empty and shared among all riscv CPU. The > > > ax25 is the only one that has its own implementation for now. > > > > Right, so why are caches are disabled on all harts before booting Linux > > on ax25? Is there a requirement for this on ax25 which that other > > platforms (which have always-on caches like k210, or which have > > non-disableable caches like fuX40) do not have? > > > > --Sean > > > > > > > > FU540/FU740 also leverages the dummy i/dcache enable/disable() > > > functions (only main hart calls them). L2 cache on FU540/FU740 is > > > enabled as SRAM purpose. And according to the HW design behavior, once > > > L2 is enabled, it can't be disabled unless doing a reset.[1] The Linux > > > L2$ driver will handle that according to the configuration of L2 > > > registers. > > > > > > [1] https://static.dev.sifive.com/FU540-C000-v1.0.pdf > > > > > > Thanks, > > > > > > On Fri, Apr 9, 2021 at 9:18 PM Sean Anderson <seanga2(a)gmail.com> wrote: > > >> > > >> On 4/9/21 4:16 AM, Rick Chen wrote: > > >>> Hi Sean ,Bin > > >>> > > >>>> From: Bin Meng [mailto:bmeng.cn@gmail.com] > > >>>> Sent: Tuesday, April 06, 2021 5:16 PM > > >>>> To: Sean Anderson > > >>>> Cc: Green Wan; Rick Jian-Zhi Chen(陳建志); Paul Walmsley; Pragnesh Patel; Bin Meng; Simon Glass; Atish Patra; Leo Yu-Chi Liang(梁育齊); Brad Kim; U-Boot Mailing List > > >>>> Subject: Re: [RFC PATCH v4 1/2] arch: riscv: cpu: Add callback to init each core > > >>>> > > >>>> On Sat, Apr 3, 2021 at 6:53 AM Sean Anderson <seanga2(a)gmail.com> wrote: > > >>>>> > > >>>>> On 3/30/21 1:26 AM, Green Wan wrote: > > >>>>>> Add a callback riscv_hart_early_init() to ./arch/riscv/cpu/start.S to > > >>>>>> allow different riscv hart perform setup code for each hart as early > > >>>>>> as possible. Since all the harts enter the callback, they must be able > > >>>>>> to run the same setup. > > >>>>>> > > >>>>>> Signed-off-by: Green Wan <green.wan(a)sifive.com> > > >>>>>> --- > > >>>>>> arch/riscv/cpu/cpu.c | 15 +++++++++++++++ > > >>>>>> arch/riscv/cpu/start.S | 14 ++++++++++++++ > > >>>>>> 2 files changed, 29 insertions(+) > > >>>>>> > > >>>>>> diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c > > >>>>>> index 85592f5bee..1652e51137 100644 > > >>>>>> --- a/arch/riscv/cpu/cpu.c > > >>>>>> +++ b/arch/riscv/cpu/cpu.c > > >>>>>> @@ -140,3 +140,18 @@ int arch_early_init_r(void) > > >>>>>> { > > >>>>>> return riscv_cpu_probe(); > > >>>>>> } > > >>>>>> + > > >>>>>> +/** > > >>>>>> + * riscv_hart_early_init() - A dummy function called by > > >>>>>> + * ./arch/riscv/cpu/start.S to allow to disable/enable features of each core. > > >>>>>> + * For example, turn on or off the functional block of CPU harts. > > >>>>>> + * > > >>>>>> + * In a multi-core system, this function must not access shared resources. > > >>>>>> + * > > >>>>>> + * Any access to such resources would probably be better done with > > >>>>>> + * available_harts_lock held. However, I doubt that any such access will be > > >>>>>> + * necessary. > > >>>>>> + */ > > >>>>>> +__weak void riscv_hart_early_init(void) > > >>>>>> +{ > > >>>>>> +} > > >>>>>> diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S > > >>>>>> index 8589509e01..ab73008f23 100644 > > >>>>>> --- a/arch/riscv/cpu/start.S > > >>>>>> +++ b/arch/riscv/cpu/start.S > > >>>>>> @@ -117,6 +117,20 @@ call_board_init_f_0: > > >>>>>> mv sp, a0 > > >>>>>> #endif > > >>>>>> > > >>>>>> +#if CONFIG_IS_ENABLED(RISCV_MMODE) > > >>>>>> + /* > > >>>>>> + * Jump to riscv_hart_early_init() to perform init for each core. Not > > >>>>>> + * expect to access gd since gd is not initialized. All operations in the > > >>>>>> + * function should affect core itself only. In multi-core system, any access > > >>>>>> + * to common resource or registers outside core should be avoided or need a > > >>>>>> + * protection for multicore. > > >>>>>> + * > > >>>>>> + * A dummy implementation is provided in ./arch/riscv/cpu/cpu.c. > > >>>>>> + */ > > >>>>>> +call_riscv_hart_early_init: > > >>>>>> + jal riscv_hart_early_init > > >>>>>> +#endif > > >>>>>> + > > >>>>> > > >>>>> I wonder if we could move the calls to icache_enable and dcache_enable > > >>>>> into this function. Though this would have the consequence of enabling > > >>>>> caches on all harts for CPUs which previously only enabled them for the > > >>>>> boot hart. I think ax25 is the only CPU which currently does this. Bin, > > >>>>> would this be an issue? > > >>> > > >>> No, they are functions shall be called in different stage about lottery. > > >>> riscv_hart_early_init() is called before lottery for all harts. > > >>> It shall not move icache_enable() and dcache_enable() into > > >>> riscv_hart_early_init(), they are belong to the stage after lottery > > >>> only for main hart. > > >>> > > >>>> > > >>>> Good catch. I believe AX25 cache support is currently somehow broken? > > >>> > > >>> No, AX25 cache support is currently work well. > > >>> > > >>>> > > >>>> I think Rick has to comment on this as he added this via commit: > > >>>> > > >>>> commit 52923c6db7f00e0197ec894c8c1bb8a7681974bb > > >>>> Author: Rick Chen <rick(a)andestech.com> > > >>>> Date: Wed Nov 7 09:34:06 2018 +0800 > > >>>> > > >>>> riscv: cache: Implement i/dcache [status, enable, disable] > > >>>> > > >>>> AndeStar RISC-V(V5) provide mcache_ctl register which > > >>>> can configure I/D cache as enabled or disabled. > > >>>> > > >>>> This CSR will be encapsulated by CONFIG_RISCV_NDS. > > >>>> If you want to configure cache on AndeStar V5 > > >>>> AE350 platform. YOu can enable [*] AndeStar V5 ISA support > > >>>> by make menuconfig. > > >>>> > > >>>> This approach also provide the expansion when the > > >>>> vender specific features are going to join in. > > >>>> > > >>>> Signed-off-by: Rick Chen <rick(a)andestech.com> > > >>>> Cc: Greentime Hu <greentime(a)andestech.com> > > >>>> > > >>>> The original commit has i/d cache enabled on all harts. But it was > > >>>> later moved to boot hart due to SMP support. > > >>> > > >>> Not all harts will enable i/d cache during startup currently, only > > >>> main hart will enable i/d cache here. > > >>> So only main hart will disable i/d cache in cleanup_before_linux(). > > >> > > >> Ok, so we have ax25 where cache is disabled on all harts before Linux, > > >> and fu740 where cache will be enabled on all harts. Is there any > > >> guidance from Linux on what should be happening here? > > >> > > >> --Sean > > >> > > >>> Thanks, > > >>> Rick > > >>> > > >>>> > > >>>> However on the cleanup side, it looks only the boot hart calls i/d > > >>>> cache disable? > > >>> > > >>>> > > >>>> See arch/riscv/cpu/ax25/cpu.c:: cleanup_before_linux() > > >>>> > > >>>> Regards, > > >>>> Bin > > >> > > >> > >

3 7

[PATCH] lib/rsa: Use EVP_PKEY instead of RSA
by Chan, Donald 16 Apr '21

16 Apr '21

Most modern OpenSSL engines have methods overridden at the EVP level rather than at RSA level, to make these engines work properly with mkimage, the RSA signing code needs to switch to using EVP_* APIs as much as possible. Signed-off-by: Donald Chan <hoiho(a)lab126.com> --- lib/rsa/rsa-sign.c | 168 +++++++++++++++++++++-------------------------------- 1 file changed, 66 insertions(+), 102 deletions(-) diff --git a/lib/rsa/rsa-sign.c b/lib/rsa/rsa-sign.c index 1f0d81b..0eb480b 100644 --- a/lib/rsa/rsa-sign.c +++ b/lib/rsa/rsa-sign.c @@ -51,19 +51,21 @@ static int rsa_err(const char *msg) * * @keydir: Directory containins the key * @name Name of key file (will have a .crt extension) - * @rsap Returns RSA object, or NULL on failure - * @return 0 if ok, -ve on error (in which case *rsap will be set to NULL) + * @evpp Returns EVP_PKEY object, or NULL on failure + * @return 0 if ok, -ve on error (in which case *evpp will be set to NULL) */ -static int rsa_pem_get_pub_key(const char *keydir, const char *name, RSA **rsap) +static int rsa_pem_get_pub_key(const char *keydir, const char *name, EVP_PKEY **evpp) { char path[1024]; - EVP_PKEY *key; + EVP_PKEY *key = NULL; X509 *cert; - RSA *rsa; FILE *f; int ret; - *rsap = NULL; + if (!evpp) + return -EINVAL; + + *evpp = NULL; snprintf(path, sizeof(path), "%s/%s.crt", keydir, name); f = fopen(path, "r"); if (!f) { @@ -88,22 +90,12 @@ static int rsa_pem_get_pub_key(const char *keydir, const char *name, RSA **rsap) goto err_pubkey; } - /* Convert to a RSA_style key. */ - rsa = EVP_PKEY_get1_RSA(key); - if (!rsa) { - rsa_err("Couldn't convert to a RSA style key"); - ret = -EINVAL; - goto err_rsa; - } fclose(f); - EVP_PKEY_free(key); + *evpp = key; X509_free(cert); - *rsap = rsa; return 0; -err_rsa: - EVP_PKEY_free(key); err_pubkey: X509_free(cert); err_cert: @@ -117,19 +109,20 @@ err_cert: * @keydir: Key prefix * @name Name of key * @engine Engine to use - * @rsap Returns RSA object, or NULL on failure - * @return 0 if ok, -ve on error (in which case *rsap will be set to NULL) + * @evpp Returns EVP_PKEY object, or NULL on failure + * @return 0 if ok, -ve on error (in which case *evpp will be set to NULL) */ static int rsa_engine_get_pub_key(const char *keydir, const char *name, - ENGINE *engine, RSA **rsap) + ENGINE *engine, EVP_PKEY **evpp) { const char *engine_id; char key_id[1024]; - EVP_PKEY *key; - RSA *rsa; - int ret; + EVP_PKEY *key = NULL; + + if (!evpp) + return -EINVAL; - *rsap = NULL; + *evpp = NULL; engine_id = ENGINE_get_id(engine); @@ -165,22 +158,9 @@ static int rsa_engine_get_pub_key(const char *keydir, const char *name, if (!key) return rsa_err("Failure loading public key from engine"); - /* Convert to a RSA_style key. */ - rsa = EVP_PKEY_get1_RSA(key); - if (!rsa) { - rsa_err("Couldn't convert to a RSA style key"); - ret = -EINVAL; - goto err_rsa; - } - - EVP_PKEY_free(key); - *rsap = rsa; + *evpp = key; return 0; - -err_rsa: - EVP_PKEY_free(key); - return ret; } /** @@ -189,15 +169,15 @@ err_rsa: * @keydir: Directory containing the key (PEM file) or key prefix (engine) * @name Name of key file (will have a .crt extension) * @engine Engine to use - * @rsap Returns RSA object, or NULL on failure - * @return 0 if ok, -ve on error (in which case *rsap will be set to NULL) + * @evpp Returns EVP_PKEY object, or NULL on failure + * @return 0 if ok, -ve on error (in which case *evpp will be set to NULL) */ static int rsa_get_pub_key(const char *keydir, const char *name, - ENGINE *engine, RSA **rsap) + ENGINE *engine, EVP_PKEY **evpp) { if (engine) - return rsa_engine_get_pub_key(keydir, name, engine, rsap); - return rsa_pem_get_pub_key(keydir, name, rsap); + return rsa_engine_get_pub_key(keydir, name, engine, evpp); + return rsa_pem_get_pub_key(keydir, name, evpp); } /** @@ -205,17 +185,19 @@ static int rsa_get_pub_key(const char *keydir, const char *name, * * @keydir: Directory containing the key * @name Name of key file (will have a .key extension) - * @rsap Returns RSA object, or NULL on failure - * @return 0 if ok, -ve on error (in which case *rsap will be set to NULL) + * @evpp Returns EVP_PKEY object, or NULL on failure + * @return 0 if ok, -ve on error (in which case *evpp will be set to NULL) */ static int rsa_pem_get_priv_key(const char *keydir, const char *name, - RSA **rsap) + EVP_PKEY **evpp) { - char path[1024]; - RSA *rsa; - FILE *f; + char path[1024] = {0}; + FILE *f = NULL; - *rsap = NULL; + if (!evpp) + return -EINVAL; + + *evpp = NULL; snprintf(path, sizeof(path), "%s/%s.key", keydir, name); f = fopen(path, "r"); if (!f) { @@ -224,14 +206,12 @@ static int rsa_pem_get_priv_key(const char *keydir, const char *name, return -ENOENT; } - rsa = PEM_read_RSAPrivateKey(f, 0, NULL, path); - if (!rsa) { + if (!PEM_read_PrivateKey(f, evpp, NULL, path)) { rsa_err("Failure reading private key"); fclose(f); return -EPROTO; } fclose(f); - *rsap = rsa; return 0; } @@ -242,19 +222,18 @@ static int rsa_pem_get_priv_key(const char *keydir, const char *name, * @keydir: Key prefix * @name Name of key * @engine Engine to use - * @rsap Returns RSA object, or NULL on failure - * @return 0 if ok, -ve on error (in which case *rsap will be set to NULL) + * @evpp Returns EVP_PKEY object, or NULL on failure + * @return 0 if ok, -ve on error (in which case *evpp will be set to NULL) */ static int rsa_engine_get_priv_key(const char *keydir, const char *name, - ENGINE *engine, RSA **rsap) + ENGINE *engine, EVP_PKEY **evpp) { const char *engine_id; char key_id[1024]; - EVP_PKEY *key; - RSA *rsa; - int ret; + EVP_PKEY *key = NULL; - *rsap = NULL; + if (!evpp) + return -EINVAL; engine_id = ENGINE_get_id(engine); @@ -290,22 +269,9 @@ static int rsa_engine_get_priv_key(const char *keydir, const char *name, if (!key) return rsa_err("Failure loading private key from engine"); - /* Convert to a RSA_style key. */ - rsa = EVP_PKEY_get1_RSA(key); - if (!rsa) { - rsa_err("Couldn't convert to a RSA style key"); - ret = -EINVAL; - goto err_rsa; - } - - EVP_PKEY_free(key); - *rsap = rsa; + *evpp = key; return 0; - -err_rsa: - EVP_PKEY_free(key); - return ret; } /** @@ -314,15 +280,15 @@ err_rsa: * @keydir: Directory containing the key (PEM file) or key prefix (engine) * @name Name of key * @engine Engine to use for signing - * @rsap Returns RSA object, or NULL on failure - * @return 0 if ok, -ve on error (in which case *rsap will be set to NULL) + * @evpp Returns EVP_PKEY object, or NULL on failure + * @return 0 if ok, -ve on error (in which case *evpp will be set to NULL) */ static int rsa_get_priv_key(const char *keydir, const char *name, - ENGINE *engine, RSA **rsap) + ENGINE *engine, EVP_PKEY **evpp) { if (engine) - return rsa_engine_get_priv_key(keydir, name, engine, rsap); - return rsa_pem_get_priv_key(keydir, name, rsap); + return rsa_engine_get_priv_key(keydir, name, engine, evpp); + return rsa_pem_get_priv_key(keydir, name, evpp); } static int rsa_init(void) @@ -416,12 +382,11 @@ static void rsa_engine_remove(ENGINE *e) } } -static int rsa_sign_with_key(RSA *rsa, struct padding_algo *padding_algo, +static int rsa_sign_with_key(EVP_PKEY *pkey, struct padding_algo *padding_algo, struct checksum_algo *checksum_algo, const struct image_region region[], int region_count, uint8_t **sigp, uint *sig_size) { - EVP_PKEY *key; EVP_PKEY_CTX *ckey; EVP_MD_CTX *context; int ret = 0; @@ -429,16 +394,7 @@ static int rsa_sign_with_key(RSA *rsa, struct padding_algo *padding_algo, uint8_t *sig; int i; - key = EVP_PKEY_new(); - if (!key) - return rsa_err("EVP_PKEY object creation failed"); - - if (!EVP_PKEY_set1_RSA(key, rsa)) { - ret = rsa_err("EVP key setup failed"); - goto err_set; - } - - size = EVP_PKEY_size(key); + size = EVP_PKEY_size(pkey); sig = malloc(size); if (!sig) { fprintf(stderr, "Out of memory for signature (%zu bytes)\n", @@ -454,7 +410,7 @@ static int rsa_sign_with_key(RSA *rsa, struct padding_algo *padding_algo, } EVP_MD_CTX_init(context); - ckey = EVP_PKEY_CTX_new(key, NULL); + ckey = EVP_PKEY_CTX_new(pkey, NULL); if (!ckey) { ret = rsa_err("EVP key context creation failed"); goto err_create; @@ -462,7 +418,7 @@ static int rsa_sign_with_key(RSA *rsa, struct padding_algo *padding_algo, if (EVP_DigestSignInit(context, &ckey, checksum_algo->calculate_sign(), - NULL, key) <= 0) { + NULL, pkey) <= 0) { ret = rsa_err("Signer setup failed"); goto err_sign; } @@ -497,7 +453,6 @@ static int rsa_sign_with_key(RSA *rsa, struct padding_algo *padding_algo, EVP_MD_CTX_reset(context); #endif EVP_MD_CTX_destroy(context); - EVP_PKEY_free(key); debug("Got signature: %d bytes, expected %zu\n", *sig_size, size); *sigp = sig; @@ -510,8 +465,6 @@ err_sign: err_create: free(sig); err_alloc: -err_set: - EVP_PKEY_free(key); return ret; } @@ -519,7 +472,7 @@ int rsa_sign(struct image_sign_info *info, const struct image_region region[], int region_count, uint8_t **sigp, uint *sig_len) { - RSA *rsa; + EVP_PKEY *pkey = NULL; ENGINE *e = NULL; int ret; @@ -533,15 +486,15 @@ int rsa_sign(struct image_sign_info *info, goto err_engine; } - ret = rsa_get_priv_key(info->keydir, info->keyname, e, &rsa); + ret = rsa_get_priv_key(info->keydir, info->keyname, e, &pkey); if (ret) goto err_priv; - ret = rsa_sign_with_key(rsa, info->padding, info->checksum, region, + ret = rsa_sign_with_key(pkey, info->padding, info->checksum, region, region_count, sigp, sig_len); if (ret) goto err_sign; - RSA_free(rsa); + EVP_PKEY_free(pkey); if (info->engine_id) rsa_engine_remove(e); rsa_remove(); @@ -549,7 +502,7 @@ int rsa_sign(struct image_sign_info *info, return ret; err_sign: - RSA_free(rsa); + EVP_PKEY_free(pkey); err_priv: if (info->engine_id) rsa_engine_remove(e); @@ -754,6 +707,7 @@ int rsa_add_verify_data(struct image_sign_info *info, void *keydest) int ret; int bits; RSA *rsa; + EVP_PKEY *pkey = NULL; ENGINE *e = NULL; debug("%s: Getting verification data\n", __func__); @@ -762,9 +716,15 @@ int rsa_add_verify_data(struct image_sign_info *info, void *keydest) if (ret) return ret; } - ret = rsa_get_pub_key(info->keydir, info->keyname, e, &rsa); + ret = rsa_get_pub_key(info->keydir, info->keyname, e, &pkey); if (ret) goto err_get_pub_key; +#if OPENSSL_VERSION_NUMBER < 0x10100000L || \ + (defined(LIBRESSL_VERSION_NUMBER) && LIBRESSL_VERSION_NUMBER < 0x02070000fL) + rsa = EVP_PKEY_get1_RSA(pkey); +#else + rsa = EVP_PKEY_get0_RSA(pkey); +#endif ret = rsa_get_params(rsa, &exponent, &n0_inv, &modulus, &r_squared); if (ret) goto err_get_params; @@ -834,7 +794,11 @@ done: if (ret) ret = ret == -FDT_ERR_NOSPACE ? -ENOSPC : -EIO; err_get_params: +#if OPENSSL_VERSION_NUMBER < 0x10100000L || \ + (defined(LIBRESSL_VERSION_NUMBER) && LIBRESSL_VERSION_NUMBER < 0x02070000fL) RSA_free(rsa); +#endif + EVP_PKEY_free(pkey); err_get_pub_key: if (info->engine_id) rsa_engine_remove(e); -- 2.7.4

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[PATCH v3 0/6] SPL: FIT: Fix some omissions of SPL_LOAD_FIT_FULL and bootm
by Alexandru Gagniuc 16 Apr '21

16 Apr '21

Although this series focuses on SPL_LOAD_FIT_FULL, some of the fixes will also apply to bootm, as they are sharing significant amounts of code. Originally SPL_LOAD_FIT_FULL could not start either a linux FIT or a u-boot image. It didn't even take FIT images generated automatically by mkimage, as part of the u-boot build!!! The goal is to at the very least, be able to boot autogenerated mkimage FITs. This brings us much more in line with SPL_LOAD_FIT, and the documentation. It's not perfect, and the fpga 'compatible =' support is still not implemented. That's all I currently have time for before someone notices I'm working on u-boot again. Changes since v2: - spl_load_fit_image: Use "if (fit_image_get_os())" -- without the "!" Changes since v1: - Update commit message of "spl: LOAD_FIT_FULL: Fix selection of the "fdt" node" Alexandru Gagniuc (6): spl: LOAD_FIT_FULL: Fix selection of the "fdt" node spl: LOAD_FIT_FULL: Do not hard-code os to IH_OS_U_BOOT spl: LOAD_FIT_FULL: Relocate FDT for u-boot payloads spl: LOAD_FIT_FULL: Support 'kernel' and 'firmware' properties image-fit: Accept IH_TYPE_FIRMWARE in fit_image_load() as valid image-fit: Accept OP-TEE images when booting a FIT common/image-fit.c | 4 ++++ common/spl/spl.c | 40 +++++++++++++++++++++++++++++++++------- 2 files changed, 37 insertions(+), 7 deletions(-) -- 2.26.3

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[PATCH] common: fit: Add weak board_fit_config_name_match
by Sean Anderson 16 Apr '21

16 Apr '21

Several architectures had a default board_fit_config_name_match already; this provides a generic weak version. We default to rejecting all configs. This will use the FIT's default config, instead of the first config. This may result in boot failures if there are multiple configurations and the first config is *not* the default. Signed-off-by: Sean Anderson <sean.anderson(a)seco.com> --- arch/arm/cpu/armv8/fsl-layerscape/spl.c | 9 --------- arch/arm/mach-rockchip/spl.c | 10 ---------- common/common_fit.c | 5 +++++ 3 files changed, 5 insertions(+), 19 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c b/arch/arm/cpu/armv8/fsl-layerscape/spl.c index d5131bcf4b..46e8af8ebd 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c @@ -139,13 +139,4 @@ int spl_start_uboot(void) return 1; } #endif /* CONFIG_SPL_OS_BOOT */ -#ifdef CONFIG_SPL_LOAD_FIT -__weak int board_fit_config_name_match(const char *name) -{ - /* Just empty function now - can't decide what to choose */ - debug("%s: %s\n", __func__, name); - - return 0; -} -#endif #endif /* CONFIG_SPL_BUILD */ diff --git a/arch/arm/mach-rockchip/spl.c b/arch/arm/mach-rockchip/spl.c index 4b5c22dc13..02c40fb37e 100644 --- a/arch/arm/mach-rockchip/spl.c +++ b/arch/arm/mach-rockchip/spl.c @@ -151,13 +151,3 @@ void board_init_f(ulong dummy) #endif preloader_console_init(); } - -#ifdef CONFIG_SPL_LOAD_FIT -int __weak board_fit_config_name_match(const char *name) -{ - /* Just empty function now - can't decide what to choose */ - debug("%s: %s\n", __func__, name); - - return 0; -} -#endif diff --git a/common/common_fit.c b/common/common_fit.c index 219674d467..cde2dc45e9 100644 --- a/common/common_fit.c +++ b/common/common_fit.c @@ -22,6 +22,11 @@ ulong fdt_getprop_u32(const void *fdt, int node, const char *prop) return fdt32_to_cpu(*cell); } +__weak int board_fit_config_name_match(const char *name) +{ + return -EINVAL; +} + /* * Iterate over all /configurations subnodes and call a platform specific * function to find the matching configuration. -- 2.25.1

2 1

[PATCH v2 0/7] SPL: FIT: Bring the SPL_LOAD_FIT path in line with documentation
by Alexandru Gagniuc 16 Apr '21

16 Apr '21

When I wrote commit 4afc4f37c70e ("doc: FIT image: Clarify format and simplify syntax"), I did not expect it to go through without objection. I didn't also write the code to go along with it. This series fixes that by updating one of the three FIT code paths to be compliant. There are three code paths that deal with loading a FIT: * ( )'bootm' command * (x) SPL_LOAD_FIT * ( ) SPL_LOAD_FIT_FULL This series deals with SPL_LOAD_FIT. I chose not to fix every nook and cranny because nobody is using those corner cases -- as evidenced by the lack of support. Known limitations are documented and clearly visible in the Kconfig menu. Changes since v1: - Replace NULL with 0 in comment for spl_load_fit_image(). - Updated Kconfig description for SPL_LOAD_FIT (add "property" word) - Remove middle printf in warn_deprecated() - Add newline before return in spl_fit_upload_fpga() Alexandru Gagniuc (7): spl: fit: Don't overwrite previous loadable if "load" is missing doc: FIT image: Introduce "u-boot,fpga-legacy" property spl: fit: Move FPGA loading code to separate functions spl: fit: Warn if FIT contains "fpga" property in config node spl: fit: Support loading FPGA images from list of "loadables" Kconfig: Document the limitations of the simple SPL_LOAD_FIT path doc: FIT image: Update FPGA example to make use of "loadables" common/Kconfig.boot | 10 +++ common/spl/spl_fit.c | 113 ++++++++++++++++++++------ doc/uImage.FIT/multi-with-fpga.its | 3 +- doc/uImage.FIT/source_file_format.txt | 1 + 4 files changed, 99 insertions(+), 28 deletions(-) -- 2.26.3

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