April 2021 - U-Boot

[PATCH] spi: zynqmp: Remove gd reference
by Michal Simek 29 Apr '21

29 Apr '21

gd is not used in this file that's why doesn't make sense to declare it. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- drivers/spi/zynqmp_gqspi.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c index 900cb2610c7f..eee8e9df0f7d 100644 --- a/drivers/spi/zynqmp_gqspi.c +++ b/drivers/spi/zynqmp_gqspi.c @@ -10,7 +10,6 @@ #include <log.h> #include <asm/arch/sys_proto.h> #include <asm/cache.h> -#include <asm/global_data.h> #include <asm/io.h> #include <clk.h> #include <dm.h> @@ -156,8 +155,6 @@ struct zynqmp_qspi_dma_regs { u32 dmadstmsb; /* 0x28 */ }; -DECLARE_GLOBAL_DATA_PTR; - struct zynqmp_qspi_plat { struct zynqmp_qspi_regs *regs; struct zynqmp_qspi_dma_regs *dma_regs; -- 2.31.1

2 1

[v1 00/17] Add Intel N5X SoC support
by Siew Chin Lim 29 Apr '21

29 Apr '21

This patchset add Intel N5X SoC[1] support. Intel N5X SoC is with a 64-bit quad core ARM Cortex-A53 MPCore hard processor system (HPS). New IPs in N5X are clock manager and DDR subsystem, other IPs have minor changes compared to Agilex. Intel N5X SoC supports legacy boot without ATF, ATF boot, and ATF boot with VAB enabled. [1]: https://www.intel.com/content/www/us/en/products/programmable/asic/easic-de… Siew Chin Lim (16): arm: socfpga: Changed base_addr_s10.h to base_addr_soc64.h arm: socfpga: Add base address for Intel N5X device arm: socfpga: Add handoff data support for Intel N5X device drivers: clk: Add clock driver for Intel N5X device arm: socfpga: Get clock manager base address for Intel N5X device drivers: clk: Add memory clock driver for Intel N5X device arm: socfpga: Move cm_get_mpu_clk_hz function declaration to clock_manager.h arm: socfpga: Add clock manager for Intel N5X device arm: socfpga: Changed misc_s10.c to misc_soc64.c arm: socfpga: Add SDRAM driver helper function for Intel N5X device ddr: altera: Add SDRAM driver for Intel N5X device arm: socfpga: Add SPL for Intel N5X device board: intel: Add socdk board support for Intel N5X device arm: dts: Add base dtsi and devkit dts for Intel N5X device include: configs: Add Intel N5X device CONFIGs arm: socfpga: Enable Intel N5X device build Tien Fong Chee (1): ddr: socfpga: Enable memory test on memory size less than 1GB arch/arm/dts/Makefile | 1 + arch/arm/dts/socfpga_n5x-u-boot.dtsi | 101 + arch/arm/dts/socfpga_n5x.dtsi | 640 ++++++ arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi | 67 + arch/arm/dts/socfpga_n5x_socdk.dts | 143 ++ arch/arm/mach-socfpga/Kconfig | 20 +- arch/arm/mach-socfpga/Makefile | 26 +- arch/arm/mach-socfpga/clock_manager_n5x.c | 80 + .../mach/{base_addr_s10.h => base_addr_soc64.h} | 11 +- arch/arm/mach-socfpga/include/mach/clock_manager.h | 3 + .../include/mach/clock_manager_agilex.h | 2 - .../include/mach/clock_manager_arria10.h | 1 - .../mach-socfpga/include/mach/clock_manager_gen5.h | 1 - .../mach-socfpga/include/mach/clock_manager_n5x.h | 12 + .../mach-socfpga/include/mach/clock_manager_s10.h | 1 - arch/arm/mach-socfpga/include/mach/firewall.h | 6 + arch/arm/mach-socfpga/include/mach/handoff_soc64.h | 28 + arch/arm/mach-socfpga/include/mach/misc.h | 4 + .../include/mach/system_manager_soc64.h | 10 +- arch/arm/mach-socfpga/misc.c | 3 + arch/arm/mach-socfpga/{misc_s10.c => misc_soc64.c} | 79 +- arch/arm/mach-socfpga/spl_n5x.c | 94 + arch/arm/mach-socfpga/wrap_handoff_soc64.c | 40 + board/intel/n5x-socdk/MAINTAINERS | 7 + board/intel/n5x-socdk/Makefile | 7 + board/intel/n5x-socdk/socfpga.c | 7 + configs/socfpga_n5x_atf_defconfig | 77 + configs/socfpga_n5x_defconfig | 65 + configs/socfpga_n5x_vab_defconfig | 79 + drivers/clk/altera/Makefile | 4 +- drivers/clk/altera/clk-mem-n5x.c | 136 ++ drivers/clk/altera/clk-mem-n5x.h | 84 + drivers/clk/altera/clk-n5x.c | 489 +++++ drivers/clk/altera/clk-n5x.h | 217 ++ drivers/ddr/altera/Makefile | 3 +- drivers/ddr/altera/sdram_n5x.c | 2316 ++++++++++++++++++++ drivers/ddr/altera/sdram_soc64.c | 28 +- include/configs/socfpga_n5x_socdk.h | 45 + include/configs/socfpga_soc64_common.h | 2 +- include/dt-bindings/clock/n5x-clock.h | 71 + 40 files changed, 4982 insertions(+), 28 deletions(-) create mode 100644 arch/arm/dts/socfpga_n5x-u-boot.dtsi create mode 100644 arch/arm/dts/socfpga_n5x.dtsi create mode 100644 arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi create mode 100644 arch/arm/dts/socfpga_n5x_socdk.dts create mode 100644 arch/arm/mach-socfpga/clock_manager_n5x.c rename arch/arm/mach-socfpga/include/mach/{base_addr_s10.h => base_addr_soc64.h} (85%) create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_n5x.h rename arch/arm/mach-socfpga/{misc_s10.c => misc_soc64.c} (51%) create mode 100644 arch/arm/mach-socfpga/spl_n5x.c create mode 100644 board/intel/n5x-socdk/MAINTAINERS create mode 100644 board/intel/n5x-socdk/Makefile create mode 100644 board/intel/n5x-socdk/socfpga.c create mode 100644 configs/socfpga_n5x_atf_defconfig create mode 100644 configs/socfpga_n5x_defconfig create mode 100644 configs/socfpga_n5x_vab_defconfig create mode 100644 drivers/clk/altera/clk-mem-n5x.c create mode 100644 drivers/clk/altera/clk-mem-n5x.h create mode 100644 drivers/clk/altera/clk-n5x.c create mode 100644 drivers/clk/altera/clk-n5x.h create mode 100644 drivers/ddr/altera/sdram_n5x.c create mode 100644 include/configs/socfpga_n5x_socdk.h create mode 100644 include/dt-bindings/clock/n5x-clock.h -- 2.13.0

4 40

[PATCH] arm64: zynqmp: Enable capsule update
by Michal Simek 29 Apr '21

29 Apr '21

Enable EFI capsule update features to be enabled by default also with all dfu valid options for ZynqMP. This feature was tested on Xilinx ZynqMP zcu104 board with defining dfu_alt_info="mmc 0:1=boot.bin fat 0 1;u-boot.itb fat 0 1" and dfu_alt_info="sf 0:0=boot.bin raw 0 0x50000;u-boot.itb raw 0x80000 0x500000". There is a need to increase malloc size for getting dfu mmc to work. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> CC: Sughosh Ganu <sughosh.ganu(a)linaro.org> CC: Ilias Apalodimas <ilias.apalodimas(a)linaro.org> CC: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- I actually didn't try to boot out of qspi because qspi writing is likely broken and should be fixed. But I have checked that images are written to that previously erased locations. U-Boot SPL 2021.04-00978-g76a8101e4548 (Apr 26 2021 - 13:01:46 +0200) PMUFW: v1.1 Loading new PMUFW cfg obj (2024 bytes) Silicon version: 3 EL Level: EL3 Chip ID: zu7e Multiboot: 0 Trying to boot from MMC2 spl: could not initialize mmc. error: -19 Trying to boot from MMC1 spl_load_image_fat_os: error reading image u-boot.bin, err - -2 NOTICE: ATF running on XCZU7EG/EV/silicon v4/RTL5.1 at 0xfffea000 NOTICE: BL31: v2.2(release):xilinx-v2020.2.2-k26 NOTICE: BL31: Built : 11:51:16, Apr 21 2021 U-Boot 2021.04-00978-g76a8101e4548 (Apr 26 2021 - 13:01:46 +0200) Model: ZynqMP ZCU104 RevC Board: Xilinx ZynqMP DRAM: 2 GiB PMUFW: v1.1 EL Level: EL2 Chip ID: zu7e WDT: Started with servicing (60s timeout) NAND: 0 MiB MMC: mmc@ff170000: 0 Loading Environment from FAT... OK In: serial Out: serial Err: serial Net: ZYNQ GEM: ff0e0000, mdio bus ff0e0000, phyaddr 12, interface rgmii-id eth0: ethernet@ff0e0000 Scanning disk mmc(a)ff170000.blk... Found 4 disks ##Hit any key to stop autoboot: 0 ZynqMP> reset resetting ... U-Boot SPL 2021.04-00978-g01e9f0ec63e4 (Apr 26 2021 - 13:04:48 +0200) PMUFW: v1.1 Loading new PMUFW cfg obj (2024 bytes) Silicon version: 3 EL Level: EL3 Chip ID: zu7e Multiboot: 0 Trying to boot from MMC2 spl: could not initialize mmc. error: -19 Trying to boot from MMC1 spl_load_image_fat_os: error reading image u-boot.bin, err - -2 NOTICE: ATF running on XCZU7EG/EV/silicon v4/RTL5.1 at 0xfffea000 NOTICE: BL31: v2.2(release):xilinx-v2020.2.2-k26 NOTICE: BL31: Built : 11:51:16, Apr 21 2021 U-Boot 2021.04-00978-g01e9f0ec63e4 (Apr 26 2021 - 13:04:48 +0200) Model: ZynqMP ZCU104 RevC Board: Xilinx ZynqMP DRAM: 2 GiB PMUFW: v1.1 EL Level: EL2 Chip ID: zu7e WDT: Started with servicing (60s timeout) NAND: 0 MiB MMC: mmc@ff170000: 0 Loading Environment from FAT... OK In: serial Out: serial Err: serial Net: ZYNQ GEM: ff0e0000, mdio bus ff0e0000, phyaddr 12, interface rgmii-id eth0: ethernet@ff0e0000 Scanning disk mmc(a)ff170000.blk... Found 4 disks Hit any key to stop autoboot: 0 ZynqMP> --- configs/xilinx_zynqmp_virt_defconfig | 9 +++++++++ include/configs/xilinx_zynqmp.h | 2 +- 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig index 89c1dae2a1d9..9c496098584f 100644 --- a/configs/xilinx_zynqmp_virt_defconfig +++ b/configs/xilinx_zynqmp_virt_defconfig @@ -86,7 +86,11 @@ CONFIG_SATA_CEVA=y CONFIG_CLK_ZYNQMP=y CONFIG_DFU_TFTP=y CONFIG_DFU_TIMEOUT=y +CONFIG_DFU_MMC=y +CONFIG_DFU_NAND=y CONFIG_DFU_RAM=y +CONFIG_DFU_SF=y +CONFIG_DFU_MTD=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_FLASH=y CONFIG_FASTBOOT_FLASH_MMC_DEV=0 @@ -178,3 +182,8 @@ CONFIG_TPM=y CONFIG_SPL_GZIP=y # CONFIG_SPL_HEXDUMP is not set CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y +CONFIG_EFI_CAPSULE_ON_DISK=y +CONFIG_EFI_CAPSULE_ON_DISK_EARLY=y +CONFIG_EFI_CAPSULE_FIRMWARE_FIT=y +CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index 36f3d962e417..986af2be7819 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -27,7 +27,7 @@ #endif /* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 0x2000000) +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 0x4000000) /* Serial setup */ #define CONFIG_CPU_ARMV8 -- 2.31.1

3 3

[PATCH] mtd: cfi: Fix PPB lock status readout
by Marek Vasut 29 Apr '21

29 Apr '21

According to S26KL512S datasheet [1] and S29GL01GS datasheet [2], the procedure to read out PPB lock bits is to send the PPB Entry, PPB Read, Reset/ASO Exit. Currently, the code does send incorrect PPB Entry, PPB Read and Reset/ASO Exit is completely missing. The PPB Entry sent is implemented by sending flash_unlock_seq() and flash_write_cmd(..., FLASH_CMD_READ_ID). This translates to sequence 0x555:0xaa, 0x2aa:0x55, 0x555:0x90=FLASH_CMD_READ_ID. However, both [1] and [2] specify the last byte of PPB Entry as 0xc0=AMD_CMD_SET_PPB_ENTRY instead of 0x90=FLASH_CMD_READ_ID, that is 0x555:0xaa, 0x2aa:0x55, 0x555:0xc0=AMD_CMD_SET_PPB_ENTRY. Since this does make sense, this patch fixes it and thus also aligns the code in flash_get_size() with flash_real_protect(). The PPB Read returns 00h in case of Protected state and 01h in case of Unprotected state, according to [1] Note 83 and [2] Note 17, so invert the result. Moreover, align the arguments with similar code in flash_real_protect(). Finally, Reset/ASO Exit command should be executed to exit the PPB mode, so add the missing reset. [1] https://www.cypress.com/file/213346/download Document Number: 001-99198 Rev. *M Table 40. Command Definitions, Nonvolatile Sector Protection Command Set Definitions [2] https://www.cypress.com/file/177976/download Document Number: 001-98285 Rev. *R Table 7.1 Command Definitions, Nonvolatile Sector Protection Command Set Definitions Fixes: 03deff433e ("cfi_flash: Read PPB sector protection from device for AMD/Spansion chips") Signed-off-by: Marek Vasut <marek.vasut+renesas(a)gmail.com> Cc: Stefan Roese <sr(a)denx.de> --- drivers/mtd/cfi_flash.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c index 9642d7c7dc..9c27fea5d8 100644 --- a/drivers/mtd/cfi_flash.c +++ b/drivers/mtd/cfi_flash.c @@ -2276,12 +2276,12 @@ ulong flash_get_size(phys_addr_t base, int banknum) flash_unlock_seq(info, 0); flash_write_cmd(info, 0, info->addr_unlock1, - FLASH_CMD_READ_ID); + AMD_CMD_SET_PPB_ENTRY); info->protect[sect_cnt] = - flash_isset( - info, sect_cnt, - FLASH_OFFSET_PROTECT, - FLASH_STATUS_PROTECT); + !flash_isset(info, sect_cnt, + 0, 0x01); + flash_write_cmd(info, 0, 0, + info->cmd_reset); break; default: /* default: not protected */ -- 2.30.2

3 3

[PATCH] net: phy: xilinx: Break while loop over ethernet phy
by Michal Simek 29 Apr '21

29 Apr '21

The commit 6c993815bbea ("net: phy: xilinx: Be compatible with live OF tree") change driver behavior to while loop which wasn't correct because the driver was looping over again and again. The reason was that ofnode_valid() is taking 0 as correct value. Fix it by changing while loop to ofnode_for_each_subnode() which is only loop over available nodes. Fixes: 6c993815bbea ("net: phy: xilinx: Be compatible with live OF tree") Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- drivers/net/phy/phy.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index dcdef9e661d6..ed197fa46d73 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -948,9 +948,9 @@ static struct phy_device *phy_connect_gmii2rgmii(struct mii_dev *bus, phy_interface_t interface) { struct phy_device *phydev = NULL; - ofnode node = dev_ofnode(dev); + ofnode node; - while (ofnode_valid(node)) { + ofnode_for_each_subnode(node, dev_ofnode(dev)) { node = ofnode_by_compatible(node, "xlnx,gmii-to-rgmii-1.0"); if (ofnode_valid(node)) { phydev = phy_device_create(bus, 0, -- 2.31.1

2 8

[PATCH] arm: a37xx: pci: Fix processing PIO transfers
by Pali Rohár 29 Apr '21

29 Apr '21

Trying to clear PIO_START register when it is non-zero (which indicates that previous PIO transfer has not finished yet) causes an External Abort with SError 0xbf000002. This bug is currently worked around in TF-A by handling External Aborts in EL3 and ignoring this particular SError. This workaround was also discussed at: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/commit/?id=3c7d… https://lore.kernel.org/linux-pci/20190316161243.29517-1-repk@triplefau.lt/ https://lore.kernel.org/linux-pci/971be151d24312cc533989a64bd454b4@www.loen… https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/1541 Implement a proper fix to prevent this External Abort. As it is not possible to cancel a pending PIO transfer, simply do not start a new one if previous has not finished yet. In this case return an error to the caller. In most cases this SError happens when there is no PCIe card connected or when PCIe link is down. The reason is that in these cases a PIO transfer takes about 1.44 seconds. For this reason we also increase the wait timeout in pcie_advk_wait_pio() to 1.5 seconds. If PIO read transfer for PCI_VENDOR_ID register times out, or if it isn't possible to read it yet because previous transfer is not finished, return Completion Retry Status value instead of failing, to give the caller a chance to send a new read request. Signed-off-by: Pali Rohár <pali(a)kernel.org> Reviewed-by: Marek Behún <marek.behun(a)nic.cz> --- drivers/pci/pci-aardvark.c | 42 +++++++++++++++++++++++++------------- 1 file changed, 28 insertions(+), 14 deletions(-) diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c index 3b9309f52c..c43d4f309b 100644 --- a/drivers/pci/pci-aardvark.c +++ b/drivers/pci/pci-aardvark.c @@ -132,8 +132,9 @@ PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where)) /* PCIe Retries & Timeout definitions */ -#define MAX_RETRIES 10 -#define PIO_WAIT_TIMEOUT 100 +#define PIO_MAX_RETRIES 1500 +#define PIO_WAIT_TIMEOUT 1000 +#define LINK_MAX_RETRIES 10 #define LINK_WAIT_TIMEOUT 100000 #define CFG_RD_UR_VAL 0xFFFFFFFF @@ -192,7 +193,7 @@ static int pcie_advk_addr_valid(pci_dev_t bdf, int first_busno) * * @pcie: The PCI device to access * - * Wait up to 1 micro second for PIO access to be accomplished. + * Wait up to 1.5 seconds for PIO access to be accomplished. * * Return 1 (true) if PIO access is accomplished. * Return 0 (false) if PIO access is timed out. @@ -202,7 +203,7 @@ static int pcie_advk_wait_pio(struct pcie_advk *pcie) uint start, isr; uint count; - for (count = 0; count < MAX_RETRIES; count++) { + for (count = 0; count < PIO_MAX_RETRIES; count++) { start = advk_readl(pcie, PIO_START); isr = advk_readl(pcie, PIO_ISR); if (!start && isr) @@ -214,7 +215,7 @@ static int pcie_advk_wait_pio(struct pcie_advk *pcie) udelay(PIO_WAIT_TIMEOUT); } - dev_err(pcie->dev, "config read/write timed out\n"); + dev_err(pcie->dev, "PIO read/write transfer time out\n"); return 0; } @@ -323,9 +324,14 @@ static int pcie_advk_read_config(const struct udevice *bus, pci_dev_t bdf, return 0; } - /* Start PIO */ - advk_writel(pcie, 0, PIO_START); - advk_writel(pcie, 1, PIO_ISR); + if (advk_readl(pcie, PIO_START)) { + dev_err(pcie->dev, + "Previous PIO read/write transfer is still running\n"); + if (offset != PCI_VENDOR_ID) + return -EINVAL; + *valuep = CFG_RD_CRS_VAL; + return 0; + } /* Program the control register */ reg = advk_readl(pcie, PIO_CTRL); @@ -342,10 +348,15 @@ static int pcie_advk_read_config(const struct udevice *bus, pci_dev_t bdf, advk_writel(pcie, 0, PIO_ADDR_MS); /* Start the transfer */ + advk_writel(pcie, 1, PIO_ISR); advk_writel(pcie, 1, PIO_START); - if (!pcie_advk_wait_pio(pcie)) - return -EINVAL; + if (!pcie_advk_wait_pio(pcie)) { + if (offset != PCI_VENDOR_ID) + return -EINVAL; + *valuep = CFG_RD_CRS_VAL; + return 0; + } /* Check PIO status and get the read result */ ret = pcie_advk_check_pio_status(pcie, true, &reg); @@ -420,9 +431,11 @@ static int pcie_advk_write_config(struct udevice *bus, pci_dev_t bdf, return 0; } - /* Start PIO */ - advk_writel(pcie, 0, PIO_START); - advk_writel(pcie, 1, PIO_ISR); + if (advk_readl(pcie, PIO_START)) { + dev_err(pcie->dev, + "Previous PIO read/write transfer is still running\n"); + return -EINVAL; + } /* Program the control register */ reg = advk_readl(pcie, PIO_CTRL); @@ -450,6 +463,7 @@ static int pcie_advk_write_config(struct udevice *bus, pci_dev_t bdf, dev_dbg(pcie->dev, "\tPIO req. - strb = 0x%02x\n", reg); /* Start the transfer */ + advk_writel(pcie, 1, PIO_ISR); advk_writel(pcie, 1, PIO_START); if (!pcie_advk_wait_pio(pcie)) { @@ -494,7 +508,7 @@ static int pcie_advk_wait_for_link(struct pcie_advk *pcie) int retries; /* check if the link is up or not */ - for (retries = 0; retries < MAX_RETRIES; retries++) { + for (retries = 0; retries < LINK_MAX_RETRIES; retries++) { if (pcie_advk_link_up(pcie)) { printf("PCIE-%d: Link up\n", pcie->first_busno); return 0; -- 2.26.3

2 2

[PATCH v2] power: regulator: Add support for regulator-force-boot-off
by Stefan Roese 29 Apr '21

29 Apr '21

From: Konstantin Porotchkin <kostap(a)marvell.com> Add support for regulator-force-boot-off DT property. This property can be used by the board/device drivers for turning off regulators on early init stages as pre-requisite for the other components initialization. Signed-off-by: Konstantin Porotchkin <kostap(a)marvell.com> Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Jaehoon Chung <jh80.chung(a)samsung.com> Cc: Simon Glass <sjg(a)chromium.org> --- v2: - Add check for uc_pdata in regulator_unset() drivers/power/regulator/regulator-uclass.c | 38 ++++++++++++++++++++++ include/power/regulator.h | 23 +++++++++++++ 2 files changed, 61 insertions(+) diff --git a/drivers/power/regulator/regulator-uclass.c b/drivers/power/regulator/regulator-uclass.c index 4d2e730271f9..fac960682331 100644 --- a/drivers/power/regulator/regulator-uclass.c +++ b/drivers/power/regulator/regulator-uclass.c @@ -311,6 +311,17 @@ int regulator_autoset(struct udevice *dev) return ret; } +int regulator_unset(struct udevice *dev) +{ + struct dm_regulator_uclass_plat *uc_pdata; + + uc_pdata = dev_get_uclass_plat(dev); + if (uc_pdata && uc_pdata->force_off) + return regulator_set_enable(dev, false); + + return -EMEDIUMTYPE; +} + static void regulator_show(struct udevice *dev, int ret) { struct dm_regulator_uclass_plat *uc_pdata; @@ -443,6 +454,7 @@ static int regulator_pre_probe(struct udevice *dev) uc_pdata->boot_on = dev_read_bool(dev, "regulator-boot-on"); uc_pdata->ramp_delay = dev_read_u32_default(dev, "regulator-ramp-delay", 0); + uc_pdata->force_off = dev_read_bool(dev, "regulator-force-boot-off"); node = dev_read_subnode(dev, "regulator-state-mem"); if (ofnode_valid(node)) { @@ -495,6 +507,32 @@ int regulators_enable_boot_on(bool verbose) return ret; } +int regulators_enable_boot_off(bool verbose) +{ + struct udevice *dev; + struct uclass *uc; + int ret; + + ret = uclass_get(UCLASS_REGULATOR, &uc); + if (ret) + return ret; + for (uclass_first_device(UCLASS_REGULATOR, &dev); + dev; + uclass_next_device(&dev)) { + ret = regulator_unset(dev); + if (ret == -EMEDIUMTYPE) { + ret = 0; + continue; + } + if (verbose) + regulator_show(dev, ret); + if (ret == -ENOSYS) + ret = 0; + } + + return ret; +} + UCLASS_DRIVER(regulator) = { .id = UCLASS_REGULATOR, .name = "regulator", diff --git a/include/power/regulator.h b/include/power/regulator.h index da9a065bdde0..fad87c99e5db 100644 --- a/include/power/regulator.h +++ b/include/power/regulator.h @@ -151,6 +151,7 @@ enum regulator_flag { * @max_uA* - maximum amperage (micro Amps) * @always_on* - bool type, true or false * @boot_on* - bool type, true or false + * @force_off* - bool type, true or false * TODO(sjg(a)chromium.org): Consider putting the above two into @flags * @ramp_delay - Time to settle down after voltage change (unit: uV/us) * @flags: - flags value (see REGULATOR_FLAG_...) @@ -176,6 +177,7 @@ struct dm_regulator_uclass_plat { unsigned int ramp_delay; bool always_on; bool boot_on; + bool force_off; const char *name; int flags; u8 ctrl_reg; @@ -420,6 +422,15 @@ int regulator_set_mode(struct udevice *dev, int mode_id); */ int regulators_enable_boot_on(bool verbose); +/** + * regulators_enable_boot_off() - disable regulators needed for boot + * + * This disables all regulators which are marked to be off at boot time. + * + * This effectively calls regulator_unset() for every regulator. + */ +int regulators_enable_boot_off(bool verbose); + /** * regulator_autoset: setup the voltage/current on a regulator * @@ -439,6 +450,18 @@ int regulators_enable_boot_on(bool verbose); */ int regulator_autoset(struct udevice *dev); +/** + * regulator_unset: turn off a regulator + * + * The setup depends on constraints found in device's uclass's platform data + * (struct dm_regulator_uclass_platdata): + * + * - Disable - will set - if 'force_off' is set to true, + * + * The function returns on the first-encountered error. + */ +int regulator_unset(struct udevice *dev); + /** * regulator_autoset_by_name: setup the regulator given by its uclass's * platform data name field. The setup depends on constraints found in device's -- 2.31.1

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[PATCH v1 0/6] arm: armada: Add Octeon TX2 CN9130 base support
by Stefan Roese 29 Apr '21

29 Apr '21

This patchset adds the base support for the Marvell Octeon TX2 CN9130 CRB. This includes the necessary restructuring of the dtsi files to support the AP807. Thanks, Stefan Konstantin Porotchkin (6): cmd/mvebu: fix the bubt command arm: armada: dts: Use a single dtsi for cp110 die description arm: armada: dts: Add support for ap807-based platforms arm: armada: configs: Move environment location for mvebu arm: octeontx2: Add dtsi/dts files for Octeon TX2 CN9130 CRB arm: octeontx2: Add Octeon TX2 CN9130 CRB support arch/arm/dts/Makefile | 4 +- arch/arm/dts/armada-7040-db-nand.dts | 73 +--- arch/arm/dts/armada-7040-db.dts | 81 ++-- arch/arm/dts/armada-7040.dtsi | 91 +++-- arch/arm/dts/armada-8020.dtsi | 56 --- arch/arm/dts/armada-8040-clearfog-gt-8k.dts | 72 ++-- arch/arm/dts/armada-8040-db.dts | 101 ++--- arch/arm/dts/armada-8040-mcbin.dts | 64 +-- arch/arm/dts/armada-8040-puzzle-m801.dts | 94 ++--- arch/arm/dts/armada-8040.dtsi | 116 ++++-- arch/arm/dts/armada-8k.dtsi | 18 + arch/arm/dts/armada-ap806-quad.dtsi | 82 ---- arch/arm/dts/armada-ap806.dtsi | 281 ++----------- arch/arm/dts/armada-ap807.dtsi | 40 ++ arch/arm/dts/armada-ap80x-quad.dtsi | 52 +++ arch/arm/dts/armada-ap80x.dtsi | 211 ++++++++++ arch/arm/dts/armada-common.dtsi | 30 ++ arch/arm/dts/armada-cp110-slave.dtsi | 368 ------------------ ...da-cp110-master.dtsi => armada-cp110.dtsi} | 282 ++++++-------- arch/arm/dts/cn9130-crb-A.dts | 57 +++ arch/arm/dts/cn9130-crb-B.dts | 61 +++ arch/arm/dts/cn9130-crb.dtsi | 253 ++++++++++++ arch/arm/dts/cn9130.dtsi | 73 ++++ arch/arm/mach-mvebu/Kconfig | 10 + board/Marvell/octeontx2_cn913x/MAINTAINERS | 6 + board/Marvell/octeontx2_cn913x/Makefile | 8 + board/Marvell/octeontx2_cn913x/board.c | 45 +++ cmd/mvebu/Kconfig | 2 +- cmd/mvebu/bubt.c | 2 +- configs/mvebu_crb_cn9130_defconfig | 84 ++++ configs/mvebu_db-88f3720_defconfig | 2 +- configs/mvebu_db_armada8k_defconfig | 2 +- 32 files changed, 1415 insertions(+), 1306 deletions(-) delete mode 100644 arch/arm/dts/armada-8020.dtsi create mode 100644 arch/arm/dts/armada-8k.dtsi delete mode 100644 arch/arm/dts/armada-ap806-quad.dtsi create mode 100644 arch/arm/dts/armada-ap807.dtsi create mode 100644 arch/arm/dts/armada-ap80x-quad.dtsi create mode 100644 arch/arm/dts/armada-ap80x.dtsi create mode 100644 arch/arm/dts/armada-common.dtsi delete mode 100644 arch/arm/dts/armada-cp110-slave.dtsi rename arch/arm/dts/{armada-cp110-master.dtsi => armada-cp110.dtsi} (55%) create mode 100644 arch/arm/dts/cn9130-crb-A.dts create mode 100644 arch/arm/dts/cn9130-crb-B.dts create mode 100644 arch/arm/dts/cn9130-crb.dtsi create mode 100644 arch/arm/dts/cn9130.dtsi create mode 100644 board/Marvell/octeontx2_cn913x/MAINTAINERS create mode 100644 board/Marvell/octeontx2_cn913x/Makefile create mode 100644 board/Marvell/octeontx2_cn913x/board.c create mode 100644 configs/mvebu_crb_cn9130_defconfig -- 2.31.1

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[PATCH 0/5] Revert "fdt: translate address if #size-cells = <0>"
by Dario Binacchi 29 Apr '21

29 Apr '21

As pointed by [1] and [2] the d64b9cdcd4 ("fdt: translate address if #size-cells = <0>") commit was wrong. The series reverts the patch and fixes the issue with platform code, adding custom routines to access the clocks registers. The solution has been inspired by the Linux Kernel code. [1] https://patchwork.ozlabs.org/project/uboot/patch/1614324949-61314-1-git-sen… [2] https://lore.kernel.org/linux-clk/20210402192054.7934-1-dariobin@libero.it/… Dario Binacchi (5): clk: ti: add custom API for memory access clk: ti: change clk_ti_latch() signature clk: ti: gate: use custom API for memory access clk: ti: am3-dpll: use custom API for memory access Revert "fdt: translate address if #size-cells = <0>" arch/sandbox/dts/test.dts | 21 ------ common/fdt_support.c | 6 +- drivers/clk/ti/clk-am3-dpll.c | 86 +++++++++++++++---------- drivers/clk/ti/clk-divider.c | 20 +++--- drivers/clk/ti/clk-gate.c | 23 +++---- drivers/clk/ti/clk-mux.c | 20 +++--- drivers/clk/ti/clk.c | 102 ++++++++++++++++++++++++++++-- drivers/clk/ti/clk.h | 15 ++++- drivers/core/Kconfig | 12 ---- drivers/core/fdtaddr.c | 2 +- drivers/core/of_addr.c | 13 +++- drivers/core/ofnode.c | 7 +- drivers/core/root.c | 3 - include/asm-generic/global_data.h | 24 ------- test/dm/test-fdt.c | 68 -------------------- 15 files changed, 213 insertions(+), 209 deletions(-) -- 2.17.1

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[PATCH] sunxi: H616: Enable full 4GB of DRAM
by Andre Przywara 29 Apr '21

29 Apr '21

The H616 is our first supported Allwinner SoC which goes beyond the 4GB address space "barrier", by having more than 32 address bits. Lift the preliminary 3GB DRAM limit for the H616, and update the page table setup on the way, to actually map that last GB as well. This will presumably break the EMAC, as the DMA descriptors only hold 32 bits worth of addresses, but this is no problem for now, as all boards with 4GB of DRAM cannot use the EMAC at the moment (missing PHY support). Signed-off-by: Andre Przywara <andre.przywara(a)arm.com> --- arch/arm/mach-sunxi/Kconfig | 4 ++-- arch/arm/mach-sunxi/board.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index b6463bca71d..4d71030e655 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -192,10 +192,10 @@ config MACH_SUNXI_H3_H5 select SUPPORT_SPL # TODO: try out A80's 8GiB DRAM space -# TODO: H616 supports 4 GiB DRAM space config SUNXI_DRAM_MAX_SIZE hex - default 0xC0000000 if MACH_SUN50I || MACH_SUN50I_H5 || MACH_SUN50I_H6 || MACH_SUN50I_H616 + default 0x100000000 if MACH_SUN50I_H616 + default 0xC0000000 if MACH_SUN50I || MACH_SUN50I_H5 || MACH_SUN50I_H6 default 0x80000000 choice diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c index 8cbd926f51d..edcfaee187e 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -56,7 +56,7 @@ static struct mm_region sunxi_mem_map[] = { /* RAM */ .virt = 0x40000000UL, .phys = 0x40000000UL, - .size = 0xC0000000UL, + .size = CONFIG_SUNXI_DRAM_MAX_SIZE, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE }, { -- 2.17.5

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