March 2021 - U-Boot

[RFC PATCH 1/3] net: phy: Add a generic phy file for TI generic PHYs
by Dan Murphy 27 Apr '21

27 Apr '21

Add a TI Generic init file that will initialize TI PHYs that follow that not require special handling. These PHYs can connect with the standard MII register set. This generice file will register the PHY IDs and names of the PHYs so when the command 'mdio list' is executed the PHY name will display as opposed to 'Generic PHY'. The DP8382X PHY series is a generic PHY that requires the generic registration. The DP83867 driver was updated to rename the init to a more PHY specific init call. Signed-off-by: Dan Murphy <dmurphy(a)ti.com> --- configs/am65x_evm_a53_defconfig | 2 +- configs/am65x_hs_evm_a53_defconfig | 2 +- configs/dra7xx_evm_defconfig | 2 +- configs/dra7xx_hs_evm_defconfig | 2 +- configs/dra7xx_hs_evm_usb_defconfig | 2 +- configs/j721e_evm_a72_defconfig | 2 +- configs/j721e_hs_evm_a72_defconfig | 2 +- configs/k2g_evm_defconfig | 2 +- configs/xilinx_versal_virt_defconfig | 2 +- configs/xilinx_zynqmp_virt_defconfig | 2 +- drivers/net/phy/Kconfig | 8 ++ drivers/net/phy/Makefile | 3 +- drivers/net/phy/dp83867.c | 3 +- drivers/net/phy/ti_phy_init.c | 106 +++++++++++++++++++++++++++ drivers/net/phy/ti_phy_init.h | 16 ++++ 15 files changed, 144 insertions(+), 12 deletions(-) create mode 100644 drivers/net/phy/ti_phy_init.c create mode 100644 drivers/net/phy/ti_phy_init.h diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig index 542bbd992c53..7051d6c40505 100644 --- a/configs/am65x_evm_a53_defconfig +++ b/configs/am65x_evm_a53_defconfig @@ -101,7 +101,7 @@ CONFIG_SPI_FLASH_SFDP_SUPPORT CONFIG_SPI_FLASH_STMICRO=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_SPI_FLASH_MTD=y -CONFIG_PHY_TI=y +CONFIG_PHY_DP83867=y CONFIG_PHY_FIXED=y CONFIG_DM_ETH=y CONFIG_E1000=y diff --git a/configs/am65x_hs_evm_a53_defconfig b/configs/am65x_hs_evm_a53_defconfig index 9f43cee39611..29da3826f12a 100644 --- a/configs/am65x_hs_evm_a53_defconfig +++ b/configs/am65x_hs_evm_a53_defconfig @@ -103,7 +103,7 @@ CONFIG_SPI_FLASH_SFDP_SUPPORT CONFIG_SPI_FLASH_STMICRO=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_SPI_FLASH_MTD=y -CONFIG_PHY_TI=y +CONFIG_PHY_DP83867=y CONFIG_PHY_FIXED=y CONFIG_DM_ETH=y CONFIG_E1000=y diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig index 4d765da4e052..19c024889155 100644 --- a/configs/dra7xx_evm_defconfig +++ b/configs/dra7xx_evm_defconfig @@ -86,7 +86,7 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=76800000 CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_TI=y +CONFIG_PHY_DP83867=y CONFIG_DM_ETH=y CONFIG_PHY_GIGE=y CONFIG_MII=y diff --git a/configs/dra7xx_hs_evm_defconfig b/configs/dra7xx_hs_evm_defconfig index c25d4ce5c142..e97f1a3ba338 100644 --- a/configs/dra7xx_hs_evm_defconfig +++ b/configs/dra7xx_hs_evm_defconfig @@ -89,7 +89,7 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=76800000 CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_TI=y +CONFIG_PHY_DP83867=y CONFIG_DM_ETH=y CONFIG_PHY_GIGE=y CONFIG_MII=y diff --git a/configs/dra7xx_hs_evm_usb_defconfig b/configs/dra7xx_hs_evm_usb_defconfig index 8e74496b2ccd..46970e31f02e 100644 --- a/configs/dra7xx_hs_evm_usb_defconfig +++ b/configs/dra7xx_hs_evm_usb_defconfig @@ -87,7 +87,7 @@ CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=76800000 CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_TI=y +CONFIG_PHY_DP83867=y CONFIG_DM_ETH=y CONFIG_PHY_GIGE=y CONFIG_MII=y diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig index e9e82bb4309d..784a6ff396c3 100644 --- a/configs/j721e_evm_a72_defconfig +++ b/configs/j721e_evm_a72_defconfig @@ -124,7 +124,7 @@ CONFIG_SPI_FLASH_SFDP_SUPPORT CONFIG_SPI_FLASH_STMICRO=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_SPI_FLASH_MTD=y -CONFIG_PHY_TI=y +CONFIG_PHY_DP83867=y CONFIG_PHY_FIXED=y CONFIG_DM_ETH=y CONFIG_TI_AM65_CPSW_NUSS=y diff --git a/configs/j721e_hs_evm_a72_defconfig b/configs/j721e_hs_evm_a72_defconfig index a723e2718e5e..dd93a955cefd 100644 --- a/configs/j721e_hs_evm_a72_defconfig +++ b/configs/j721e_hs_evm_a72_defconfig @@ -114,7 +114,7 @@ CONFIG_SPI_FLASH_SFDP_SUPPORT CONFIG_SPI_FLASH_STMICRO=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_SPI_FLASH_MTD=y -CONFIG_PHY_TI=y +CONFIG_PHY_DP83867=y CONFIG_PHY_FIXED=y CONFIG_DM_ETH=y CONFIG_TI_AM65_CPSW_NUSS=y diff --git a/configs/k2g_evm_defconfig b/configs/k2g_evm_defconfig index 5abf5faa450e..f47b1cabe9a8 100644 --- a/configs/k2g_evm_defconfig +++ b/configs/k2g_evm_defconfig @@ -58,7 +58,7 @@ CONFIG_PHYLIB=y CONFIG_PHY_MARVELL=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ8XXX=y -CONFIG_PHY_TI=y +CONFIG_PHY_DP83867=y CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_DRIVER_TI_KEYSTONE_NET=y diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig index e8c349261207..eb2a26bc2c7d 100644 --- a/configs/xilinx_versal_virt_defconfig +++ b/configs/xilinx_versal_virt_defconfig @@ -61,7 +61,7 @@ CONFIG_SPI_FLASH_WINBOND=y CONFIG_PHY_MARVELL=y CONFIG_PHY_NATSEMI=y CONFIG_PHY_REALTEK=y -CONFIG_PHY_TI=y +CONFIG_PHY_DP83867=y CONFIG_PHY_VITESSE=y CONFIG_PHY_FIXED=y CONFIG_PHY_GIGE=y diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig index 7b09edd78e1b..5c320f93fe5f 100644 --- a/configs/xilinx_zynqmp_virt_defconfig +++ b/configs/xilinx_zynqmp_virt_defconfig @@ -101,7 +101,7 @@ CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_PHY_NATSEMI=y CONFIG_PHY_REALTEK=y -CONFIG_PHY_TI=y +CONFIG_PHY_DP83867=y CONFIG_PHY_VITESSE=y CONFIG_PHY_XILINX_GMII2RGMII=y CONFIG_PHY_FIXED=y diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index d1f049e62ab7..e366f10afc59 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -244,6 +244,14 @@ config PHY_TERANETICS config PHY_TI bool "Texas Instruments Ethernet PHYs support" +config PHY_TI_GENERIC + select PHY_TI + bool "Texas Instruments Ethernet PHYs support" + +config PHY_DP83867 + select PHY_TI + bool "Texas Instruments Ethernet DP83867 PHY support" + config PHY_VITESSE bool "Vitesse Ethernet PHYs support" diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile index 1d81516ecd1d..9c6d31718c00 100644 --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile @@ -25,7 +25,8 @@ obj-$(CONFIG_PHY_NATSEMI) += natsemi.o obj-$(CONFIG_PHY_REALTEK) += realtek.o obj-$(CONFIG_PHY_SMSC) += smsc.o obj-$(CONFIG_PHY_TERANETICS) += teranetics.o -obj-$(CONFIG_PHY_TI) += dp83867.o +obj-$(CONFIG_PHY_TI) += ti_phy_init.o +obj-$(CONFIG_PHY_DP83867) += dp83867.o obj-$(CONFIG_PHY_XILINX) += xilinx_phy.o obj-$(CONFIG_PHY_XILINX_GMII2RGMII) += xilinx_gmii2rgmii.o obj-$(CONFIG_PHY_VITESSE) += vitesse.o diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c index 50804c130efd..c9ed4a44d4db 100644 --- a/drivers/net/phy/dp83867.c +++ b/drivers/net/phy/dp83867.c @@ -12,6 +12,7 @@ #include <dm.h> #include <dt-bindings/net/ti-dp83867.h> +#include "ti_phy_init.h" /* TI DP83867 */ #define DP83867_DEVADDR 0x1f @@ -428,7 +429,7 @@ static struct phy_driver DP83867_driver = { .shutdown = &genphy_shutdown, }; -int phy_ti_init(void) +int phy_dp83867_init(void) { phy_register(&DP83867_driver); return 0; diff --git a/drivers/net/phy/ti_phy_init.c b/drivers/net/phy/ti_phy_init.c new file mode 100644 index 000000000000..11c4c166b2f5 --- /dev/null +++ b/drivers/net/phy/ti_phy_init.c @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * TI Generic PHY Init to register all TI Ethernet PHYs + * + * Author: Dan Murphy <dmurphy(a)ti.com> + * + * Copyright (C) 2019 Texas Instruments Inc. + */ + +#include <phy.h> + +#define DP83822_PHY_ID 0x2000a240 +#define DP83825S_PHY_ID 0x2000a140 +#define DP83825I_PHY_ID 0x2000a150 +#define DP83825CM_PHY_ID 0x2000a160 +#define DP83825CS_PHY_ID 0x2000a170 +#define DP83826C_PHY_ID 0x2000a130 +#define DP83826NC_PHY_ID 0x2000a110 + +static struct phy_driver dp83822_driver = { + .name = "TI DP83822", + .uid = DP83822_PHY_ID, + .mask = 0xfffffff0, + .features = PHY_BASIC_FEATURES, + .config = &genphy_config_aneg, + .startup = &genphy_startup, + .shutdown = &genphy_shutdown, +}; + +static struct phy_driver dp83825s_driver = { + .name = "TI DP83825S", + .uid = DP83825S_PHY_ID, + .mask = 0xfffffff0, + .features = PHY_BASIC_FEATURES, + .config = &genphy_config_aneg, + .startup = &genphy_startup, + .shutdown = &genphy_shutdown, +}; + +static struct phy_driver dp83825i_driver = { + .name = "TI DP83825I", + .uid = DP83825I_PHY_ID, + .mask = 0xfffffff0, + .features = PHY_BASIC_FEATURES, + .config = &genphy_config_aneg, + .startup = &genphy_startup, + .shutdown = &genphy_shutdown, +}; + +static struct phy_driver dp83825m_driver = { + .name = "TI DP83825M", + .uid = DP83825CM_PHY_ID, + .mask = 0xfffffff0, + .features = PHY_BASIC_FEATURES, + .config = &genphy_config_aneg, + .startup = &genphy_startup, + .shutdown = &genphy_shutdown, +}; + +static struct phy_driver dp83825cs_driver = { + .name = "TI DP83825CS", + .uid = DP83825CS_PHY_ID, + .mask = 0xfffffff0, + .features = PHY_BASIC_FEATURES, + .config = &genphy_config_aneg, + .startup = &genphy_startup, + .shutdown = &genphy_shutdown, +}; + +static struct phy_driver dp83826c_driver = { + .name = "TI DP83826C", + .uid = DP83826C_PHY_ID, + .mask = 0xfffffff0, + .features = PHY_BASIC_FEATURES, + .config = &genphy_config_aneg, + .startup = &genphy_startup, + .shutdown = &genphy_shutdown, +}; +static struct phy_driver dp83826nc_driver = { + .name = "TI DP83826NC", + .uid = DP83826NC_PHY_ID, + .mask = 0xfffffff0, + .features = PHY_BASIC_FEATURES, + .config = &genphy_config_aneg, + .startup = &genphy_startup, + .shutdown = &genphy_shutdown, +}; + +int phy_ti_init(void) +{ +#ifdef CONFIG_PHY_DP83867 + phy_dp83867_init(); +#endif + +#ifdef CONFIG_PHY_TI_GENERIC + phy_register(&dp83822_driver); + phy_register(&dp83825s_driver); + phy_register(&dp83825i_driver); + phy_register(&dp83825m_driver); + phy_register(&dp83825cs_driver); + phy_register(&dp83826c_driver); + phy_register(&dp83826nc_driver); +#endif + + return 0; +} diff --git a/drivers/net/phy/ti_phy_init.h b/drivers/net/phy/ti_phy_init.h new file mode 100644 index 000000000000..309da2aacccb --- /dev/null +++ b/drivers/net/phy/ti_phy_init.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * TI Generic Ethernet PHY + * Based on code in sungem_phy.c and (long-removed) gianfar_phy.c + * + * Author: Dan Murphy <dmurphy(a)ti.com> + * + * Copyright (C) 2019 Texas Instruments Inc. + */ + +#ifndef _TI_GEN_PHY_H +#define _TI_GEN_PHY_H + +int phy_dp83867_init(void); + +#endif /* _TI_GEN_PHY_H */ -- 2.25.1

4 14

[PATCH v1 00/50] mips: octeon: Add serdes and device helper support incl. DM PCIe driver
by Stefan Roese 25 Apr '21

25 Apr '21

This patchset adds the serdes and (mostly networking) device helper macros and functions, needed to support the still missing Octeon II / III devices in mainline U-Boot. Please excuse the massive amount of files in this patch series. Also the sometimes huge files (mostly headers with register definitions) that I needed to include. The infrastructure code with all the headers is ported without any intended functional changes from the 2013 Cavium / Marvell U-Boot version. It has undergone many hours of extensive code cleanup and reformatting. Some of it done by using tools (checkpatch, Lindent, clang format etc) and also some of it done manually, as I couldn't find some tools that could do the needed work in a reliable and functional way. The result is that checkpatch now only throws a "few" warnings that are left. Some of those can't be removed without an even more extensive cleanup / rewrite of the code, like the addition of typedefs. The added headers and helper functions will be used by the upcoming support for the Octeon II / III networking drivers, including PHY & switch support. It was not easily possible to split these infrastructure files into a separate patchset, as it is heavily interconnected in the common QLM/DLM serdes interface initialization. The result is, that the upcoming ethernet driver support will be much smaller (this is at least my current assumption). The added PCIe RC support with the included DM PCIe driver is the first driver making use of this Octeon serdes infrastructure. This has been tested with an Intel E1000 PCIe network card in the Octeon 7304 EBB. Thanks, Stefan Aaron Williams (42): mips: octeon: Add misc cvmx-helper header files mips: octeon: Add cvmx-agl-defs.h header file mips: octeon: Add cvmx-asxx-defs.h header file mips: octeon: Add cvmx-bgxx-defs.h header file mips: octeon: Add cvmx-ciu-defs.h header file mips: octeon: Add cvmx-dbg-defs.h header file mips: octeon: Add cvmx-dpi-defs.h header file mips: octeon: Add cvmx-dtx-defs.h header file mips: octeon: Add cvmx-fpa-defs.h header file mips: octeon: Add cvmx-gmxx-defs.h header file mips: octeon: Add cvmx-gserx-defs.h header file mips: octeon: Add cvmx-ipd-defs.h header file mips: octeon: Add cvmx-l2c-defs.h header file mips: octeon: Add cvmx-mio-defs.h header file mips: octeon: Add cvmx-npi-defs.h header file mips: octeon: Add cvmx-pcieepx-defs.h header file mips: octeon: Add cvmx-pciercx-defs.h header file mips: octeon: Add cvmx-pcsx-defs.h header file mips: octeon: Add cvmx-pemx-defs.h header file mips: octeon: Add cvmx-pepx-defs.h header file mips: octeon: Add cvmx-pip-defs.h header file mips: octeon: Add cvmx-pki-defs.h header file mips: octeon: Add cvmx-pko-defs.h header file mips: octeon: Add cvmx-pow-defs.h header file mips: octeon: Add cvmx-rst-defs.h header file mips: octeon: Add cvmx-sata-defs.h header file mips: octeon: Add cvmx-sli-defs.h header file mips: octeon: Add cvmx-smix-defs.h header file mips: octeon: Add cvmx-sriomaintx-defs.h header file mips: octeon: Add cvmx-sriox-defs.h header file mips: octeon: Add cvmx-sso-defs.h header file mips: octeon: Add misc remaining header files mips: octeon: Add cvmx-helper-cfg.c mips: octeon: Add cvmx-helper-fdt.c mips: octeon: Add cvmx-helper-jtag.c mips: octeon: Add cvmx-helper-util.c mips: octeon: Add cvmx-helper.c mips: octeon: Add cvmx-pcie.c mips: octeon: Add cvmx-qlm.c mips: octeon: Add octeon_fdt.c mips: octeon: Add octeon_qlm.c mips: octeon: octeon_ebb7304: Add board specific QLM init code Stefan Roese (8): mips: global_data.h: Add Octeon specific data to arch_global_data struct mips: octeon: Misc changes required because of the newly added headers mips: octeon: Move cvmx-lmcx-defs.h from mach/cvmx to mach mips: octeon: Makefile: Enable building of the newly added C files mips: octeon: Kconfig: Enable CONFIG_SYS_PCI_64BIT mips: octeon: mrvl,cn73xx.dtsi: Add PCIe controller DT node mips: octeon: Add Octeon PCIe host controller driver mips: octeon: octeon_ebb7304_defconfig: Enable Octeon PCIe and E1000 arch/mips/dts/mrvl,cn73xx.dtsi | 16 + arch/mips/include/asm/global_data.h | 9 + arch/mips/mach-octeon/Kconfig | 4 + arch/mips/mach-octeon/Makefile | 11 + arch/mips/mach-octeon/bootoctlinux.c | 1 + arch/mips/mach-octeon/cvmx-bootmem.c | 6 - arch/mips/mach-octeon/cvmx-coremask.c | 1 + arch/mips/mach-octeon/cvmx-helper-cfg.c | 1914 ++++ arch/mips/mach-octeon/cvmx-helper-fdt.c | 970 ++ arch/mips/mach-octeon/cvmx-helper-jtag.c | 172 + arch/mips/mach-octeon/cvmx-helper-util.c | 1225 +++ arch/mips/mach-octeon/cvmx-helper.c | 2611 +++++ arch/mips/mach-octeon/cvmx-pcie.c | 2487 +++++ arch/mips/mach-octeon/cvmx-qlm.c | 2350 +++++ .../mach-octeon/include/mach/cvmx-address.h | 209 + .../mach-octeon/include/mach/cvmx-agl-defs.h | 3135 ++++++ .../mach-octeon/include/mach/cvmx-asxx-defs.h | 709 ++ .../mach-octeon/include/mach/cvmx-bgxx-defs.h | 4106 +++++++ .../mach-octeon/include/mach/cvmx-ciu-defs.h | 7351 +++++++++++++ .../mach-octeon/include/mach/cvmx-cmd-queue.h | 441 + .../mach-octeon/include/mach/cvmx-csr-enums.h | 87 + arch/mips/mach-octeon/include/mach/cvmx-csr.h | 78 + .../mach-octeon/include/mach/cvmx-dbg-defs.h | 33 + .../mach-octeon/include/mach/cvmx-dpi-defs.h | 1460 +++ .../mach-octeon/include/mach/cvmx-dtx-defs.h | 6962 ++++++++++++ .../mach-octeon/include/mach/cvmx-error.h | 456 + .../mach-octeon/include/mach/cvmx-fpa-defs.h | 1866 ++++ arch/mips/mach-octeon/include/mach/cvmx-fpa.h | 217 + .../mips/mach-octeon/include/mach/cvmx-fpa1.h | 196 + .../mips/mach-octeon/include/mach/cvmx-fpa3.h | 566 + .../include/mach/cvmx-global-resources.h | 213 + arch/mips/mach-octeon/include/mach/cvmx-gmx.h | 16 + .../mach-octeon/include/mach/cvmx-gmxx-defs.h | 6378 +++++++++++ .../include/mach/cvmx-gserx-defs.h | 2191 ++++ .../include/mach/cvmx-helper-agl.h | 68 + .../include/mach/cvmx-helper-bgx.h | 335 + .../include/mach/cvmx-helper-board.h | 558 + .../include/mach/cvmx-helper-cfg.h | 884 ++ .../include/mach/cvmx-helper-errata.h | 50 + .../include/mach/cvmx-helper-fdt.h | 568 + .../include/mach/cvmx-helper-fpa.h | 43 + .../include/mach/cvmx-helper-gpio.h | 427 + .../include/mach/cvmx-helper-ilk.h | 93 + .../include/mach/cvmx-helper-ipd.h | 16 + .../include/mach/cvmx-helper-jtag.h | 84 + .../include/mach/cvmx-helper-loop.h | 37 + .../include/mach/cvmx-helper-npi.h | 42 + .../include/mach/cvmx-helper-pki.h | 319 + .../include/mach/cvmx-helper-pko.h | 51 + .../include/mach/cvmx-helper-pko3.h | 76 + .../include/mach/cvmx-helper-rgmii.h | 99 + .../include/mach/cvmx-helper-sfp.h | 437 + .../include/mach/cvmx-helper-sgmii.h | 81 + .../include/mach/cvmx-helper-spi.h | 73 + .../include/mach/cvmx-helper-srio.h | 72 + .../include/mach/cvmx-helper-util.h | 412 + .../include/mach/cvmx-helper-xaui.h | 108 + .../mach-octeon/include/mach/cvmx-helper.h | 565 + .../mach-octeon/include/mach/cvmx-hwfau.h | 606 ++ .../mach-octeon/include/mach/cvmx-hwpko.h | 570 + arch/mips/mach-octeon/include/mach/cvmx-ilk.h | 154 + .../mach-octeon/include/mach/cvmx-ipd-defs.h | 1925 ++++ arch/mips/mach-octeon/include/mach/cvmx-ipd.h | 233 + .../mach-octeon/include/mach/cvmx-l2c-defs.h | 172 + .../include/mach/{cvmx => }/cvmx-lmcx-defs.h | 0 .../mach-octeon/include/mach/cvmx-mio-defs.h | 353 + .../mach-octeon/include/mach/cvmx-npi-defs.h | 1953 ++++ .../mach-octeon/include/mach/cvmx-packet.h | 40 + .../mips/mach-octeon/include/mach/cvmx-pcie.h | 279 + .../include/mach/cvmx-pcieepx-defs.h | 6848 ++++++++++++ .../include/mach/cvmx-pciercx-defs.h | 5586 ++++++++++ .../mach-octeon/include/mach/cvmx-pcsx-defs.h | 1005 ++ .../mach-octeon/include/mach/cvmx-pemx-defs.h | 2028 ++++ .../mach-octeon/include/mach/cvmx-pexp-defs.h | 1382 +++ .../mach-octeon/include/mach/cvmx-pip-defs.h | 3040 ++++++ arch/mips/mach-octeon/include/mach/cvmx-pip.h | 1080 ++ .../mach-octeon/include/mach/cvmx-pki-defs.h | 2353 +++++ .../include/mach/cvmx-pki-resources.h | 157 + arch/mips/mach-octeon/include/mach/cvmx-pki.h | 970 ++ .../mach-octeon/include/mach/cvmx-pko-defs.h | 9388 +++++++++++++++++ .../mach/cvmx-pko-internal-ports-range.h | 43 + .../include/mach/cvmx-pko3-queue.h | 175 + .../mach-octeon/include/mach/cvmx-pow-defs.h | 1135 ++ arch/mips/mach-octeon/include/mach/cvmx-pow.h | 2991 ++++++ arch/mips/mach-octeon/include/mach/cvmx-qlm.h | 304 + .../mips/mach-octeon/include/mach/cvmx-regs.h | 330 +- .../mach-octeon/include/mach/cvmx-rst-defs.h | 77 + .../mach-octeon/include/mach/cvmx-sata-defs.h | 311 + .../mach-octeon/include/mach/cvmx-scratch.h | 113 + .../mach-octeon/include/mach/cvmx-sli-defs.h | 6548 ++++++++++++ .../mach-octeon/include/mach/cvmx-smix-defs.h | 360 + .../include/mach/cvmx-sriomaintx-defs.h | 61 + .../include/mach/cvmx-sriox-defs.h | 44 + .../mach-octeon/include/mach/cvmx-sso-defs.h | 2904 +++++ arch/mips/mach-octeon/include/mach/cvmx-wqe.h | 1462 +++ .../mach-octeon/include/mach/octeon-feature.h | 2 + .../mach-octeon/include/mach/octeon-model.h | 2 + .../mach-octeon/include/mach/octeon_ddr.h | 189 +- arch/mips/mach-octeon/octeon_fdt.c | 1040 ++ arch/mips/mach-octeon/octeon_qlm.c | 5853 ++++++++++ board/Marvell/octeon_ebb7304/board.c | 732 +- configs/octeon_ebb7304_defconfig | 5 +- drivers/pci/Kconfig | 6 + drivers/pci/Makefile | 1 + drivers/pci/pcie_octeon.c | 159 + drivers/ram/octeon/octeon3_lmc.c | 28 +- drivers/ram/octeon/octeon_ddr.c | 22 +- 107 files changed, 118724 insertions(+), 240 deletions(-) create mode 100644 arch/mips/mach-octeon/cvmx-helper-cfg.c create mode 100644 arch/mips/mach-octeon/cvmx-helper-fdt.c create mode 100644 arch/mips/mach-octeon/cvmx-helper-jtag.c create mode 100644 arch/mips/mach-octeon/cvmx-helper-util.c create mode 100644 arch/mips/mach-octeon/cvmx-helper.c create mode 100644 arch/mips/mach-octeon/cvmx-pcie.c create mode 100644 arch/mips/mach-octeon/cvmx-qlm.c create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-address.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-agl-defs.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-asxx-defs.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-bgxx-defs.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-ciu-defs.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-cmd-queue.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-csr-enums.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-csr.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-dbg-defs.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-dpi-defs.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-dtx-defs.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-error.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-fpa-defs.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-fpa.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-fpa1.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-fpa3.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-global-resources.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-gmx.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-gmxx-defs.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-gserx-defs.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-helper-agl.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-helper-bgx.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-helper-board.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-helper-cfg.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-helper-errata.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-helper-fdt.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-helper-fpa.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-helper-gpio.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-helper-ilk.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-helper-ipd.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-helper-jtag.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-helper-loop.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-helper-npi.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-helper-pki.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-helper-pko.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-helper-pko3.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-helper-rgmii.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-helper-sfp.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-helper-sgmii.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-helper-spi.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-helper-srio.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-helper-util.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-helper-xaui.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-helper.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-hwfau.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-hwpko.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-ilk.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-ipd-defs.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-ipd.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-l2c-defs.h rename arch/mips/mach-octeon/include/mach/{cvmx => }/cvmx-lmcx-defs.h (100%) create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-mio-defs.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-npi-defs.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-packet.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-pcie.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-pcieepx-defs.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-pciercx-defs.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-pcsx-defs.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-pemx-defs.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-pexp-defs.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-pip-defs.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-pip.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-pki-defs.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-pki-resources.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-pki.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-pko-defs.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-pko-internal-ports-range.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-pko3-queue.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-pow-defs.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-pow.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-qlm.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-rst-defs.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-sata-defs.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-scratch.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-sli-defs.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-smix-defs.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-sriomaintx-defs.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-sriox-defs.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-sso-defs.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-wqe.h create mode 100644 arch/mips/mach-octeon/octeon_fdt.c create mode 100644 arch/mips/mach-octeon/octeon_qlm.c create mode 100644 drivers/pci/pcie_octeon.c -- 2.29.2

2 56

[PATCH v2 0/6] Enable ECDSA FIT verification for stm32mp
by Alexandru Gagniuc 24 Apr '21

24 Apr '21

This series is Part II of the ECDSA saga. It applies on top of [1]: * [PATCH v6 00/11] Add support for ECDSA image signing I've designed the UCLASS_ECDSA such that it aligns with the ROM API of the stm32mp. Instead of splitting the verification into (1) curve operations and (2) modular exponentiation, I've concatenated everything in a 'verify' step. It would be impossible to split the steps and use the stm32mp ROM for verification. Should more granular control be required, this API could be extended at a later time. Until we have more hardware supporting ECDSA, this is purely speculative. The ROM API of the stm32mp is passed in 'r0' when the FSBL is called. While we can save 'r0' in SPL, this series does not implement a mechanism to pass this to u-boot. Thus the ROM API, and ECDSA verification are only available for SPL. Although possible, extending this to u-boot by adding the ROM address to the FDT blob, implementing and verifying this is beyond the scope of this series. Changes since v1: - Add test to make sure the UCLASS is enabled - Fix check against wrong sig_len in ecdsa_romapi.c - s/U_BOOT_DEVICE/U_BOOT_DRVINFO/ - Use "if(!ret)" instead of "if (ret == 0)" - Use uclass_first_device_err() instead of uclass_first_device() - Make sure #includes are correctly alphabetized Alexandru Gagniuc (6): dm: crypto: Define UCLASS API for ECDSA signature verification lib: ecdsa: Add skeleton to implement ecdsa verification in u-boot lib: ecdsa: Implement signature verification for crypto_algo API arm: stm32mp1: Implement ECDSA signature verification Kconfig: FIT_SIGNATURE should not select RSA_VERIFY test: dm: Add test for ECDSA UCLASS support arch/arm/mach-stm32mp/Kconfig | 10 ++- arch/arm/mach-stm32mp/Makefile | 1 + arch/arm/mach-stm32mp/ecdsa_romapi.c | 106 ++++++++++++++++++++++ common/Kconfig.boot | 8 +- configs/sandbox_defconfig | 2 + include/crypto/ecdsa-uclass.h | 39 ++++++++ include/dm/uclass-id.h | 1 + include/image.h | 10 +-- include/u-boot/rsa.h | 2 +- lib/Kconfig | 1 + lib/Makefile | 1 + lib/ecdsa/Kconfig | 23 +++++ lib/ecdsa/Makefile | 1 + lib/ecdsa/ecdsa-verify.c | 128 +++++++++++++++++++++++++++ test/dm/Makefile | 1 + test/dm/ecdsa.c | 38 ++++++++ 16 files changed, 361 insertions(+), 11 deletions(-) create mode 100644 arch/arm/mach-stm32mp/ecdsa_romapi.c create mode 100644 include/crypto/ecdsa-uclass.h create mode 100644 lib/ecdsa/Kconfig create mode 100644 lib/ecdsa/Makefile create mode 100644 lib/ecdsa/ecdsa-verify.c create mode 100644 test/dm/ecdsa.c -- 2.26.2

6 18

[PATCH v2 0/8] lmb: Add config for the number of memory and reserved regions
by Patrick Delaunay 23 Apr '21

23 Apr '21

Hi, It is the V2 of [1] I propose a update of the lmb library to allow the configuration with Kconfig of the number of memory regions and of reserved regions in lmb library with: - CONFIG_LMB_RESERVED_REGIONS - CONFIG_LMB_MEMORY_REGIONS This serie avoids issue on stm32mp15 platform, as the kernel device tree defines many and non contiguous reserved regions. It is based on latest memblock library in kernel (it was a preliminary step for dynamic allocation of regions array to avoid any static limitation). PS: in patch 1, I manage CONFIG_LMB dependency in lib/Kconfig file, with default y depends on ... but it can do also in each arch by an imply or a select as it is done in [2]. I am not sure what is the best solution for this dependency. In this V2 series, I keep the default value of 8 regions defined in struct lmb_region with: - CONFIG_LMB_USE_MAX_REGIONS = n - CONFIG_LMB_MAX_REGIONS = 8 When the array is located in struct lmb_region (with CONFIG_LMB_USE_MAX_REGIONS = n), the compiler do some optimization useful for size-constraint target, for example the nokia_rx51 target increases by 152 bytes. arm: (for 3/3 boards) all +50.7 bss +2.7 text +48.0 nokia_rx51 : all +152 bss +8 text +144 u-boot: add: 2/0, grow: 5/-2 bytes: 192/-40 (152) function old new delta lmb_remove_region - 96 +96 lmb_init - 44 +44 lmb_add_region 416 440 +24 __lmb_alloc_base 224 236 +12 images 288 296 +8 lmb_overlaps_region 80 84 +4 lmb_alloc_addr 108 112 +4 lmb_init_and_reserve_range 56 36 -20 lmb_init_and_reserve 100 80 -20 But it is not the case for all platform (STM32MP15 for example). To optimize this size impact, I reduce the the regions array size and add a test on overflow management in the lmb, but it is not enough. So I try to optimized the lmb code to avoid the size impact when CONFIG_LMB_USE_MAX_REGIONS = y but it is not working and I prefer kept a code align with Linux kernel memblock library and kept the current behavior a this. With v2 the CI/CD build is now OK [3] [1] lmb: Add config for the number of memory and reserved regions http://patchwork.ozlabs.org/project/uboot/list/?series=227570&state=* [2] arch: Move NEEDS_MANUAL_RELOC symbol to Kconfig http://patchwork.ozlabs.org/project/uboot/list/?series=212154&state=* [3] https://source.denx.de/u-boot/custodians/u-boot-stm/-/pipelines/6616 Changes in v2: - add a max parameter extracted from v1 [3/5] - new in v2: introduced MAX_LMB_REGIONS - new in V2: reduce size impact by correct regions array size - new in V2: add test for overflow protection in lmb libary - rework v1 [4/5] to keep current optimization by default when CONFIG_LMB_USE_MAX_REGIONS=n - Add CONFIG_LMB_USE_MAX_REGIONS=n and reduce LMB_MEMORY_REGIONS to reduce the used size in stack Patrick Delaunay (8): lmb: move CONFIG_LMB in Kconfig lmb: remove lmb_region.size lmb: add a max parameter in the struct lmb_region lmb: move MAX_LMB_REGIONS value in Kconfig lmb: correct size of the regions array test: lmb: add test for overflow protection in lmb_add_region lmb: Add 2 config to define the max number of regions configs: stm32mp15: increase the number of reserved memory region in lmb arch/arc/include/asm/config.h | 2 - arch/arm/include/asm/config.h | 1 - arch/m68k/include/asm/config.h | 1 - arch/microblaze/include/asm/config.h | 2 - arch/mips/include/asm/config.h | 1 - arch/nds32/include/asm/config.h | 1 - arch/powerpc/include/asm/config.h | 1 - arch/riscv/include/asm/config.h | 1 - arch/sh/include/asm/config.h | 2 - arch/x86/include/asm/config.h | 1 - arch/xtensa/include/asm/config.h | 2 - configs/stm32mp15_basic_defconfig | 3 ++ configs/stm32mp15_trusted_defconfig | 3 ++ include/configs/10m50_devboard.h | 5 --- include/configs/3c120_devboard.h | 5 --- include/configs/sandbox.h | 2 - include/configs/x86-common.h | 2 - include/image.h | 2 +- include/lmb.h | 40 +++++++++++++++-- lib/Kconfig | 44 ++++++++++++++++++- lib/lmb.c | 17 +++++--- scripts/config_whitelist.txt | 1 - test/lib/lmb.c | 64 ++++++++++++++++++++++++++++ 23 files changed, 160 insertions(+), 43 deletions(-) -- 2.17.1

2 16

[PATCH v4 00/22] ppc: qemu: Add eTSEC support
by Bin Meng 23 Apr '21

23 Apr '21

QEMU ppce500 machine can dynamically instantiate an eTSEC device if "-device eTSEC" is given to QEMU. This series updates the fixed-link ethernet PHY driver as well as the Freescale eTSEC driver to support the QEMU ppce500 board. 3 patches related to fixed phy in v1 are dropped in v2 as the changes were done by Vladimir's fixed phy & Sandbox DSA series [1]. Vladimir's series is now included in v2 to avoid dependencies. This cover letter is cc'ed to QEMU mailing list for a heads-up. A future patch will be sent to QEMU mailing list to bring its in-tree U-Boot source codes up-to-date. Azure results: PASS https://dev.azure.com/bmeng/GitHub/_build/results?buildId=343&view=results This series is avaiable at u-boot-x86/eTSEC for testing. [1] https://patchwork.ozlabs.org/project/uboot/patch/20210216224804.3355044-2-o… Changes in v4: - describe "ranges" is required fo the alternate description - make platform_bus_map_region() return void Changes in v3: - mention that U-Boot deliberately ignores the 'phy_id' and unconditionally uses PHY_FIXED_ID - update the code logic to prefer the new binding if both new and old bindings exist - sort variable definitions by line length - reuse the sandbox dsa nodes for the fixed-link testing - new patch: net: tsec: Use map_physmem() directly instead of dev_remap_addr() - add "ranges" in the alternate example - keep the variable definitions sorted - invert the strncmp logic to reduce the indentation level - add a comment to mention only the first "queue-group" is used - call the same map_physmem() in the common code path - extract platform bus virtual memory mapping codes to a new routine - add a "break" in case multiple "qemu,platform" nodes exist Changes in v2: - move device tree parsing from xilinxgmiitorgmii_probe() to xilinxgmiitorgmii_config() and use OF APIs - new patch: split from <20210216224804.3355044-4-olteanv(a)gmail.com> - include <asm/global_data.h> - use a Kconfig option CONFIG_SIMPLE_BUS_CORRECT_RANGE to control the new behavior for boards that want this - default y if SANDBOX for CONFIG_SIMPLE_BUS_CORRECT_RANGE - turn on CONFIG_SIMPLE_BUS_CORRECT_RANGE in qemu-ppce500_defconfig Bin Meng (18): dt-bindings: net: Add the old DT bindings for "fixed-link" of: extra: Introduce ofnode_phy_is_fixed_link() API dm: mdio: Use ofnode_phy_is_fixed_link() API net: phy: xilinx: Be compatible with live OF tree net: phy: xilinx: Drop #ifdef CONFIG_DM_ETH around phy_connect_gmii2rgmii() net: phy: Simplify the logic of phy_connect_fixed() net: phy: fixed: Make driver ops static net: phy: fixed: Add the missing ending newline net: phy: fixed: Support the old DT binding test: dm: Add a case to test ofnode_phy_is_fixed_link() net: tsec: Use map_physmem() directly instead of dev_remap_addr() dt-bindings: net: Update Freescale TSEC to support "queue-group" net: tsec: Support <reg> property from the subnode "queue-group" dm: core: Correctly read <ranges> of simple-bus test: dm: Add a test case for simple-bus <ranges> ppc: qemu: Create a virtual memory mapping of the platform bus ppc: qemu: Enable eTSEC support doc: board: qemu-ppce500: Document eTSEC usage Claudiu Manoil (1): sandbox: Add a DSA sandbox driver and unit test Vladimir Oltean (3): net: phy: fixed: Be compatible with live OF tree net: phy: fixed: Drop #ifdef CONFIG_DM_ETH around phy_connect_fixed net: tsec: Use dm_eth_phy_connect() directly for the DM case arch/Kconfig | 2 + arch/sandbox/dts/test.dts | 44 +++++ board/emulation/qemu-ppce500/Kconfig | 6 + board/emulation/qemu-ppce500/qemu-ppce500.c | 29 +++ configs/qemu-ppce500_defconfig | 5 + doc/board/emulation/qemu-ppce500.rst | 5 + doc/device-tree-bindings/net/fixed-link.txt | 48 +++-- doc/device-tree-bindings/net/fsl-tsec-phy.txt | 19 +- drivers/core/Kconfig | 14 ++ drivers/core/of_extra.c | 23 +++ drivers/core/simple-bus.c | 32 +++- drivers/net/Kconfig | 9 + drivers/net/Makefile | 1 + drivers/net/dsa_sandbox.c | 179 ++++++++++++++++++ drivers/net/phy/Kconfig | 1 + drivers/net/phy/fixed.c | 54 ++++-- drivers/net/phy/phy.c | 63 +++--- drivers/net/phy/xilinx_gmii2rgmii.c | 61 +++--- drivers/net/tsec.c | 36 +++- include/configs/sandbox.h | 2 + include/dm/of_extra.h | 20 ++ include/dm/simple_bus.h | 6 +- net/mdio-uclass.c | 7 +- test/dm/Makefile | 2 + test/dm/dsa.c | 82 ++++++++ test/dm/eth.c | 10 +- test/dm/of_extra.c | 18 ++ test/dm/simple-bus.c | 33 ++++ 28 files changed, 691 insertions(+), 120 deletions(-) create mode 100644 drivers/net/dsa_sandbox.c create mode 100644 test/dm/dsa.c create mode 100644 test/dm/simple-bus.c -- 2.25.1

4 31

[PATCH 1/3] samsung: exynos: Convert SROMC interface to a driver
by Simon Glass 23 Apr '21

23 Apr '21

Add a bus driver for this and use it to configure the bus parameters for the Ethernet interface. Drop the old pre-driver-model code. Switch over to use driver model for Ethernet. Signed-off-by: Simon Glass <sjg(a)chromium.org> --- arch/arm/Kconfig | 1 + arch/arm/dts/exynos5250-smdk5250.dts | 1 + arch/arm/mach-exynos/include/mach/sromc.h | 18 ------ board/samsung/common/Makefile | 2 +- board/samsung/common/board.c | 78 ----------------------- board/samsung/common/sromc.c | 76 ++++++++++++++++++++++ board/samsung/smdkv310/smdkv310.c | 9 --- configs/arndale_defconfig | 1 - configs/odroid-xu3_defconfig | 1 - configs/peach-pi_defconfig | 1 - configs/peach-pit_defconfig | 1 - configs/smdk5250_defconfig | 1 - configs/smdk5420_defconfig | 1 - configs/smdkv310_defconfig | 1 - configs/snow_defconfig | 1 - configs/spring_defconfig | 1 - include/fdtdec.h | 2 - lib/fdtdec.c | 2 - 18 files changed, 79 insertions(+), 119 deletions(-) create mode 100644 board/samsung/common/sromc.c diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 3307f2b3fc5..eb25474ab27 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -727,6 +727,7 @@ config ARCH_EXYNOS select DM select DM_GPIO select DM_I2C + select DM_ETH select DM_KEYBOARD select DM_SERIAL select DM_SPI diff --git a/arch/arm/dts/exynos5250-smdk5250.dts b/arch/arm/dts/exynos5250-smdk5250.dts index e542a790761..afe0cca48a9 100644 --- a/arch/arm/dts/exynos5250-smdk5250.dts +++ b/arch/arm/dts/exynos5250-smdk5250.dts @@ -41,6 +41,7 @@ }; sromc@12250000 { + compatible = "samsung,exynos5-sromc"; bank = <1>; srom-timing = <1 9 12 1 6 1 1>; width = <2>; diff --git a/arch/arm/mach-exynos/include/mach/sromc.h b/arch/arm/mach-exynos/include/mach/sromc.h index 15c9ccc723d..ac229e0d169 100644 --- a/arch/arm/mach-exynos/include/mach/sromc.h +++ b/arch/arm/mach-exynos/include/mach/sromc.h @@ -33,22 +33,4 @@ struct s5p_sromc { /* Configure the Band Width and Bank Control Regs for required SROMC Bank */ void s5p_config_sromc(u32 srom_bank, u32 srom_bw_conf, u32 srom_bc_conf); -enum { - FDT_SROM_PMC, - FDT_SROM_TACP, - FDT_SROM_TAH, - FDT_SROM_TCOH, - FDT_SROM_TACC, - FDT_SROM_TCOS, - FDT_SROM_TACS, - - FDT_SROM_TIMING_COUNT, -}; - -struct fdt_sromc { - u8 bank; /* srom bank number */ - u8 width; /* bus width in bytes */ - unsigned int timing[FDT_SROM_TIMING_COUNT]; /* timing parameters */ -}; - #endif /* __ASM_ARCH_SROMC_H_ */ diff --git a/board/samsung/common/Makefile b/board/samsung/common/Makefile index 3593c77cbc2..d31b81abf1e 100644 --- a/board/samsung/common/Makefile +++ b/board/samsung/common/Makefile @@ -7,7 +7,7 @@ obj-$(CONFIG_USB_GADGET_DOWNLOAD) += gadget.o obj-$(CONFIG_MISC_COMMON) += misc.o ifndef CONFIG_SPL_BUILD -obj-$(CONFIG_BOARD_COMMON) += board.o +obj-$(CONFIG_BOARD_COMMON) += board.o sromc.o ifdef CONFIG_EXYNOS5_DT obj-y += exynos5-dt.o obj-$(CONFIG_BOARD_TYPES) += exynos5-dt-types.o diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c index 104d2a65746..1c2fe025e89 100644 --- a/board/samsung/common/board.c +++ b/board/samsung/common/board.c @@ -26,7 +26,6 @@ #include <asm/arch/pinmux.h> #include <asm/arch/power.h> #include <asm/arch/system.h> -#include <asm/arch/sromc.h> #include <lcd.h> #include <i2c.h> #include <mmc.h> @@ -195,83 +194,6 @@ int power_init_board(void) } #endif -#ifdef CONFIG_SMC911X -static int decode_sromc(const void *blob, struct fdt_sromc *config) -{ - int err; - int node; - - node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS5_SROMC); - if (node < 0) { - debug("Could not find SROMC node\n"); - return node; - } - - config->bank = fdtdec_get_int(blob, node, "bank", 0); - config->width = fdtdec_get_int(blob, node, "width", 2); - - err = fdtdec_get_int_array(blob, node, "srom-timing", config->timing, - FDT_SROM_TIMING_COUNT); - if (err < 0) { - debug("Could not decode SROMC configuration Error: %s\n", - fdt_strerror(err)); - return -FDT_ERR_NOTFOUND; - } - return 0; -} -#endif - -int board_eth_init(struct bd_info *bis) -{ -#ifdef CONFIG_SMC911X - u32 smc_bw_conf, smc_bc_conf; - struct fdt_sromc config; - fdt_addr_t base_addr; - int node; - - node = decode_sromc(gd->fdt_blob, &config); - if (node < 0) { - debug("%s: Could not find sromc configuration\n", __func__); - return 0; - } - node = fdtdec_next_compatible(gd->fdt_blob, node, COMPAT_SMSC_LAN9215); - if (node < 0) { - debug("%s: Could not find lan9215 configuration\n", __func__); - return 0; - } - - /* We now have a node, so any problems from now on are errors */ - base_addr = fdtdec_get_addr(gd->fdt_blob, node, "reg"); - if (base_addr == FDT_ADDR_T_NONE) { - debug("%s: Could not find lan9215 address\n", __func__); - return -1; - } - - /* Ethernet needs data bus width of 16 bits */ - if (config.width != 2) { - debug("%s: Unsupported bus width %d\n", __func__, - config.width); - return -1; - } - smc_bw_conf = SROMC_DATA16_WIDTH(config.bank) - | SROMC_BYTE_ENABLE(config.bank); - - smc_bc_conf = SROMC_BC_TACS(config.timing[FDT_SROM_TACS]) | - SROMC_BC_TCOS(config.timing[FDT_SROM_TCOS]) | - SROMC_BC_TACC(config.timing[FDT_SROM_TACC]) | - SROMC_BC_TCOH(config.timing[FDT_SROM_TCOH]) | - SROMC_BC_TAH(config.timing[FDT_SROM_TAH]) | - SROMC_BC_TACP(config.timing[FDT_SROM_TACP]) | - SROMC_BC_PMC(config.timing[FDT_SROM_PMC]); - - /* Select and configure the SROMC bank */ - exynos_pinmux_config(PERIPH_ID_SROMC, config.bank); - s5p_config_sromc(config.bank, smc_bw_conf, smc_bc_conf); - return smc911x_initialize(0, base_addr); -#endif - return 0; -} - #if defined(CONFIG_DISPLAY_BOARDINFO) || defined(CONFIG_DISPLAY_BOARDINFO_LATE) int checkboard(void) { diff --git a/board/samsung/common/sromc.c b/board/samsung/common/sromc.c new file mode 100644 index 00000000000..76e37dfe262 --- /dev/null +++ b/board/samsung/common/sromc.c @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2021 Google LLC + */ + +#define LOG_CATEGORY UCLASS_ETH + +#include <common.h> +#include <dm.h> +#include <log.h> +#include <asm/arch/pinmux.h> +#include <asm/arch/sromc.h> + +enum { + FDT_SROM_PMC, + FDT_SROM_TACP, + FDT_SROM_TAH, + FDT_SROM_TCOH, + FDT_SROM_TACC, + FDT_SROM_TCOS, + FDT_SROM_TACS, + + FDT_SROM_TIMING_COUNT, +}; + +static int exyno5_sromc_probe(struct udevice *dev) +{ + u32 timing[FDT_SROM_TIMING_COUNT]; /* timing parameters */ + u32 smc_bw_conf, smc_bc_conf; + int bank; /* srom bank number */ + int width; /* bus width in bytes */ + int ret; + + if (!IS_ENABLED(CONFIG_SMC911X)) + return 0; + + bank = dev_read_s32_default(dev, "bank", 0); + width = dev_read_s32_default(dev, "width", 2); + + /* Ethernet needs data bus width of 16 bits */ + if (width != 2) { + log_debug("Unsupported bus width %d\n", width); + return log_msg_ret("width", -EINVAL); + } + ret = dev_read_u32_array(dev, "srom-timing", timing, + FDT_SROM_TIMING_COUNT); + if (ret) + return log_msg_ret("sromc", -EINVAL); + + smc_bw_conf = SROMC_DATA16_WIDTH(bank) | SROMC_BYTE_ENABLE(bank); + smc_bc_conf = SROMC_BC_TACS(timing[FDT_SROM_TACS]) | + SROMC_BC_TCOS(timing[FDT_SROM_TCOS]) | + SROMC_BC_TACC(timing[FDT_SROM_TACC]) | + SROMC_BC_TCOH(timing[FDT_SROM_TCOH]) | + SROMC_BC_TAH(timing[FDT_SROM_TAH]) | + SROMC_BC_TACP(timing[FDT_SROM_TACP]) | + SROMC_BC_PMC(timing[FDT_SROM_PMC]); + + /* Select and configure the SROMC bank */ + exynos_pinmux_config(PERIPH_ID_SROMC, bank); + s5p_config_sromc(bank, smc_bw_conf, smc_bc_conf); + + return 0; +} + +static const struct udevice_id exyno5_sromc_ids[] = { + { .compatible = "samsung,exynos5-sromc" }, + {} +}; + +U_BOOT_DRIVER(exyno5_sromc) = { + .name = "exyno5_sromc", + .id = UCLASS_SIMPLE_BUS, + .of_match = exyno5_sromc_ids, + .probe = exyno5_sromc_probe, +}; diff --git a/board/samsung/smdkv310/smdkv310.c b/board/samsung/smdkv310/smdkv310.c index 8811cbb9ad0..bb61ba1f81c 100644 --- a/board/samsung/smdkv310/smdkv310.c +++ b/board/samsung/smdkv310/smdkv310.c @@ -73,15 +73,6 @@ int dram_init_banksize(void) return 0; } -int board_eth_init(struct bd_info *bis) -{ - int rc = 0; -#ifdef CONFIG_SMC911X - rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); -#endif - return rc; -} - #ifdef CONFIG_DISPLAY_BOARDINFO int checkboard(void) { diff --git a/configs/arndale_defconfig b/configs/arndale_defconfig index 1b4dd324b8d..84b248ddde2 100644 --- a/configs/arndale_defconfig +++ b/configs/arndale_defconfig @@ -37,7 +37,6 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_S5P=y CONFIG_MTD=y CONFIG_SMC911X=y -CONFIG_SMC911X_BASE=0x5000000 CONFIG_SOUND=y CONFIG_I2S=y CONFIG_I2S_SAMSUNG=y diff --git a/configs/odroid-xu3_defconfig b/configs/odroid-xu3_defconfig index 755a2ca9add..1dbb3550e48 100644 --- a/configs/odroid-xu3_defconfig +++ b/configs/odroid-xu3_defconfig @@ -45,7 +45,6 @@ CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_DW=y CONFIG_MTD=y CONFIG_SMC911X=y -CONFIG_SMC911X_BASE=0x5000000 CONFIG_DM_PMIC=y CONFIG_PMIC_S2MPS11=y CONFIG_DM_REGULATOR=y diff --git a/configs/peach-pi_defconfig b/configs/peach-pi_defconfig index 01054b0ee48..3cef18c188c 100644 --- a/configs/peach-pi_defconfig +++ b/configs/peach-pi_defconfig @@ -53,7 +53,6 @@ CONFIG_SF_DEFAULT_SPEED=50000000 CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SMC911X=y -CONFIG_SMC911X_BASE=0x5000000 CONFIG_DM_PMIC=y CONFIG_PMIC_TPS65090=y CONFIG_DM_REGULATOR=y diff --git a/configs/peach-pit_defconfig b/configs/peach-pit_defconfig index c6646dcd6e6..da517eab621 100644 --- a/configs/peach-pit_defconfig +++ b/configs/peach-pit_defconfig @@ -52,7 +52,6 @@ CONFIG_SF_DEFAULT_SPEED=50000000 CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SMC911X=y -CONFIG_SMC911X_BASE=0x5000000 CONFIG_DM_PMIC=y CONFIG_PMIC_TPS65090=y CONFIG_DM_REGULATOR=y diff --git a/configs/smdk5250_defconfig b/configs/smdk5250_defconfig index 8e60f46a5c7..84318aac975 100644 --- a/configs/smdk5250_defconfig +++ b/configs/smdk5250_defconfig @@ -48,7 +48,6 @@ CONFIG_SF_DEFAULT_SPEED=50000000 CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SMC911X=y -CONFIG_SMC911X_BASE=0x5000000 CONFIG_DM_PMIC=y CONFIG_DM_PMIC_MAX77686=y CONFIG_DM_REGULATOR=y diff --git a/configs/smdk5420_defconfig b/configs/smdk5420_defconfig index 429b0638cdb..69f6d581f04 100644 --- a/configs/smdk5420_defconfig +++ b/configs/smdk5420_defconfig @@ -43,7 +43,6 @@ CONFIG_SF_DEFAULT_SPEED=50000000 CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SMC911X=y -CONFIG_SMC911X_BASE=0x5000000 CONFIG_DM_PMIC=y CONFIG_DM_REGULATOR=y CONFIG_EXYNOS_SPI=y diff --git a/configs/smdkv310_defconfig b/configs/smdkv310_defconfig index 9d4cf3533eb..5be91670dcc 100644 --- a/configs/smdkv310_defconfig +++ b/configs/smdkv310_defconfig @@ -28,6 +28,5 @@ CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_S5P=y CONFIG_MTD=y CONFIG_SMC911X=y -CONFIG_SMC911X_BASE=0x5000000 CONFIG_USB=y CONFIG_DM_USB=y diff --git a/configs/snow_defconfig b/configs/snow_defconfig index 76215034acf..8b646cac67a 100644 --- a/configs/snow_defconfig +++ b/configs/snow_defconfig @@ -58,7 +58,6 @@ CONFIG_SF_DEFAULT_SPEED=50000000 CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SMC911X=y -CONFIG_SMC911X_BASE=0x5000000 CONFIG_DM_PMIC=y CONFIG_DM_PMIC_MAX77686=y CONFIG_PMIC_S5M8767=y diff --git a/configs/spring_defconfig b/configs/spring_defconfig index a1fdf1d1f68..8cf4a5dbe17 100644 --- a/configs/spring_defconfig +++ b/configs/spring_defconfig @@ -58,7 +58,6 @@ CONFIG_SF_DEFAULT_SPEED=50000000 CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SMC911X=y -CONFIG_SMC911X_BASE=0x5000000 CONFIG_DM_PMIC=y CONFIG_DM_PMIC_MAX77686=y CONFIG_PMIC_S5M8767=y diff --git a/include/fdtdec.h b/include/fdtdec.h index 62d16609732..38b1352a013 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -139,8 +139,6 @@ enum fdt_compat_id { /* Tegra124 XUSB pad controller */ COMPAT_NVIDIA_TEGRA210_XUSB_PADCTL, /* Tegra210 XUSB pad controller */ - COMPAT_SMSC_LAN9215, /* SMSC 10/100 Ethernet LAN9215 */ - COMPAT_SAMSUNG_EXYNOS5_SROMC, /* Exynos5 SROMC */ COMPAT_SAMSUNG_EXYNOS_USB_PHY, /* Exynos phy controller for usb2.0 */ COMPAT_SAMSUNG_EXYNOS5_USB3_PHY,/* Exynos phy controller for usb3.0 */ COMPAT_SAMSUNG_EXYNOS_TMU, /* Exynos TMU */ diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 864589193b4..6bb418236d0 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -47,8 +47,6 @@ static const char * const compat_names[COMPAT_COUNT] = { COMPAT(NVIDIA_TEGRA20_NAND, "nvidia,tegra20-nand"), COMPAT(NVIDIA_TEGRA124_XUSB_PADCTL, "nvidia,tegra124-xusb-padctl"), COMPAT(NVIDIA_TEGRA210_XUSB_PADCTL, "nvidia,tegra210-xusb-padctl"), - COMPAT(SMSC_LAN9215, "smsc,lan9215"), - COMPAT(SAMSUNG_EXYNOS5_SROMC, "samsung,exynos-sromc"), COMPAT(SAMSUNG_EXYNOS_USB_PHY, "samsung,exynos-usb-phy"), COMPAT(SAMSUNG_EXYNOS5_USB3_PHY, "samsung,exynos5250-usb3-phy"), COMPAT(SAMSUNG_EXYNOS_TMU, "samsung,exynos-tmu"), -- 2.31.0.291.g576ba9dcdaf-goog

4 7

[PATCH 0/6] xilinx: Align usb dfu boot mode and bootcommand with distroboot
by Michal Simek 23 Apr '21

23 Apr '21

Hi, usb dfu was handled differently then other boot commands. First of all fix usb dfu boot mode for zynqmp where usb boot mode is not usb host but usb dfu. Align also versal, zynq and zynqmp implementations to each other. Thanks, Michal Michal Simek (2): cmd: dfu: Propagate error if dfu gadget fails xilinx: zynqmp: Remove dfu_ram_info setup T Karthik Reddy (4): xilinx: zynqmp: Add usb dfu/thor distro boot support xilinx: versal: Add usb dfu/thor distro boot support xilinx: zynq: Add usb dfu/thor distro boot support xilinx: Enable DFU_TIMEOUT config board/xilinx/versal/board.c | 2 +- board/xilinx/zynqmp/zynqmp.c | 2 +- cmd/dfu.c | 2 +- configs/xilinx_versal_virt_defconfig | 1 + configs/xilinx_zynq_virt_defconfig | 1 + configs/xilinx_zynqmp_virt_defconfig | 1 + include/configs/syzygy_hub.h | 1 - include/configs/topic_miami.h | 1 - include/configs/xilinx_versal.h | 52 ++++++++++++------------ include/configs/xilinx_zynqmp.h | 49 ++++++++++++++-------- include/configs/zynq-common.h | 61 ++++++++++++++-------------- 11 files changed, 94 insertions(+), 79 deletions(-) -- 2.31.0

2 7

[PATCH 0/4] xilinx: Enable redundant variables for all Xilinx SoCs
by Michal Simek 23 Apr '21

23 Apr '21

Hi, based on discussion with Tom here https://lists.denx.de/pipermail/u-boot/2021-January/437234.html I decided to enable redundant variables on all Xilinx SoCs. Users who don't want to use it can disable this option. But having extended structure for variable storing is based on that thread above the right way to go. It means switch to the right approach is better to do earlier rather than later. Thanks, Michal Ashok Reddy Soma (2): xilinx: zynq: Add support for saving env based on bootmode xilinx: versal: Add support for saving env based on bootmode Michal Simek (2): env: Setup default value for ENV_OFFSET_REDUND xilinx: Enable redundant variable handling board/xilinx/versal/board.c | 30 ++++++++++++++++++++++++++ board/xilinx/zynq/board.c | 32 ++++++++++++++++++++++++++++ configs/microblaze-generic_defconfig | 1 + configs/xilinx_versal_virt_defconfig | 4 ++++ configs/xilinx_zynq_virt_defconfig | 6 +++++- configs/xilinx_zynqmp_virt_defconfig | 1 + env/Kconfig | 3 ++- 7 files changed, 75 insertions(+), 2 deletions(-) -- 2.31.0

2 5

[PATCH] lib: Move selection of SPL hash algorithms from common/
by Alexandru Gagniuc 22 Apr '21

22 Apr '21

When God said, "May there be FIT signature verification in SPL", Chuck Norris said "SPL image too big". And then there was this patch. Enabling SPL_FIT_SIGNATURE increased the code size (armv7 platform) by about 16KiB, just enough to go over the SPL image limit. Of that: * .text.sha256_process 3.8 KiB * SHA1 implementation 4.4 KiB Although SHA1 wasn't required, it could not be disabled. The hash algorithms are implemented in lib/, as is their Kconfig selection for u-boot main. However, Kconfig selection for SPL is implemented in common/. To put it mildly, this is inconsistent. MD5 selection, on the other hand, does not have this problem. Moving the SPL hash switches to lib/ solves half the problem. They have to be renamed from SPL_<hash>_SUPPORT to SPL_<hash> to make them work elegantly with the CONFIG_IS_ENABLED() macro. The second half of the problem is not referencing the <hash> symbols when <hash> is disabled. Unfortunately, this requires some more The above #ifdef problem could be solved in several ways. One way could be to move the hash handlers to linker lists. This, however, won't work for userspace tools (mkimage), as they don't implement custom linker scripts. One could implement a <hash>_register() function for this case, and manually register all hashes. However, this is beyond the scope of this patch. Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- This is designed to apply on top of the following series: * [PATCH v6 00/11] Add support for ECDSA image signing common/hash.c | 4 ++-- common/image-sig.c | 8 +++++-- common/spl/Kconfig | 54 ---------------------------------------------- include/image.h | 12 +++++------ lib/Kconfig | 39 +++++++++++++++++++++++++++++++++ lib/Makefile | 6 +++--- 6 files changed, 56 insertions(+), 67 deletions(-) diff --git a/common/hash.c b/common/hash.c index fc64002f73..dbce70e89b 100644 --- a/common/hash.c +++ b/common/hash.c @@ -41,7 +41,7 @@ DECLARE_GLOBAL_DATA_PTR; static void reloc_update(void); -#if defined(CONFIG_SHA1) && !defined(CONFIG_SHA_PROG_HW_ACCEL) +#if IMAGE_ENABLE_SHA1 && !defined(CONFIG_SHA_PROG_HW_ACCEL) static int hash_init_sha1(struct hash_algo *algo, void **ctxp) { sha1_context *ctx = malloc(sizeof(sha1_context)); @@ -213,7 +213,7 @@ static int hash_finish_crc32(struct hash_algo *algo, void *ctx, void *dest_buf, * Note that algorithm names must be in lower case. */ static struct hash_algo hash_algo[] = { -#ifdef CONFIG_SHA1 +#if IMAGE_ENABLE_SHA1 { .name = "sha1", .digest_size = SHA1_SUM_LEN, diff --git a/common/image-sig.c b/common/image-sig.c index 0f8e592aba..dbef978bef 100644 --- a/common/image-sig.c +++ b/common/image-sig.c @@ -23,6 +23,7 @@ DECLARE_GLOBAL_DATA_PTR; #define IMAGE_MAX_HASHED_NODES 100 struct checksum_algo checksum_algos[] = { +#if IMAGE_ENABLE_SHA1 { .name = "sha1", .checksum_len = SHA1_SUM_LEN, @@ -33,6 +34,8 @@ struct checksum_algo checksum_algos[] = { #endif .calculate = hash_calculate, }, +#endif +#if IMAGE_ENABLE_SHA256 { .name = "sha256", .checksum_len = SHA256_SUM_LEN, @@ -43,7 +46,8 @@ struct checksum_algo checksum_algos[] = { #endif .calculate = hash_calculate, }, -#ifdef CONFIG_SHA384 +#endif +#if IMAGE_ENABLE_SHA384 { .name = "sha384", .checksum_len = SHA384_SUM_LEN, @@ -55,7 +59,7 @@ struct checksum_algo checksum_algos[] = { .calculate = hash_calculate, }, #endif -#ifdef CONFIG_SHA512 +#if IMAGE_ENABLE_SHA512 { .name = "sha512", .checksum_len = SHA512_SUM_LEN, diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 774541c02b..85c542e0e0 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -412,60 +412,6 @@ config SPL_CRC32_SUPPORT for detected accidental image corruption. For secure applications you should consider SHA1 or SHA256. -config SPL_MD5_SUPPORT - bool "Support MD5" - depends on SPL_FIT - help - Enable this to support MD5 in FIT images within SPL. An MD5 - checksum is a 128-bit hash value used to check that the image - contents have not been corrupted. Note that MD5 is not considered - secure as it is possible (with a brute-force attack) to adjust the - image while still retaining the same MD5 hash value. For secure - applications where images may be changed maliciously, you should - consider SHA256 or SHA384. - -config SPL_SHA1_SUPPORT - bool "Support SHA1" - depends on SPL_FIT - select SHA1 - help - Enable this to support SHA1 in FIT images within SPL. A SHA1 - checksum is a 160-bit (20-byte) hash value used to check that the - image contents have not been corrupted or maliciously altered. - While SHA1 is fairly secure it is coming to the end of its life - due to the expanding computing power available to brute-force - attacks. For more security, consider SHA256 or SHA384. - -config SPL_SHA256_SUPPORT - bool "Support SHA256" - depends on SPL_FIT - select SHA256 - help - Enable this to support SHA256 in FIT images within SPL. A SHA256 - checksum is a 256-bit (32-byte) hash value used to check that the - image contents have not been corrupted. - -config SPL_SHA384_SUPPORT - bool "Support SHA384" - depends on SPL_FIT - select SHA384 - select SHA512_ALGO - help - Enable this to support SHA384 in FIT images within SPL. A SHA384 - checksum is a 384-bit (48-byte) hash value used to check that the - image contents have not been corrupted. Use this for the highest - security. - -config SPL_SHA512_SUPPORT - bool "Support SHA512" - depends on SPL_FIT - select SHA512 - select SHA512_ALGO - help - Enable this to support SHA512 in FIT images within SPL. A SHA512 - checksum is a 512-bit (64-byte) hash value used to check that the - image contents have not been corrupted. - config SPL_FIT_IMAGE_TINY bool "Remove functionality from SPL FIT loading to reduce size" depends on SPL_FIT diff --git a/include/image.h b/include/image.h index b5bcf08e61..f85e935f0c 100644 --- a/include/image.h +++ b/include/image.h @@ -62,13 +62,13 @@ struct fdt_region; #include <linux/libfdt.h> #include <fdt_support.h> # ifdef CONFIG_SPL_BUILD -# ifdef CONFIG_SPL_CRC32_SUPPORT +# ifdef CONFIG_SPL_CRC32 # define IMAGE_ENABLE_CRC32 1 # endif -# ifdef CONFIG_SPL_MD5_SUPPORT +# ifdef CONFIG_SPL_MD5 # define IMAGE_ENABLE_MD5 1 # endif -# ifdef CONFIG_SPL_SHA1_SUPPORT +# ifdef CONFIG_SPL_SHA1 # define IMAGE_ENABLE_SHA1 1 # endif # else @@ -90,21 +90,21 @@ struct fdt_region; #endif #if defined(CONFIG_FIT_ENABLE_SHA256_SUPPORT) || \ - defined(CONFIG_SPL_SHA256_SUPPORT) + defined(CONFIG_SPL_SHA256) #define IMAGE_ENABLE_SHA256 1 #else #define IMAGE_ENABLE_SHA256 0 #endif #if defined(CONFIG_FIT_ENABLE_SHA384_SUPPORT) || \ - defined(CONFIG_SPL_SHA384_SUPPORT) + defined(CONFIG_SPL_SHA384) #define IMAGE_ENABLE_SHA384 1 #else #define IMAGE_ENABLE_SHA384 0 #endif #if defined(CONFIG_FIT_ENABLE_SHA512_SUPPORT) || \ - defined(CONFIG_SPL_SHA512_SUPPORT) + defined(CONFIG_SPL_SHA512_ALGO) #define IMAGE_ENABLE_SHA512 1 #else #define IMAGE_ENABLE_SHA512 0 diff --git a/lib/Kconfig b/lib/Kconfig index 7288340614..8222120cf2 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -357,6 +357,18 @@ config SHA1 The SHA1 algorithm produces a 160-bit (20-byte) hash value (digest). + config SPL_SHA1 + bool "Support SHA1 in SPL" + default y if SHA1 + help + Enable this to support SHA1 in FIT images within SPL. A SHA1 + checksum is a 160-bit (20-byte) hash value used to check that the + image contents have not been corrupted or maliciously altered. + While SHA1 is fairly secure it is coming to the end of its life + due to the expanding computing power available to brute-force + attacks. For more security, consider SHA256 or SHA384. + + config SHA256 bool "Enable SHA256 support" help @@ -365,6 +377,14 @@ config SHA256 The SHA256 algorithm produces a 256-bit (32-byte) hash value (digest). +config SPL_SHA256 + bool "Support SHA256 in SPL" + default y if SHA256 + help + Enable this to support SHA256 in FIT images within SPL. A SHA256 + checksum is a 256-bit (32-byte) hash value used to check that the + image contents have not been corrupted. + config SHA512_ALGO bool "Enable SHA512 algorithm" help @@ -379,6 +399,15 @@ config SHA512 The SHA512 algorithm produces a 512-bit (64-byte) hash value (digest). +config SPL_SHA512_ALGO + bool "Support SHA512 in SPL" + default y if SHA512 + help + Enable this to support SHA512 in FIT images within SPL. A SHA512 + checksum is a 512-bit (64-byte) hash value used to check that the + image contents have not been corrupted. + + config SHA384 bool "Enable SHA384 support" depends on SHA512_ALGO @@ -388,6 +417,16 @@ config SHA384 The SHA384 algorithm produces a 384-bit (48-byte) hash value (digest). +config SPL_SHA384 + bool "Support SHA384 in SPL" + depends on SPL_SHA512_ALGO + default y if SHA384 + help + Enable this to support SHA384 in FIT images within SPL. A SHA384 + checksum is a 384-bit (48-byte) hash value used to check that the + image contents have not been corrupted. Use this for the highest + security. + config SHA_HW_ACCEL bool "Enable hashing using hardware" help diff --git a/lib/Makefile b/lib/Makefile index 1d4b7d3aad..382a537709 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -61,9 +61,9 @@ obj-$(CONFIG_$(SPL_)ACPIGEN) += acpi/ obj-$(CONFIG_$(SPL_)MD5) += md5.o obj-$(CONFIG_$(SPL_)RSA) += rsa/ obj-$(CONFIG_FIT_SIGNATURE) += hash-checksum.o -obj-$(CONFIG_SHA1) += sha1.o -obj-$(CONFIG_SHA256) += sha256.o -obj-$(CONFIG_SHA512_ALGO) += sha512.o +obj-$(CONFIG_$(SPL_)SHA1) += sha1.o +obj-$(CONFIG_$(SPL_)SHA256) += sha256.o +obj-$(CONFIG_$(SPL_)SHA512_ALGO) += sha512.o obj-$(CONFIG_$(SPL_)ZLIB) += zlib/ obj-$(CONFIG_$(SPL_)ZSTD) += zstd/ -- 2.26.2

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[PATCH] mips: octeon: octeon_ebb7304_defconfig: Enable USB storage support
by Stefan Roese 22 Apr '21

22 Apr '21

This patch enables USB storage support with the necessary partition support on the MIPS Octeon EBB7304. Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Aaron Williams <awilliams(a)marvell.com> Cc: Chandrakala Chavva <cchavva(a)marvell.com> --- configs/octeon_ebb7304_defconfig | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/configs/octeon_ebb7304_defconfig b/configs/octeon_ebb7304_defconfig index a98d73a268..b8670c9165 100644 --- a/configs/octeon_ebb7304_defconfig +++ b/configs/octeon_ebb7304_defconfig @@ -24,7 +24,9 @@ CONFIG_CMD_TIME=y CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y -# CONFIG_DOS_PARTITION is not set +CONFIG_AMIGA_PARTITION=y +CONFIG_EFI_PARTITION=y +CONFIG_PARTITION_TYPE_GUID=y CONFIG_ENV_IS_IN_FLASH=y CONFIG_ENV_ADDR=0x1FBFE000 CONFIG_BLK=y @@ -59,6 +61,7 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_ASIX88179=y -- 2.30.1

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