March 2021 - U-Boot

[PATCH v2] arm: Add support for Kobol Helios64 board
by Christian Glombek 30 Mar '21

30 Mar '21

The hardware is described in detail on Kobol's wiki at https://wiki.kobol.io/helios64/intro/. This commit is based on downstream work in Armbian by Aditya Prayoga [1]. The devicetree is taken from Linux v5.12-rc1 and was originally submitted there by Uwe Kleine-Koenig [2]. [1] https://github.com/ukleinek/armbian-build/blob/35c85295d351830aa59b624db524… [2] https://github.com/torvalds/linux/blob/7a7fd0de4a9804299793e564a555a49c1fc9… --- arch/arm/dts/Makefile | 1 + .../arm/dts/rk3399-kobol-helios64-u-boot.dtsi | 136 +++++++ arch/arm/dts/rk3399-kobol-helios64.dts | 372 ++++++++++++++++++ arch/arm/mach-rockchip/rk3399/Kconfig | 17 + board/kobol/helios64/Kconfig | 24 ++ board/kobol/helios64/MAINTAINERS | 6 + board/kobol/helios64/Makefile | 5 + board/kobol/helios64/helios64.c | 304 ++++++++++++++ board/kobol/helios64/sys_otp.c | 250 ++++++++++++ board/kobol/helios64/sys_otp.h | 12 + configs/helios64-rk3399_defconfig | 147 +++++++ include/configs/helios64.h | 47 +++ 12 files changed, 1321 insertions(+) create mode 100644 arch/arm/dts/rk3399-kobol-helios64-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-kobol-helios64.dts create mode 100644 board/kobol/helios64/Kconfig create mode 100644 board/kobol/helios64/MAINTAINERS create mode 100644 board/kobol/helios64/Makefile create mode 100644 board/kobol/helios64/helios64.c create mode 100644 board/kobol/helios64/sys_otp.c create mode 100644 board/kobol/helios64/sys_otp.h create mode 100644 configs/helios64-rk3399_defconfig create mode 100644 include/configs/helios64.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 33e483f4fb..2c820bc2b7 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -124,6 +124,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ rk3399-ficus.dtb \ rk3399-firefly.dtb \ rk3399-gru-bob.dtb \ + rk3399-kobol-helios64.dtb \ rk3399-khadas-edge.dtb \ rk3399-khadas-edge-captain.dtb \ rk3399-khadas-edge-v.dtb \ diff --git a/arch/arm/dts/rk3399-kobol-helios64-u-boot.dtsi b/arch/arm/dts/rk3399-kobol-helios64-u-boot.dtsi new file mode 100644 index 0000000000..6fe9d59df3 --- /dev/null +++ b/arch/arm/dts/rk3399-kobol-helios64-u-boot.dtsi @@ -0,0 +1,136 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2020 Aditya Prayoga <aditya(a)kobol.io> + */ + +#include "rk3399-u-boot.dtsi" +#include "rk3399-sdram-lpddr4-100.dtsi" +/ { + aliases { + spi0 = &spi1; + spi1 = &spi2; + spi2 = &spi5; + ethernet0 = &gmac; + ethernet1 = &usb_lan; + }; + + chosen { + bootargs = "earlycon=uart8250,mmio32,0xff1a0000 earlyprintk"; + stdout-path = "serial2:1500000n8"; + u-boot,spl-boot-order = "same-as-spl", &spiflash, &sdmmc, &sdhci; + }; + + config { + u-boot,spl-payload-offset = <0x80000>; /* @ 512KB */ + }; +}; + +&gpio1 { + usb-mux-hs { + gpio-hog; + gpios = <RK_PA4 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "USB_MUX_HS"; + }; + + usb-mux-oe { + gpio-hog; + gpios = <RK_PB5 GPIO_ACTIVE_LOW>; + output-high; + line-name = "USB_MUX_OE#"; + }; + + soc-flash-wp { + gpio-hog; + gpios = <RK_PC2 GPIO_ACTIVE_LOW>; + output-low; + line-name = "SOC_WP#"; + }; +}; + +&gpio2 { + sata-flash-wp { + gpio-hog; + gpios = <RK_PD0 GPIO_ACTIVE_LOW>; + output-high; + line-name = "SATA_WP#_LV"; + }; +}; + +&gpio4 { + auto-on-en-d { + gpio-hog; + gpios = <RK_PD1 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "AUTO_ON_EN_D"; + }; + + auto-on-en-clk { + gpio-hog; + gpios = <RK_PD2 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "AUTO_ON_EN_CLK"; + }; + + board-rev-id-0 { + gpio-hog; + gpios = <RK_PD5 GPIO_ACTIVE_HIGH>; + input; + }; + + board-rev-id-1 { + gpio-hog; + gpios = <RK_PD6 GPIO_ACTIVE_HIGH>; + input; + }; +}; + +&int_hub { + compatible = "usb-hub"; + usb,device-class = <USB_CLASS_HUB>; +}; + +&pcie_prst { + rockchip,pins = + <2 RK_PD4 RK_FUNC_GPIO &pcfg_output_low>; +}; + +&pcie_pwr_en { + rockchip,pins = + <1 RK_PD0 RK_FUNC_GPIO &pcfg_output_low>; +}; + +&pinctrl { + usb { + usb_mux_hs: usb-mux-hs { + rockchip,pins = + <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usb_mux_oe: usb-mux-oe { + rockchip,pins = + <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&spi1 { + spiflash: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-max-frequency = <25000000>; + status = "okay"; + m25p,fast-read; + u-boot,dm-pre-reloc; + }; +}; + +&vdd_center { + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <950000>; + regulator-init-microvolt = <950000>; +}; + +&vdd_log { + regulator-init-microvolt = <900000>; +}; diff --git a/arch/arm/dts/rk3399-kobol-helios64.dts b/arch/arm/dts/rk3399-kobol-helios64.dts new file mode 100644 index 0000000000..66c725a342 --- /dev/null +++ b/arch/arm/dts/rk3399-kobol-helios64.dts @@ -0,0 +1,372 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Aditya Prayoga <aditya(a)kobol.io> + */ + +/* + * The Kobol Helios64 is a board designed to operate as a NAS and optionally + * ships with an enclosing that can host five 2.5" hard disks. + * + * See https://wiki.kobol.io/helios64/intro/ for further details. + */ + +/dts-v1/; +#include "rk3399.dtsi" +#include "rk3399-opp.dtsi" + +/ { + model = "Kobol Helios64"; + compatible = "kobol,helios64", "rockchip,rk3399"; + + avdd_1v8_s0: avdd-1v8-s0 { + compatible = "regulator-fixed"; + regulator-name = "avdd_1v8_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc3v3_sys_s3>; + }; + + clkin_gmac: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "clkin_gmac"; + #clock-cells = <0>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&sys_grn_led_on &sys_red_led_on>; + + led-0 { + label = "helios64:green:status"; + gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + led-1 { + label = "helios64:red:fault"; + gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + }; + + vcc1v8_sys_s0: vcc1v8-sys-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc1v8_sys_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc1v8_sys_s3>; + }; + + vcc3v0_sd: vcc3v0-sd { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; + regulator-name = "vcc3v0_sd"; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_pwr_h>; + vin-supply = <&vcc3v3_sys_s3>; + }; + + vcc3v3_sys_s3: vcc_lan: vcc3v3-sys-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin_bkup>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc12v_dcin: vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc12v_dcin_bkup: vcc12v-dcin-bkup { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin_bkup"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + vin-supply = <&vcc12v_dcin>; + }; +}; + +/* + * The system doesn't run stable with cpu freq enabled, so disallow the lower + * frequencies until this problem is properly understood and resolved. + */ +&cluster0_opp { + /delete-node/ opp00; + /delete-node/ opp01; + /delete-node/ opp02; + /delete-node/ opp03; + /delete-node/ opp04; +}; + +&cluster1_opp { + /delete-node/ opp00; + /delete-node/ opp01; + /delete-node/ opp02; + /delete-node/ opp03; + /delete-node/ opp04; + /delete-node/ opp05; + /delete-node/ opp06; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_l>; +}; + +&emmc_phy { + status = "okay"; +}; + +&gmac { + assigned-clock-parents = <&clkin_gmac>; + assigned-clocks = <&cru SCLK_RMII_SRC>; + clock_in_out = "input"; + phy-mode = "rgmii"; + phy-supply = <&vcc_lan>; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins &gphy_reset>; + rx_delay = <0x20>; + tx_delay = <0x28>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <168>; + i2c-scl-falling-time-ns = <4>; + status = "okay"; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio0>; + interrupts = <10 IRQ_TYPE_LEVEL_LOW>; + clock-output-names = "xin32k", "rk808-clkout2"; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc3v3_sys_s3>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc5v0_sys>; + vcc12-supply = <&vcc3v3_sys_s3>; + vddio-supply = <&vcc3v0_s3>; + wakeup-source; + #clock-cells = <1>; + + regulators { + vdd_cpu_l: DCDC_REG2 { + regulator-name = "vdd_cpu_l"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v8_sys_s3: DCDC_REG4 { + regulator-name = "vcc1v8_sys_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_sdio_s0: LDO_REG4 { + regulator-name = "vcc_sdio_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc3v0_s3: LDO_REG8 { + regulator-name = "vcc3v0_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + }; + }; + + vdd_cpu_b: regulator@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_b"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <160>; + i2c-scl-falling-time-ns = <30>; + status = "okay"; + + temp@4c { + compatible = "national,lm75"; + reg = <0x4c>; + }; +}; + +&io_domains { + audio-supply = <&vcc1v8_sys_s0>; + bt656-supply = <&vcc1v8_sys_s0>; + gpio1830-supply = <&vcc3v0_s3>; + sdmmc-supply = <&vcc_sdio_s0>; + status = "okay"; +}; + +&pinctrl { + gmac { + gphy_reset: gphy-reset { + rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_output_low>; + }; + }; + + leds { + sys_grn_led_on: sys-grn-led-on { + rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + sys_red_led_on: sys-red-led-on { + rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + vcc3v0-sd { + sdmmc0_pwr_h: sdmmc0-pwr-h { + rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pmu_io_domains { + pmu1830-supply = <&vcc3v0_s3>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + mmc-hs200-1_8v; + non-removable; + vqmmc-supply = <&vcc1v8_sys_s0>; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; + vmmc-supply = <&vcc3v0_sd>; + vqmmc-supply = <&vcc_sdio_s0>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig index 17628f9171..7890bafe56 100644 --- a/arch/arm/mach-rockchip/rk3399/Kconfig +++ b/arch/arm/mach-rockchip/rk3399/Kconfig @@ -28,6 +28,22 @@ config TARGET_PINEBOOK_PRO_RK3399 with 4Gb RAM, onboard eMMC, USB-C, a USB3 and USB2 port, 1920*1080 screen and all the usual laptop features. +config TARGET_HELIOS64 + bool "Kobol Innovations Helios64" + select BOARD_LATE_INIT + help + Helios64 is a Network Attached Storage board based on Rockchip RK3399. + + Key features of the Helios64 include: + * on-board PCIe to 5 Ports SATA Controller JMB585 + * on-board USB 3.0 hub (3x USB 3.0 host) + * USB Type-C (Support DisplayPort Alt Mode) + * on-board 1 Gigabit Ethernet + * on-board 2.5 Gigabit Ethernet (Realtek RTL8156) + * on-board eMMC + * on-board LPDDR4 + * SPI, I2C, UART, GPIO + config TARGET_PUMA_RK3399 bool "Theobroma Systems RK3399-Q7 (Puma)" help @@ -153,6 +169,7 @@ endif # BOOTCOUNT_LIMIT source "board/firefly/roc-pc-rk3399/Kconfig" source "board/google/gru/Kconfig" +source "board/kobol/helios64/Kconfig" source "board/pine64/pinebook-pro-rk3399/Kconfig" source "board/pine64/rockpro64_rk3399/Kconfig" source "board/rockchip/evb_rk3399/Kconfig" diff --git a/board/kobol/helios64/Kconfig b/board/kobol/helios64/Kconfig new file mode 100644 index 0000000000..644cdbd8f3 --- /dev/null +++ b/board/kobol/helios64/Kconfig @@ -0,0 +1,24 @@ +if TARGET_HELIOS64 + +config SYS_BOARD + default "helios64" + +config SYS_VENDOR + default "kobol" + +config SYS_CONFIG_NAME + default "helios64" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +config ENV_SECT_SIZE + default 0x1000 if ENV_IS_IN_SPI_FLASH + +config ENV_SIZE + default 0x8000 + +config ENV_OFFSET + default 0x460000 if ENV_IS_IN_SPI_FLASH + +endif diff --git a/board/kobol/helios64/MAINTAINERS b/board/kobol/helios64/MAINTAINERS new file mode 100644 index 0000000000..646644d485 --- /dev/null +++ b/board/kobol/helios64/MAINTAINERS @@ -0,0 +1,6 @@ +HELIOS64 BOARD +M: Christian Glombek <lorbus(a)fedoraproject.org> +S: Maintained +F: board/kobol/helios64/ +F: include/configs/helios64.h +F: configs/helios64_defconfig diff --git a/board/kobol/helios64/Makefile b/board/kobol/helios64/Makefile new file mode 100644 index 0000000000..ab34245a6d --- /dev/null +++ b/board/kobol/helios64/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2020 Aditya Prayoga <aditya(a)kobol.io> + +obj-y := helios64.o sys_otp.o diff --git a/board/kobol/helios64/helios64.c b/board/kobol/helios64/helios64.c new file mode 100644 index 0000000000..86349339fb --- /dev/null +++ b/board/kobol/helios64/helios64.c @@ -0,0 +1,304 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2020 Aditya Prayoga <aditya(a)kobol.io> + */ + +#include <common.h> +#include <dm.h> +#include <env.h> +#include <log.h> +#include <led.h> +#include <pci.h> +#include <power/regulator.h> +#include <scsi.h> +#include <spl_gpio.h> +#include <syscon.h> +#include <usb.h> +#include <linux/delay.h> +#include <asm/io.h> +#include <asm/gpio.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/gpio.h> +#include <asm/arch-rockchip/grf_rk3399.h> +#include <asm/arch-rockchip/hardware.h> +#include <asm/arch-rockchip/misc.h> +#include <asm/arch-rockchip/periph.h> + +#include "sys_otp.h" + +#ifndef CONFIG_TPL_BUILD +int board_early_init_f(void) +{ +#ifdef CONFIG_SPL_BUILD +#define GPIO0_BASE 0xff720000 +#define GRF_BASE 0xff770000 + struct rk3399_grf_regs * const grf = (void *)GRF_BASE; + struct rockchip_gpio_regs * const gpio = (void *)GPIO0_BASE; + + /* Turn ON status LED. At this stage, FDT & DM is not initialized yet */ + spl_gpio_output(gpio, GPIO(BANK_B, 4), 1); +#endif + return 0; +} +#endif + +#ifndef CONFIG_SPL_BUILD +int board_early_init_r(void) +{ + read_otp_data(); + return 0; +} +#endif + +#ifdef CONFIG_MISC_INIT_R +#define GRF_IO_VSEL_BT565_SHIFT 0 +#define GRF_IO_VSEL_AUDIO_SHIFT 1 +#define GRF_IO_VSEL_SDMMC_SHIFT 2 +#define GRF_IO_VSEL_GPIO1830_SHIFT 3 + +#define PMUGRF_CON0_VSEL_SHIFT 8 +#define PMUGRF_CON0_PMU1830_VOL_SHIFT 9 +static void setup_iodomain(void) +{ + struct rk3399_grf_regs *grf = + syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + struct rk3399_pmugrf_regs *pmugrf = + syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); + + /* BT565 is in 1.8v domain */ + rk_setreg(&grf->io_vsel, 1 << GRF_IO_VSEL_BT565_SHIFT); + + /* AUDIO is in 1.8v domain */ + rk_setreg(&grf->io_vsel, 1 << GRF_IO_VSEL_AUDIO_SHIFT); + + /* SDMMC is in 3.0v domain */ + rk_setreg(&grf->io_vsel, 0 << GRF_IO_VSEL_SDMMC_SHIFT); + + /* GPIO1830 is in 3.0v domain */ + rk_setreg(&grf->io_vsel, 0 << GRF_IO_VSEL_GPIO1830_SHIFT); + + /* Set GPIO1 1.8v/3.0v source select to PMU1830_VOL */ + rk_setreg(&pmugrf->soc_con0, 1 << PMUGRF_CON0_VSEL_SHIFT); + rk_setreg(&pmugrf->soc_con0, 0 << PMUGRF_CON0_PMU1830_VOL_SHIFT); +} + +/* + * Swap mmc0 and mmc1 in boot_targets if booted from SD-Card. + * + * If bootsource is uSD-card we can assume that we want to use the + * SD-Card instead of the eMMC as first boot_target for distroboot. + * We only want to swap the defaults and not any custom environment a + * user has set. We exit early if a changed boot_targets environment + * is detected. + */ +static int setup_boottargets(void) +{ + const char *boot_device = + ofnode_read_chosen_string("u-boot,spl-boot-device"); + char *env_default, *env; + + if (!boot_device) { + debug("%s: /chosen/u-boot,spl-boot-device not set\n", + __func__); + return -1; + } + debug("%s: booted from %s\n", __func__, boot_device); + + env_default = env_get_default("boot_targets"); + env = env_get("boot_targets"); + if (!env) { + debug("%s: boot_targets does not exist\n", __func__); + return -1; + } + debug("%s: boot_targets current: %s - default: %s\n", + __func__, env, env_default); + + if (strcmp(env_default, env) != 0) { + debug("%s: boot_targets not default, don't change it\n", + __func__); + return 0; + } + + /* + * Only run, if booting from mmc1 (i.e. /mmc@fe320000) and + * only consider cases where the default boot-order first + * tries to boot from mmc0 (eMMC) and then from mmc1 + * (i.e. external SD). + * + * In other words: the SD card will be moved to earlier in the + * order, if U-Boot was also loaded from the SD-card. + */ + if (!strcmp(boot_device, "/mmc@fe320000")) { + char *mmc0, *mmc1; + + debug("%s: booted from SD-Card\n", __func__); + mmc0 = strstr(env, "mmc0"); + mmc1 = strstr(env, "mmc1"); + + if (!mmc0 || !mmc1) { + debug("%s: only one mmc boot_target found\n", __func__); + return -1; + } + + /* + * If mmc0 comes first in the boot order, we need to change + * the strings to make mmc1 first. + */ + if (mmc0 < mmc1) { + mmc0[3] = '1'; + mmc1[3] = '0'; + debug("%s: set boot_targets to: %s\n", __func__, env); + env_set("boot_targets", env); + } + } + + return 0; +} + +static void setup_leds(void) +{ + struct udevice *dev; + + led_get_by_label("helios64::status", &dev); + led_set_state(dev, LEDST_OFF); + mdelay(250); + led_set_state(dev, LEDST_ON); +} + +int misc_init_r(void) +{ + const u32 cpuid_offset = 0x7; + const u32 cpuid_length = 0x10; + u8 cpuid[cpuid_length]; + int ret; + + setup_iodomain(); + set_board_info(); + + ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid); + if (ret) + return ret; + + ret = rockchip_cpuid_set(cpuid, cpuid_length); + if (ret) + return ret; + + if (mac_read_from_otp()) + ret = rockchip_setup_macaddr(); + + setup_boottargets(); + setup_leds(); + + return ret; +} +#endif + +#ifdef CONFIG_ROCKCHIP_ADVANCED_RECOVERY +void rockchip_prepare_download_mode(void) +{ + struct gpio_desc *enable, *mux; + + if (gpio_hog_lookup_name("USB_MUX_OE#", &enable)) { + debug("Fail to get USB_MUX_OE\n"); + return; + } + + if (gpio_hog_lookup_name("USB_MUX_HS", &mux)) { + debug("Fail to get USB_MUX_HS\n"); + return; + } + + dm_gpio_set_value(enable, 0); + mdelay(100); + dm_gpio_set_value(mux, 1); + mdelay(100); + dm_gpio_set_value(enable, 1); +} +#endif + +#ifdef CONFIG_LAST_STAGE_INIT +static void auto_power_enable(void) +{ + struct gpio_desc *enable, *clock; + + if (gpio_hog_lookup_name("AUTO_ON_EN_D", &enable)) { + debug("Fail to get AUTO_ON_EN_D\n"); + return; + } + + if (gpio_hog_lookup_name("AUTO_ON_EN_CLK", &clock)) { + debug("Fail to get AUTO_ON_EN_CLK\n"); + return; + } + + dm_gpio_set_value(enable, 1); + dm_gpio_set_value(clock, 1); + mdelay(10); + dm_gpio_set_value(clock, 0); +} + +static void sata_power_enable(void) +{ + struct udevice *rail_a, *rail_b; + int ret; + + ret = regulator_get_by_platname("power_hdd_a", &rail_a); + if (!ret) { + ret = regulator_set_enable(rail_a, true); + if (!ret) + mdelay(10000); + } + + ret = regulator_get_by_platname("power_hdd_b", &rail_b); + if (!ret) + ret = regulator_set_enable(rail_b, true); + +} + +int last_stage_init(void) +{ + auto_power_enable(); + sata_power_enable(); + +#ifdef CONFIG_PCI + scsi_scan(true); +#endif + + return 0; +} +#endif + +#if defined(CONFIG_DISPLAY_BOARDINFO_LATE) +int checkboard(void) +{ + int major, minor; + + printf("Revision: "); + + if (!get_revision(&major, &minor)) + printf("%i.%i - %s\n", major, minor, get_variant()); + else + printf("UNKNOWN\n"); + + return 0; +} +#endif + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +int ft_board_setup(void *blob, struct bd_info *bd) +{ + char *env; + + env = env_get("board_rev"); + if (env) + fdt_setprop_string(blob, fdt_path_offset(blob, "/"), + "kobol,board-rev", env); + + env = env_get("cpuid#"); + if (env) + fdt_setprop_string(blob, fdt_path_offset(blob, "/"), + "kobol,cpu-id", env); + + return 0; +} +#endif diff --git a/board/kobol/helios64/sys_otp.c b/board/kobol/helios64/sys_otp.c new file mode 100644 index 0000000000..8c20693c0e --- /dev/null +++ b/board/kobol/helios64/sys_otp.c @@ -0,0 +1,250 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#include <linux/types.h> +#include <dm.h> +#include <spi.h> +#include <log.h> +#include <net.h> +#include <u-boot/crc.h> + +#include "sys_otp.h" + +#define OTP_DEVICE_BUS 0 +#define OTP_DEVICE_CS 0 +#define MAX_NUM_PORTS 2 + +enum board_variant { + BOARD_VARIANT_INVALID = 0, + BOARD_VARIANT_ENG_SAMPLE, + BOARD_VARIANT_4G_PROD_NO_ECC, + BOARD_VARIANT_MAX +}; + +struct __attribute__ ((__packed__)) otp_data_t { + u8 magic[8]; + u8 part_num[16]; + u8 variant; + u8 revision; + u8 serial_num[6]; + u8 mfg_year[2]; + u8 mfg_month; + u8 mfg_day; + u8 mac_addr[MAX_NUM_PORTS][6]; + u8 reserved[204]; + u32 checksum; +} otp; + +static struct spi_slave *slave; +static int has_been_read = 0; +static int data_valid = 0; + +static inline int is_data_valid(void) +{ + return data_valid; +} + +static inline int is_valid_header(void) +{ + if ((otp.magic[0] == 'H') || (otp.magic[1] == '6') || + (otp.magic[2] == '4') || (otp.magic[3] == 'N') || + (otp.magic[4] == 'P') || (otp.magic[5] == 'V') || + (otp.magic[6] == '1') || (otp.magic[7] == 0)) + + return 1; + + return 0; +} + +static int init_system_otp(int bus, int cs) +{ + int ret; + char name[30], *str; + struct udevice *dev; + + snprintf(name, sizeof(name), "generic_%d:%d", bus, cs); + str = strdup(name); + if (!str) + return -ENOMEM; + ret = spi_get_bus_and_cs(bus, cs, 25000000, CONFIG_DEFAULT_SPI_MODE, "spi_generic_drv", + str, &dev, &slave); + return ret; +} + +#ifdef DEBUG +/** + * show_otp_data - display the contents of the OTP register + */ +static void show_otp_data(void) +{ + u32 i; + u32 crc; + + const char* var_str[BOARD_VARIANT_MAX] = { + "Invalid variant", + "Engineering Sample", + "Production - 4GB non ECC" + }; + + printf("\n"); + printf("Register dump: (%lu bytes)\n", sizeof(otp)); + for (i = 0; i < sizeof(otp); i++) { + if ((i % 16) == 0) + printf("%02X: ", i); + printf("%02X ", ((u8 *)&otp)[i]); + if (((i % 16) == 15) || (i == sizeof(otp) - 1)) + printf("\n"); + } + + if (!is_valid_header()) + return; + + printf("Part Number: %s\n", otp.part_num); + printf("Variant: %s\n", var_str[otp.variant]); + printf("Revision: %x.%x\n", (otp.revision & 0xf0) >> 4, otp.revision & 0x0f); + printf("Serial Number: %012llx\n", *((uint64_t*) otp.serial_num) & + 0xFFFFFFFFFFFF); + printf("Manufacturing Date: %02X-%02X-%04X (DD-MM-YYYY)\n", otp.mfg_day, + otp.mfg_month, *(u16*) otp.mfg_year); + + printf("1GbE MAC Address: %02X:%02X:%02X:%02X:%02X:%02X\n", + otp.mac_addr[0][0], otp.mac_addr[0][1], otp.mac_addr[0][2], + otp.mac_addr[0][3], otp.mac_addr[0][4], otp.mac_addr[0][5]); + + printf("2.5GbE MAC Address: %02X:%02X:%02X:%02X:%02X:%02X\n", + otp.mac_addr[1][0], otp.mac_addr[1][1], otp.mac_addr[1][2], + otp.mac_addr[1][3], otp.mac_addr[1][4], otp.mac_addr[1][5]); + + crc = crc32(0, (void *)&otp, sizeof(otp) - 4); + + if (crc == le32_to_cpu(otp.checksum)) + printf("CRC: %08x\n\n", le32_to_cpu(otp.checksum)); + else + printf("CRC: %08x (should be %08x)\n\n", + le32_to_cpu(otp.checksum), crc); + +} +#endif + +int read_otp_data(void) +{ + int ret; + u8 dout[5]; + + if (has_been_read) { + if (is_data_valid()) + return 0; + else + goto data_invalid; + } + + ret = init_system_otp(OTP_DEVICE_BUS, OTP_DEVICE_CS); + if (ret) + return ret; + + ret = spi_claim_bus(slave); + if (ret) { + debug("SPI: Failed to claim SPI bus: %d\n", ret); + return ret; + } + + dout[0] = 0x48; + dout[1] = 0x00; + dout[2] = 0x10; /* Security Register #1 */ + dout[3] = 0x00; + dout[4] = 0x00; /* Dummy Byte */ + + ret = spi_write_then_read(slave, dout, sizeof(dout), NULL, (u8 *)&otp, + sizeof(otp)); + + spi_release_bus(slave); +#ifdef DEBUG + show_otp_data(); +#endif + + has_been_read = (ret == 0) ? 1 : 0; + if (!is_valid_header()) + goto data_invalid; + + if (crc32(0, (void *)&otp, sizeof(otp) - 4) == + le32_to_cpu(otp.checksum)) + data_valid = 1; + + if (!is_data_valid()) + goto data_invalid; + + return 0; + +data_invalid: + printf("Invalid board ID data!\n"); + return -1; +} + +int get_revision(int *major, int *minor) +{ + if (!is_data_valid()) + return -1; + + *major = (otp.revision & 0xf0) >> 4; + *minor = otp.revision & 0x0f; + + return 0; +} + +const char *get_variant(void) +{ + const char* var_str[BOARD_VARIANT_MAX] = { + "Unknown", + "Engineering Sample", + "4GB non ECC" + }; + + if ((otp.variant < BOARD_VARIANT_ENG_SAMPLE) || + (otp.variant >= BOARD_VARIANT_MAX)) + return var_str[0]; + + return var_str[otp.variant]; +} + +void set_board_info(void) +{ + char env_str[13]; + + if (!is_data_valid()) + return; + + snprintf(env_str, sizeof(env_str), "%i.%i", (otp.revision & 0xf0) >> 4, otp.revision & 0x0f); + env_set("board_rev", env_str); + + sprintf(env_str, "%012llx", *((uint64_t*) otp.serial_num) & + 0xFFFFFFFFFFFF); + + env_set("serial#", env_str); +} + +int mac_read_from_otp(void) +{ + unsigned int i; + int ret; + + if (!is_data_valid()) + return -1; + + for (i = 0; i < MAX_NUM_PORTS; i++) { + char enetvar[9]; + + sprintf(enetvar, i ? "eth%daddr" : "ethaddr", i); + + if (!is_valid_ethaddr(otp.mac_addr[i])) { + debug("Not valid %s!\n", enetvar); + continue; + } + + /* Only initialize environment variables that are blank + * (i.e. have not yet been set) + */ + if (!env_get(enetvar)) + eth_env_set_enetaddr(enetvar, otp.mac_addr[i]); + } + + return ret; +} diff --git a/board/kobol/helios64/sys_otp.h b/board/kobol/helios64/sys_otp.h new file mode 100644 index 0000000000..48273d4a95 --- /dev/null +++ b/board/kobol/helios64/sys_otp.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __HELIOS64_SYS_OTP_H +#define __HELIOS64_SYS_OTP_H + +int read_otp_data(void); +void set_board_info(void); +int get_revision(int *major, int *minor); +const char *get_variant(void); +int mac_read_from_otp(void); + +#endif diff --git a/configs/helios64-rk3399_defconfig b/configs/helios64-rk3399_defconfig new file mode 100644 index 0000000000..3b4ed62ab6 --- /dev/null +++ b/configs/helios64-rk3399_defconfig @@ -0,0 +1,147 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_ENV_OFFSET=0x3F8000 +CONFIG_ROCKCHIP_RK3399=y +CONFIG_ROCKCHIP_ADVANCED_RECOVERY=y +CONFIG_ROCKCHIP_ADVANCED_RECOVERY_LED="helios64::status" +# CONFIG_ROCKCHIP_ADVANCED_RECOVERY_ROCKUSB is not set +CONFIG_TARGET_HELIOS64=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEBUG_UART_BASE=0xFF1A0000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_DEBUG_UART=y +CONFIG_AHCI=y +# CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_OF_BOARD_SETUP=y +CONFIG_USE_PREBOOT=y +CONFIG_CONSOLE_MUX=y +CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-kobol-helios64.dtb" +CONFIG_MISC_INIT_R=y +CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_BOARD_TYPES=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_LAST_STAGE_INIT=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_TPL=y +CONFIG_CMD_CONFIG=y +CONFIG_CMD_BOOTZ=y +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_BOOTM_VXWORKS is not set +CONFIG_CMD_BOOTEFI_HELLO=y +CONFIG_CMD_BOOTMENU=y +CONFIG_CRC32_VERIFY=y +CONFIG_CMD_MD5SUM=y +CONFIG_MD5SUM_VERIFY=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MX_CYCLIC=y +CONFIG_CMD_SHA1SUM=y +CONFIG_SHA1SUM_VERIFY=y +CONFIG_CMD_STRINGS=y +CONFIG_CMD_ADC=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_POWEROFF=y +CONFIG_CMD_READ=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_ROCKUSB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_EFIDEBUG=y +CONFIG_CMD_EXCEPTION=y +CONFIG_CMD_TIME=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_FS_UUID=y +CONFIG_PARTITION_TYPE_GUID=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_DEFAULT_DEVICE_TREE="rk3399-kobol-helios64" +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_IP_DEFRAG=y +# CONFIG_DM_DEVICE_REMOVE is not set +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y +CONFIG_SPL_FIRMWARE=y +CONFIG_GPIO_HOG=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_I2C_DEFAULT_BUS_NUMBER=0x8 +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_MISC=y +CONFIG_ROCKCHIP_EFUSE=y +CONFIG_ROCKCHIP_OTP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y +CONFIG_PHY_GIGE=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_RGMII=y +CONFIG_MII=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PCI=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_TYPEC=y +CONFIG_DM_PMIC_FAN53555=y +CONFIG_PMIC_RK8XX=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_REGULATOR_PWM=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_DM_REGULATOR_GPIO=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM_RK3399_LPDDR4=y +CONFIG_DM_RESET=y +CONFIG_DM_RNG=y +CONFIG_RNG_ROCKCHIP=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_ROCKCHIP_SPI=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_SYSCON=y +CONFIG_DM_THERMAL=y +CONFIG_USB=y +# CONFIG_SPL_DM_USB is not set +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_GADGET=y +CONFIG_USB_FUNCTION_ROCKUSB=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_ERRNO_STR=y +CONFIG_HEXDUMP=y diff --git a/include/configs/helios64.h b/include/configs/helios64.h new file mode 100644 index 0000000000..6fca9a6be0 --- /dev/null +++ b/include/configs/helios64.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2020 Aditya Prayoga <aditya(a)kobol.io> + */ + +#ifndef __HELIOS64_H +#define __HELIOS64_H + +#include <configs/rk3399_common.h> + +#define SDRAM_BANK_SIZE (2UL << 30) + +#if defined(CONFIG_ENV_IS_IN_MMC) + #define CONFIG_SYS_MMC_ENV_DEV 0 +#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH) + #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS + #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS + #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE + #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#endif + + +#ifndef CONFIG_SPL_BUILD +#if CONFIG_IS_ENABLED(SCSI) + + #define CONFIG_SYS_SCSI_MAX_SCSI_ID 5 + #define CONFIG_SYS_SCSI_MAX_LUN 1 + #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) + + #define BOOT_TARGET_SCSI(func) \ + func(SCSI, scsi, 0) +#else + #define BOOT_TARGET_SCSI(func) +#endif + +#undef BOOT_TARGET_DEVICES +#define BOOT_TARGET_DEVICES(func) \ + BOOT_TARGET_MMC(func) \ + BOOT_TARGET_USB(func) \ + BOOT_TARGET_SCSI(func) \ + BOOT_TARGET_PXE(func) \ + BOOT_TARGET_DHCP(func) + +#endif + +#endif -- 2.29.2

3 3

[PATCH] spi: zynqmp_gqspi: Simplify baud_rate_val calculation
by Michal Simek 30 Mar '21

30 Mar '21

Condition to setup GQSPI_DFLT_BAUD_RATE_VAL(number 2) in case when baud_rate_val is more then 7 is wrong. There should be really the biggest possible value which is 7. This can be achieve in easier way by enabling calculation till GQSPI_MAX_BAUD_RATE_VAL. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- drivers/spi/zynqmp_gqspi.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c index f8d13d193e30..900cb2610c7f 100644 --- a/drivers/spi/zynqmp_gqspi.c +++ b/drivers/spi/zynqmp_gqspi.c @@ -324,14 +324,10 @@ static int zynqmp_qspi_set_speed(struct udevice *bus, uint speed) if (plat->speed_hz != speed) { /* Set the clock frequency */ /* If speed == 0, default to lowest speed */ - while ((baud_rate_val < 8) && - ((plat->frequency / - (2 << baud_rate_val)) > speed)) + while (baud_rate_val < GQSPI_MAX_BAUD_RATE_VAL && + (plat->frequency / (2 << baud_rate_val)) > speed) baud_rate_val++; - if (baud_rate_val > GQSPI_MAX_BAUD_RATE_VAL) - baud_rate_val = GQSPI_DFLT_BAUD_RATE_VAL; - plat->speed_hz = plat->frequency / (2 << baud_rate_val); confr = readl(&regs->confr); -- 2.30.1

2 1

[PATCH 0/3] ARM: bitmain: Extend bitmain S9 board
by Michal Simek 30 Mar '21

30 Mar '21

Hi, a lot of these boards are very cheap to buy now. Get this board up to date based on latest features available for zynq. Thanks, Michal Michal Simek (3): ARM: bitmain: Enable nand and smcc drivers ARM: bitmain: Enable legacy u-boot format ARM: bitmain: Enable saving variables to SD card arch/arm/dts/bitmain-antminer-s9.dts | 8 ++++++++ configs/bitmain_antminer_s9_defconfig | 2 ++ 2 files changed, 10 insertions(+) -- 2.31.0

2 4

[PATCH] spi: xilinx_spi: Trivial fixes in axi qspi driver
by Michal Simek 30 Mar '21

30 Mar '21

From: T Karthik Reddy <t.karthik.reddy(a)xilinx.com> Use __func__ instead for function name in debug. Use Linux style u32 instead of uint32_t. Signed-off-by: T Karthik Reddy <t.karthik.reddy(a)xilinx.com> Acked-by: Ashok Reddy Soma <ashok.reddy.soma(a)xilinx.com> Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- drivers/spi/xilinx_spi.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c index 0274afdc6e0d..b892cdae9bab 100644 --- a/drivers/spi/xilinx_spi.c +++ b/drivers/spi/xilinx_spi.c @@ -314,8 +314,7 @@ static int xilinx_spi_set_speed(struct udevice *bus, uint speed) priv->freq = speed; - debug("xilinx_spi_set_speed: regs=%p, speed=%d\n", priv->regs, - priv->freq); + debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq); return 0; } @@ -324,7 +323,7 @@ static int xilinx_spi_set_mode(struct udevice *bus, uint mode) { struct xilinx_spi_priv *priv = dev_get_priv(bus); struct xilinx_spi_regs *regs = priv->regs; - uint32_t spicr; + u32 spicr; spicr = readl(&regs->spicr); if (mode & SPI_LSB_FIRST) @@ -339,8 +338,7 @@ static int xilinx_spi_set_mode(struct udevice *bus, uint mode) writel(spicr, &regs->spicr); priv->mode = mode; - debug("xilinx_spi_set_mode: regs=%p, mode=%d\n", priv->regs, - priv->mode); + debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode); return 0; } -- 2.30.1

2 1

[PATCH] xilinx: Sync DTs with Linux kernel
by Michal Simek 30 Mar '21

30 Mar '21

There are several changes which happen in mainline kernel which should get also to U-Boot. Here is the list of patches from the kernel: - ARM: zynq: Fix leds subnode name for zc702/zybo-z7 - arm64: dts: zynqmp: Fix leds subnode name for zcu100/ultra96 v1 - arm64: dts: zynqmp: Fix u48 si5382 chip on zcu111 - arm64: dts: zynqmp: Wire up the DisplayPort subsystem - arm64: dts: zynqmp: Add DisplayPort subsystem - arm64: dts: zynqmp: Add DPDMA node - arm64: dts: zynqmp: Enable phy driver for Sata on zcu102/zcu104/zcu106 - arm64: dts: zynqmp: Enable si5341 driver for zcu102/106/111 - arm64: dts: zynqmp: Add DT description for si5328 for zcu102/zcu106 - arm64: dts: zynqmp-zcu100-revC: correct interrupt flags - arm64: dts: xilinx: align GPIO hog names with dtschema - arm64: zynqmp: Add Xilinx AES node - dt: bindings: dma: xilinx: dpdma: DT bindings for Xilinx DPDMA but also some other changes have been done. - Using only one compatible string for adxl345 on zturn - Remove Xilinx internal DP bindings - Remove USB3.0 serdes configurations - Remove SATA serdes configuration for zc1232 - Resort nvmem_firmware - Update nand compatible string - Aling power-domains property for sd0/1 Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- arch/arm/dts/zynq-zc702.dts | 2 +- arch/arm/dts/zynq-zturn-common.dtsi | 2 +- arch/arm/dts/zynq-zybo-z7.dts | 2 +- arch/arm/dts/zynqmp-clk-ccf.dtsi | 16 +- arch/arm/dts/zynqmp-g-a2197-00-revA.dts | 3 - arch/arm/dts/zynqmp-m-a2197-01-revA.dts | 3 - arch/arm/dts/zynqmp-zc1232-revA.dts | 2 - arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts | 19 +-- arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts | 2 +- arch/arm/dts/zynqmp-zcu100-revC.dts | 48 ++++-- arch/arm/dts/zynqmp-zcu102-revA.dts | 106 ++++++++++---- arch/arm/dts/zynqmp-zcu104-revA.dts | 44 +++++- arch/arm/dts/zynqmp-zcu104-revC.dts | 44 +++++- arch/arm/dts/zynqmp-zcu106-revA.dts | 96 ++++++++++-- arch/arm/dts/zynqmp-zcu111-revA.dts | 78 ++++++++-- arch/arm/dts/zynqmp-zcu208-revA.dts | 58 ++++++-- arch/arm/dts/zynqmp-zcu216-revA.dts | 58 ++++++-- arch/arm/dts/zynqmp.dtsi | 154 +++++--------------- include/dt-bindings/dma/xlnx-zynqmp-dpdma.h | 16 ++ 19 files changed, 498 insertions(+), 255 deletions(-) create mode 100644 include/dt-bindings/dma/xlnx-zynqmp-dpdma.h diff --git a/arch/arm/dts/zynq-zc702.dts b/arch/arm/dts/zynq-zc702.dts index b043d341d680..e45eba3d90b3 100644 --- a/arch/arm/dts/zynq-zc702.dts +++ b/arch/arm/dts/zynq-zc702.dts @@ -51,7 +51,7 @@ leds { compatible = "gpio-leds"; - ds23 { + led-ds23 { label = "ds23"; gpios = <&gpio0 10 0>; linux,default-trigger = "heartbeat"; diff --git a/arch/arm/dts/zynq-zturn-common.dtsi b/arch/arm/dts/zynq-zturn-common.dtsi index 1d7af02893dc..486b6fa2e1b8 100644 --- a/arch/arm/dts/zynq-zturn-common.dtsi +++ b/arch/arm/dts/zynq-zturn-common.dtsi @@ -112,7 +112,7 @@ }; accelerometer@53 { - compatible = "adi,adxl345", "adxl345", "adi,adxl34x", "adxl34x"; + compatible = "adi,adxl345"; reg = <0x53>; interrupt-parent = <&intc>; interrupts = <0x0 0x1e 0x4>; diff --git a/arch/arm/dts/zynq-zybo-z7.dts b/arch/arm/dts/zynq-zybo-z7.dts index 3f8a3bfa0ff7..116958ec97aa 100644 --- a/arch/arm/dts/zynq-zybo-z7.dts +++ b/arch/arm/dts/zynq-zybo-z7.dts @@ -31,7 +31,7 @@ gpio-leds { compatible = "gpio-leds"; - ld4 { + led-ld4 { label = "zynq-zybo-z7:green:ld4"; gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm/dts/zynqmp-clk-ccf.dtsi b/arch/arm/dts/zynqmp-clk-ccf.dtsi index b02ef22abd20..987792e5c511 100644 --- a/arch/arm/dts/zynqmp-clk-ccf.dtsi +++ b/arch/arm/dts/zynqmp-clk-ccf.dtsi @@ -284,18 +284,16 @@ clocks = <&zynqmp_clk AMS_REF>; }; -&zynqmp_dpsub { - clocks = <&dp_aclk>, <&zynqmp_clk DP_AUDIO_REF>, <&zynqmp_clk DP_VIDEO_REF>; +&zynqmp_pcap { + clocks = <&zynqmp_clk PCAP>; }; -&xlnx_dpdma { +&zynqmp_dpdma { clocks = <&zynqmp_clk DPDMA_REF>; }; -&zynqmp_dp_snd_codec0 { - clocks = <&zynqmp_clk DP_AUDIO_REF>; -}; - -&zynqmp_pcap { - clocks = <&zynqmp_clk PCAP>; +&zynqmp_dpsub { + clocks = <&zynqmp_clk TOPSW_LSBUS>, + <&zynqmp_clk DP_AUDIO_REF>, + <&zynqmp_clk DP_VIDEO_REF>; }; diff --git a/arch/arm/dts/zynqmp-g-a2197-00-revA.dts b/arch/arm/dts/zynqmp-g-a2197-00-revA.dts index 9468dc574fd8..f94b797d1a24 100644 --- a/arch/arm/dts/zynqmp-g-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-g-a2197-00-revA.dts @@ -88,9 +88,6 @@ reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>; /* xlnx,phy-type = <PHY_TYPE_SGMII>; */ }; -/* phy-names = "..."; - phys = <&lane0 PHY_TYPE_SGMII ... > - Note: lane0 sgmii/lane1 usb3 */ }; &gpio { diff --git a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts index 66ea02e5be7f..19e1ebdb1d6a 100644 --- a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts +++ b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts @@ -118,9 +118,6 @@ reg = <0>; /* xlnx,phy-type = <PHY_TYPE_SGMII>; */ }; -/* phy-names = "..."; - phys = <&lane0 PHY_TYPE_SGMII ... > - Note: lane0 sgmii/lane1 usb3 */ }; &gpio { diff --git a/arch/arm/dts/zynqmp-zc1232-revA.dts b/arch/arm/dts/zynqmp-zc1232-revA.dts index afb3e96520b8..ef7cf0a36b21 100644 --- a/arch/arm/dts/zynqmp-zc1232-revA.dts +++ b/arch/arm/dts/zynqmp-zc1232-revA.dts @@ -78,8 +78,6 @@ ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; - phy-names = "sata-phy"; - phys = <&lane0 PHY_TYPE_SATA 0 0 125000000>, <&lane1 PHY_TYPE_SATA 1 1 125000000>; }; &uart0 { diff --git a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts index e2428ec974a3..b8c5efb6a914 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts @@ -175,26 +175,11 @@ dr_mode = "host"; }; -&zynqmp_dpsub { - status = "okay"; -}; - -&zynqmp_dp_snd_pcm0 { - status = "okay"; -}; - -&zynqmp_dp_snd_pcm1 { +&zynqmp_dpdma { status = "okay"; }; -&zynqmp_dp_snd_card0 { - status = "okay"; -}; - -&zynqmp_dp_snd_codec0 { +&zynqmp_dpsub { status = "okay"; }; -&xlnx_dpdma { - status = "okay"; -}; diff --git a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts index 9b38b8b919e2..aadda179c323 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts @@ -119,7 +119,7 @@ status = "okay"; }; -&xlnx_dpdma { +&zynqmp_dpdma { status = "okay"; }; diff --git a/arch/arm/dts/zynqmp-zcu100-revC.dts b/arch/arm/dts/zynqmp-zcu100-revC.dts index d6c914c917f5..bbcc69c79673 100644 --- a/arch/arm/dts/zynqmp-zcu100-revC.dts +++ b/arch/arm/dts/zynqmp-zcu100-revC.dts @@ -69,27 +69,27 @@ leds { compatible = "gpio-leds"; - ds2 { + led-ds2 { label = "ds2"; gpios = <&gpio 20 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; - ds3 { + led-ds3 { label = "ds3"; gpios = <&gpio 19 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0tx"; /* WLAN tx */ default-state = "off"; }; - ds4 { + led-ds4 { label = "ds4"; gpios = <&gpio 18 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0rx"; /* WLAN rx */ default-state = "off"; }; - ds5 { + led-ds5 { label = "ds5"; gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; linux,default-trigger = "bluetooth-power"; @@ -130,6 +130,18 @@ compatible = "iio-hwmon"; io-channels = <&u35 0>, <&u35 1>, <&u35 2>, <&u35 3>; }; + + si5335a_0: clk26 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + }; + + si5335a_1: clk27 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <27000000>; + }; }; &dcc { @@ -212,7 +224,7 @@ compatible = "ti,tps65086"; reg = <0x5e>; interrupt-parent = <&gpio>; - interrupts = <77 GPIO_ACTIVE_LOW>; + interrupts = <77 IRQ_TYPE_LEVEL_LOW>; #gpio-cells = <2>; gpio-controller; }; @@ -250,6 +262,13 @@ }; }; +&psgtr { + status = "okay"; + /* usb3, dps */ + clocks = <&si5335a_0>, <&si5335a_1>; + clock-names = "ref0", "ref1"; +}; + &rtc { status = "okay"; }; @@ -281,10 +300,6 @@ }; }; -&serdes { - status = "okay"; -}; - &spi0 { /* Low Speed connector */ status = "okay"; label = "LS-SPI0"; @@ -318,8 +333,6 @@ &dwc3_0 { status = "okay"; dr_mode = "peripheral"; - phy-names = "usb3-phy"; - phys = <&lane2 PHY_TYPE_USB3 0 0 26000000>; maximum-speed = "super-speed"; }; @@ -331,8 +344,6 @@ &dwc3_1 { status = "okay"; dr_mode = "host"; - phy-names = "usb3-phy"; - phys = <&lane3 PHY_TYPE_USB3 1 0 26000000>; maximum-speed = "super-speed"; }; @@ -347,3 +358,14 @@ &ams_ps { status = "okay"; }; + +&zynqmp_dpdma { + status = "okay"; +}; + +&zynqmp_dpsub { + status = "okay"; + phy-names = "dp-phy0", "dp-phy1"; + phys = <&psgtr 1 PHY_TYPE_DP 0 1>, + <&psgtr 0 PHY_TYPE_DP 1 1>; +}; diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts index ed036e68f5e3..9323b8d64d56 100644 --- a/arch/arm/dts/zynqmp-zcu102-revA.dts +++ b/arch/arm/dts/zynqmp-zcu102-revA.dts @@ -137,6 +137,19 @@ compatible = "iio-hwmon"; io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>; }; + + /* 48MHz reference crystal */ + ref48: ref48M { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + }; + + refhdmi: refhdmi { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <114285000>; + }; }; &can1 { @@ -213,25 +226,25 @@ gpio-line-names = "PS_GTR_LAN_SEL0", "PS_GTR_LAN_SEL1", "PS_GTR_LAN_SEL2", "PS_GTR_LAN_SEL3", "PCI_CLK_DIR_SEL", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "", "", "", "", "", "", "", "", ""; - gtr-sel0 { + gtr-sel0-hog { gpio-hog; gpios = <0 0>; output-low; /* PCIE = 0, DP = 1 */ line-name = "sel0"; }; - gtr-sel1 { + gtr-sel1-hog { gpio-hog; gpios = <1 0>; output-high; /* PCIE = 0, DP = 1 */ line-name = "sel1"; }; - gtr-sel2 { + gtr-sel2-hog { gpio-hog; gpios = <2 0>; output-high; /* PCIE = 0, USB0 = 1 */ line-name = "sel2"; }; - gtr-sel3 { + gtr-sel3-hog { gpio-hog; gpios = <3 0>; output-high; /* PCIE = 0, SATA = 1 */ @@ -494,8 +507,54 @@ si5341: clock-generator@36 { /* SI5341 - u69 */ compatible = "silabs,si5341"; reg = <0x36>; + #clock-cells = <2>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&ref48>; + clock-names = "xtal"; + clock-output-names = "si5341"; + + si5341_0: out@0 { + /* refclk0 for PS-GT, used for DP */ + reg = <0>; + always-on; + }; + si5341_2: out@2 { + /* refclk2 for PS-GT, used for USB3 */ + reg = <2>; + always-on; + }; + si5341_3: out@3 { + /* refclk3 for PS-GT, used for SATA */ + reg = <3>; + always-on; + }; + si5341_4: out@4 { + /* refclk4 for PS-GT, used for PCIE slot */ + reg = <4>; + always-on; + }; + si5341_5: out@5 { + /* refclk5 for PS-GT, used for PCIE */ + reg = <5>; + always-on; + }; + si5341_6: out@6 { + /* refclk6 PL CLK125 */ + reg = <6>; + always-on; + }; + si5341_7: out@7 { + /* refclk7 PL CLK74 */ + reg = <7>; + always-on; + }; + si5341_9: out@9 { + /* refclk9 used for PS_REF_CLK 33.3 MHz */ + reg = <9>; + always-on; + }; }; - }; i2c@2 { #address-cells = <1>; @@ -603,6 +662,13 @@ status = "okay"; }; +&psgtr { + status = "okay"; + /* pcie, sata, usb3, dp */ + clocks = <&si5341 0 5>, <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>; + clock-names = "ref0", "ref1", "ref2", "ref3"; +}; + &qspi { status = "okay"; is-dual = <1>; @@ -649,7 +715,7 @@ ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; - phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>; + phys = <&psgtr 3 PHY_TYPE_SATA 1 1>; }; /* SD1 with level shifter */ @@ -663,10 +729,6 @@ xlnx,mio-bank = <1>; }; -&serdes { - status = "okay"; -}; - &uart0 { status = "okay"; }; @@ -684,8 +746,6 @@ status = "okay"; dr_mode = "host"; snps,usb3_lpm_capable; - phy-names = "usb3-phy"; - phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>; maximum-speed = "super-speed"; }; @@ -705,26 +765,12 @@ status = "okay"; }; -&zynqmp_dpsub { +&zynqmp_dpdma { status = "okay"; }; -&zynqmp_dp_snd_codec0 { - status = "okay"; -}; - -&zynqmp_dp_snd_pcm0 { - status = "okay"; -}; - -&zynqmp_dp_snd_pcm1 { - status = "okay"; -}; - -&zynqmp_dp_snd_card0 { - status = "okay"; -}; - -&xlnx_dpdma { +&zynqmp_dpsub { status = "okay"; + phy-names = "dp-phy0"; + phys = <&psgtr 1 PHY_TYPE_DP 0 3>; }; diff --git a/arch/arm/dts/zynqmp-zcu104-revA.dts b/arch/arm/dts/zynqmp-zcu104-revA.dts index cb8ffdff9771..a95bd4922a62 100644 --- a/arch/arm/dts/zynqmp-zcu104-revA.dts +++ b/arch/arm/dts/zynqmp-zcu104-revA.dts @@ -40,6 +40,24 @@ device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>; }; + + clock_8t49n287_5: clk125 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; + + clock_8t49n287_2: clk26 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + }; + + clock_8t49n287_3: clk27 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <27000000>; + }; }; &can1 { @@ -226,6 +244,13 @@ }; }; +&psgtr { + status = "okay"; + /* nc, sata, usb3, dp */ + clocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>; + clock-names = "ref1", "ref2", "ref3"; +}; + &rtc { status = "okay"; }; @@ -242,7 +267,7 @@ ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; - phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>; + phys = <&psgtr 3 PHY_TYPE_SATA 1 1>; }; /* SD1 with level shifter */ @@ -253,10 +278,6 @@ disable-wp; }; -&serdes { - status = "okay"; -}; - &uart0 { status = "okay"; }; @@ -274,8 +295,6 @@ status = "okay"; dr_mode = "host"; snps,usb3_lpm_capable; - phy-names = "usb3-phy"; - phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>; maximum-speed = "super-speed"; }; @@ -294,3 +313,14 @@ &ams_pl { status = "okay"; }; + +&zynqmp_dpdma { + status = "okay"; +}; + +&zynqmp_dpsub { + status = "okay"; + phy-names = "dp-phy0", "dp-phy1"; + phys = <&psgtr 1 PHY_TYPE_DP 0 3>, + <&psgtr 0 PHY_TYPE_DP 1 3>; +}; diff --git a/arch/arm/dts/zynqmp-zcu104-revC.dts b/arch/arm/dts/zynqmp-zcu104-revC.dts index e203280f0eca..8f30a2883e27 100644 --- a/arch/arm/dts/zynqmp-zcu104-revC.dts +++ b/arch/arm/dts/zynqmp-zcu104-revC.dts @@ -46,6 +46,24 @@ compatible = "iio-hwmon"; io-channels = <&u183 0>, <&u183 1>, <&u183 2>, <&u183 3>; }; + + clock_8t49n287_5: clk125 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; + + clock_8t49n287_2: clk26 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + }; + + clock_8t49n287_3: clk27 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <27000000>; + }; }; &can1 { @@ -243,6 +261,13 @@ status = "okay"; }; +&psgtr { + status = "okay"; + /* nc, sata, usb3, dp */ + clocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>; + clock-names = "ref1", "ref2", "ref3"; +}; + &sata { status = "okay"; /* SATA OOB timing settings */ @@ -255,7 +280,7 @@ ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; - phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>; + phys = <&psgtr 3 PHY_TYPE_SATA 1 1>; }; /* SD1 with level shifter */ @@ -266,10 +291,6 @@ disable-wp; }; -&serdes { - status = "okay"; -}; - &uart0 { status = "okay"; }; @@ -287,8 +308,6 @@ status = "okay"; dr_mode = "host"; snps,usb3_lpm_capable; - phy-names = "usb3-phy"; - phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>; maximum-speed = "super-speed"; }; @@ -307,3 +326,14 @@ &ams_pl { status = "okay"; }; + +&zynqmp_dpdma { + status = "okay"; +}; + +&zynqmp_dpsub { + status = "okay"; + phy-names = "dp-phy0", "dp-phy1"; + phys = <&psgtr 1 PHY_TYPE_DP 0 3>, + <&psgtr 0 PHY_TYPE_DP 1 3>; +}; diff --git a/arch/arm/dts/zynqmp-zcu106-revA.dts b/arch/arm/dts/zynqmp-zcu106-revA.dts index 1dff845ceeb6..971f76f1cabe 100644 --- a/arch/arm/dts/zynqmp-zcu106-revA.dts +++ b/arch/arm/dts/zynqmp-zcu106-revA.dts @@ -137,6 +137,19 @@ compatible = "iio-hwmon"; io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>; }; + + /* 48MHz reference crystal */ + ref48: ref48M { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + }; + + refhdmi: refhdmi { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <114285000>; + }; }; &can1 { @@ -147,6 +160,18 @@ status = "okay"; }; +&zynqmp_dpdma { + status = "okay"; +}; + +&zynqmp_dpsub { + status = "okay"; + phy-names = "dp-phy0", "dp-phy1"; + phys = <&psgtr 1 PHY_TYPE_DP 0 3>, + <&psgtr 0 PHY_TYPE_DP 1 3>; +}; + +/* fpd_dma clk 667MHz, lpd_dma 500MHz */ &fpd_dma_chan1 { status = "okay"; }; @@ -490,8 +515,45 @@ #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u69 */ - compatible = "si5341"; + compatible = "silabs,si5341"; reg = <0x36>; + #clock-cells = <2>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&ref48>; + clock-names = "xtal"; + clock-output-names = "si5341"; + + si5341_0: out@0 { + /* refclk0 for PS-GT, used for DP */ + reg = <0>; + always-on; + }; + si5341_2: out@2 { + /* refclk2 for PS-GT, used for USB3 */ + reg = <2>; + always-on; + }; + si5341_3: out@3 { + /* refclk3 for PS-GT, used for SATA */ + reg = <3>; + always-on; + }; + si5341_6: out@6 { + /* refclk6 PL CLK125 */ + reg = <6>; + always-on; + }; + si5341_7: out@7 { + /* refclk7 PL CLK74 */ + reg = <7>; + always-on; + }; + si5341_9: out@9 { + /* refclk9 used for PS_REF_CLK 33.3 MHz */ + reg = <9>; + always-on; + }; }; }; @@ -528,8 +590,23 @@ #size-cells = <0>; reg = <4>; si5328: clock-generator@69 {/* SI5328 - u20 */ - compatible = "silabs,si5328"; reg = <0x69>; + /* + * Chip has interrupt present connected to PL + * interrupt-parent = <&>; + * interrupts = <>; + */ + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <1>; + clocks = <&refhdmi>; + clock-names = "xtal"; + clock-output-names = "si5328"; + + si5328_clk: clk0@0 { + reg = <0>; + clock-frequency = <27000000>; + }; }; }; i2c@5 { @@ -601,6 +678,13 @@ }; }; +&psgtr { + status = "okay"; + /* nc, sata, usb3, dp */ + clocks = <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>; + clock-names = "ref1", "ref2", "ref3"; +}; + &qspi { status = "okay"; is-dual = <1>; @@ -647,7 +731,7 @@ ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; - phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>; + phys = <&psgtr 3 PHY_TYPE_SATA 1 1>; }; /* SD1 with level shifter */ @@ -660,10 +744,6 @@ xlnx,mio-bank = <1>; }; -&serdes { - status = "okay"; -}; - &uart0 { status = "okay"; }; @@ -681,8 +761,6 @@ status = "okay"; dr_mode = "host"; snps,usb3_lpm_capable; - phy-names = "usb3-phy"; - phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>; }; &watchdog0 { diff --git a/arch/arm/dts/zynqmp-zcu111-revA.dts b/arch/arm/dts/zynqmp-zcu111-revA.dts index 82e6c8d3cdfd..9e47008542ae 100644 --- a/arch/arm/dts/zynqmp-zcu111-revA.dts +++ b/arch/arm/dts/zynqmp-zcu111-revA.dts @@ -121,6 +121,13 @@ compatible = "iio-hwmon"; io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; }; + + /* 48MHz reference crystal */ + ref48: ref48M { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + }; }; &dcc { @@ -386,10 +393,46 @@ #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u46 */ - compatible = "si5341"; + compatible = "silabs,si5341"; reg = <0x36>; + #clock-cells = <2>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&ref48>; + clock-names = "xtal"; + clock-output-names = "si5341"; + + si5341_0: out@0 { + /* refclk0 for PS-GT, used for DP */ + reg = <0>; + always-on; + }; + si5341_2: out@2 { + /* refclk2 for PS-GT, used for USB3 */ + reg = <2>; + always-on; + }; + si5341_3: out@3 { + /* refclk3 for PS-GT, used for SATA */ + reg = <3>; + always-on; + }; + si5341_5: out@5 { + /* refclk5 PL CLK100 */ + reg = <5>; + always-on; + }; + si5341_6: out@6 { + /* refclk6 PL CLK125 */ + reg = <6>; + always-on; + }; + si5341_9: out@9 { + /* refclk9 used for PS_REF_CLK 33.3 MHz */ + reg = <9>; + always-on; + }; }; - }; i2c@2 { #address-cells = <1>; @@ -423,8 +466,8 @@ #address-cells = <1>; #size-cells = <0>; reg = <4>; - si5328: clock-generator@69 { /* SI5328 - u48 */ - compatible = "silabs,si5328"; + si5382: clock-generator@69 { /* SI5382 - u48 */ + compatible = "silabs,si5382"; reg = <0x69>; }; }; @@ -511,6 +554,13 @@ }; }; +&psgtr { + status = "okay"; + /* nc, sata, usb3, dp */ + clocks = <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>; + clock-names = "ref1", "ref2", "ref3"; +}; + &qspi { status = "okay"; is-dual = <1>; @@ -557,7 +607,7 @@ ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; - phys = <&lane3 PHY_TYPE_SATA 1 3 125000000>; + phys = <&psgtr 3 PHY_TYPE_SATA 1 1>; }; /* SD1 with level shifter */ @@ -571,10 +621,6 @@ xlnx,mio-bank = <1>; }; -&serdes { - status = "okay"; -}; - &uart0 { status = "okay"; }; @@ -582,12 +628,16 @@ /* ULPI SMSC USB3320 */ &usb0 { status = "okay"; + dr_mode = "host"; }; -&dwc3_0 { +&zynqmp_dpdma { status = "okay"; - dr_mode = "host"; - snps,usb3_lpm_capable; - phy-names = "usb3-phy"; - phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>; +}; + +&zynqmp_dpsub { + status = "okay"; + phy-names = "dp-phy0", "dp-phy1"; + phys = <&psgtr 1 PHY_TYPE_DP 0 1>, + <&psgtr 0 PHY_TYPE_DP 1 1>; }; diff --git a/arch/arm/dts/zynqmp-zcu208-revA.dts b/arch/arm/dts/zynqmp-zcu208-revA.dts index 268e368b7657..0e114cdacb1a 100644 --- a/arch/arm/dts/zynqmp-zcu208-revA.dts +++ b/arch/arm/dts/zynqmp-zcu208-revA.dts @@ -120,6 +120,13 @@ compatible = "iio-hwmon"; io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>; }; + + /* 48MHz reference crystal */ + ref48: ref48M { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + }; }; &dcc { @@ -404,10 +411,41 @@ #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u43 */ - compatible = "si5341"; + compatible = "silabs,si5341"; reg = <0x36>; + #clock-cells = <2>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&ref48>; + clock-names = "xtal"; + clock-output-names = "si5341"; + + si5341_2: out@2 { + /* refclk2 for PS-GT, used for USB3 */ + reg = <2>; + always-on; /* assigned-clocks does not enable, so do it here */ + }; + si5341_3: out@3 { + /* refclk3 for PS-GT, used for SATA */ + reg = <3>; + always-on; /* assigned-clocks does not enable, so do it here */ + }; + si5341_5: out@5 { + /* refclk5 PL CLK100 */ + reg = <5>; + always-on; /* assigned-clocks does not enable, so do it here */ + }; + si5341_6: out@6 { + /* refclk6 PL CLK125 */ + reg = <6>; + always-on; /* assigned-clocks does not enable, so do it here */ + }; + si5341_9: out@9 { + /* refclk9 used for PS_REF_CLK 33.3 MHz */ + reg = <9>; + always-on; /* assigned-clocks does not enable, so do it here */ + }; }; - }; i2c_si570_user_c0: i2c@2 { #address-cells = <1>; @@ -541,6 +579,13 @@ }; }; +&psgtr { + status = "okay"; + /* pcie, sata, usb3, dp */ + clocks = <&si5341 0 5>, <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>; + clock-names = "ref0", "ref1", "ref2", "ref3"; +}; + &rtc { status = "okay"; }; @@ -556,8 +601,7 @@ ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; - phy-names = "sata-phy"; - phys = <&lane3 PHY_TYPE_SATA 1 3 125000000>; + phys = <&psgtr 3 PHY_TYPE_SATA 1 3>; }; /* SD1 with level shifter */ @@ -571,10 +615,6 @@ xlnx,mio-bank = <1>; }; -&serdes { - status = "okay"; -}; - &uart0 { status = "okay"; }; @@ -588,6 +628,4 @@ status = "okay"; dr_mode = "host"; snps,usb3_lpm_capable; - phy-names = "usb3-phy"; - phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>; }; diff --git a/arch/arm/dts/zynqmp-zcu216-revA.dts b/arch/arm/dts/zynqmp-zcu216-revA.dts index 847e689c155f..2302b07c4825 100644 --- a/arch/arm/dts/zynqmp-zcu216-revA.dts +++ b/arch/arm/dts/zynqmp-zcu216-revA.dts @@ -120,6 +120,20 @@ compatible = "iio-hwmon"; io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>; }; + + /* 48MHz reference crystal */ + ref48: ref48M { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + }; +}; + +&psgtr { + status = "okay"; + /* pcie, sata, usb3, dp */ + clocks = <&si5341 0 5>, <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>; + clock-names = "ref0", "ref1", "ref2", "ref3"; }; &dcc { @@ -408,10 +422,41 @@ #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u43 */ - compatible = "si5341"; + compatible = "silabs,si5341"; reg = <0x36>; + #clock-cells = <2>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&ref48>; + clock-names = "xtal"; + clock-output-names = "si5341"; + + si5341_2: out@2 { + /* refclk2 for PS-GT, used for USB3 */ + reg = <2>; + always-on; /* assigned-clocks does not enable, so do it here */ + }; + si5341_3: out@3 { + /* refclk3 for PS-GT, used for SATA */ + reg = <3>; + always-on; /* assigned-clocks does not enable, so do it here */ + }; + si5341_5: out@5 { + /* refclk5 PL CLK100 */ + reg = <5>; + always-on; /* assigned-clocks does not enable, so do it here */ + }; + si5341_6: out@6 { + /* refclk6 PL CLK125 */ + reg = <6>; + always-on; /* assigned-clocks does not enable, so do it here */ + }; + si5341_9: out@9 { + /* refclk9 used for PS_REF_CLK 33.3 MHz */ + reg = <9>; + always-on; /* assigned-clocks does not enable, so do it here */ + }; }; - }; i2c_si570_user_c0: i2c@2 { #address-cells = <1>; @@ -560,8 +605,7 @@ ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; - phy-names = "sata-phy"; - phys = <&lane3 PHY_TYPE_SATA 1 3 125000000>; + phys = <&psgtr 3 PHY_TYPE_SATA 1 3>; }; /* SD1 with level shifter */ @@ -575,10 +619,6 @@ xlnx,mio-bank = <1>; }; -&serdes { - status = "okay"; -}; - &uart0 { status = "okay"; }; @@ -592,6 +632,4 @@ status = "okay"; dr_mode = "host"; snps,usb3_lpm_capable; - phy-names = "usb3-phy"; - phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>; }; diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 2917a956eb3d..84d9770225aa 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -12,6 +12,7 @@ * the License, or (at your option) any later version. */ +#include <dt-bindings/dma/xlnx-zynqmp-dpdma.h> #include <dt-bindings/power/xlnx-zynqmp-power.h> #include <dt-bindings/reset/xlnx-zynqmp-resets.h> @@ -160,11 +161,25 @@ mbox-names = "tx", "rx"; }; + nvmem_firmware { + compatible = "xlnx,zynqmp-nvmem-fw"; + #address-cells = <1>; + #size-cells = <1>; + + soc_revision: soc_revision@0 { + reg = <0x0 0x4>; + }; + }; + zynqmp_pcap: pcap { compatible = "xlnx,zynqmp-pcap-fpga"; clock-names = "ref_clk"; }; + xlnx_aes: zynqmp-aes { + compatible = "xlnx,zynqmp-aes"; + }; + zynqmp_reset: reset-controller { compatible = "xlnx,zynqmp-reset"; #reset-cells = <1>; @@ -198,16 +213,6 @@ ranges; }; - nvmem_firmware { - compatible = "xlnx,zynqmp-nvmem-fw"; - #address-cells = <1>; - #size-cells = <1>; - - soc_revision: soc_revision@0 { - reg = <0x0 0x4>; - }; - }; - amba: axi { compatible = "simple-bus"; u-boot,dm-pre-reloc; @@ -501,8 +506,8 @@ interrupts = <0 112 4>; }; - nand0: nand@ff100000 { - compatible = "arasan,nfc-v3p10"; + nand0: nand-controller@ff100000 { + compatible = "xlnx,zynqmp-nand-controller", "arasan,nfc-v3p10"; status = "disabled"; reg = <0x0 0xff100000 0x0 0x1000>; clock-names = "controller", "bus"; @@ -667,6 +672,15 @@ power-domains = <&zynqmp_firmware PD_QSPI>; }; + psgtr: phy@fd400000 { + compatible = "xlnx,zynqmp-psgtr-v1.1"; + status = "disabled"; + reg = <0x0 0xfd400000 0x0 0x40000>, + <0x0 0xfd3d0000 0x0 0x1000>; + reg-names = "serdes", "siou"; + #phy-cells = <4>; + }; + rtc: rtc@ffa60000 { compatible = "xlnx,zynqmp-rtc"; status = "disabled"; @@ -677,45 +691,6 @@ calibration = <0x8000>; }; - serdes: zynqmp_phy@fd400000 { - compatible = "xlnx,zynqmp-psgtr"; - status = "disabled"; - reg = <0x0 0xfd400000 0x0 0x40000>, - <0x0 0xfd3d0000 0x0 0x1000>, - <0x0 0xff5e0000 0x0 0x1000>; - reg-names = "serdes", "siou", "lpd"; - nvmem-cells = <&soc_revision>; - nvmem-cell-names = "soc_revision"; - resets = <&zynqmp_reset ZYNQMP_RESET_SATA>, - <&zynqmp_reset ZYNQMP_RESET_USB0_CORERESET>, - <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>, - <&zynqmp_reset ZYNQMP_RESET_USB0_HIBERRESET>, - <&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>, - <&zynqmp_reset ZYNQMP_RESET_USB0_APB>, - <&zynqmp_reset ZYNQMP_RESET_USB1_APB>, - <&zynqmp_reset ZYNQMP_RESET_DP>, - <&zynqmp_reset ZYNQMP_RESET_GEM0>, - <&zynqmp_reset ZYNQMP_RESET_GEM1>, - <&zynqmp_reset ZYNQMP_RESET_GEM2>, - <&zynqmp_reset ZYNQMP_RESET_GEM3>; - reset-names = "sata_rst", "usb0_crst", "usb1_crst", - "usb0_hibrst", "usb1_hibrst", "usb0_apbrst", - "usb1_apbrst", "dp_rst", "gem0_rst", - "gem1_rst", "gem2_rst", "gem3_rst"; - lane0: lane0 { - #phy-cells = <4>; - }; - lane1: lane1 { - #phy-cells = <4>; - }; - lane2: lane2 { - #phy-cells = <4>; - }; - lane3: lane3 { - #phy-cells = <4>; - }; - }; - sata: ahci@fd0c0000 { compatible = "ceva,ahci-1v84"; status = "disabled"; @@ -740,11 +715,11 @@ xlnx,device_id = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x870>; - power-domains = <&zynqmp_firmware PD_SD_0>; nvmem-cells = <&soc_revision>; nvmem-cell-names = "soc_revision"; #clock-cells = <1>; clock-output-names = "clk_out_sd0", "clk_in_sd0"; + power-domains = <&zynqmp_firmware PD_SD_0>; }; sdhci1: mmc@ff170000 { @@ -758,11 +733,11 @@ xlnx,device_id = <1>; #stream-id-cells = <1>; iommus = <&smmu 0x871>; - power-domains = <&zynqmp_firmware PD_SD_1>; nvmem-cells = <&soc_revision>; nvmem-cell-names = "soc_revision"; #clock-cells = <1>; clock-output-names = "clk_out_sd1", "clk_in_sd1"; + power-domains = <&zynqmp_firmware PD_SD_1>; }; smmu: iommu@fd800000 { @@ -962,37 +937,18 @@ }; }; - xlnx_dpdma: dma@fd4c0000 { - compatible = "xlnx,dpdma"; + zynqmp_dpdma: dma-controller@fd4c0000 { + compatible = "xlnx,zynqmp-dpdma"; status = "disabled"; reg = <0x0 0xfd4c0000 0x0 0x1000>; interrupts = <0 122 4>; interrupt-parent = <&gic>; clock-names = "axi_clk"; power-domains = <&zynqmp_firmware PD_DP>; - dma-channels = <6>; #dma-cells = <1>; - dma-video0channel { - compatible = "xlnx,video0"; - }; - dma-video1channel { - compatible = "xlnx,video1"; - }; - dma-video2channel { - compatible = "xlnx,video2"; - }; - dma-graphicschannel { - compatible = "xlnx,graphics"; - }; - dma-audio0channel { - compatible = "xlnx,audio0"; - }; - dma-audio1channel { - compatible = "xlnx,audio1"; - }; }; - zynqmp_dpsub: zynqmp-display@fd4a0000 { + zynqmp_dpsub: display@fd4a0000 { compatible = "xlnx,zynqmp-dpsub-1.7"; status = "disabled"; reg = <0x0 0xfd4a0000 0x0 0x1000>, @@ -1002,51 +958,15 @@ reg-names = "dp", "blend", "av_buf", "aud"; interrupts = <0 119 4>; interrupt-parent = <&gic>; - clock-names = "dp_apb_clk", "dp_aud_clk", "dp_vtc_pixel_clk_in"; - power-domains = <&zynqmp_firmware PD_DP>; - - vid-layer { - dma-names = "vid0", "vid1", "vid2"; - dmas = <&xlnx_dpdma 0>, - <&xlnx_dpdma 1>, - <&xlnx_dpdma 2>; - }; - - gfx-layer { - dma-names = "gfx0"; - dmas = <&xlnx_dpdma 3>; - }; - - /* dummy node to indicate there's no child i2c device */ - i2c-bus { - }; - - zynqmp_dp_snd_codec0: zynqmp_dp_snd_codec0 { - compatible = "xlnx,dp-snd-codec"; - clock-names = "aud_clk"; - }; - - zynqmp_dp_snd_pcm0: zynqmp_dp_snd_pcm0 { - compatible = "xlnx,dp-snd-pcm"; - dmas = <&xlnx_dpdma 4>; - dma-names = "tx"; - }; - - zynqmp_dp_snd_pcm1: zynqmp_dp_snd_pcm1 { - compatible = "xlnx,dp-snd-pcm"; - dmas = <&xlnx_dpdma 5>; - dma-names = "tx"; - }; - - zynqmp_dp_snd_card0: zynqmp_dp_snd_card { - compatible = "xlnx,dp-snd-card"; - xlnx,dp-snd-pcm = <&zynqmp_dp_snd_pcm0>, - <&zynqmp_dp_snd_pcm1>; - xlnx,dp-snd-codec = <&zynqmp_dp_snd_codec0>; - }; + resets = <&zynqmp_reset ZYNQMP_RESET_DP>; + dma-names = "vid0", "vid1", "vid2", "gfx0"; + dmas = <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO0>, + <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO1>, + <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO2>, + <&zynqmp_dpdma ZYNQMP_DPDMA_GRAPHICS>; }; }; }; diff --git a/include/dt-bindings/dma/xlnx-zynqmp-dpdma.h b/include/dt-bindings/dma/xlnx-zynqmp-dpdma.h new file mode 100644 index 000000000000..3719cda5679d --- /dev/null +++ b/include/dt-bindings/dma/xlnx-zynqmp-dpdma.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Copyright 2019 Laurent Pinchart <laurent.pinchart(a)ideasonboard.com> + */ + +#ifndef __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ +#define __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ + +#define ZYNQMP_DPDMA_VIDEO0 0 +#define ZYNQMP_DPDMA_VIDEO1 1 +#define ZYNQMP_DPDMA_VIDEO2 2 +#define ZYNQMP_DPDMA_GRAPHICS 3 +#define ZYNQMP_DPDMA_AUDIO0 4 +#define ZYNQMP_DPDMA_AUDIO1 5 + +#endif /* __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ */ -- 2.30.1

2 1

[PATCH] clk: zynqmp: Fix clk dump values
by Michal Simek 30 Mar '21

30 Mar '21

From: T Karthik Reddy <t.karthik.reddy(a)xilinx.com> With "clk dump" command, few clocks are showing up incorrect values and some clocks are displayed as "unknown". Add missing clocks to zynqmp clock driver to display proper clocks rates. Implement a simple way to get clock source, instead of calling functions. Change existing functions to this simple mechanism. Fix gem clock name "gem_rx" to "gem_tx" which was incorrect. Change dbf_fpd & dbf_lpd clk names to dbg_fpd & dbg_lpd. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> Signed-off-by: T Karthik Reddy <t.karthik.reddy(a)xilinx.com> --- drivers/clk/clk_zynqmp.c | 251 ++++++++++++++++++++++++++------------- 1 file changed, 170 insertions(+), 81 deletions(-) diff --git a/drivers/clk/clk_zynqmp.c b/drivers/clk/clk_zynqmp.c index 609d8e3b2fff..13a623fdb96a 100644 --- a/drivers/clk/clk_zynqmp.c +++ b/drivers/clk/clk_zynqmp.c @@ -97,8 +97,7 @@ static const resource_size_t zynqmp_crl_apb_clkc_base = 0xff5e0020; #define CLK_CTRL_DIV1_MASK (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV1_SHIFT) #define CLK_CTRL_DIV0_SHIFT 8 #define CLK_CTRL_DIV0_MASK (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV0_SHIFT) -#define CLK_CTRL_SRCSEL_SHIFT 0 -#define CLK_CTRL_SRCSEL_MASK (0x3 << CLK_CTRL_SRCSEL_SHIFT) +#define CLK_CTRL_SRCSEL_MASK 0x7 #define PLLCTRL_FBDIV_MASK 0x7f00 #define PLLCTRL_FBDIV_SHIFT 8 #define PLLCTRL_RESET_MASK 1 @@ -132,7 +131,7 @@ enum zynqmp_clk { iou_switch, gem_tsu_ref, gem_tsu, gem0_ref, gem1_ref, gem2_ref, gem3_ref, - gem0_rx, gem1_rx, gem2_rx, gem3_rx, + gem0_tx, gem1_tx, gem2_tx, gem3_tx, qspi_ref, sdio0_ref, sdio1_ref, uart0_ref, uart1_ref, @@ -152,7 +151,7 @@ static const char * const clk_names[clk_max] = { "iopll", "rpll", "apll", "dpll", "vpll", "iopll_to_fpd", "rpll_to_fpd", "apll_to_lpd", "dpll_to_lpd", "vpll_to_lpd", - "acpu", "acpu_half", "dbf_fpd", "dbf_lpd", + "acpu", "acpu_half", "dbg_fpd", "dbg_lpd", "dbg_trace", "dbg_tstmp", "dp_video_ref", "dp_audio_ref", "dp_stc_ref", "gdma_ref", "dpdma_ref", "ddr_ref", "sata_ref", "pcie_ref", @@ -172,6 +171,38 @@ static const char * const clk_names[clk_max] = { "ams_ref", "pl0", "pl1", "pl2", "pl3", "wdt" }; +static const u32 pll_src[][4] = { + {apll, 0xff, dpll, vpll}, /* acpu */ + {dpll, vpll, 0xff, 0xff}, /* ddr_ref */ + {rpll, iopll, 0xff, 0xff}, /* dll_ref */ + {iopll, 0xff, rpll, dpll_to_lpd}, /* gem_tsu_ref */ + {iopll, 0xff, rpll, dpll}, /* peripheral */ + {apll, 0xff, iopll_to_fpd, dpll}, /* wdt */ + {iopll_to_fpd, 0xff, dpll, apll}, /* dbg_fpd */ + {iopll, 0xff, rpll, dpll_to_lpd}, /* timestamp_ref */ + {iopll_to_fpd, 0xff, apll, dpll}, /* sata_ref */ + {iopll_to_fpd, 0xff, rpll_to_fpd, dpll},/* pcie_ref */ + {iopll_to_fpd, 0xff, vpll, dpll}, /* gpu_ref */ + {apll, 0xff, vpll, dpll}, /* topsw_main_ref */ + {rpll, 0xff, iopll, dpll_to_lpd}, /* cpu_r5_ref */ +}; + +enum zynqmp_clk_pll_src { + ACPU_CLK_SRC = 0, + DDR_CLK_SRC, + DLL_CLK_SRC, + GEM_TSU_CLK_SRC, + PERI_CLK_SRC, + WDT_CLK_SRC, + DBG_FPD_CLK_SRC, + TIMESTAMP_CLK_SRC, + SATA_CLK_SRC, + PCIE_CLK_SRC, + GPU_CLK_SRC, + TOPSW_MAIN_CLK_SRC, + CPU_R5_CLK_SRC +}; + struct zynqmp_clk_priv { unsigned long ps_clk_freq; unsigned long video_clk; @@ -195,12 +226,38 @@ static u32 zynqmp_clk_get_register(enum zynqmp_clk id) return CRF_APB_VPLL_CTRL; case acpu: return CRF_APB_ACPU_CTRL; + case dbg_fpd: + return CRF_APB_DBG_FPD_CTRL; + case dbg_trace: + return CRF_APB_DBG_TRACE_CTRL; + case dbg_tstmp: + return CRF_APB_DBG_TSTMP_CTRL; + case gpu_ref ... gpu_pp1_ref: + return CRF_APB_GPU_REF_CTRL; case ddr_ref: return CRF_APB_DDR_CTRL; + case sata_ref: + return CRF_APB_SATA_REF_CTRL; + case pcie_ref: + return CRF_APB_PCIE_REF_CTRL; + case gdma_ref: + return CRF_APB_GDMA_REF_CTRL; + case dpdma_ref: + return CRF_APB_DPDMA_REF_CTRL; + case topsw_main: + return CRF_APB_TOPSW_MAIN_CTRL; + case topsw_lsbus: + return CRF_APB_TOPSW_LSBUS_CTRL; + case lpd_switch: + return CRL_APB_LPD_SWITCH_CTRL; + case lpd_lsbus: + return CRL_APB_LPD_LSBUS_CTRL; case qspi_ref: return CRL_APB_QSPI_REF_CTRL; case usb3_dual_ref: return CRL_APB_USB3_DUAL_REF_CTRL; + case gem_tsu_ref: + return CRL_APB_GEM_TSU_REF_CTRL; case gem0_ref: return CRL_APB_GEM0_REF_CTRL; case gem1_ref: @@ -213,6 +270,8 @@ static u32 zynqmp_clk_get_register(enum zynqmp_clk id) return CRL_APB_USB0_BUS_REF_CTRL; case usb1_bus_ref: return CRL_APB_USB1_BUS_REF_CTRL; + case cpu_r5: + return CRL_APB_CPU_R5_CTRL; case uart0_ref: return CRL_APB_UART0_REF_CTRL; case uart1_ref: @@ -235,6 +294,14 @@ static u32 zynqmp_clk_get_register(enum zynqmp_clk id) return CRL_APB_CAN0_REF_CTRL; case can1_ref: return CRL_APB_CAN1_REF_CTRL; + case dll_ref: + return CRL_APB_DLL_REF_CTRL; + case adma_ref: + return CRL_APB_ADMA_REF_CTRL; + case timestamp_ref: + return CRL_APB_TIMESTAMP_REF_CTRL; + case ams_ref: + return CRL_APB_AMS_REF_CTRL; case pl0: return CRL_APB_PL0_REF_CTRL; case pl1: @@ -253,68 +320,6 @@ static u32 zynqmp_clk_get_register(enum zynqmp_clk id) return 0; } -static enum zynqmp_clk zynqmp_clk_get_cpu_pll(u32 clk_ctrl) -{ - u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >> - CLK_CTRL_SRCSEL_SHIFT; - - switch (srcsel) { - case 2: - return dpll; - case 3: - return vpll; - case 0 ... 1: - default: - return apll; - } -} - -static enum zynqmp_clk zynqmp_clk_get_ddr_pll(u32 clk_ctrl) -{ - u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >> - CLK_CTRL_SRCSEL_SHIFT; - - switch (srcsel) { - case 1: - return vpll; - case 0: - default: - return dpll; - } -} - -static enum zynqmp_clk zynqmp_clk_get_peripheral_pll(u32 clk_ctrl) -{ - u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >> - CLK_CTRL_SRCSEL_SHIFT; - - switch (srcsel) { - case 2: - return rpll; - case 3: - return dpll; - case 0 ... 1: - default: - return iopll; - } -} - -static enum zynqmp_clk zynqmp_clk_get_wdt_pll(u32 clk_ctrl) -{ - u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >> - CLK_CTRL_SRCSEL_SHIFT; - - switch (srcsel) { - case 2: - return iopll_to_fpd; - case 3: - return dpll; - case 0 ... 1: - default: - return apll; - } -} - static ulong zynqmp_clk_get_pll_src(ulong clk_ctrl, struct zynqmp_clk_priv *priv, bool is_pre_src) @@ -378,7 +383,7 @@ static ulong zynqmp_clk_get_pll_rate(struct zynqmp_clk_priv *priv, static ulong zynqmp_clk_get_cpu_rate(struct zynqmp_clk_priv *priv, enum zynqmp_clk id) { - u32 clk_ctrl, div; + u32 clk_ctrl, div, srcsel; enum zynqmp_clk pll; int ret; unsigned long pllrate; @@ -391,7 +396,8 @@ static ulong zynqmp_clk_get_cpu_rate(struct zynqmp_clk_priv *priv, div = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT; - pll = zynqmp_clk_get_cpu_pll(clk_ctrl); + srcsel = clk_ctrl & CLK_CTRL_SRCSEL_MASK; + pll = pll_src[ACPU_CLK_SRC][srcsel]; pllrate = zynqmp_clk_get_pll_rate(priv, pll); if (IS_ERR_VALUE(pllrate)) return pllrate; @@ -401,7 +407,7 @@ static ulong zynqmp_clk_get_cpu_rate(struct zynqmp_clk_priv *priv, static ulong zynqmp_clk_get_ddr_rate(struct zynqmp_clk_priv *priv) { - u32 clk_ctrl, div; + u32 clk_ctrl, div, srcsel; enum zynqmp_clk pll; int ret; ulong pllrate; @@ -414,7 +420,8 @@ static ulong zynqmp_clk_get_ddr_rate(struct zynqmp_clk_priv *priv) div = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT; - pll = zynqmp_clk_get_ddr_pll(clk_ctrl); + srcsel = clk_ctrl & CLK_CTRL_SRCSEL_MASK; + pll = pll_src[DDR_CLK_SRC][srcsel]; pllrate = zynqmp_clk_get_pll_rate(priv, pll); if (IS_ERR_VALUE(pllrate)) return pllrate; @@ -422,11 +429,33 @@ static ulong zynqmp_clk_get_ddr_rate(struct zynqmp_clk_priv *priv) return DIV_ROUND_CLOSEST(pllrate, div); } +static ulong zynqmp_clk_get_dll_rate(struct zynqmp_clk_priv *priv) +{ + u32 clk_ctrl, srcsel; + enum zynqmp_clk pll; + ulong pllrate; + int ret; + + ret = zynqmp_mmio_read(CRL_APB_DLL_REF_CTRL, &clk_ctrl); + if (ret) { + printf("%s mio read fail\n", __func__); + return -EIO; + } + + srcsel = clk_ctrl & CLK_CTRL_SRCSEL_MASK; + pll = pll_src[DLL_CLK_SRC][srcsel]; + pllrate = zynqmp_clk_get_pll_rate(priv, pll); + if (IS_ERR_VALUE(pllrate)) + return pllrate; + + return pllrate; +} + static ulong zynqmp_clk_get_peripheral_rate(struct zynqmp_clk_priv *priv, - enum zynqmp_clk id, bool two_divs) + enum zynqmp_clk id, bool two_divs) { enum zynqmp_clk pll; - u32 clk_ctrl, div0; + u32 clk_ctrl, div0, srcsel; u32 div1 = 1; int ret; ulong pllrate; @@ -446,8 +475,13 @@ static ulong zynqmp_clk_get_peripheral_rate(struct zynqmp_clk_priv *priv, if (!div1) div1 = 1; } + srcsel = clk_ctrl & CLK_CTRL_SRCSEL_MASK; + + if (id == gem_tsu_ref) + pll = pll_src[GEM_TSU_CLK_SRC][srcsel]; + else + pll = pll_src[PERI_CLK_SRC][srcsel]; - pll = zynqmp_clk_get_peripheral_pll(clk_ctrl); pllrate = zynqmp_clk_get_pll_rate(priv, pll); if (IS_ERR_VALUE(pllrate)) return pllrate; @@ -457,11 +491,11 @@ static ulong zynqmp_clk_get_peripheral_rate(struct zynqmp_clk_priv *priv, DIV_ROUND_CLOSEST(pllrate, div0), div1); } -static ulong zynqmp_clk_get_wdt_rate(struct zynqmp_clk_priv *priv, - enum zynqmp_clk id, bool two_divs) +static ulong zynqmp_clk_get_crf_crl_rate(struct zynqmp_clk_priv *priv, + enum zynqmp_clk id, bool two_divs) { enum zynqmp_clk pll; - u32 clk_ctrl, div0; + u32 clk_ctrl, div0, srcsel; u32 div1 = 1; int ret; ulong pllrate; @@ -475,8 +509,45 @@ static ulong zynqmp_clk_get_wdt_rate(struct zynqmp_clk_priv *priv, div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT; if (!div0) div0 = 1; + srcsel = clk_ctrl & CLK_CTRL_SRCSEL_MASK; - pll = zynqmp_clk_get_wdt_pll(clk_ctrl); + switch (id) { + case wdt: + case dbg_trace: + case topsw_lsbus: + pll = pll_src[WDT_CLK_SRC][srcsel]; + break; + case dbg_fpd: + case dbg_tstmp: + pll = pll_src[DBG_FPD_CLK_SRC][srcsel]; + break; + case timestamp_ref: + pll = pll_src[TIMESTAMP_CLK_SRC][srcsel]; + break; + case sata_ref: + pll = pll_src[SATA_CLK_SRC][srcsel]; + break; + case pcie_ref: + pll = pll_src[PCIE_CLK_SRC][srcsel]; + break; + case gpu_ref ... gpu_pp1_ref: + pll = pll_src[GPU_CLK_SRC][srcsel]; + break; + case gdma_ref: + case dpdma_ref: + case topsw_main: + pll = pll_src[TOPSW_MAIN_CLK_SRC][srcsel]; + break; + case cpu_r5: + case ams_ref: + case adma_ref: + case lpd_lsbus: + case lpd_switch: + pll = pll_src[CPU_R5_CLK_SRC][srcsel]; + break; + default: + return -ENXIO; + } if (two_divs) { ret = zynqmp_mmio_read(zynqmp_clk_get_register(pll), &clk_ctrl); if (ret) { @@ -533,7 +604,7 @@ static ulong zynqmp_clk_set_peripheral_rate(struct zynqmp_clk_priv *priv, enum zynqmp_clk pll; u32 clk_ctrl, div0 = 0, div1 = 0; ulong pll_rate, new_rate; - u32 reg; + u32 reg, srcsel; int ret; u32 mask; @@ -544,7 +615,8 @@ static ulong zynqmp_clk_set_peripheral_rate(struct zynqmp_clk_priv *priv, return -EIO; } - pll = zynqmp_clk_get_peripheral_pll(clk_ctrl); + srcsel = clk_ctrl & CLK_CTRL_SRCSEL_MASK; + pll = pll_src[PERI_CLK_SRC][srcsel]; pll_rate = zynqmp_clk_get_pll_rate(priv, pll); if (IS_ERR_VALUE(pll_rate)) return pll_rate; @@ -588,14 +660,31 @@ static ulong zynqmp_clk_get_rate(struct clk *clk) return zynqmp_clk_get_cpu_rate(priv, id); case ddr_ref: return zynqmp_clk_get_ddr_rate(priv); + case dll_ref: + return zynqmp_clk_get_dll_rate(priv); + case gem_tsu_ref: + case pl0 ... pl3: case gem0_ref ... gem3_ref: case qspi_ref ... can1_ref: - case pl0 ... pl3: + case usb0_bus_ref ... usb3_dual_ref: two_divs = true; return zynqmp_clk_get_peripheral_rate(priv, id, two_divs); case wdt: + case topsw_lsbus: + case sata_ref ... gpu_pp1_ref: two_divs = true; - return zynqmp_clk_get_wdt_rate(priv, id, two_divs); + case cpu_r5: + case dbg_fpd: + case ams_ref: + case adma_ref: + case lpd_lsbus: + case dbg_trace: + case dbg_tstmp: + case lpd_switch: + case topsw_main: + case timestamp_ref: + case gdma_ref ... dpdma_ref: + return zynqmp_clk_get_crf_crl_rate(priv, id, two_divs); default: return -ENXIO; } -- 2.30.0

2 1

[PATCH] arm64: zynqmp: Rename clocks as per the Arasan NAND driver
by Michal Simek 30 Mar '21

30 Mar '21

From: Amit Kumar Mahapatra <amit.kumar-mahapatra(a)xilinx.com> In zynqmp.dtsi file renamed "clk_sys" clock to "controller" and "clk_flash" clock to "bus" as per upstreamed Arasan NAND driver. This fixes NAND driver probe failure. Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra(a)xilinx.com> Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- arch/arm/dts/zynqmp.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index aa0ac95e122e..2917a956eb3d 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -505,7 +505,7 @@ compatible = "arasan,nfc-v3p10"; status = "disabled"; reg = <0x0 0xff100000 0x0 0x1000>; - clock-names = "clk_sys", "clk_flash"; + clock-names = "controller", "bus"; interrupt-parent = <&gic>; interrupts = <0 14 4>; #address-cells = <1>; -- 2.30.0

2 1

[PATCH] arm64: zynqmp: Update device tree properties for nand flash
by Michal Simek 30 Mar '21

30 Mar '21

From: Amit Kumar Mahapatra <amit.kumar-mahapatra(a)xilinx.com> Update the following device tree properties for nand flash - Set software ecc mode. - Set bch as ecc algo. - Set read block to 0. Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra(a)xilinx.com> Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts index 92d938d665d2..3204456e6451 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts @@ -124,6 +124,10 @@ reg = <0x0>; #address-cells = <0x2>; #size-cells = <0x1>; + nand-ecc-mode = "soft"; + nand-ecc-algo = "bch"; + nand-rb = <0>; + label = "main-storage-0"; partition@0 { /* for testing purpose */ label = "nand-fsbl-uboot"; @@ -154,6 +158,10 @@ reg = <0x1>; #address-cells = <0x2>; #size-cells = <0x1>; + nand-ecc-mode = "soft"; + nand-ecc-algo = "bch"; + nand-rb = <0>; + label = "main-storage-1"; partition@0 { /* for testing purpose */ label = "nand1-fsbl-uboot"; -- 2.30.0

2 1

[PATCH] arm64: zynqmp: Update psu_init for zcu1275
by Michal Simek 30 Mar '21

30 Mar '21

Update clock/pll setup, ddr, MIOs based on 2020.2 hw design. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- .../zynqmp/zynqmp-zcu1275-revB/psu_init_gpl.c | 230 +++++++++++------- 1 file changed, 148 insertions(+), 82 deletions(-) diff --git a/board/xilinx/zynqmp/zynqmp-zcu1275-revB/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zcu1275-revB/psu_init_gpl.c index d3eb713e9eeb..2d93b2005bcc 100644 --- a/board/xilinx/zynqmp/zynqmp-zcu1275-revB/psu_init_gpl.c +++ b/board/xilinx/zynqmp/zynqmp-zcu1275-revB/psu_init_gpl.c @@ -8,77 +8,88 @@ static unsigned long psu_pll_init_data(void) { - psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4E2C62U); - psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00013C00U); + psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U); + psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014600U); psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U); psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U); psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U); mask_poll(0xFF5E0040, 0x00000002U); psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U); - psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000200U); - psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E4B0C82U); - psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00015A00U); + psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFF5E0038, 0x8000FFFFU, 0x00000000U); + psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012300U); + psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E672C6CU); + psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00002D00U); psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U); psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U); psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U); mask_poll(0xFF5E0040, 0x00000001U); psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U); psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFF5E0028, 0x8000FFFFU, 0x00000000U); psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U); - psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014200U); + psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U); psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U); psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U); psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U); mask_poll(0xFD1A0044, 0x00000001U); psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U); psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFD1A0028, 0x8000FFFFU, 0x00000000U); psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U); - psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014800U); + psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014000U); psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U); psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U); psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U); mask_poll(0xFD1A0044, 0x00000002U); psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U); psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFD1A0034, 0x8000FFFFU, 0x00000000U); psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C62U); - psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00014000U); + psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00014700U); psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U); psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U); psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U); mask_poll(0xFD1A0044, 0x00000004U); psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U); - psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000200U); + psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFD1A0040, 0x8000FFFFU, 0x00000000U); return 1; } static unsigned long psu_clock_init_data(void) { + psu_mask_write(0xFF5E0054, 0x063F3F07U, 0x06010C00U); + psu_mask_write(0xFF180308, 0x00000060U, 0x00000060U); + psu_mask_write(0xFF5E0100, 0x013F3F07U, 0x01010600U); + psu_mask_write(0xFF5E0060, 0x023F3F07U, 0x02010600U); + psu_mask_write(0xFF5E004C, 0x023F3F07U, 0x020F0500U); psu_mask_write(0xFF5E0068, 0x013F3F07U, 0x01010C00U); - psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010502U); + psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010800U); psu_mask_write(0xFF18030C, 0x00020000U, 0x00000000U); psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U); psu_mask_write(0xFF5E0120, 0x013F3F07U, 0x01010F00U); psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U); - psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000400U); - psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000900U); + psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U); + psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U); psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U); psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U); psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U); psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U); - psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010A02U); - psu_mask_write(0xFF5E00C4, 0x013F3F07U, 0x01010402U); - psu_mask_write(0xFF5E00C8, 0x013F3F07U, 0x01010802U); + psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E00C4, 0x013F3F07U, 0x01010400U); + psu_mask_write(0xFF5E00C8, 0x013F3F07U, 0x01010C00U); + psu_mask_write(0xFF5E00CC, 0x013F3F07U, 0x01010400U); psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011D02U); psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U); - psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000104U); + psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U); psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U); psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U); - psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000600U); - psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000203U); - psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000203U); - psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000203U); - psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000202U); + psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U); + psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000203U); psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U); psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U); psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U); @@ -94,50 +105,50 @@ static unsigned long psu_ddr_init_data(void) psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U); psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x81040001U); psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U); - psu_mask_write(0xFD070020, 0x000003F3U, 0x00000100U); + psu_mask_write(0xFD070020, 0x000003F3U, 0x00000200U); psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U); psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U); - psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00403210U); + psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408410U); psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U); psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U); psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U); - psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x00308034U); + psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x0081808BU); psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U); psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U); psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U); psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0030051FU); - psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020063U); - psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00290000U); - psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00000E05U); - psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x05200004U); - psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020106U); + psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x006A0000U); + psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002305U); + psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x01240004U); + psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00280000U); psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00110004U); psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x00000000U); psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x00000000U); psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U); psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU); - psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x07080D07U); - psu_mask_write(0xFD070104, 0x001F1F7FU, 0x0005020BU); - psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x03030607U); - psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x00502006U); - psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x13020206U); - psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x03030202U); - psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010003U); - psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000303U); - psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x02020909U); + psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x0F102412U); + psu_mask_write(0xFD070104, 0x001F1F7FU, 0x000D041AU); + psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0507070BU); + psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x00502008U); + psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x07020408U); + psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x06060403U); + psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U); + psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000606U); + psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x03030909U); psu_mask_write(0xFD070124, 0x40070F3FU, 0x0004040DU); psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x440C011CU); psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U); - psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x80800020U); - psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x02009896U); - psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x04828202U); + psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x80AB002BU); + psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x020196E6U); + psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048A8207U); psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00020304U); psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U); psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U); psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U); psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x00C800FFU); psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U); - psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000000U); + psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000805U); psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000000U); psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU); psu_mask_write(0xFD070204, 0x001F1F1FU, 0x00080808U); @@ -151,7 +162,7 @@ static unsigned long psu_ddr_init_data(void) psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x07070707U); psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x07070707U); psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000007U); - psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x06000604U); + psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x06000610U); psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U); psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U); psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U); @@ -209,30 +220,30 @@ static unsigned long psu_ddr_init_data(void) psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U); psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U); psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U); - psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F05D90U); + psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F10010U); psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U); psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U); - psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x1900C810U); - psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0x4E200708U); - psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x06124000U); - psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04061U); + psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x42C21590U); + psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0xD05612C0U); + psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U); psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD0800C4, 0xFFFFFFFFU, 0x000000DAU); + psu_mask_write(0xFD0800C4, 0xFFFFFFFFU, 0x000000E3U); psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040BU); - psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x040E0A04U); - psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28100004U); + psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x08240E08U); + psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28200404U); psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x000F0200U); psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x82000800U); - psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x00682B0AU); - psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00152504U); - psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000506U); + psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01162B1AU); + psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00330E08U); + psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000A0EU); psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U); psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U); psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U); psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000520U); + psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000124U); psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000004U); - psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000028U); psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000000U); psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U); psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x00000000U); @@ -261,7 +272,7 @@ static unsigned long psu_ddr_init_data(void) psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U); psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U); psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x0088E858U); + psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008AA858U); psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000077BBU); psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U); psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U); @@ -281,13 +292,13 @@ static unsigned long psu_ddr_init_data(void) psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U); psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU); psu_mask_write(0xFD08090C, 0xFFFFFFFFU, 0x3F000008U); - psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B00CU); + psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B004U); psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09093030U); psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU); psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U); psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU); psu_mask_write(0xFD080A0C, 0xFFFFFFFFU, 0x3F000008U); - psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B00CU); + psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B004U); psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09093030U); psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU); psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U); @@ -318,7 +329,7 @@ static unsigned long psu_ddr_init_data(void) psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B00CU); psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09093030U); psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU); - psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x40803660U); + psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x80803660U); psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x55556000U); psu_mask_write(0xFD080F08, 0xFFFFFFFFU, 0xAAAAAAAAU); psu_mask_write(0xFD080F0C, 0xFFFFFFFFU, 0x0029A4A4U); @@ -326,36 +337,55 @@ static unsigned long psu_ddr_init_data(void) psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09093030U); psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU); psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU); - psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x06124000U); + psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x01100000U); psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U); psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U); psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70000000U); psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU); - psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x06124000U); + psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x01100000U); psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U); psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U); psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70000000U); psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU); - psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x06124000U); + psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x01100000U); psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U); psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U); psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70000000U); psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU); - psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x06124000U); + psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x01100000U); psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U); psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U); psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70000000U); psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x15019FFEU); - psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x06124000U); - psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x21100000U); + psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01266300U); psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U); - psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70000000U); - psu_mask_write(0xFD0817C4, 0xFFFFFFFFU, 0x06124000U); + psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70400000U); psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U); return 1; } +static unsigned long psu_ddr_qos_init_data(void) +{ + psu_mask_write(0xFD360008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD36001C, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD370008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD37001C, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD380008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD38001C, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD390008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD39001C, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD3A0008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD3A001C, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD3B0008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD3B001C, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFF9B0008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFF9B001C, 0x0000000FU, 0x00000000U); + + return 1; +} + static unsigned long psu_mio_init_data(void) { psu_mask_write(0xFF180000, 0x000000FEU, 0x00000002U); @@ -378,8 +408,20 @@ static unsigned long psu_mio_init_data(void) psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U); psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U); psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U); - psu_mask_write(0xFF180204, 0x0000007FU, 0x00000002U); - psu_mask_write(0xFF180208, 0x000FFF8CU, 0x00003004U); + psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180204, 0x00000073U, 0x00000002U); + psu_mask_write(0xFF180208, 0xFFFFFF8CU, 0x00B03004U); psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU); psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU); psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U); @@ -405,35 +447,49 @@ static unsigned long psu_mio_init_data(void) static unsigned long psu_peripherals_pre_init_data(void) { - psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x00012302U); + psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012302U); + psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000001U); return 1; } static unsigned long psu_peripherals_init_data(void) { - psu_mask_write(0xFD1A0100, 0x0000807CU, 0x00000000U); + psu_mask_write(0xFD1A0100, 0x00008044U, 0x00000000U); psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U); psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U); + psu_mask_write(0xFF5E0230, 0x00000002U, 0x00000000U); psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U); psu_mask_write(0xFF180390, 0x00000004U, 0x00000004U); + psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U); + psu_mask_write(0xFF5E023C, 0x00000140U, 0x00000140U); + psu_mask_write(0xFF9D0080, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF9D007C, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF5E023C, 0x00000140U, 0x00000000U); psu_mask_write(0xFF5E0238, 0x00000040U, 0x00000000U); psu_mask_write(0xFF180310, 0x00008000U, 0x00000000U); - psu_mask_write(0xFF180320, 0x33800000U, 0x02800000U); + psu_mask_write(0xFF180320, 0x33840000U, 0x02840000U); psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x64500000U); psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U); psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U); psu_mask_write(0xFF5E0238, 0x00000200U, 0x00000000U); psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U); - psu_mask_write(0xFF5E0238, 0x00000800U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U); psu_mask_write(0xFF5E0238, 0x00000002U, 0x00000000U); psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U); psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU); psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U); psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U); psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U); - psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x01FC9F08U); + psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5E100U); psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U); + + mask_delay(1); + psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000002U); + + mask_delay(5); + psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U); return 1; } @@ -459,15 +515,21 @@ static unsigned long psu_ddr_phybringup_data(void) while ((Xil_In32(0xFD080030) & 0x1) != 1) ; - - pll_locked = (Xil_In32(0xFD080030) & 0x80000000) >> 31; - pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000) >> 16; + pll_locked = (Xil_In32(0xFD080030) & 0x80000000) + >> 31; + pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000) + >> 16; pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000) >> 16; - pll_locked &= (Xil_In32(0xFD080BE0) & 0x10000) >> 16; - pll_locked &= (Xil_In32(0xFD080DE0) & 0x10000) >> 16; + pll_locked &= (Xil_In32(0xFD080BE0) & 0x10000) + >> 16; + pll_locked &= (Xil_In32(0xFD080DE0) & 0x10000) + >> 16; pll_retry--; } - Xil_Out32(0xFD0800C0, Xil_In32(0xFD0800C0) | (pll_retry << 16)); + Xil_Out32(0xFD0800C4, Xil_In32(0xFD0800C4) | (pll_retry << 16)); + if (!pll_locked) + return 0; + Xil_Out32(0xFD080004U, 0x00040063U); while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU) @@ -485,7 +547,10 @@ static unsigned long psu_ddr_phybringup_data(void) regval = Xil_In32(0xFD080030); while (regval != 0x80000FFF) regval = Xil_In32(0xFD080030); - Xil_Out32(0xFD070180U, 0x00800020U); + regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18); + if (regval != 0) + return 0; + Xil_Out32(0xFD070180U, 0x00AB002BU); Xil_Out32(0xFD070060U, 0x00000000U); prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U); @@ -511,6 +576,7 @@ int psu_init(void) init_peripheral(); status &= psu_afi_config(); + psu_ddr_qos_init_data(); if (status == 0) return 1; -- 2.30.0

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[PATCH] arm64: zynqmp: Add idt 8a34001 chip to zcu208/zcu216
by Michal Simek 30 Mar '21

30 Mar '21

There is Linux driver for these chips that's why add it to device tree. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- arch/arm/dts/zynqmp-zcu208-revA.dts | 5 ++++- arch/arm/dts/zynqmp-zcu216-revA.dts | 5 ++++- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/zynqmp-zcu208-revA.dts b/arch/arm/dts/zynqmp-zcu208-revA.dts index 124219314b89..268e368b7657 100644 --- a/arch/arm/dts/zynqmp-zcu208-revA.dts +++ b/arch/arm/dts/zynqmp-zcu208-revA.dts @@ -441,7 +441,10 @@ #address-cells = <1>; #size-cells = <0>; reg = <4>; - /* U409B - 8a34001 */ + idt_8a34001: phc@5b { + compatible = "idt,8a34001"; /* u409B */ + reg = <0x5b>; + }; }; i2c_clk104: i2c@5 { #address-cells = <1>; diff --git a/arch/arm/dts/zynqmp-zcu216-revA.dts b/arch/arm/dts/zynqmp-zcu216-revA.dts index 511727fa955d..847e689c155f 100644 --- a/arch/arm/dts/zynqmp-zcu216-revA.dts +++ b/arch/arm/dts/zynqmp-zcu216-revA.dts @@ -445,7 +445,10 @@ #address-cells = <1>; #size-cells = <0>; reg = <4>; - /* U409B - 8a34001 */ + idt_8a34001: phc@5b { + compatible = "idt,8a34001"; /* u409B */ + reg = <0x5b>; + }; }; i2c_clk104: i2c@5 { #address-cells = <1>; -- 2.30.0

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