February 2021 - U-Boot

[PATCH 1/1] efi_loader: '.' and '..' are directories
by Heinrich Schuchardt 09 Feb '21

09 Feb '21

'.' and '..' are directories. So when looking for capsule files it is sufficient to check that the attribute EFI_FILE_DIRECTORY is not set. We don't have to check for these special names. Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- lib/efi_loader/efi_capsule.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/lib/efi_loader/efi_capsule.c b/lib/efi_loader/efi_capsule.c index 0d5a7b63ec..d39d731080 100644 --- a/lib/efi_loader/efi_capsule.c +++ b/lib/efi_loader/efi_capsule.c @@ -753,9 +753,7 @@ static efi_status_t efi_capsule_scan_dir(u16 ***files, unsigned int *num) if (!tmp_size) break; - if (!(dirent->attribute & EFI_FILE_DIRECTORY) && - u16_strcmp(dirent->file_name, L".") && - u16_strcmp(dirent->file_name, L"..")) + if (!(dirent->attribute & EFI_FILE_DIRECTORY)) count++; } -- 2.30.0

1 0

[PATCHv4 1/6] common: SCP03 control (enable and provision of keys)
by Jorge Ramirez-Ortiz 09 Feb '21

09 Feb '21

This Trusted Application allows enabling SCP03 as well as provisioning the keys on TEE controlled secure element (ie, NXP SE050). All the information flowing on buses (ie I2C) between the processor and the secure element must be encrypted. Secure elements are pre-provisioned with a set of keys known to the user so that the secure channel protocol (encryption) can be enforced on the first boot. This situation is however unsafe since the keys are publically available. For example, in the case of the NXP SE050, these keys would be available in the OP-TEE source tree [2] and of course in the documentation corresponding to the part. To address that, users are required to rotate/provision those keys (ie, generate new keys and write them in the secure element's persistent memory). For information on SCP03, check the Global Platform HomePage and google for that term [1] [1] globalplatform.org [2] https://github.com/OP-TEE/optee_os/ check: core/drivers/crypto/se050/adaptors/utils/scp_config.c Signed-off-by: Jorge Ramirez-Ortiz <jorge(a)foundries.io> Reviewed-by: Simon Glass <sjg(a)chromium.org> --- common/Kconfig | 8 ++++++ common/Makefile | 1 + common/scp03.c | 53 ++++++++++++++++++++++++++++++++++++ include/scp03.h | 21 ++++++++++++++ include/tee/optee_ta_scp03.h | 21 ++++++++++++++ 5 files changed, 104 insertions(+) create mode 100644 common/scp03.c create mode 100644 include/scp03.h create mode 100644 include/tee/optee_ta_scp03.h diff --git a/common/Kconfig b/common/Kconfig index 2bb3798f80..482f123534 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -588,6 +588,14 @@ config AVB_BUF_SIZE endif # AVB_VERIFY +config SCP03 + bool "Build SCP03 - Secure Channel Protocol O3 - controls" + depends on OPTEE || SANDBOX + depends on TEE + help + This option allows U-Boot to enable and or provision SCP03 on an OPTEE + controlled Secured Element. + config SPL_HASH bool # "Support hashing API (SHA1, SHA256, etc.)" help diff --git a/common/Makefile b/common/Makefile index daeea67cf2..215b8b26fd 100644 --- a/common/Makefile +++ b/common/Makefile @@ -137,3 +137,4 @@ obj-$(CONFIG_CMD_LOADB) += xyzModem.o obj-$(CONFIG_$(SPL_TPL_)YMODEM_SUPPORT) += xyzModem.o obj-$(CONFIG_AVB_VERIFY) += avb_verify.o +obj-$(CONFIG_SCP03) += scp03.o diff --git a/common/scp03.c b/common/scp03.c new file mode 100644 index 0000000000..09ef7b5ba3 --- /dev/null +++ b/common/scp03.c @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2021, Foundries.IO + * + */ + +#include <common.h> +#include <scp03.h> +#include <tee.h> +#include <tee/optee_ta_scp03.h> + +static int scp03_enable(bool provision) +{ + const struct tee_optee_ta_uuid uuid = PTA_SCP03_UUID; + struct tee_open_session_arg session; + struct tee_invoke_arg invoke; + struct tee_param param; + struct udevice *tee = NULL; + + tee = tee_find_device(tee, NULL, NULL, NULL); + if (!tee) + return -ENODEV; + + memset(&session, 0, sizeof(session)); + tee_optee_ta_uuid_to_octets(session.uuid, &uuid); + if (tee_open_session(tee, &session, 0, NULL)) + return -ENXIO; + + memset(&param, 0, sizeof(param)); + param.attr = TEE_PARAM_ATTR_TYPE_VALUE_INPUT; + param.u.value.a = provision; + + memset(&invoke, 0, sizeof(invoke)); + invoke.func = PTA_CMD_ENABLE_SCP03; + invoke.session = session.session; + + if (tee_invoke_func(tee, &invoke, 1, &param)) + return -EIO; + + tee_close_session(tee, session.session); + + return 0; +} + +int tee_enable_scp03(void) +{ + return scp03_enable(false); +} + +int tee_provision_scp03(void) +{ + return scp03_enable(true); +} diff --git a/include/scp03.h b/include/scp03.h new file mode 100644 index 0000000000..729667ccd1 --- /dev/null +++ b/include/scp03.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2021, Foundries.IO + * + */ + +#ifndef _SCP03_H +#define _SCP03_H + +/* + * Requests to OPTEE to enable or provision the Secure Channel Protocol on its + * Secure Element + * + * If key provisioning is requested, OPTEE shall generate new SCP03 keys and + * write them to the Secure Element. + * + * Both functions return < 0 on error else 0. + */ +int tee_enable_scp03(void); +int tee_provision_scp03(void); +#endif /* _SCP03_H */ diff --git a/include/tee/optee_ta_scp03.h b/include/tee/optee_ta_scp03.h new file mode 100644 index 0000000000..13f9956d98 --- /dev/null +++ b/include/tee/optee_ta_scp03.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * (C) Copyright 2021, Foundries.IO + * + */ +#ifndef __TA_SCP03_H +#define __TA_SCP03_H + +#define PTA_SCP03_UUID { 0xbe0e5821, 0xe718, 0x4f77, \ + { 0xab, 0x3e, 0x8e, 0x6c, 0x73, 0xa9, 0xc7, 0x35 } } + +/* + * Enable Secure Channel Protocol functionality (SCP03) on the Secure Element. + * Setting the operation value to something different than NULL will trigger + * the SCP03 provisioning request. + * + * in params[0].a = operation + */ +#define PTA_CMD_ENABLE_SCP03 0 + +#endif /*__TA_SCP03_H*/ -- 2.30.0

1 5

[PATCH 1/1] sandbox: allow cross-compiling sandbox
by Heinrich Schuchardt 09 Feb '21

09 Feb '21

UEFI test files like helloworld.efi require an architecture specific PE-COFF header. For non-sandbox the PE-COFF header is chosen by the target architecture. For the sandbox we use the host architecture. This is not helpful for cross compiling. Allow specifying the target architecture of the sandbox via environment variable MK_ARCH, e.g. make sandbox_defconfig NO_SDL=1 CROSS_COMPILE=aarch64-linux-gnu- NO_SDL=1 MK_ARCH=aarch64 make Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- Makefile | 2 +- doc/arch/sandbox.rst | 14 ++++++++++++++ 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 23dd11f723..286e5148ae 100644 --- a/Makefile +++ b/Makefile @@ -19,7 +19,7 @@ MAKEFLAGS += -rR --include-dir=$(CURDIR) # Determine host architecture include include/host_arch.h -MK_ARCH="${shell uname -m}" +MK_ARCH?="${shell uname -m}" unexport HOST_ARCH ifeq ("x86_64", $(MK_ARCH)) export HOST_ARCH=$(HOST_ARCH_X86_64) diff --git a/doc/arch/sandbox.rst b/doc/arch/sandbox.rst index 60ee1e0741..0dd9edc8cb 100644 --- a/doc/arch/sandbox.rst +++ b/doc/arch/sandbox.rst @@ -33,6 +33,20 @@ integers can only be built on 64-bit hosts. Note that standalone/API support is not available at present. +Cross compiling +--------------- + +When cross compiling the U-Boot sandbox with CONFIG_EFI_LOADER=y the target +architecture must be specified using the MK_ARCH environment variable using one +of the values aarch64, armv7l, i386, riscv32, riscv64, x86_64, e.g. + +.. code-block:: bash + + NO_SDL=1 make sandbox_defconfig + CROSS_COMPILE=aarch64-linux-gnu- MK_ARCH=aarch64 NO_SDL=1 make + +NO_SDL=1 was chosen in the example to remove the dependency on the SDL library. +The graphical console will not be available. Prerequisites ------------- -- 2.30.0

3 8

[PATCH] arm: dts: stm32mp15: alignment with v5.11-rc2
by Patrick Delaunay 09 Feb '21

09 Feb '21

Device tree alignment with Linux kernel v5.11-rc2 - fix DCMI DMA features on stm32mp15 family - Add alternate pinmux for FMC EBI bus - Harmonize EHCI/OHCI DT nodes name on stm32mp15 - update sdmmc IP version for STM32MP15 - Add LP timer irqs on stm32mp151 - Add LP timer wakeup-source on stm32mp151 - enable HASH by default on stm32mp15 - enable CRC1 by default on stm32mp15 - enable CRYP by default on stm32mp15 - set bus-type in DCMI endpoint for stm32mp157c-ev1 board - reorder spi4 within stm32mp15-pinctrl - add STUSB1600 Type-C using I2C4 on stm32mp15xx-dkx - fix mdma1 clients channel priority level on stm32mp151 - fix dmamux reg property on stm32mp151 - adjust USB OTG gadget fifo sizes in stm32mp151 - update stm32mp151 for remote proc synchronization support - support child mfd cells for the stm32mp1 TAMP syscon Signed-off-by: Patrick Delaunay <patrick.delaunay(a)st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay(a)foss.st.com> --- arch/arm/dts/stm32mp15-pinctrl.dtsi | 87 +++++++++++++++++++++- arch/arm/dts/stm32mp151.dtsi | 48 +++++++++--- arch/arm/dts/stm32mp153.dtsi | 6 ++ arch/arm/dts/stm32mp157c-dk2.dts | 4 + arch/arm/dts/stm32mp157c-ed1.dts | 27 +++++++ arch/arm/dts/stm32mp157c-ev1.dts | 1 + arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi | 55 -------------- arch/arm/dts/stm32mp15xx-dkx.dtsi | 47 ++++++++++-- 8 files changed, 200 insertions(+), 75 deletions(-) diff --git a/arch/arm/dts/stm32mp15-pinctrl.dtsi b/arch/arm/dts/stm32mp15-pinctrl.dtsi index 154832983c..dd4bd1e554 100644 --- a/arch/arm/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/dts/stm32mp15-pinctrl.dtsi @@ -349,6 +349,61 @@ }; }; + fmc_pins_b: fmc-1 { + pins { + pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */ + <STM32_PINMUX('D', 5, AF12)>, /* FMC_NWE */ + <STM32_PINMUX('B', 7, AF12)>, /* FMC_NL */ + <STM32_PINMUX('D', 14, AF12)>, /* FMC_D0 */ + <STM32_PINMUX('D', 15, AF12)>, /* FMC_D1 */ + <STM32_PINMUX('D', 0, AF12)>, /* FMC_D2 */ + <STM32_PINMUX('D', 1, AF12)>, /* FMC_D3 */ + <STM32_PINMUX('E', 7, AF12)>, /* FMC_D4 */ + <STM32_PINMUX('E', 8, AF12)>, /* FMC_D5 */ + <STM32_PINMUX('E', 9, AF12)>, /* FMC_D6 */ + <STM32_PINMUX('E', 10, AF12)>, /* FMC_D7 */ + <STM32_PINMUX('E', 11, AF12)>, /* FMC_D8 */ + <STM32_PINMUX('E', 12, AF12)>, /* FMC_D9 */ + <STM32_PINMUX('E', 13, AF12)>, /* FMC_D10 */ + <STM32_PINMUX('E', 14, AF12)>, /* FMC_D11 */ + <STM32_PINMUX('E', 15, AF12)>, /* FMC_D12 */ + <STM32_PINMUX('D', 8, AF12)>, /* FMC_D13 */ + <STM32_PINMUX('D', 9, AF12)>, /* FMC_D14 */ + <STM32_PINMUX('D', 10, AF12)>, /* FMC_D15 */ + <STM32_PINMUX('G', 9, AF12)>, /* FMC_NE2_FMC_NCE */ + <STM32_PINMUX('G', 12, AF12)>; /* FMC_NE4 */ + bias-disable; + drive-push-pull; + slew-rate = <3>; + }; + }; + + fmc_sleep_pins_b: fmc-sleep-1 { + pins { + pinmux = <STM32_PINMUX('D', 4, ANALOG)>, /* FMC_NOE */ + <STM32_PINMUX('D', 5, ANALOG)>, /* FMC_NWE */ + <STM32_PINMUX('B', 7, ANALOG)>, /* FMC_NL */ + <STM32_PINMUX('D', 14, ANALOG)>, /* FMC_D0 */ + <STM32_PINMUX('D', 15, ANALOG)>, /* FMC_D1 */ + <STM32_PINMUX('D', 0, ANALOG)>, /* FMC_D2 */ + <STM32_PINMUX('D', 1, ANALOG)>, /* FMC_D3 */ + <STM32_PINMUX('E', 7, ANALOG)>, /* FMC_D4 */ + <STM32_PINMUX('E', 8, ANALOG)>, /* FMC_D5 */ + <STM32_PINMUX('E', 9, ANALOG)>, /* FMC_D6 */ + <STM32_PINMUX('E', 10, ANALOG)>, /* FMC_D7 */ + <STM32_PINMUX('E', 11, ANALOG)>, /* FMC_D8 */ + <STM32_PINMUX('E', 12, ANALOG)>, /* FMC_D9 */ + <STM32_PINMUX('E', 13, ANALOG)>, /* FMC_D10 */ + <STM32_PINMUX('E', 14, ANALOG)>, /* FMC_D11 */ + <STM32_PINMUX('E', 15, ANALOG)>, /* FMC_D12 */ + <STM32_PINMUX('D', 8, ANALOG)>, /* FMC_D13 */ + <STM32_PINMUX('D', 9, ANALOG)>, /* FMC_D14 */ + <STM32_PINMUX('D', 10, ANALOG)>, /* FMC_D15 */ + <STM32_PINMUX('G', 9, ANALOG)>, /* FMC_NE2_FMC_NCE */ + <STM32_PINMUX('G', 12, ANALOG)>; /* FMC_NE4 */ + }; + }; + i2c1_pins_a: i2c1-0 { pins { pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */ @@ -1437,6 +1492,24 @@ }; }; + sdmmc2_d47_pins_d: sdmmc2-d47-3 { + pins { + pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */ + <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */ + <STM32_PINMUX('E', 5, AF9)>, /* SDMMC2_D6 */ + <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */ + }; + }; + + sdmmc2_d47_sleep_pins_d: sdmmc2-d47-sleep-3 { + pins { + pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */ + <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */ + <STM32_PINMUX('E', 5, ANALOG)>, /* SDMMC2_D6 */ + <STM32_PINMUX('C', 7, ANALOG)>; /* SDMMC2_D7 */ + }; + }; + sdmmc3_b4_pins_a: sdmmc3-b4-0 { pins1 { pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */ @@ -1588,9 +1661,9 @@ }; stusb1600_pins_a: stusb1600-0 { - pins { - pinmux = <STM32_PINMUX('I', 11, ANALOG)>; - bias-pull-up; + pins { + pinmux = <STM32_PINMUX('I', 11, ANALOG)>; + bias-pull-up; }; }; @@ -1721,6 +1794,14 @@ }; }; + uart8_rtscts_pins_a: uart8rtscts-0 { + pins { + pinmux = <STM32_PINMUX('G', 7, AF8)>, /* UART8_RTS */ + <STM32_PINMUX('G', 10, AF8)>; /* UART8_CTS */ + bias-disable; + }; + }; + usart2_pins_a: usart2-0 { pins1 { pinmux = <STM32_PINMUX('F', 5, AF7)>, /* USART2_TX */ diff --git a/arch/arm/dts/stm32mp151.dtsi b/arch/arm/dts/stm32mp151.dtsi index 206d3d3c78..eedea6f4b8 100644 --- a/arch/arm/dts/stm32mp151.dtsi +++ b/arch/arm/dts/stm32mp151.dtsi @@ -41,6 +41,13 @@ }; }; + arm-pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>; + interrupt-parent = <&intc>; + }; + psci { compatible = "arm,psci-1.0"; method = "smc"; @@ -373,8 +380,10 @@ #size-cells = <0>; compatible = "st,stm32-lptimer"; reg = <0x40009000 0x400>; + interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc LPTIM1_K>; clock-names = "mux"; + wakeup-source; status = "disabled"; pwm { @@ -1010,7 +1019,7 @@ dmamux1: dma-router@48002000 { compatible = "st,stm32h7-dmamux"; - reg = <0x48002000 0x1c>; + reg = <0x48002000 0x40>; #dma-cells = <3>; dma-requests = <128>; dma-masters = <&dma1 &dma2>; @@ -1058,7 +1067,7 @@ sdmmc3: sdmmc@48004000 { compatible = "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x10153180>; + arm,primecell-periphid = <0x00253180>; reg = <0x48004000 0x400>; interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "cmd_irq"; @@ -1079,9 +1088,9 @@ resets = <&rcc USBO_R>; reset-names = "dwc2"; interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; - g-rx-fifo-size = <256>; + g-rx-fifo-size = <512>; g-np-tx-fifo-size = <32>; - g-tx-fifo-size = <128 128 64 64 64 64 32 32>; + g-tx-fifo-size = <256 16 16 16 16 16 16 16>; dr_mode = "otg"; usb33d-supply = <&usb33>; status = "disabled"; @@ -1117,7 +1126,7 @@ resets = <&rcc CAMITF_R>; clocks = <&rcc DCMI>; clock-names = "mclk"; - dmas = <&dmamux1 75 0x400 0x0d>; + dmas = <&dmamux1 75 0x400 0x01>; dma-names = "tx"; status = "disabled"; }; @@ -1175,8 +1184,10 @@ #size-cells = <0>; compatible = "st,stm32-lptimer"; reg = <0x50021000 0x400>; + interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc LPTIM2_K>; clock-names = "mux"; + wakeup-source; status = "disabled"; pwm { @@ -1202,8 +1213,10 @@ #size-cells = <0>; compatible = "st,stm32-lptimer"; reg = <0x50022000 0x400>; + interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc LPTIM3_K>; clock-names = "mux"; + wakeup-source; status = "disabled"; pwm { @@ -1222,8 +1235,10 @@ lptimer4: timer@50023000 { compatible = "st,stm32-lptimer"; reg = <0x50023000 0x400>; + interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc LPTIM4_K>; clock-names = "mux"; + wakeup-source; status = "disabled"; pwm { @@ -1236,8 +1251,10 @@ lptimer5: timer@50024000 { compatible = "st,stm32-lptimer"; reg = <0x50024000 0x400>; + interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc LPTIM5_K>; clock-names = "mux"; + wakeup-source; status = "disabled"; pwm { @@ -1303,7 +1320,7 @@ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc HASH1>; resets = <&rcc HASH1_R>; - dmas = <&mdma1 31 0x10 0x1000A02 0x0 0x0>; + dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0>; dma-names = "in"; dma-maxburst = <2>; status = "disabled"; @@ -1367,8 +1384,8 @@ reg = <0x58003000 0x1000>, <0x70000000 0x10000000>; reg-names = "qspi", "qspi_mm"; interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&mdma1 22 0x10 0x100002 0x0 0x0>, - <&mdma1 22 0x10 0x100008 0x0 0x0>; + dmas = <&mdma1 22 0x2 0x100002 0x0 0x0>, + <&mdma1 22 0x2 0x100008 0x0 0x0>; dma-names = "tx", "rx"; clocks = <&rcc QSPI_K>; resets = <&rcc QSPI_R>; @@ -1379,7 +1396,7 @@ sdmmc1: sdmmc@58005000 { compatible = "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x10153180>; + arm,primecell-periphid = <0x00253180>; reg = <0x58005000 0x1000>; interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "cmd_irq"; @@ -1394,7 +1411,7 @@ sdmmc2: sdmmc@58007000 { compatible = "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x10153180>; + arm,primecell-periphid = <0x00253180>; reg = <0x58007000 0x1000>; interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "cmd_irq"; @@ -1445,7 +1462,7 @@ status = "disabled"; }; - usbh_ohci: usbh-ohci@5800c000 { + usbh_ohci: usb@5800c000 { compatible = "generic-ohci"; reg = <0x5800c000 0x1000>; clocks = <&rcc USBH>; @@ -1454,7 +1471,7 @@ status = "disabled"; }; - usbh_ehci: usbh-ehci@5800d000 { + usbh_ehci: usb@5800d000 { compatible = "generic-ehci"; reg = <0x5800d000 0x1000>; clocks = <&rcc USBH>; @@ -1587,6 +1604,11 @@ status = "disabled"; }; + tamp: tamp@5c00a000 { + compatible = "st,stm32-tamp", "syscon", "simple-mfd"; + reg = <0x5c00a000 0x400>; + }; + /* * Break node order to solve dependency probe issue between * pinctrl and exti. @@ -1765,6 +1787,8 @@ st,syscfg-holdboot = <&rcc 0x10C 0x1>; st,syscfg-tz = <&rcc 0x000 0x1>; st,syscfg-pdds = <&pwr_mcu 0x0 0x1>; + st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>; + st,syscfg-m4-state = <&tamp 0x148 0xFFFFFFFF>; status = "disabled"; }; }; diff --git a/arch/arm/dts/stm32mp153.dtsi b/arch/arm/dts/stm32mp153.dtsi index 6d9ab08667..1c1889b194 100644 --- a/arch/arm/dts/stm32mp153.dtsi +++ b/arch/arm/dts/stm32mp153.dtsi @@ -16,6 +16,12 @@ }; }; + arm-pmu { + interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>; + }; + soc { m_can1: can@4400e000 { compatible = "bosch,m_can"; diff --git a/arch/arm/dts/stm32mp157c-dk2.dts b/arch/arm/dts/stm32mp157c-dk2.dts index 045636555d..2bc92ef3ae 100644 --- a/arch/arm/dts/stm32mp157c-dk2.dts +++ b/arch/arm/dts/stm32mp157c-dk2.dts @@ -29,6 +29,10 @@ }; }; +&cryp1 { + status = "okay"; +}; + &dsi { status = "okay"; phy-dsi-supply = <&reg18>; diff --git a/arch/arm/dts/stm32mp157c-ed1.dts b/arch/arm/dts/stm32mp157c-ed1.dts index dd911c9932..6e89f88a17 100644 --- a/arch/arm/dts/stm32mp157c-ed1.dts +++ b/arch/arm/dts/stm32mp157c-ed1.dts @@ -89,6 +89,14 @@ states = <1800000 0x1>, <2900000 0x0>; }; + + vin: vin { + compatible = "regulator-fixed"; + regulator-name = "vin"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; }; &adc { @@ -115,6 +123,14 @@ cpu-supply = <&vddcore>; }; +&crc1 { + status = "okay"; +}; + +&cryp1 { + status = "okay"; +}; + &dac { pinctrl-names = "default"; pinctrl-0 = <&dac_ch1_pins_a &dac_ch2_pins_a>; @@ -136,6 +152,10 @@ contiguous-area = <&gpu_reserved>; }; +&hash1 { + status = "okay"; +}; + &i2c4 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c4_pins_a>; @@ -158,11 +178,18 @@ regulators { compatible = "st,stpmic1-regulators"; + buck1-supply = <&vin>; + buck2-supply = <&vin>; + buck3-supply = <&vin>; + buck4-supply = <&vin>; ldo1-supply = <&v3v3>; ldo2-supply = <&v3v3>; ldo3-supply = <&vdd_ddr>; + ldo4-supply = <&vin>; ldo5-supply = <&v3v3>; ldo6-supply = <&v3v3>; + vref_ddr-supply = <&vin>; + boost-supply = <&vin>; pwr_sw1-supply = <&bst_out>; pwr_sw2-supply = <&bst_out>; diff --git a/arch/arm/dts/stm32mp157c-ev1.dts b/arch/arm/dts/stm32mp157c-ev1.dts index a55e80ce26..5c5b1ddf7b 100644 --- a/arch/arm/dts/stm32mp157c-ev1.dts +++ b/arch/arm/dts/stm32mp157c-ev1.dts @@ -90,6 +90,7 @@ port { dcmi_0: endpoint { remote-endpoint = <&ov5640_0>; + bus-type = <5>; bus-width = <8>; hsync-active = <0>; vsync-active = <0>; diff --git a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi index 6868769c6e..11bc247065 100644 --- a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi @@ -76,61 +76,6 @@ pinctrl-1 = <&fmc_sleep_pins_b &mco2_sleep_pins_a>; pinctrl-names = "default", "sleep"; - fmc_pins_b: fmc-0 { - pins1 { - pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */ - <STM32_PINMUX('D', 5, AF12)>, /* FMC_NWE */ - <STM32_PINMUX('B', 7, AF12)>, /* FMC_NL */ - <STM32_PINMUX('D', 14, AF12)>, /* FMC_D0 */ - <STM32_PINMUX('D', 15, AF12)>, /* FMC_D1 */ - <STM32_PINMUX('D', 0, AF12)>, /* FMC_D2 */ - <STM32_PINMUX('D', 1, AF12)>, /* FMC_D3 */ - <STM32_PINMUX('E', 7, AF12)>, /* FMC_D4 */ - <STM32_PINMUX('E', 8, AF12)>, /* FMC_D5 */ - <STM32_PINMUX('E', 9, AF12)>, /* FMC_D6 */ - <STM32_PINMUX('E', 10, AF12)>, /* FMC_D7 */ - <STM32_PINMUX('E', 11, AF12)>, /* FMC_D8 */ - <STM32_PINMUX('E', 12, AF12)>, /* FMC_D9 */ - <STM32_PINMUX('E', 13, AF12)>, /* FMC_D10 */ - <STM32_PINMUX('E', 14, AF12)>, /* FMC_D11 */ - <STM32_PINMUX('E', 15, AF12)>, /* FMC_D12 */ - <STM32_PINMUX('D', 8, AF12)>, /* FMC_D13 */ - <STM32_PINMUX('D', 9, AF12)>, /* FMC_D14 */ - <STM32_PINMUX('D', 10, AF12)>, /* FMC_D15 */ - <STM32_PINMUX('G', 9, AF12)>, /* FMC_NE2_FMC_NCE */ - <STM32_PINMUX('G', 12, AF12)>; /* FMC_NE4 */ - bias-disable; - drive-push-pull; - slew-rate = <3>; - }; - }; - - fmc_sleep_pins_b: fmc-sleep-0 { - pins { - pinmux = <STM32_PINMUX('D', 4, ANALOG)>, /* FMC_NOE */ - <STM32_PINMUX('D', 5, ANALOG)>, /* FMC_NWE */ - <STM32_PINMUX('B', 7, ANALOG)>, /* FMC_NL */ - <STM32_PINMUX('D', 14, ANALOG)>, /* FMC_D0 */ - <STM32_PINMUX('D', 15, ANALOG)>, /* FMC_D1 */ - <STM32_PINMUX('D', 0, ANALOG)>, /* FMC_D2 */ - <STM32_PINMUX('D', 1, ANALOG)>, /* FMC_D3 */ - <STM32_PINMUX('E', 7, ANALOG)>, /* FMC_D4 */ - <STM32_PINMUX('E', 8, ANALOG)>, /* FMC_D5 */ - <STM32_PINMUX('E', 9, ANALOG)>, /* FMC_D6 */ - <STM32_PINMUX('E', 10, ANALOG)>, /* FMC_D7 */ - <STM32_PINMUX('E', 11, ANALOG)>, /* FMC_D8 */ - <STM32_PINMUX('E', 12, ANALOG)>, /* FMC_D9 */ - <STM32_PINMUX('E', 13, ANALOG)>, /* FMC_D10 */ - <STM32_PINMUX('E', 14, ANALOG)>, /* FMC_D11 */ - <STM32_PINMUX('E', 15, ANALOG)>, /* FMC_D12 */ - <STM32_PINMUX('D', 8, ANALOG)>, /* FMC_D13 */ - <STM32_PINMUX('D', 9, ANALOG)>, /* FMC_D14 */ - <STM32_PINMUX('D', 10, ANALOG)>, /* FMC_D15 */ - <STM32_PINMUX('G', 9, ANALOG)>, /* FMC_NE2_FMC_NCE */ - <STM32_PINMUX('G', 12, ANALOG)>; /* FMC_NE4 */ - }; - }; - mco2_pins_a: mco2-0 { pins { pinmux = <STM32_PINMUX('G', 2, AF1)>; /* MCO2 */ diff --git a/arch/arm/dts/stm32mp15xx-dkx.dtsi b/arch/arm/dts/stm32mp15xx-dkx.dtsi index aa4aa83e05..68987f64c5 100644 --- a/arch/arm/dts/stm32mp15xx-dkx.dtsi +++ b/arch/arm/dts/stm32mp15xx-dkx.dtsi @@ -80,6 +80,14 @@ dais = <&sai2a_port &sai2b_port &i2s2_port>; status = "okay"; }; + + vin: vin { + compatible = "regulator-fixed"; + regulator-name = "vin"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; }; &adc { @@ -116,6 +124,10 @@ status = "okay"; }; +&crc1 { + status = "okay"; +}; + &dts { status = "okay"; }; @@ -151,6 +163,10 @@ contiguous-area = <&gpu_reserved>; }; +&hash1 { + status = "okay"; +}; + &i2c1 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c1_pins_a>; @@ -238,21 +254,27 @@ /delete-property/dmas; /delete-property/dma-names; - typec: stusb1600@28 { + stusb1600@28 { compatible = "st,stusb1600"; reg = <0x28>; interrupts = <11 IRQ_TYPE_EDGE_FALLING>; interrupt-parent = <&gpioi>; pinctrl-names = "default"; pinctrl-0 = <&stusb1600_pins_a>; - status = "okay"; + vdd-supply = <&vin>; - typec_con: connector { + connector { compatible = "usb-c-connector"; label = "USB-C"; - power-role = "sink"; - power-opmode = "default"; + power-role = "dual"; + typec-power-opmode = "default"; + + port { + con_usbotg_hs_ep: endpoint { + remote-endpoint = <&usbotg_hs_ep>; + }; + }; }; }; @@ -266,9 +288,18 @@ regulators { compatible = "st,stpmic1-regulators"; + buck1-supply = <&vin>; + buck2-supply = <&vin>; + buck3-supply = <&vin>; + buck4-supply = <&vin>; ldo1-supply = <&v3v3>; + ldo2-supply = <&vin>; ldo3-supply = <&vdd_ddr>; + ldo4-supply = <&vin>; + ldo5-supply = <&vin>; ldo6-supply = <&v3v3>; + vref_ddr-supply = <&vin>; + boost-supply = <&vin>; pwr_sw1-supply = <&bst_out>; pwr_sw2-supply = <&bst_out>; @@ -657,6 +688,12 @@ phy-names = "usb2-phy"; usb-role-switch; status = "okay"; + + port { + usbotg_hs_ep: endpoint { + remote-endpoint = <&con_usbotg_hs_ep>; + }; + }; }; &usbphyc { -- 2.17.1

3 4

[RFC PATCH] efi_loader: disable GRUB workaround by default
by matthias.bgg＠kernel.org 09 Feb '21

09 Feb '21

From: Matthias Brugger <mbrugger(a)suse.com> GRUB version 2.04 was published over a year ago. We should expect that distros use this version now. So disable the workaround by default. As we know that i.MX6 CPUs lack proper handling of caches, enable the workaround on these only. Signed-off-by: Matthias Brugger <mbrugger(a)suse.com> --- configs/imx6dl_icore_nand_defconfig | 1 + configs/imx6dl_mamoj_defconfig | 1 + configs/imx6q_icore_nand_defconfig | 1 + configs/imx6q_logic_defconfig | 1 + configs/imx6qdl_icore_mipi_defconfig | 1 + configs/imx6qdl_icore_mmc_defconfig | 1 + configs/imx6qdl_icore_nand_defconfig | 1 + configs/imx6qdl_icore_rqs_defconfig | 1 + configs/imx6ul_geam_mmc_defconfig | 1 + configs/imx6ul_geam_nand_defconfig | 1 + configs/imx6ul_isiot_emmc_defconfig | 1 + configs/imx6ul_isiot_nand_defconfig | 1 + lib/efi_loader/Kconfig | 2 +- 13 files changed, 13 insertions(+), 1 deletion(-) diff --git a/configs/imx6dl_icore_nand_defconfig b/configs/imx6dl_icore_nand_defconfig index 06005c4288..44fbbe6bd1 100644 --- a/configs/imx6dl_icore_nand_defconfig +++ b/configs/imx6dl_icore_nand_defconfig @@ -68,3 +68,4 @@ CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_VIDEO_BMP_RLE8=y CONFIG_BMP_16BPP=y +CONFIG_EFI_GRUB_ARM32_WORKAROUND=y diff --git a/configs/imx6dl_mamoj_defconfig b/configs/imx6dl_mamoj_defconfig index fa2adaf47d..7ebbb5830b 100644 --- a/configs/imx6dl_mamoj_defconfig +++ b/configs/imx6dl_mamoj_defconfig @@ -57,3 +57,4 @@ CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y +CONFIG_EFI_GRUB_ARM32_WORKAROUND=y diff --git a/configs/imx6q_icore_nand_defconfig b/configs/imx6q_icore_nand_defconfig index f38b06dab9..cef5f3448d 100644 --- a/configs/imx6q_icore_nand_defconfig +++ b/configs/imx6q_icore_nand_defconfig @@ -69,3 +69,4 @@ CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_VIDEO_BMP_RLE8=y CONFIG_BMP_16BPP=y +CONFIG_EFI_GRUB_ARM32_WORKAROUND=y diff --git a/configs/imx6q_logic_defconfig b/configs/imx6q_logic_defconfig index 36dc24d080..b5a4d3d24d 100644 --- a/configs/imx6q_logic_defconfig +++ b/configs/imx6q_logic_defconfig @@ -103,3 +103,4 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_EFI_GRUB_ARM32_WORKAROUND=y diff --git a/configs/imx6qdl_icore_mipi_defconfig b/configs/imx6qdl_icore_mipi_defconfig index f1b5389470..1d9e021844 100644 --- a/configs/imx6qdl_icore_mipi_defconfig +++ b/configs/imx6qdl_icore_mipi_defconfig @@ -63,3 +63,4 @@ CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y +CONFIG_EFI_GRUB_ARM32_WORKAROUND=y diff --git a/configs/imx6qdl_icore_mmc_defconfig b/configs/imx6qdl_icore_mmc_defconfig index a32ae6a75d..b46d19ad88 100644 --- a/configs/imx6qdl_icore_mmc_defconfig +++ b/configs/imx6qdl_icore_mmc_defconfig @@ -86,3 +86,4 @@ CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_VIDEO_BMP_RLE8=y CONFIG_BMP_16BPP=y CONFIG_IMX_WATCHDOG=y +CONFIG_EFI_GRUB_ARM32_WORKAROUND=y diff --git a/configs/imx6qdl_icore_nand_defconfig b/configs/imx6qdl_icore_nand_defconfig index f38b06dab9..cef5f3448d 100644 --- a/configs/imx6qdl_icore_nand_defconfig +++ b/configs/imx6qdl_icore_nand_defconfig @@ -69,3 +69,4 @@ CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_VIDEO_BMP_RLE8=y CONFIG_BMP_16BPP=y +CONFIG_EFI_GRUB_ARM32_WORKAROUND=y diff --git a/configs/imx6qdl_icore_rqs_defconfig b/configs/imx6qdl_icore_rqs_defconfig index 34e3250f95..db439255a5 100644 --- a/configs/imx6qdl_icore_rqs_defconfig +++ b/configs/imx6qdl_icore_rqs_defconfig @@ -60,3 +60,4 @@ CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_MXC_UART=y +CONFIG_EFI_GRUB_ARM32_WORKAROUND=y diff --git a/configs/imx6ul_geam_mmc_defconfig b/configs/imx6ul_geam_mmc_defconfig index 4b47e196f3..ae83d35a53 100644 --- a/configs/imx6ul_geam_mmc_defconfig +++ b/configs/imx6ul_geam_mmc_defconfig @@ -55,3 +55,4 @@ CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y +CONFIG_EFI_GRUB_ARM32_WORKAROUND=y diff --git a/configs/imx6ul_geam_nand_defconfig b/configs/imx6ul_geam_nand_defconfig index 9870612edf..8bffdab9c8 100644 --- a/configs/imx6ul_geam_nand_defconfig +++ b/configs/imx6ul_geam_nand_defconfig @@ -60,3 +60,4 @@ CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y +CONFIG_EFI_GRUB_ARM32_WORKAROUND=y diff --git a/configs/imx6ul_isiot_emmc_defconfig b/configs/imx6ul_isiot_emmc_defconfig index 2e33db21d8..f8614b23c9 100644 --- a/configs/imx6ul_isiot_emmc_defconfig +++ b/configs/imx6ul_isiot_emmc_defconfig @@ -55,3 +55,4 @@ CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y +CONFIG_EFI_GRUB_ARM32_WORKAROUND=y diff --git a/configs/imx6ul_isiot_nand_defconfig b/configs/imx6ul_isiot_nand_defconfig index 9c4f742135..aec4563837 100644 --- a/configs/imx6ul_isiot_nand_defconfig +++ b/configs/imx6ul_isiot_nand_defconfig @@ -60,3 +60,4 @@ CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y +CONFIG_EFI_GRUB_ARM32_WORKAROUND=y diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig index e729f727df..68ca183c68 100644 --- a/lib/efi_loader/Kconfig +++ b/lib/efi_loader/Kconfig @@ -282,7 +282,7 @@ config EFI_HAVE_RUNTIME_RESET config EFI_GRUB_ARM32_WORKAROUND bool "Workaround for GRUB on 32bit ARM" default n if ARCH_QEMU - default y + default n depends on ARM && !ARM64 help GRUB prior to version 2.04 requires U-Boot to disable caches. This -- 2.30.0

3 2

[PATCH 0/8] rockchip: resurrect rk3368 functionality and make lion bootable again
by Heiko Stuebner 09 Feb '21

09 Feb '21

From: Heiko Stuebner <heiko.stuebner(a)theobroma-systems.com> With current u-boot (and probably for some time now) rk3368-lion can't boot anymore. As the patches indicate, that is partially on the lion support but also on general rk3368-support not fitting current expectations anymore. So this series, adapts options to what other Rockchip SoCs do and makes lion also bootable again. Heiko Stuebner (8): rockchip: rk3368: adjust CONFIG_SYS_LOAD_ADDR rockchip: rk3368: set CONFIG_SYS_BOOTM_LEN to 64MB rockchip: rk3368: increase SYS_MALLOC_F_LEN to 0x4000 rockchip: rk3368: move STACK_R_ADDR address and into Kconfig rockchip: rk3368: sync clock dt-binding header from Linux rockchip: rk3368: sync main rk3368 dtsi from Linux rockchip: rk3368: sync down rk3368-lion board devicetree from Linux rockchip: lion: update board defconfig arch/arm/dts/Makefile | 2 +- arch/arm/dts/rk3368-geekbox-u-boot.dtsi | 2 + ...ot.dtsi => rk3368-lion-haikou-u-boot.dtsi} | 6 + arch/arm/dts/rk3368-lion-haikou.dts | 140 +++++ .../dts/{rk3368-lion.dts => rk3368-lion.dtsi} | 271 ++++++-- arch/arm/dts/rk3368-px5-evb-u-boot.dtsi | 3 + arch/arm/dts/rk3368-sheep-u-boot.dtsi | 2 + arch/arm/dts/rk3368-u-boot.dtsi | 27 + arch/arm/dts/rk3368.dtsi | 578 +++++++++++------- arch/arm/mach-rockchip/rk3368/Kconfig | 5 +- configs/lion-rk3368_defconfig | 19 +- include/configs/rk3368_common.h | 4 +- include/dt-bindings/clock/rk3368-cru.h | 31 +- 13 files changed, 769 insertions(+), 321 deletions(-) rename arch/arm/dts/{rk3368-lion-u-boot.dtsi => rk3368-lion-haikou-u-boot.dtsi} (96%) create mode 100644 arch/arm/dts/rk3368-lion-haikou.dts rename arch/arm/dts/{rk3368-lion.dts => rk3368-lion.dtsi} (54%) create mode 100644 arch/arm/dts/rk3368-u-boot.dtsi -- 2.29.2

1 8

[PATCH] ARM: dts: stm32: Fix cosmetic typo: use 'kHz' as kilohertz abbreviation
by Fabrice GIRARDOT 09 Feb '21

09 Feb '21

The kilohertz unit abbreviation should read 'kHz'. Note to STM32 team: modified files were generated, it may be worth to fix STM32CubeMX tool. Signed-off-by: Fabrice GIRARDOT <fabrice.girardot(a)flowbird.group> --- arch/arm/dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi | 2 +- arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi b/arch/arm/dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi index b4787c4..978331b 100644 --- a/arch/arm/dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi +++ b/arch/arm/dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi @@ -15,7 +15,7 @@ * Save Date: 2020.02.20, save Time: 18:45:20 */ #define DDR_MEM_COMPATIBLE ddr3-1066-888-bin-g-1x4gb-533mhz -#define DDR_MEM_NAME "DDR3-DDR3L 16bits 533000Khz" +#define DDR_MEM_NAME "DDR3-DDR3L 16bits 533000kHz" #define DDR_MEM_SPEED 533000 #define DDR_MEM_SIZE 0x20000000 diff --git a/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi b/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi index dc2875c..426be21 100644 --- a/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi +++ b/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi @@ -15,7 +15,7 @@ * Save Date: 2020.02.20, save Time: 18:49:33 */ #define DDR_MEM_COMPATIBLE ddr3-1066-888-bin-g-2x4gb-533mhz -#define DDR_MEM_NAME "DDR3-DDR3L 32bits 533000Khz" +#define DDR_MEM_NAME "DDR3-DDR3L 32bits 533000kHz" #define DDR_MEM_SPEED 533000 #define DDR_MEM_SIZE 0x40000000 -- 2.7.4

2 2

[PATCH] clk: stm32mp1: add support of I2C6_K
by Patrick Delaunay 09 Feb '21

09 Feb '21

Add support of missing I2C6_K with bit 3 of RCC_MC_APB5ENSETR = I2C6EN: I2C6 peripheral clocks enable. This patch allows customer to use I2C6 in SPL or in U-Boot as other I2C instance, already support in clk driver. Signed-off-by: Patrick Delaunay <patrick.delaunay(a)foss.st.com> --- drivers/clk/clk_stm32mp1.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/clk_stm32mp1.c index d4f1048591..8a5bdcb11d 100644 --- a/drivers/clk/clk_stm32mp1.c +++ b/drivers/clk/clk_stm32mp1.c @@ -549,6 +549,7 @@ static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = { STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL), STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL), + STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 3, I2C6_K, _I2C46_SEL), STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 8, RTCAPB, _PCLK5), STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL), -- 2.17.1

3 2

[PATCH 0/2] pinctrl: stm32: correction for pinmux status
by Patrick Delaunay 09 Feb '21

09 Feb '21

This serie solve 2 issues found in output of command "pinmux status -a" when I test the serie [1]. [1] "gpio: Update and simplify the uclass API" http://patchwork.ozlabs.org/project/uboot/list/?series=225585 Patrick Delaunay (2): pinctrl: stm32: correct management pin display of OTYPE pinctrl: stm32: bind only the enabled GPIO subnode drivers/pinctrl/pinctrl_stm32.c | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) -- 2.17.1

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[PATCH v2 0/3] Allow disabling driver model for I2C in SPL
by Igor Opaniuk 09 Feb '21

09 Feb '21

From: Igor Opaniuk <igor.opaniuk(a)foundries.io> At present if U-Boot proper uses driver model for I2C, then SPL has to also. While this is desirable, it places a significant barrier to moving to driver model in some cases. For example, with a space-constrained SPL it may be necessary to enable CONFIG_SPL_OF_PLATDATA which involves adjusting some drivers. This patch introduces a separate Kconfig symbols for enabling DM_I2C and DM_I2C_GPIO support in SPL. This will also help to get away from dirty workarounds to achieve non-DM I2C support for SPL, which is currently used in some board header files like: ifdef CONFIG_SPL_BUILD undef CONFIG_DM_I2C endif All occurences were replaced automatically using these bash cmds: $ find . -type f -exec sed -i 's/ifndef CONFIG_DM_I2C/if !CONFIG_IS_ENABLED(DM_I2C)/g' {} + $ find . -type f -exec sed -i 's/ifdef CONFIG_DM_I2C/if CONFIG_IS_ENABLED(DM_I2C)/g' {} + $ find . -type f -exec sed -i 's/defined(CONFIG_DM_I2C)/CONFIG_IS_ENABLED(DM_I2C)/g' {} + $ find . -type f -exec sed -i 's/ifndef CONFIG_DM_I2C_GPIO/if !CONFIG_IS_ENABLED(DM_I2C_GPIO)/g' {} + $ find . -type f -exec sed -i 's/ifdef CONFIG_DM_I2C_GPIO/if CONFIG_IS_ENABLED(DM_I2C_GPIO)/g' {} + $ find . -type f -exec sed -i 's/defined(CONFIG_DM_I2C_GPIO)/CONFIG_IS_ENABLED(DM_I2C_GPIO)/g' {} + Azure CI results: https://dev.azure.com/igoropaniuk/u-boot/_build/results?buildId=5&view=resu… Changes in v2: - Applied R-b tags from Simon and Heiko - Added additional patches that replace CONFIG_DM_I2C undefs with CONFIG_SPL_DM_I2C for SPL build case (this should be moved to board defconfigs by board maintainers) Igor Opaniuk (3): dm: i2c: allow disabling driver model in SPL board: freescale: undef CONFIG_SPL_DM_I2C for SPL dm: i2c: use CONFIG_IS_ENABLED macro for DM_I2C/DM_I2C_GPIO .../include/asm/arch-fsl-layerscape/config.h | 2 +- arch/arm/include/asm/arch-lpc32xx/i2c.h | 2 +- arch/arm/include/asm/mach-imx/mxc_i2c.h | 2 +- arch/arm/include/asm/omap_i2c.h | 2 +- arch/arm/mach-imx/i2c-mxv7.c | 2 +- arch/arm/mach-keystone/ddr3_spd.c | 2 +- arch/arm/mach-kirkwood/include/mach/config.h | 2 +- arch/arm/mach-omap2/am33xx/board.c | 2 +- arch/arm/mach-omap2/am33xx/clk_synthesizer.c | 6 +- arch/arm/mach-omap2/boot-common.c | 2 +- arch/arm/mach-omap2/clocks-common.c | 2 +- arch/arm/mach-sunxi/board.c | 2 +- arch/powerpc/include/asm/fsl_i2c.h | 2 +- board/freescale/common/dcu_sii9022a.c | 2 +- board/freescale/common/diu_ch7301.c | 2 +- board/freescale/common/emc2305.c | 4 +- board/freescale/common/qixis.c | 4 +- board/freescale/common/sys_eeprom.c | 20 ++-- board/freescale/common/vid.c | 24 ++--- board/freescale/common/vsc3316_3308.c | 10 +- board/freescale/ls1012aqds/ls1012aqds.c | 2 +- board/freescale/ls1012ardb/eth.c | 2 +- board/freescale/ls1012ardb/ls1012ardb.c | 12 +-- board/freescale/ls1021aqds/dcu.c | 6 +- board/freescale/ls1021aqds/ls1021aqds.c | 2 +- board/freescale/ls1021atwr/ls1021atwr.c | 2 +- board/freescale/ls1028a/ls1028a.c | 2 +- board/freescale/ls1043aqds/ls1043aqds.c | 4 +- board/freescale/ls1046afrwy/ls1046afrwy.c | 2 +- board/freescale/ls1046aqds/ls1046aqds.c | 2 +- board/freescale/ls1088a/eth_ls1088aqds.c | 16 +-- board/freescale/ls1088a/ls1088a.c | 60 ++++++------ board/freescale/ls2080aqds/eth.c | 14 +-- board/freescale/ls2080aqds/ls2080aqds.c | 4 +- board/freescale/ls2080ardb/ls2080ardb.c | 2 +- board/freescale/lx2160a/lx2160a.c | 2 +- board/freescale/p1010rdb/p1010rdb.c | 8 +- board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 2 +- board/freescale/t102xrdb/t102xrdb.c | 2 +- board/freescale/t208xqds/t208xqds.c | 2 +- board/friendlyarm/nanopi2/onewire.c | 6 +- board/keymile/common/ivm.c | 2 +- board/samsung/common/misc.c | 2 +- board/samsung/trats/trats.c | 10 +- board/samsung/trats2/trats2.c | 10 +- board/sunxi/board.c | 2 +- board/ti/am335x/board.c | 8 +- board/ti/am335x/mux.c | 2 +- board/ti/am43xx/board.c | 12 +-- board/ti/common/board_detect.c | 4 +- board/ti/ks2_evm/board_k2g.c | 2 +- board/wandboard/wandboard.c | 4 +- cmd/eeprom.c | 6 +- cmd/i2c.c | 98 +++++++++---------- doc/driver-model/i2c-howto.rst | 2 +- drivers/ddr/fsl/main.c | 8 +- drivers/i2c/Kconfig | 21 ++++ drivers/i2c/Makefile | 4 +- drivers/i2c/davinci_i2c.c | 4 +- drivers/i2c/designware_i2c.c | 4 +- drivers/i2c/fsl_i2c.c | 6 +- drivers/i2c/ihs_i2c.c | 42 ++++---- drivers/i2c/lpc32xx_i2c.c | 4 +- drivers/i2c/mv_i2c.c | 2 +- drivers/i2c/mvtwsi.c | 16 +-- drivers/i2c/mxc_i2c.c | 4 +- drivers/i2c/omap24xx_i2c.c | 2 +- drivers/misc/Makefile | 2 +- drivers/power/palmas.c | 2 +- drivers/power/pmic/pmic_tps62362.c | 6 +- drivers/power/pmic/pmic_tps65217.c | 14 +-- drivers/power/pmic/pmic_tps65218.c | 4 +- drivers/power/pmic/pmic_tps65910.c | 6 +- drivers/power/twl4030.c | 2 +- drivers/power/twl6030.c | 2 +- drivers/tpm/tpm_atmel_twi.c | 6 +- drivers/usb/host/ohci-lpc32xx.c | 8 +- include/_exports.h | 2 +- include/config_fallbacks.h | 2 +- include/configs/MPC8548CDS.h | 2 +- include/configs/P1010RDB.h | 2 +- include/configs/P2041RDB.h | 2 +- include/configs/T102xRDB.h | 2 +- include/configs/T104xRDB.h | 4 +- include/configs/T208xQDS.h | 2 +- include/configs/T208xRDB.h | 2 +- include/configs/T4240RDB.h | 2 +- include/configs/am43xx_evm.h | 2 +- include/configs/corenet_ds.h | 2 +- include/configs/imx8mp_evk.h | 2 +- include/configs/ls1012a_common.h | 2 +- include/configs/ls1021aiot.h | 2 +- include/configs/ls1021aqds.h | 2 +- include/configs/ls1021atsn.h | 2 +- include/configs/ls1021atwr.h | 4 +- include/configs/ls1028a_common.h | 2 +- include/configs/ls1043a_common.h | 2 +- include/configs/ls1046a_common.h | 4 +- include/configs/ls1088a_common.h | 2 +- include/configs/ls1088aqds.h | 2 +- include/configs/ls2080a_common.h | 2 +- include/configs/ls2080aqds.h | 2 +- include/configs/ls2080ardb.h | 2 +- include/configs/p1_p2_rdb_pc.h | 2 +- include/configs/phycore_imx8mp.h | 2 +- include/configs/sunxi-common.h | 2 +- include/configs/ti_armv7_common.h | 2 +- include/exports.h | 2 +- include/i2c.h | 2 +- include/palmas.h | 2 +- include/twl4030.h | 2 +- include/twl6030.h | 2 +- 112 files changed, 340 insertions(+), 319 deletions(-) -- 2.25.1

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