February 2021 - U-Boot

[U-Boot] [PATCH] usb: Make USB_MUSB_PIO_ONLY conditional on USB_MUSB_{HOST, GADGET}
by Samuel Dionne-Riel 15 Nov '21

15 Nov '21

This ensures the USB_MUSB_PIO_ONLY config is set to an apppropriate default values from the changes enabling USB_MUSB_GADGET does. Namely, USB_MUSB_PIO_ONLY default to =y on USB_MUSB_SUNXI being y. Since USB_MUSB_SUNXI is behind the conditional, the option does not exist when using make ..._defconfig, thus the default of USB_MUSB_PIO_ONLY is kept "# ... is not set". This, _is_ counter-intuitively a set value, meaning that the default will not be applied once USB_MUSB_SUNXI is set to y by toggling USB_MUSB_GADGET via menuconfig. Signed-off-by: Samuel Dionne-Riel <samuel(a)dionne-riel.com> --- Some additional context about the bug. Using `make ..._defconfig` for a sunxi board, then using `make menuconfig` to change the option `CONFIG_USB_MUSB_GADGET=y` causes builds to fail. When the same option is set to `=y` via the defconfig file, the option work. Follows the failure: ``` CC drivers/usb/musb-new/musb_gadget.o drivers/usb/musb-new/musb_gadget.c: In function 'map_dma_buffer': drivers/usb/musb-new/musb_gadget.c:103:26: warning: implicit declaration of function 'dma_map_single'; did you mean 'malloc_simple'? [-Wimplicit-function-declaration] request->request.dma = dma_map_single( ^~~~~~~~~~~~~~ malloc_simple drivers/usb/musb-new/musb_gadget.c:108:8: error: 'DMA_TO_DEVICE' undeclared (first use in this function); did you mean 'USB_DT_DEVICE'? ? DMA_TO_DEVICE ^~~~~~~~~~~~~ USB_DT_DEVICE drivers/usb/musb-new/musb_gadget.c:108:8: note: each undeclared identifier is reported only once for each function it appears in drivers/usb/musb-new/musb_gadget.c:109:8: error: 'DMA_FROM_DEVICE' undeclared (first use in this function); did you mean 'U_BOOT_DEVICE'? : DMA_FROM_DEVICE); ^~~~~~~~~~~~~~~ U_BOOT_DEVICE drivers/usb/musb-new/musb_gadget.c:112:3: warning: implicit declaration of function 'dma_sync_single_for_device' [-Wimplicit-function-declaration] dma_sync_single_for_device(musb->controller, ^~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/usb/musb-new/musb_gadget.c: In function 'unmap_dma_buffer': drivers/usb/musb-new/musb_gadget.c:135:3: warning: implicit declaration of function 'dma_unmap_single' [-Wimplicit-function-declaration] dma_unmap_single(musb->controller, ^~~~~~~~~~~~~~~~ drivers/usb/musb-new/musb_gadget.c:139:7: error: 'DMA_TO_DEVICE' undeclared (first use in this function); did you mean 'USB_DT_DEVICE'? ? DMA_TO_DEVICE ^~~~~~~~~~~~~ USB_DT_DEVICE drivers/usb/musb-new/musb_gadget.c:140:7: error: 'DMA_FROM_DEVICE' undeclared (first use in this function); did you mean 'U_BOOT_DEVICE'? : DMA_FROM_DEVICE); ^~~~~~~~~~~~~~~ U_BOOT_DEVICE drivers/usb/musb-new/musb_gadget.c:143:3: warning: implicit declaration of function 'dma_sync_single_for_cpu' [-Wimplicit-function-declaration] dma_sync_single_for_cpu(musb->controller, ^~~~~~~~~~~~~~~~~~~~~~~ make[1]: *** [scripts/Makefile.build:279: drivers/usb/musb-new/musb_gadget.o] Error 1 ``` By diffing the resulting configuration, Othe main difference found is `CONFIG_USB_MUSB_PIO_ONLY` is not set when failing, and set to `=y` when working. This was verified to be the missing option. As far as I understand it in Kconfig, "is not set" basically marks the option as using a negative "unset" value, and does not mean that it will use the default value. This difference in meaning makes it so that when toggling the option with `make menuconfig`, the option has already been set to "is not set", and it does not change to its default value. The actual bug may be that there is a regression and the code should work when this value is unset, in this case I do not know how to provide the proper fix. This fix corrects the issue by gating the option behind `if USB_MUSB_HOST || USB_MUSB_GADGET`. To me, it looks like this was the intention, in the initial patch, but might have been overlooked. I assume so since the option was defined after the `if`, rather than before, like the other options not gated behind the option. drivers/usb/musb-new/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/usb/musb-new/Kconfig b/drivers/usb/musb-new/Kconfig index 79ad14ef66..95499f1b17 100644 --- a/drivers/usb/musb-new/Kconfig +++ b/drivers/usb/musb-new/Kconfig @@ -72,11 +72,11 @@ config USB_MUSB_DISABLE_BULK_COMBINE_SPLIT support it yet. Select this option to disable the feature until the driver adds the support. -endif - config USB_MUSB_PIO_ONLY bool "Disable DMA (always use PIO)" default y if USB_MUSB_AM35X || USB_MUSB_PIC32 || USB_MUSB_OMAP2PLUS || USB_MUSB_DSPS || USB_MUSB_SUNXI help All data is copied between memory and FIFO by the CPU. DMA controllers are ignored. + +endif -- 2.23.0

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[PATCH 1/1] video: fix positioning in TrueType console
by Heinrich Schuchardt 28 Oct '21

28 Oct '21

With the patch accurate positioning is possible for mono-typed fonts: Fix the return value of console_truetype_putc_xy(). The current position is passed as parameter x. Some part of x represents a fractional pixel. The return value represents how much the character position must be advanced. This should only comprise the width of the current character and not the preexisting fractional pixel position. Characters are not square. As all characters of a mono-type font we can take the width of any character. 'W' as one of the widest ANSI characters provides also a good value for variable width fonts. The character width must be a float. Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- drivers/video/console_truetype.c | 27 ++++++++++++++++++++------- include/video_console.h | 2 +- 2 files changed, 21 insertions(+), 8 deletions(-) diff --git a/drivers/video/console_truetype.c b/drivers/video/console_truetype.c index 318a060926..56939af849 100644 --- a/drivers/video/console_truetype.c +++ b/drivers/video/console_truetype.c @@ -211,7 +211,7 @@ static int console_truetype_putc_xy(struct udevice *dev, uint x, uint y, int width_frac, linenum; struct pos_info *pos; u8 *bits, *data; - int advance; + int advance, kern_adv; void *start, *line, *sync_start, *sync_end; int row, ret; int bg_r, bg_g, bg_b; @@ -226,8 +226,11 @@ static int console_truetype_putc_xy(struct udevice *dev, uint x, uint y, * this character */ xpos = frac(VID_TO_PIXEL((double)x)); if (vc_priv->last_ch) { - xpos += priv->scale * stbtt_GetCodepointKernAdvance(font, - vc_priv->last_ch, ch); + kern_adv = stbtt_GetCodepointKernAdvance(font, vc_priv->last_ch, + ch); + xpos += priv->scale * kern_adv; + } else { + kern_adv = 0; } /* @@ -238,8 +241,8 @@ static int console_truetype_putc_xy(struct udevice *dev, uint x, uint y, */ x_shift = xpos - (double)tt_floor(xpos); xpos += advance * priv->scale; - width_frac = (int)VID_TO_POS(xpos); - if (x + width_frac >= vc_priv->xsize_frac) + width_frac = VID_TO_POS(priv->scale * (kern_adv + advance)); + if (x + (int)VID_TO_POS(xpos) >= vc_priv->xsize_frac) return -EAGAIN; /* Write the current cursor position into history */ @@ -591,20 +594,21 @@ static int console_truetype_probe(struct udevice *dev) struct udevice *vid_dev = dev->parent; struct video_priv *vid_priv = dev_get_uclass_priv(vid_dev); stbtt_fontinfo *font = &priv->font; - int ascent; + int advance, ascent, lsb; debug("%s: start\n", __func__); + if (vid_priv->font_size) priv->font_size = vid_priv->font_size; else priv->font_size = CONFIG_CONSOLE_TRUETYPE_SIZE; + priv->font_data = console_truetype_find_font(); if (!priv->font_data) { debug("%s: Could not find any fonts\n", __func__); return -EBFONT; } - vc_priv->x_charsize = priv->font_size; vc_priv->y_charsize = priv->font_size; vc_priv->xstart_frac = VID_TO_POS(2); vc_priv->cols = vid_priv->xsize / priv->font_size; @@ -618,6 +622,15 @@ static int console_truetype_probe(struct udevice *dev) /* Pre-calculate some things we will need regularly */ priv->scale = stbtt_ScaleForPixelHeight(font, priv->font_size); + + /* Assuming that 'W' is the widest character */ + stbtt_GetCodepointHMetrics(font, 'W', &advance, &lsb); + advance += stbtt_GetCodepointKernAdvance(font, 'W', 'W'); + vc_priv->cols = + (int)VID_TO_POS(vid_priv->xsize - 2) / + (int)VID_TO_POS(advance * priv->scale); + vc_priv->x_charsize = advance * priv->scale; + stbtt_GetFontVMetrics(font, &ascent, 0, 0); priv->baseline = (int)(ascent * priv->scale); debug("%s: ready\n", __func__); diff --git a/include/video_console.h b/include/video_console.h index 8747299d61..cf306e5ca2 100644 --- a/include/video_console.h +++ b/include/video_console.h @@ -68,7 +68,7 @@ struct vidconsole_priv { int ycur; int rows; int cols; - int x_charsize; + double x_charsize; int y_charsize; int tab_width_frac; int xsize_frac; -- 2.30.1

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[PATCH v3 0/2] Use RNG to get random behaviour
by matthias.bgg＠kernel.org 22 Oct '21

22 Oct '21

From: Matthias Brugger <mbrugger(a)suse.com> For now bootp and uuid code use a weak seed for generating random data. U-Boot as support for RNG devices now, so we should change to code to use them if they are present. This will help mitigate issues like seen in CVE-2019-11690. Changes in v3: - use IS_ENABLED instead of #if - use 4 byte for entropy - use IS_ENABLED instead of #if Changes in v2: - fix dm_rng_read() parameters - add missing include - fix dm_rng_read() parameters - add missing include file Matthias Brugger (2): lib: uuid: use RNG device if present net: Use NDRNG device in srand_mac() lib/uuid.c | 21 ++++++++++++++++++--- net/net_rand.h | 19 ++++++++++++++++++- 2 files changed, 36 insertions(+), 4 deletions(-) -- 2.29.2

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[PATCH v2 0/6] dwc3-generic: Add Layerscape support
by Ran Wang 03 Oct '21

03 Oct '21

Hello, The purpose of this patch set is to switch from driver xhci-fsl to dwc3-generic for DWC3 IP on Layerscape platforms. Whith this change, now user can enable USB device mode by merely updating property 'dr_mode' accordingly. I also port some DWC3's errata workaorunds from driver xhci-fsl (by referring to Linux kernel mainline version implemenattion). Besides that, I fixed a PHY init problem which observed on Lyerscape platforms (such as LS1088ardb). Regards, Ran Change in v2: - Remove [2/7] usb: dwc3: add disable receiver detection in P3 quirk, because I found it causes Linux kenrel fail to detect USB device, need further check. Ran Wang (6): usb: dwc3: Add frame length adjustment quirk usb: dwc3: Enable undefined length INCR burst type usb: dwc3-generic: fix dwc3_setup_phy() return -ENOTSUPP causing init failure usb: dwc3-generic: Add support for the layerscape configs: ls1088a: add usb mass storage (device mode) support arm: dts: ls1088a: change dwc3 compatible to match dwc3-generic driver arch/arm/dts/fsl-ls1088a.dtsi | 38 ++++++--- configs/ls1088aqds_defconfig | 5 ++ configs/ls1088aqds_qspi_defconfig | 5 ++ configs/ls1088aqds_sdcard_ifc_defconfig | 5 ++ configs/ls1088aqds_sdcard_qspi_defconfig | 5 ++ configs/ls1088aqds_tfa_defconfig | 5 ++ configs/ls1088ardb_qspi_defconfig | 5 ++ configs/ls1088ardb_sdcard_qspi_defconfig | 5 ++ configs/ls1088ardb_tfa_defconfig | 5 ++ drivers/usb/dwc3/core.c | 130 +++++++++++++++++++++++++++++++ drivers/usb/dwc3/core.h | 20 +++++ drivers/usb/dwc3/dwc3-generic.c | 3 +- 12 files changed, 220 insertions(+), 11 deletions(-) -- 2.7.4

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Bug: qemu_arm64: Cannot access the second flash bank
by Robin Randhawa 13 Sep '21

13 Sep '21

Hi folks. [CC'ing some hopefully relevant folks]. As of: commit 0ba41ce1b7816c229cc19e0621148b98f990cb68 libfdt: return correct value if #size-cells property is not present .. accesses to the second flash bank on the qemu_arm64 virtual board appear broken. To demonstrate, consider that the physical memory map for the 2 flash banks is: Bank 1: 0x0000_0000 - 0x03FC_0000 Bank 2: 0x0400_0000 - 0x7FC0_0000 Now, consider the abbreviated output of the flinfo command pre and post the above commit: Pre: === => flinfo Bank # 1: CFI conformant flash (32 x 16) Size: 64 MB in 256 Sectors Intel Extended command set, Manufacturer ID: 0x89, Device ID: 0x0018 Erase timeout: 16384 ms, write timeout: 3 ms Buffer write timeout: 3 ms, buffer size: 2048 bytes Sector Start Addresses: 00000000 RO 00040000 RO 00080000 RO 000C0000 00100000 00140000 00180000 001C0000 00200000 00240000 . . 03E80000 03EC0000 03F00000 03F40000 03F80000 03FC0000 Bank # 2: CFI conformant flash (32 x 16) Size: 64 MB in 256 Sectors Intel Extended command set, Manufacturer ID: 0x89, Device ID: 0x0018 Erase timeout: 16384 ms, write timeout: 3 ms Buffer write timeout: 3 ms, buffer size: 2048 bytes Sector Start Addresses: 04000000 RO 04040000 04080000 040C0000 04100000 04140000 04180000 041C0000 04200000 04240000 . . 07E80000 07EC0000 07F00000 07F40000 07F80000 07FC0000 Post: ==== => flinfo Bank # 1: CFI conformant flash (32 x 16) Size: 64 MB in 256 Sectors Intel Extended command set, Manufacturer ID: 0x89, Device ID: 0x0018 Erase timeout: 16384 ms, write timeout: 3 ms Buffer write timeout: 3 ms, buffer size: 2048 bytes Sector Start Addresses: 00000000 RO 00040000 RO 00080000 RO 000C0000 00100000 00140000 00180000 001C0000 00200000 00240000 . . 03E80000 03EC0000 03F00000 03F40000 03F80000 03FC0000 Bank # 2: CFI conformant flash (32 x 16) Size: 64 MB in 256 Sectors Intel Extended command set, Manufacturer ID: 0x89, Device ID: 0x0018 Erase timeout: 16384 ms, write timeout: 3 ms Buffer write timeout: 3 ms, buffer size: 2048 bytes Sector Start Addresses: 400000000000000 400000000040000 400000000080000 4000000000C0000 400000000100000 400000000140000 400000000180000 4000000001C0000 400000000200000 400000000240000 . . 400000003E80000 400000003EC0000 400000003F00000 40 0000003F40000 400000003F80000 400000003FC0000 As a result, the second bank is unusable for environment stores (CONFIG_ENV_ADDR is 0x4000000): => saveenv Saving Environment to Flash... Error: start and/or end address not on sector boundary Error: start and/or end address not on sector boundary Failed (1) Rewinding the u-boot repo to before this commit fixes the problem. Manually (uncleanly) reverting the commit and it's dependent commits fixes the problem. Here are the HEAD commits from the relevant repos that I used for the data above: qemu: commit dd5b0f95490883cd8bc7d070db8de70d5c979cbc u-boot: commit 6cb87cbb1475f668689f95911d1521ee6ba7f55c Here is the qemu invocation I used: $ dd if=/dev/zero of=./flash0-with-uboot.img bs=1M count=64 && dd if=/path/to/u-boot.bin of=./flash0-with-uboot.img conv=notrunc $ qemu-system-aarch64 -M virt -cpu cortex-a53 -m 1024M -nographic -drive if=pflash,format=raw,index=0,file=flash0-with-uboot.img -drive if=pflash,format=raw,index=1,file=flash1.img I'm happy to help test any fixes if and as needed. Cheers, Robin

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[u-boot PATCH] arm: mach-k3: am6_init: Prioritize MSMC traffic over DDR in NAVSS Northbridge
by Roger Quadros 08 Sep '21

08 Sep '21

NB0 is bridge to SRAM and NB1 is bridge to DDR. To ensure that SRAM transfers are not stalled due to delays during DDR refreshes, SRAM traffic should be higher priority (threadmap=2) than DDR traffic (threadmap=0). This patch does just that. This is required to fix ICSSG TX lock-ups due to delays in MSMC transfers due to incorrect Northbridge configuration. Signed-off-by: Roger Quadros <rogerq(a)ti.com> Acked-by: Andrew F. Davis <afd(a)ti.com> Acked-by: Tomi Valkeinen <tomi.valkeinen(a)ti.com> Acked-by: Benoit Parrot <bparrot(a)ti.com> --- arch/arm/mach-k3/am6_init.c | 14 ++++++++++++++ arch/arm/mach-k3/include/mach/am6_hardware.h | 7 +++++++ 2 files changed, 21 insertions(+) diff --git a/arch/arm/mach-k3/am6_init.c b/arch/arm/mach-k3/am6_init.c index 8d107b870b..9379b95bdb 100644 --- a/arch/arm/mach-k3/am6_init.c +++ b/arch/arm/mach-k3/am6_init.c @@ -86,6 +86,18 @@ static void store_boot_index_from_rom(void) bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX); } +static void setup_am654_navss_northbridge(void) +{ + /* + * NB0 is bridge to SRAM and NB1 is bridge to DDR. + * To ensure that SRAM transfers are not stalled due to + * delays during DDR refreshes, SRAM traffic should be higher + * priority (threadmap=2) than DDR traffic (threadmap=0). + */ + writel(0x2, NAVSS0_NBSS_NB0_CFG_BASE + NAVSS_NBSS_THREADMAP); + writel(0x0, NAVSS0_NBSS_NB1_CFG_BASE + NAVSS_NBSS_THREADMAP); +} + void board_init_f(ulong dummy) { #if defined(CONFIG_K3_LOAD_SYSFW) || defined(CONFIG_K3_AM654_DDRSS) @@ -101,6 +113,8 @@ void board_init_f(ulong dummy) /* Make all control module registers accessible */ ctrl_mmr_unlock(); + setup_am654_navss_northbridge(); + #ifdef CONFIG_CPU_V7R disable_linefill_optimization(); setup_k3_mpu_regions(); diff --git a/arch/arm/mach-k3/include/mach/am6_hardware.h b/arch/arm/mach-k3/include/mach/am6_hardware.h index 6df7631545..45a5b31c52 100644 --- a/arch/arm/mach-k3/include/mach/am6_hardware.h +++ b/arch/arm/mach-k3/include/mach/am6_hardware.h @@ -47,4 +47,11 @@ /* MCU SCRATCHPAD usage */ #define TI_SRAM_SCRATCH_BOARD_EEPROM_START CONFIG_SYS_K3_MCU_SCRATCHPAD_BASE +/* NAVSS Northbridge config */ +#define NAVSS0_NBSS_NB0_CFG_BASE 0x03802000 +#define NAVSS0_NBSS_NB1_CFG_BASE 0x03803000 + +#define NAVSS_NBSS_PID 0x0 +#define NAVSS_NBSS_THREADMAP 0x10 + #endif /* __ASM_ARCH_AM6_HARDWARE_H */ -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki

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[PATCH] doc: Add basic information about running CI tests
by Tom Rini 05 Aug '21

05 Aug '21

Start out by documenting general expectations on when CI is run, how anyone can run Azure pipelines, and how GitLab CI pipelines can be run. Signed-off-by: Tom Rini <trini(a)konsulko.com> --- doc/develop/ci_testing.rst | 45 ++++++++++++++++++++++++++++++++++++++ doc/develop/index.rst | 1 + 2 files changed, 46 insertions(+) create mode 100644 doc/develop/ci_testing.rst diff --git a/doc/develop/ci_testing.rst b/doc/develop/ci_testing.rst new file mode 100644 index 000000000000..48dbec4a4452 --- /dev/null +++ b/doc/develop/ci_testing.rst @@ -0,0 +1,45 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Continuous Integration testing +============================== + +All changes require passing our continuous integration tests prior to being +merged in to mainline. To help facilitate merges being accepted quickly, +custodians are encouraged but not required to run a pipeline prior to sending a +pull request. Individual developers submitting significant or widespread +changes are encouraged to run a pipeline themselves prior to posting. + +In order to make this process as easy as possible, the ability to run a CI +pipeline is provided in both Azure and GitLab. Both of these pipelines perform +their Linux build jobs on the same Docker container image. + +Azure Pipelines +--------------- + +Currently there are two ways to run a Microsoft Azure Pipeline test for U-Boot. +The first way is to create an account with Microsoft at +https://azure.microsoft.com/en-us/services/devops/ and then use the +``.azure-pipelines.yml`` file in the U-Boot repository as the pipeline +description. The second way is to use GitHub and submit a pull request against +https://github.com/u-boot/u-boot as this will trigger an Azure pipeline run. +Clicking on your pull request on the list at +https://github.com/u-boot/u-boot/pulls and then the "Checks" tab will show the +results. + +GitLab CI Pipelines +------------------- + +Currently, we support running GitLab CI pipelines only for custodians, due to +the resources the project has available. For Custodians, it is a matter of +enabling the pipeline feature in your project repository following the standard +GitLab documentation. For non-custodians, the pipeline itself is part of the +tree and should be able to be used on any GitLab instance, with whatever +runners you are able to provide. + +Docker container +---------------- + +As previously states, both of the above pipelines build using the same Docker +container image. This is maintained in the repository at +https://gitlab.denx.de/u-boot/gitlab-ci-runner and new images are made as +needed to support new tests or features. diff --git a/doc/develop/index.rst b/doc/develop/index.rst index 0a7e204b3438..d5619e8fce86 100644 --- a/doc/develop/index.rst +++ b/doc/develop/index.rst @@ -7,6 +7,7 @@ Develop U-Boot .. toctree:: :maxdepth: 2 + ci_testing coccinelle commands crash_dumps -- 2.17.1

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[PATCH 1/9] net: eqos: Add PHY reset control for i.MX platform
by Ye Li 21 Jul '21

21 Jul '21

Parse the "phy-reset-gpios", "phy-reset-post-delay" and "phy-reset-duration" properties from eqos node to control the ethernet PHY reset at driver probe. Reset PHY once is enough that can reduce the time cost to get IP after the first time. Signed-off-by: Ye Li <ye.li(a)nxp.com> --- drivers/net/dwc_eth_qos.c | 55 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c index e8242ca..14aafc6 100644 --- a/drivers/net/dwc_eth_qos.c +++ b/drivers/net/dwc_eth_qos.c @@ -303,6 +303,8 @@ struct eqos_priv { struct eqos_tegra186_regs *tegra186_regs; struct reset_ctl reset_ctl; struct gpio_desc phy_reset_gpio; + uint32_t reset_delay; + uint32_t reset_post_delay; struct clk clk_master_bus; struct clk clk_rx; struct clk clk_ptp_ref; @@ -1880,6 +1882,7 @@ static int eqos_probe_resources_imx(struct udevice *dev) { struct eqos_priv *eqos = dev_get_priv(dev); phy_interface_t interface; + int ret = 0; debug("%s(dev=%p):\n", __func__, dev); @@ -1890,8 +1893,52 @@ static int eqos_probe_resources_imx(struct udevice *dev) return -EINVAL; } + ret = gpio_request_by_name(dev, "phy-reset-gpios", 0, + &eqos->phy_reset_gpio, + GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + if (ret) { + pr_debug("gpio_request_by_name(phy reset) failed: %d", ret); + } + + if (dm_gpio_is_valid(&eqos->phy_reset_gpio)) { + eqos->reset_delay = dev_read_u32_default(dev, "phy-reset-duration", 1); + if (eqos->reset_delay > 1000) { + pr_err("phy reset duration should be <= 1000ms\n"); + /* property value wrong, use default value */ + eqos->reset_delay = 1; + } + + mdelay(eqos->reset_delay); + + eqos->reset_post_delay = dev_read_u32_default(dev, + "phy-reset-post-delay", + 0); + if (eqos->reset_post_delay > 1000) { + pr_err("phy reset post delay should be <= 1000ms\n"); + /* property value wrong, use default value */ + eqos->reset_post_delay = 0; + } + + ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 0); + if (ret < 0) { + pr_err("dm_gpio_set_value(phy_reset, deassert) failed: %d", ret); + goto err_free_gpio_phy_reset; + } + + if (eqos->reset_post_delay) + mdelay(eqos->reset_post_delay); + } + debug("%s: OK\n", __func__); return 0; + +err_free_gpio_phy_reset: + if (dm_gpio_is_valid(&eqos->phy_reset_gpio)) { + dm_gpio_free(dev, &eqos->phy_reset_gpio); + } + + debug("%s: returns %d\n", __func__, ret); + return ret; } static phy_interface_t eqos_get_interface_imx(struct udevice *dev) @@ -1951,6 +1998,14 @@ static int eqos_remove_resources_stm32(struct udevice *dev) static int eqos_remove_resources_imx(struct udevice *dev) { + struct eqos_priv *eqos = dev_get_priv(dev); + + debug("%s(dev=%p):\n", __func__, dev); + if (dm_gpio_is_valid(&eqos->phy_reset_gpio)) { + dm_gpio_free(dev, &eqos->phy_reset_gpio); + } + + debug("%s: OK\n", __func__); return 0; } -- 2.7.4

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[PATCH] arm64: Update memcpy_{from, to}io() helpers
by Patrice Chotard 19 Jul '21

19 Jul '21

At early U-Boot stage, before relocation, MMU is not yet configured and disabled. DDR may not be configured with the correct memory attributes (can be configured in MT_DEVICE instead of MT_MEMORY). In this case, usage of memcpy_{from, to}io() may leads to synchronous abort in AARCH64 in case the normal memory address is not 64Bits aligned. To avoid such situation, forbid usage of normal memory cast to (u64 *) in case MMU is not enabled. Signed-off-by: Patrice Chotard <patrice.chotard(a)foss.st.com> Cc: mark.kettenis(a)xs4all.nl --- arch/arm/cpu/armv8/cache_v8.c | 10 ++++++++++ arch/arm/include/asm/io.h | 25 +++++++++++++++---------- include/cpu_func.h | 1 + 3 files changed, 26 insertions(+), 10 deletions(-) diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index 15cecb5e0b..3de18c7675 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -719,6 +719,11 @@ int icache_status(void) return (get_sctlr() & CR_I) != 0; } +int mmu_status(void) +{ + return (get_sctlr() & CR_M) != 0; +} + void invalidate_icache_all(void) { __asm_invalidate_icache_all(); @@ -740,6 +745,11 @@ int icache_status(void) return 0; } +int mmu_status(void) +{ + return 0; +} + void invalidate_icache_all(void) { } diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h index df264a170b..36b840378a 100644 --- a/arch/arm/include/asm/io.h +++ b/arch/arm/include/asm/io.h @@ -338,6 +338,7 @@ extern void __readwrite_bug(const char *fn); /* Optimized copy functions to read from/write to IO sapce */ #ifdef CONFIG_ARM64 +#include <cpu_func.h> /* * Copy data from IO memory space to "real" memory space. */ @@ -351,11 +352,13 @@ void __memcpy_fromio(void *to, const volatile void __iomem *from, size_t count) count--; } - while (count >= 8) { - *(u64 *)to = __raw_readq(from); - from += 8; - to += 8; - count -= 8; + if (mmu_status()) { + while (count >= 8) { + *(u64 *)to = __raw_readq(from); + from += 8; + to += 8; + count -= 8; + } } while (count) { @@ -379,11 +382,13 @@ void __memcpy_toio(volatile void __iomem *to, const void *from, size_t count) count--; } - while (count >= 8) { - __raw_writeq(*(u64 *)from, to); - from += 8; - to += 8; - count -= 8; + if (mmu_status()) { + while (count >= 8) { + __raw_writeq(*(u64 *)from, to); + from += 8; + to += 8; + count -= 8; + } } while (count) { diff --git a/include/cpu_func.h b/include/cpu_func.h index 8aa825daa4..a8806dd295 100644 --- a/include/cpu_func.h +++ b/include/cpu_func.h @@ -59,6 +59,7 @@ int dcache_status(void); void dcache_enable(void); void dcache_disable(void); void mmu_disable(void); +int mmu_status(void); /* arch/$(ARCH)/lib/cache.c */ void enable_caches(void); -- 2.17.1

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[PATCH 1/4] phy: phy-imx8mq-usb: Add USB PHY driver for i.MX8MQ
by Ye Li 13 Jul '21

13 Jul '21

Add the USB PHY driver for i.MX8MQ to work with DWC3 USB controller. Signed-off-by: Ye Li <ye.li(a)nxp.com> --- drivers/phy/Kconfig | 7 ++ drivers/phy/Makefile | 1 + drivers/phy/phy-imx8mq-usb.c | 197 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 205 insertions(+) create mode 100644 drivers/phy/phy-imx8mq-usb.c diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 008186a..09cb744 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -268,5 +268,12 @@ config PHY_MTK_TPHY multi-ports is first version, otherwise is second veriosn, so you can easily distinguish them by banks layout. +config PHY_IMX8MQ_USB + bool "NXP i.MX8MQ USB PHY Driver" + depends on PHY + depends on IMX8MQ + help + Support the USB3.0 PHY in NXP i.MX8MQ SoC + source "drivers/phy/rockchip/Kconfig" endmenu diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index 3c4a673..c6ad3b1 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -31,3 +31,4 @@ obj-$(CONFIG_MT7620_USB_PHY) += mt7620-usb-phy.o obj-$(CONFIG_MT76X8_USB_PHY) += mt76x8-usb-phy.o obj-$(CONFIG_PHY_DA8XX_USB) += phy-da8xx-usb.o obj-$(CONFIG_PHY_MTK_TPHY) += phy-mtk-tphy.o +obj-$(CONFIG_PHY_IMX8MQ_USB) += phy-imx8mq-usb.o diff --git a/drivers/phy/phy-imx8mq-usb.c b/drivers/phy/phy-imx8mq-usb.c new file mode 100644 index 0000000..afbc7ad --- /dev/null +++ b/drivers/phy/phy-imx8mq-usb.c @@ -0,0 +1,197 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2021 NXP + * + */ + +#include <common.h> +#include <asm/io.h> +#include <dm.h> +#include <errno.h> +#include <generic-phy.h> +#include <linux/bitops.h> +#include <linux/err.h> +#include <clk.h> + +#define PHY_CTRL0 0x0 +#define PHY_CTRL0_REF_SSP_EN BIT(2) +#define PHY_CTRL0_FSEL_MASK GENMASK(10, 5) +#define PHY_CTRL0_FSEL_24M 0x2a +#define PHY_CTRL0_FSEL_100M 0x27 +#define PHY_CTRL0_SSC_RANGE_MASK GENMASK(23, 21) +#define PHY_CTRL0_SSC_RANGE_4003PPM (0x2 << 21) + +#define PHY_CTRL1 0x4 +#define PHY_CTRL1_RESET BIT(0) +#define PHY_CTRL1_COMMONONN BIT(1) +#define PHY_CTRL1_ATERESET BIT(3) +#define PHY_CTRL1_DCDENB BIT(17) +#define PHY_CTRL1_CHRGSEL BIT(18) +#define PHY_CTRL1_VDATSRCENB0 BIT(19) +#define PHY_CTRL1_VDATDETENB0 BIT(20) + +#define PHY_CTRL2 0x8 +#define PHY_CTRL2_TXENABLEN0 BIT(8) +#define PHY_CTRL2_OTG_DISABLE BIT(9) + +#define PHY_CTRL3 0xc +#define PHY_CTRL3_COMPDISTUNE_MASK GENMASK(2, 0) +#define PHY_CTRL3_TXPREEMP_TUNE_MASK GENMASK(16, 15) +#define PHY_CTRL3_TXPREEMP_TUNE_SHIFT 15 +#define PHY_CTRL3_TXRISE_TUNE_MASK GENMASK(21, 20) +#define PHY_CTRL3_TXRISE_TUNE_SHIFT 20 +/* 1111: +24% ... 0000: -6% step: 2% */ +#define PHY_CTRL3_TXVREF_TUNE_MASK GENMASK(25, 22) +#define PHY_CTRL3_TXVREF_TUNE_SHIFT 22 +#define PHY_CTRL3_TX_VBOOST_LEVEL_MASK GENMASK(31, 29) +#define PHY_CTRL3_TX_VBOOST_LEVEL_SHIFT 29 + +#define PHY_CTRL4 0x10 +#define PHY_CTRL4_PCS_TX_DEEMPH_3P5DB_MASK GENMASK(20, 15) +#define PHY_CTRL4_PCS_TX_DEEMPH_3P5DB_SHIFT 15 + +#define PHY_CTRL5 0x14 +#define PHY_CTRL5_DMPWD_OVERRIDE_SEL BIT(23) +#define PHY_CTRL5_DMPWD_OVERRIDE BIT(22) +#define PHY_CTRL5_DPPWD_OVERRIDE_SEL BIT(21) +#define PHY_CTRL5_DPPWD_OVERRIDE BIT(20) +#define PHY_CTRL5_PCS_TX_SWING_FULL_MASK GENMASK(6, 0) + +#define PHY_CTRL6 0x18 +#define PHY_CTRL6_RXTERM_OVERRIDE_SEL BIT(29) +#define PHY_CTRL6_ALT_CLK_EN BIT(1) +#define PHY_CTRL6_ALT_CLK_SEL BIT(0) + +#define PHY_STS0 0x40 +#define PHY_STS0_OTGSESSVLD BIT(7) +#define PHY_STS0_CHGDET BIT(4) +#define PHY_STS0_FSVPLUS BIT(3) +#define PHY_STS0_FSVMINUS BIT(2) + +struct imx8mq_usb_phy { +#if CONFIG_IS_ENABLED(CLK) + struct clk phy_clk; +#endif + void __iomem *base; +}; + +static const struct udevice_id imx8mq_usb_phy_of_match[] = { + { + .compatible = "fsl,imx8mq-usb-phy", + }, + {}, +}; + +static int imx8mq_usb_phy_init(struct phy *usb_phy) +{ + struct udevice *dev = usb_phy->dev; + struct imx8mq_usb_phy *imx_phy = dev_get_priv(dev); + u32 value; + + value = readl(imx_phy->base + PHY_CTRL1); + value &= ~(PHY_CTRL1_VDATSRCENB0 | PHY_CTRL1_VDATDETENB0 | + PHY_CTRL1_COMMONONN); + value |= PHY_CTRL1_RESET | PHY_CTRL1_ATERESET; + writel(value, imx_phy->base + PHY_CTRL1); + + value = readl(imx_phy->base + PHY_CTRL0); + value |= PHY_CTRL0_REF_SSP_EN; + value &= ~PHY_CTRL0_SSC_RANGE_MASK; + value |= PHY_CTRL0_SSC_RANGE_4003PPM; + writel(value, imx_phy->base + PHY_CTRL0); + + value = readl(imx_phy->base + PHY_CTRL2); + value |= PHY_CTRL2_TXENABLEN0; + writel(value, imx_phy->base + PHY_CTRL2); + + value = readl(imx_phy->base + PHY_CTRL1); + value &= ~(PHY_CTRL1_RESET | PHY_CTRL1_ATERESET); + writel(value, imx_phy->base + PHY_CTRL1); + + return 0; +} + +static int imx8mq_usb_phy_power_on(struct phy *usb_phy) +{ + struct udevice *dev = usb_phy->dev; + struct imx8mq_usb_phy *imx_phy = dev_get_priv(dev); + u32 value; + +#if CONFIG_IS_ENABLED(CLK) + int ret; + ret = clk_enable(&imx_phy->phy_clk); + if (ret) { + printf("Failed to enable usb phy clock\n"); + return ret; + } +#endif + + /* Disable rx term override */ + value = readl(imx_phy->base + PHY_CTRL6); + value &= ~PHY_CTRL6_RXTERM_OVERRIDE_SEL; + writel(value, imx_phy->base + PHY_CTRL6); + + return 0; +} + +static int imx8mq_usb_phy_power_off(struct phy *usb_phy) +{ + struct udevice *dev = usb_phy->dev; + struct imx8mq_usb_phy *imx_phy = dev_get_priv(dev); + u32 value; + + /* Override rx term to be 0 */ + value = readl(imx_phy->base + PHY_CTRL6); + value |= PHY_CTRL6_RXTERM_OVERRIDE_SEL; + writel(value, imx_phy->base + PHY_CTRL6); + +#if CONFIG_IS_ENABLED(CLK) + clk_disable(&imx_phy->phy_clk); +#endif + + return 0; +} + +static int imx8mq_usb_phy_exit(struct phy *usb_phy) +{ + return imx8mq_usb_phy_power_off(usb_phy); +} + +struct phy_ops imx8mq_usb_phy_ops = { + .init = imx8mq_usb_phy_init, + .power_on = imx8mq_usb_phy_power_on, + .power_off = imx8mq_usb_phy_power_off, + .exit = imx8mq_usb_phy_exit, +}; + +int imx8mq_usb_phy_probe(struct udevice *dev) +{ + struct imx8mq_usb_phy *priv = dev_get_priv(dev); + + priv->base = dev_read_addr_ptr(dev); + + if (!priv->base) + return -EINVAL; + +#if CONFIG_IS_ENABLED(CLK) + int ret; + + /* Assigned clock already set clock */ + ret = clk_get_by_name(dev, "phy", &priv->phy_clk); + if (ret) { + printf("Failed to get usb phy clock\n"); + return ret; + } +#endif + + return 0; +} + +U_BOOT_DRIVER(nxp_imx8mq_usb_phy) = { + .name = "nxp_imx8mq_usb_phy", + .id = UCLASS_PHY, + .of_match = imx8mq_usb_phy_of_match, + .probe = imx8mq_usb_phy_probe, + .ops = &imx8mq_usb_phy_ops, + .priv_auto = sizeof(struct imx8mq_usb_phy), +}; -- 2.7.4

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