December 2021 - U-Boot

[PATCH 0/3] clk: Some build infrastructure cleanups
by Sean Anderson 15 Jan '22

15 Jan '22

This makes some minor clean ups to the clock build infrastructure. Sean Anderson (3): clk: Alphabetize Makefile clk: Alphabetize Kconfig clk: Rename ICS8N3QV01 to CLK_ICS8N3QV01 configs/gazerbeam_defconfig | 2 +- drivers/clk/Kconfig | 182 ++++++++++++++++++------------------ drivers/clk/Makefile | 20 ++-- 3 files changed, 102 insertions(+), 102 deletions(-) -- 2.33.0

1 4

[PATCH 0/6] arm: sunxi: v3s: add ethernet support
by Andreas Rehn 15 Jan '22

15 Jan '22

This patchset enables ethernet on Allwinner V3/Sochip S3 SoCs. It is tested with an LicheePi Zero Dock board in combination with different switches and one direct link. Test scenario: Download mainline kernel and device-tree over tftp and start kernel with nfs rootfs. Without [PATCH 6/6], i wasn't able to get a stable connection on 100 Mb full duplex switches with autonegation enabled. Maybe the internal phy has a different behavior on softreset then others which results in a delayed established link. Andreas Rehn (6): dts: sunxi: add licheepi-zero-dock clk: sunxi: v3s: Implement EMAC clocks/resets clk: sunxi: v3s: fix tabs / spaces net: sun8i-emac: add v3s pinmux setting dts: sunxi: v3s: enable emac support net: sun8i-emac: v3s: fix soft reset timeout arch/arm/dts/Makefile | 3 ++- arch/arm/dts/sun8i-v3s-licheepi-zero-dock.dts | 11 +++++++++++ arch/arm/dts/sun8i-v3s.dtsi | 10 +++++++++- board/sunxi/MAINTAINERS | 5 +++++ configs/LicheePi_Zero_dock_defconfig | 7 +++++++ drivers/clk/sunxi/clk_v3s.c | 10 ++++++++-- drivers/net/sun8i_emac.c | 5 ++++- 7 files changed, 46 insertions(+), 5 deletions(-) create mode 100644 configs/LicheePi_Zero_dock_defconfig -- 2.25.1

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[PATCH] net: phy: add TI DP83869HM ethernet driver
by Christian Gmeiner 15 Jan '22

15 Jan '22

From: Dominic Rath <rath(a)ibv-augsburg.net> This driver is based on an older downstream TI kernel, with changes and cleanups to work with mainline device-tree bindings. Signed-off-by: Dominic Rath <rath(a)ibv-augsburg.net> Signed-off-by: Christian Gmeiner <christian.gmeiner(a)gmail.com> --- drivers/net/phy/Kconfig | 6 + drivers/net/phy/Makefile | 1 + drivers/net/phy/dp83869.c | 507 +++++++++++++++++++++++++++ drivers/net/phy/ti_phy_init.c | 4 + drivers/net/phy/ti_phy_init.h | 1 + include/dt-bindings/net/ti-dp83869.h | 60 ++++ 6 files changed, 579 insertions(+) create mode 100644 drivers/net/phy/dp83869.c create mode 100644 include/dt-bindings/net/ti-dp83869.h diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index 68ee7d7a2d..c6e58058d9 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -290,6 +290,12 @@ config PHY_TI_DP83867 ---help--- Adds support for the TI DP83867 1Gbit PHY. +config PHY_TI_DP83869 + select PHY_TI + bool "Texas Instruments Ethernet DP83869 PHY support" + ---help--- + Adds support for the TI DP83869 1Gbit PHY. + config PHY_TI_GENERIC select PHY_TI bool "Texas Instruments Generic Ethernet PHYs support" diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile index 218b8c7669..77f7f60621 100644 --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile @@ -29,6 +29,7 @@ obj-$(CONFIG_PHY_SMSC) += smsc.o obj-$(CONFIG_PHY_TERANETICS) += teranetics.o obj-$(CONFIG_PHY_TI) += ti_phy_init.o obj-$(CONFIG_PHY_TI_DP83867) += dp83867.o +obj-$(CONFIG_PHY_TI_DP83869) += dp83869.o obj-$(CONFIG_PHY_XILINX) += xilinx_phy.o obj-$(CONFIG_PHY_XILINX_GMII2RGMII) += xilinx_gmii2rgmii.o obj-$(CONFIG_PHY_VITESSE) += vitesse.o diff --git a/drivers/net/phy/dp83869.c b/drivers/net/phy/dp83869.c new file mode 100644 index 0000000000..c9461185cf --- /dev/null +++ b/drivers/net/phy/dp83869.c @@ -0,0 +1,507 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * TI PHY drivers + * + */ + +#include <common.h> +#include <phy.h> +#include <linux/compat.h> +#include <malloc.h> + +#include <dm.h> +#include <dt-bindings/net/ti-dp83869.h> + +/* TI DP83869 */ +#define DP83869_DEVADDR 0x1f + +#define MII_DP83869_PHYCTRL 0x10 +#define MII_DP83869_MICR 0x12 +#define MII_DP83869_CFG2 0x14 +#define MII_DP83869_BISCR 0x16 +#define DP83869_CTRL 0x1f +#define DP83869_CFG4 0x1e + +/* Extended Registers */ +#define DP83869_GEN_CFG3 0x0031 +#define DP83869_RGMIICTL 0x0032 +#define DP83869_STRAP_STS1 0x006E +#define DP83869_RGMIIDCTL 0x0086 +#define DP83869_IO_MUX_CFG 0x0170 +#define DP83869_OP_MODE 0x01df +#define DP83869_FX_CTRL 0x0c00 + +#define DP83869_SW_RESET BIT(15) +#define DP83869_SW_RESTART BIT(14) + +/* MICR Interrupt bits */ +#define MII_DP83869_MICR_AN_ERR_INT_EN BIT(15) +#define MII_DP83869_MICR_SPEED_CHNG_INT_EN BIT(14) +#define MII_DP83869_MICR_DUP_MODE_CHNG_INT_EN BIT(13) +#define MII_DP83869_MICR_PAGE_RXD_INT_EN BIT(12) +#define MII_DP83869_MICR_AUTONEG_COMP_INT_EN BIT(11) +#define MII_DP83869_MICR_LINK_STS_CHNG_INT_EN BIT(10) +#define MII_DP83869_MICR_FALSE_CARRIER_INT_EN BIT(8) +#define MII_DP83869_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4) +#define MII_DP83869_MICR_WOL_INT_EN BIT(3) +#define MII_DP83869_MICR_XGMII_ERR_INT_EN BIT(2) +#define MII_DP83869_MICR_POL_CHNG_INT_EN BIT(1) +#define MII_DP83869_MICR_JABBER_INT_EN BIT(0) + +#define MII_DP83869_BMCR_DEFAULT (BMCR_ANENABLE | \ + BMCR_FULLDPLX | \ + BMCR_SPEED1000) + +/* This is the same bit mask as the BMCR so re-use the BMCR default */ +#define DP83869_FX_CTRL_DEFAULT MII_DP83869_BMCR_DEFAULT + +/* CFG1 bits */ +#define DP83869_CFG1_DEFAULT (ADVERTISE_1000HALF | \ + ADVERTISE_1000FULL | \ + CTL1000_AS_MASTER) + +/* RGMIICTL bits */ +#define DP83869_RGMII_TX_CLK_DELAY_EN BIT(1) +#define DP83869_RGMII_RX_CLK_DELAY_EN BIT(0) + +/* STRAP_STS1 bits */ +#define DP83869_STRAP_OP_MODE_MASK GENMASK(2, 0) +#define DP83869_STRAP_STS1_RESERVED BIT(11) +#define DP83869_STRAP_MIRROR_ENABLED BIT(12) + +/* PHY CTRL bits */ +#define DP83869_PHYCR_RX_FIFO_DEPTH_SHIFT 12 +#define DP83869_PHYCR_RX_FIFO_DEPTH_MASK GENMASK(13, 12) +#define DP83869_PHYCR_TX_FIFO_DEPTH_SHIFT 14 +#define DP83869_PHYCR_TX_FIFO_DEPTH_MASK GENMASK(15, 14) +#define DP83869_PHYCR_RESERVED_MASK BIT(11) +#define DP83869_PHYCR_MDI_CROSSOVER_SHIFT 5 +#define DP83869_PHYCR_MDI_CROSSOVER_MDIX 2 +#define DP83869_PHY_CTRL_DEFAULT 0x48 + +/* RGMIIDCTL bits */ +#define DP83869_RGMII_TX_CLK_DELAY_SHIFT 4 +#define DP83869_CLK_DELAY_DEF 7 + +/* CFG2 bits */ +#define MII_DP83869_CFG2_SPEEDOPT_10EN 0x0040 +#define MII_DP83869_CFG2_SGMII_AUTONEGEN 0x0080 +#define MII_DP83869_CFG2_SPEEDOPT_ENH 0x0100 +#define MII_DP83869_CFG2_SPEEDOPT_CNT 0x0800 +#define MII_DP83869_CFG2_SPEEDOPT_INTLOW 0x2000 +#define MII_DP83869_CFG2_MASK 0x003F + +/* User setting - can be taken from DTS */ +#define DEFAULT_FIFO_DEPTH DP83869_PHYCR_FIFO_DEPTH_4_B_NIB + +/* IO_MUX_CFG bits */ +#define DP83869_IO_MUX_CFG_IO_IMPEDANCE_CTRL 0x1f + +#define DP83869_IO_MUX_CFG_IO_IMPEDANCE_MAX 0x0 +#define DP83869_IO_MUX_CFG_IO_IMPEDANCE_MIN 0x1f +#define DP83869_IO_MUX_CFG_CLK_O_DISABLE BIT(6) +#define DP83869_IO_MUX_CFG_CLK_O_SEL_SHIFT 8 +#define DP83869_IO_MUX_CFG_CLK_O_SEL_MASK \ + GENMASK(0x1f, DP83869_IO_MUX_CFG_CLK_O_SEL_SHIFT) + +/* CFG3 bits */ +#define DP83869_CFG3_PORT_MIRROR_EN BIT(0) + +/* OP MODE bits */ +#define DP83869_OP_MODE_MII BIT(5) +#define DP83869_SGMII_RGMII_BRIDGE BIT(6) + +enum { + DP83869_PORT_MIRRORING_KEEP, + DP83869_PORT_MIRRORING_EN, + DP83869_PORT_MIRRORING_DIS, +}; + +struct dp83869_private { + int tx_fifo_depth; + int rx_fifo_depth; + s32 rx_int_delay; + s32 tx_int_delay; + int io_impedance; + int port_mirroring; + bool set_clk_output; + int clk_output_sel; + int mode; +}; + +static int dp83869_readext(struct phy_device *phydev, int addr, int devad, int reg) +{ + return phy_read_mmd(phydev, devad, reg); +} + +static int dp83869_writeext(struct phy_device *phydev, int addr, int devad, int reg, u16 val) +{ + return phy_write_mmd(phydev, devad, reg, val); +} + +static int dp83869_config_port_mirroring(struct phy_device *phydev) +{ + struct dp83869_private *dp83869 = + (struct dp83869_private *)phydev->priv; + u16 val; + + val = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_CFG4); + + if (dp83869->port_mirroring == DP83869_PORT_MIRRORING_EN) + val |= DP83869_CFG3_PORT_MIRROR_EN; + else + val &= ~DP83869_CFG3_PORT_MIRROR_EN; + + phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_CFG4, val); + + return 0; +} + +#ifdef CONFIG_DM_ETH +static const int dp83869_internal_delay[] = {250, 500, 750, 1000, 1250, 1500, + 1750, 2000, 2250, 2500, 2750, 3000, + 3250, 3500, 3750, 4000}; + +static int dp83869_set_strapped_mode(struct phy_device *phydev) +{ + struct dp83869_private *dp83869 = phydev->priv; + int val; + + val = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_STRAP_STS1); + if (val < 0) + return val; + + dp83869->mode = val & DP83869_STRAP_OP_MODE_MASK; + + return 0; +} + +/** + * dp83869_data_init - Convenience function for setting PHY specific data + * + * @phydev: the phy_device struct + */ +static int dp83869_of_init(struct phy_device *phydev) +{ + struct dp83869_private * const dp83869 = phydev->priv; + const int delay_entries = ARRAY_SIZE(dp83869_internal_delay); + int ret; + ofnode node; + + node = phy_get_ofnode(phydev); + if (!ofnode_valid(node)) + return -EINVAL; + + dp83869->io_impedance = -EINVAL; + + /* Optional configuration, set to default if required */ + dp83869->clk_output_sel = ofnode_read_u32_default(node, "ti,clk-output-sel", + DP83869_CLK_O_SEL_CHN_A_RCLK); + + if (dp83869->clk_output_sel > DP83869_CLK_O_SEL_REF_CLK && + dp83869->clk_output_sel != DP83869_CLK_O_SEL_OFF) + dp83869->clk_output_sel = DP83869_CLK_O_SEL_REF_CLK; + + /* If operation mode is not set use setting from straps */ + ret = ofnode_read_s32(node, "ti,op-mode", &dp83869->mode); + if (ret == 0) { + if (dp83869->mode < DP83869_RGMII_COPPER_ETHERNET || + dp83869->mode > DP83869_SGMII_COPPER_ETHERNET) + return -EINVAL; + } else { + ret = dp83869_set_strapped_mode(phydev); + if (ret) + return ret; + } + + if (ofnode_read_bool(node, "ti,max-output-impedance")) + dp83869->io_impedance = DP83869_IO_MUX_CFG_IO_IMPEDANCE_MAX; + else if (ofnode_read_bool(node, "ti,min-output-impedance")) + dp83869->io_impedance = DP83869_IO_MUX_CFG_IO_IMPEDANCE_MIN; + + if (ofnode_read_bool(node, "enet-phy-lane-swap")) { + dp83869->port_mirroring = DP83869_PORT_MIRRORING_EN; + } else { + ret = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_STRAP_STS1); + + if (ret < 0) + return ret; + + if (ret & DP83869_STRAP_MIRROR_ENABLED) + dp83869->port_mirroring = DP83869_PORT_MIRRORING_EN; + else + dp83869->port_mirroring = DP83869_PORT_MIRRORING_DIS; + } + + dp83869->rx_fifo_depth = ofnode_read_s32_default(node, "rx-fifo-depth", + DP83869_PHYCR_FIFO_DEPTH_4_B_NIB); + + dp83869->tx_fifo_depth = ofnode_read_s32_default(node, "tx-fifo-depth", + DP83869_PHYCR_FIFO_DEPTH_4_B_NIB); + + /* RX delay *must* be specified if internal delay of RX is used. */ + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || + phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) { + dp83869->rx_int_delay = ofnode_read_u32_default(node, "rx-internal-delay-ps", + DP83869_CLK_DELAY_DEF); + if (dp83869->rx_int_delay > delay_entries) { + dp83869->rx_int_delay = DP83869_CLK_DELAY_DEF; + pr_debug("rx-internal-delay-ps not set/invalid, default to %ups\n", + dp83869_internal_delay[dp83869->rx_int_delay]); + } + + dp83869->rx_int_delay = dp83869_internal_delay[dp83869->rx_int_delay]; + } + + /* TX delay *must* be specified if internal delay of RX is used. */ + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || + phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) { + dp83869->tx_int_delay = ofnode_read_u32_default(node, "tx-internal-delay-ps", + DP83869_CLK_DELAY_DEF); + if (dp83869->tx_int_delay > delay_entries) { + dp83869->tx_int_delay = DP83869_CLK_DELAY_DEF; + pr_debug("tx-internal-delay-ps not set/invalid, default to %ups\n", + dp83869_internal_delay[dp83869->tx_int_delay]); + } + + dp83869->tx_int_delay = dp83869_internal_delay[dp83869->tx_int_delay]; + } + + return 0; +} +#else +static int dp83869_of_init(struct phy_device *phydev) +{ + struct dp83869_private *dp83869 = phydev->priv; + + dp83869->rx_int_delay = DP83869_RGMIIDCTL_2_25_NS; + dp83869->tx_int_delay = DP83869_RGMIIDCTL_2_75_NS; + dp83869->fifo_depth = DEFAULT_FIFO_DEPTH; + dp83869->io_impedance = -EINVAL; + + return 0; +} +#endif /* CONFIG_OF_MDIO */ + +static int dp83869_configure_rgmii(struct phy_device *phydev, + struct dp83869_private *dp83869) +{ + int ret = 0, val; + + if (phy_interface_is_rgmii(phydev)) { + val = phy_read(phydev, MDIO_DEVAD_NONE, MII_DP83869_PHYCTRL); + if (val < 0) + return val; + + val &= ~(DP83869_PHYCR_TX_FIFO_DEPTH_MASK | DP83869_PHYCR_RX_FIFO_DEPTH_MASK); + val |= (dp83869->tx_fifo_depth << DP83869_PHYCR_TX_FIFO_DEPTH_SHIFT); + val |= (dp83869->rx_fifo_depth << DP83869_PHYCR_RX_FIFO_DEPTH_SHIFT); + + ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83869_PHYCTRL, val); + if (ret) + return ret; + } + + if (dp83869->io_impedance >= 0) { + val = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_IO_MUX_CFG); + + val &= ~DP83869_IO_MUX_CFG_IO_IMPEDANCE_CTRL; + val |= dp83869->io_impedance & DP83869_IO_MUX_CFG_IO_IMPEDANCE_CTRL; + + ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_IO_MUX_CFG, val); + + if (ret) + return ret; + } + + return ret; +} + +static int dp83869_configure_mode(struct phy_device *phydev, + struct dp83869_private *dp83869) +{ + int phy_ctrl_val; + int ret, val; + + if (dp83869->mode < DP83869_RGMII_COPPER_ETHERNET || + dp83869->mode > DP83869_SGMII_COPPER_ETHERNET) + return -EINVAL; + + /* Below init sequence for each operational mode is defined in + * section 9.4.8 of the datasheet. + */ + ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_OP_MODE, + dp83869->mode); + if (ret) + return ret; + + ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, MII_DP83869_BMCR_DEFAULT); + if (ret) + return ret; + + phy_ctrl_val = (dp83869->rx_fifo_depth << DP83869_PHYCR_RX_FIFO_DEPTH_SHIFT | + dp83869->tx_fifo_depth << DP83869_PHYCR_TX_FIFO_DEPTH_SHIFT | + DP83869_PHY_CTRL_DEFAULT); + + switch (dp83869->mode) { + case DP83869_RGMII_COPPER_ETHERNET: + ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83869_PHYCTRL, + phy_ctrl_val); + if (ret) + return ret; + + ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, DP83869_CFG1_DEFAULT); + if (ret) + return ret; + + ret = dp83869_configure_rgmii(phydev, dp83869); + if (ret) + return ret; + break; + case DP83869_RGMII_SGMII_BRIDGE: + val = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_OP_MODE); + + val |= DP83869_SGMII_RGMII_BRIDGE; + + ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_OP_MODE, val); + + if (ret) + return ret; + + ret = phy_write_mmd(phydev, DP83869_DEVADDR, + DP83869_FX_CTRL, DP83869_FX_CTRL_DEFAULT); + if (ret) + return ret; + + break; + case DP83869_1000M_MEDIA_CONVERT: + ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83869_PHYCTRL, + phy_ctrl_val); + if (ret) + return ret; + + ret = phy_write_mmd(phydev, DP83869_DEVADDR, + DP83869_FX_CTRL, DP83869_FX_CTRL_DEFAULT); + if (ret) + return ret; + break; + case DP83869_100M_MEDIA_CONVERT: + ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83869_PHYCTRL, + phy_ctrl_val); + if (ret) + return ret; + break; + case DP83869_SGMII_COPPER_ETHERNET: + ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83869_PHYCTRL, + phy_ctrl_val); + if (ret) + return ret; + + ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, DP83869_CFG1_DEFAULT); + if (ret) + return ret; + + ret = phy_write_mmd(phydev, DP83869_DEVADDR, + DP83869_FX_CTRL, DP83869_FX_CTRL_DEFAULT); + if (ret) + return ret; + + break; + default: + return -EINVAL; + } + + return ret; +} + +static int dp83869_config(struct phy_device *phydev) +{ + struct dp83869_private *dp83869; + unsigned int val; + int ret; + + dp83869 = (struct dp83869_private *)phydev->priv; + + ret = dp83869_of_init(phydev); + if (ret) + return ret; + + ret = dp83869_configure_mode(phydev, dp83869); + if (ret) + return ret; + + if (dp83869->port_mirroring != DP83869_PORT_MIRRORING_KEEP) + dp83869_config_port_mirroring(phydev); + + /* Clock output selection if muxing property is set */ + if (dp83869->clk_output_sel != DP83869_CLK_O_SEL_REF_CLK) { + val = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_IO_MUX_CFG); + + val &= ~DP83869_IO_MUX_CFG_CLK_O_SEL_MASK; + val |= dp83869->clk_output_sel << DP83869_IO_MUX_CFG_CLK_O_SEL_SHIFT; + + ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_IO_MUX_CFG, val); + + if (ret) + return ret; + } + + if (phy_interface_is_rgmii(phydev)) { + ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIIDCTL, + dp83869->rx_int_delay | + dp83869->tx_int_delay << DP83869_RGMII_TX_CLK_DELAY_SHIFT); + if (ret) + return ret; + + val = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIICTL); + val |= (DP83869_RGMII_TX_CLK_DELAY_EN | + DP83869_RGMII_RX_CLK_DELAY_EN); + + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) + val &= ~(DP83869_RGMII_TX_CLK_DELAY_EN | + DP83869_RGMII_RX_CLK_DELAY_EN); + + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) + val &= ~DP83869_RGMII_TX_CLK_DELAY_EN; + + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) + val &= ~DP83869_RGMII_RX_CLK_DELAY_EN; + + ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIICTL, + val); + } + + genphy_config_aneg(phydev); + return 0; +} + +static int dp83869_probe(struct phy_device *phydev) +{ + struct dp83869_private *dp83869; + + dp83869 = kzalloc(sizeof(*dp83869), GFP_KERNEL); + if (!dp83869) + return -ENOMEM; + + phydev->priv = dp83869; + return 0; +} + +static struct phy_driver DP83869_driver = { + .name = "TI DP83869", + .uid = 0x2000a0f1, + .mask = 0xfffffff0, + .features = PHY_GBIT_FEATURES, + .probe = dp83869_probe, + .config = &dp83869_config, + .startup = &genphy_startup, + .shutdown = &genphy_shutdown, + .readext = dp83869_readext, + .writeext = dp83869_writeext +}; + +int phy_dp83869_init(void) +{ + phy_register(&DP83869_driver); + return 0; +} diff --git a/drivers/net/phy/ti_phy_init.c b/drivers/net/phy/ti_phy_init.c index 50eff77692..075b19a39f 100644 --- a/drivers/net/phy/ti_phy_init.c +++ b/drivers/net/phy/ti_phy_init.c @@ -88,6 +88,10 @@ int phy_ti_init(void) phy_dp83867_init(); #endif +#ifdef CONFIG_PHY_TI_DP83869 + phy_dp83869_init(); +#endif + #ifdef CONFIG_PHY_TI_GENERIC phy_register(&dp83822_driver); phy_register(&dp83825s_driver); diff --git a/drivers/net/phy/ti_phy_init.h b/drivers/net/phy/ti_phy_init.h index 6c7f6c640a..bcb3d320d3 100644 --- a/drivers/net/phy/ti_phy_init.h +++ b/drivers/net/phy/ti_phy_init.h @@ -11,5 +11,6 @@ #define _TI_GEN_PHY_H int phy_dp83867_init(void); +int phy_dp83869_init(void); #endif /* _TI_GEN_PHY_H */ diff --git a/include/dt-bindings/net/ti-dp83869.h b/include/dt-bindings/net/ti-dp83869.h new file mode 100644 index 0000000000..b3a5ac4a17 --- /dev/null +++ b/include/dt-bindings/net/ti-dp83869.h @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * TI DP83869 PHY drivers + * + */ + +#ifndef _DT_BINDINGS_TI_DP83869_H +#define _DT_BINDINGS_TI_DP83869_H + +/* PHY CTRL bits */ +#define DP83869_PHYCR_FIFO_DEPTH_3_B_NIB 0x00 +#define DP83869_PHYCR_FIFO_DEPTH_4_B_NIB 0x01 +#define DP83869_PHYCR_FIFO_DEPTH_6_B_NIB 0x02 +#define DP83869_PHYCR_FIFO_DEPTH_8_B_NIB 0x03 + +/* RGMIIDCTL internal delay for rx and tx */ +#define DP83869_RGMIIDCTL_250_PS 0x0 +#define DP83869_RGMIIDCTL_500_PS 0x1 +#define DP83869_RGMIIDCTL_750_PS 0x2 +#define DP83869_RGMIIDCTL_1_NS 0x3 +#define DP83869_RGMIIDCTL_1_25_NS 0x4 +#define DP83869_RGMIIDCTL_1_50_NS 0x5 +#define DP83869_RGMIIDCTL_1_75_NS 0x6 +#define DP83869_RGMIIDCTL_2_00_NS 0x7 +#define DP83869_RGMIIDCTL_2_25_NS 0x8 +#define DP83869_RGMIIDCTL_2_50_NS 0x9 +#define DP83869_RGMIIDCTL_2_75_NS 0xa +#define DP83869_RGMIIDCTL_3_00_NS 0xb +#define DP83869_RGMIIDCTL_3_25_NS 0xc +#define DP83869_RGMIIDCTL_3_50_NS 0xd +#define DP83869_RGMIIDCTL_3_75_NS 0xe +#define DP83869_RGMIIDCTL_4_00_NS 0xf + +/* IO_MUX_CFG - Clock output selection */ +#define DP83869_CLK_O_SEL_CHN_A_RCLK 0x0 +#define DP83869_CLK_O_SEL_CHN_B_RCLK 0x1 +#define DP83869_CLK_O_SEL_CHN_C_RCLK 0x2 +#define DP83869_CLK_O_SEL_CHN_D_RCLK 0x3 +#define DP83869_CLK_O_SEL_CHN_A_RCLK_DIV5 0x4 +#define DP83869_CLK_O_SEL_CHN_B_RCLK_DIV5 0x5 +#define DP83869_CLK_O_SEL_CHN_C_RCLK_DIV5 0x6 +#define DP83869_CLK_O_SEL_CHN_D_RCLK_DIV5 0x7 +#define DP83869_CLK_O_SEL_CHN_A_TCLK 0x8 +#define DP83869_CLK_O_SEL_CHN_B_TCLK 0x9 +#define DP83869_CLK_O_SEL_CHN_C_TCLK 0xA +#define DP83869_CLK_O_SEL_CHN_D_TCLK 0xB +#define DP83869_CLK_O_SEL_REF_CLK 0xC +/* Special flag to indicate clock should be off */ +#define DP83869_CLK_O_SEL_OFF 0xFFFFFFFF + +/* OPMODE - Operation mode */ +#define DP83869_RGMII_COPPER_ETHERNET 0x00 +#define DP83869_RGMII_1000_BASE 0x01 +#define DP83869_RGMII_100_BASE 0x02 +#define DP83869_RGMII_SGMII_BRIDGE 0x03 +#define DP83869_1000M_MEDIA_CONVERT 0x04 +#define DP83869_100M_MEDIA_CONVERT 0x05 +#define DP83869_SGMII_COPPER_ETHERNET 0x06 + +#endif -- 2.33.1

2 2

[PATCH v2] cmd: pxe_utils: sysboot: add label override support
by Amjad Ouled-Ameur 15 Jan '22

15 Jan '22

This will allow consumers to choose a pxe label at runtime instead of having to prompt the user. One good use-case for this, is choosing whether or not to apply a dtbo depending on the hardware configuration. e.g: for TI's AM335x EVM, it would be convenient to apply a particular dtbo only when the J9 jumper is on PRUSS mode. To achieve this, the pxe menu should have 2 labels, one with the dtbo and the other without, then the "pxe_label_override" env variable should point to the label with the dtbo at runtime only when the jumper is on PRUSS mode. This change can be used for different use-cases and bring more flexibilty to consumers who use sysboot/pxe_utils. if "pxe_label_override" is set but does not exist in the pxe menu, the code should fallback to the default label if given, and no failure is returned but rather a warning message. Signed-off-by: Amjad Ouled-Ameur <aouledameur(a)baylibre.com> --- Changes in v2: - Use !strcmp() instead of strcmp()==0 - Add "pxe_label_override" documentation boot/pxe_utils.c | 15 +++++++++++++++ doc/README.pxe | 6 ++++++ 2 files changed, 21 insertions(+) diff --git a/boot/pxe_utils.c b/boot/pxe_utils.c index a7a84f26c1d5..defc806fdc4f 100644 --- a/boot/pxe_utils.c +++ b/boot/pxe_utils.c @@ -1349,9 +1349,11 @@ static struct menu *pxe_menu_to_menu(struct pxe_menu *cfg) struct pxe_label *label; struct list_head *pos; struct menu *m; + char *label_override; int err; int i = 1; char *default_num = NULL; + char *override_num = NULL; /* * Create a menu and add items for all the labels. @@ -1361,6 +1363,8 @@ static struct menu *pxe_menu_to_menu(struct pxe_menu *cfg) if (!m) return NULL; + label_override = env_get("pxe_label_override"); + list_for_each(pos, &cfg->labels) { label = list_entry(pos, struct pxe_label, list); @@ -1372,6 +1376,17 @@ static struct menu *pxe_menu_to_menu(struct pxe_menu *cfg) if (cfg->default_label && (strcmp(label->name, cfg->default_label) == 0)) default_num = label->num; + if (label_override && !strcmp(label->name, label_override)) + override_num = label->num; + } + + + if (label_override) { + if (override_num) + default_num = override_num; + else + printf("Missing override pxe label: %s\n", + label_override); } /* diff --git a/doc/README.pxe b/doc/README.pxe index b67151ca510e..a1f0423adbec 100644 --- a/doc/README.pxe +++ b/doc/README.pxe @@ -92,6 +92,12 @@ pxe boot fdtoverlay_addr_r - location in RAM at which 'pxe boot' will temporarily store fdt overlay(s) before applying them to the fdt blob stored at 'fdt_addr_r'. + pxe_label_override - override label to be used, if exists, instead of the + default label. This will allow consumers to choose a pxe label at + runtime instead of having to prompt the user. If "pxe_label_override" is set + but does not exist in the pxe menu, pxe would fallback to the default label if + given, and no failure is returned but rather a warning message. + pxe file format =============== The pxe file format is nearly a subset of the PXELINUX file format; see -- 2.25.1

4 6

[PATCH] spi: mxc_spi: remove redundant code in spi_xchg_single()
by li.haolin＠qq.com 15 Jan '22

15 Jan '22

From: Haolin Li <li.haolin(a)qq.com> The value of cnt is overwritten without being used. Signed-off-by: Haolin Li <li.haolin(a)qq.com> --- drivers/spi/mxc_spi.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c index 3c53de165d..5adfdf8b5f 100644 --- a/drivers/spi/mxc_spi.c +++ b/drivers/spi/mxc_spi.c @@ -391,8 +391,6 @@ int spi_xchg_single(struct mxc_spi_slave *mxcs, unsigned int bitlen, nbytes = DIV_ROUND_UP(bitlen, 8); - cnt = nbytes % 32; - if (bitlen % 32) { data = reg_read(&regs->rxdata); cnt = (bitlen % 32) / 8; -- 2.25.1

2 1

[PATCH 1/1] configs: opos6uldev: update to have screen working at power on
by Sébastien Szymanski 15 Jan '22

15 Jan '22

Signed-off-by: Sébastien Szymanski <sebastien.szymanski(a)armadeus.com> --- configs/opos6uldev_defconfig | 3 --- 1 file changed, 3 deletions(-) diff --git a/configs/opos6uldev_defconfig b/configs/opos6uldev_defconfig index c52d2a5d39..409c48451e 100644 --- a/configs/opos6uldev_defconfig +++ b/configs/opos6uldev_defconfig @@ -103,13 +103,10 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_DM_VIDEO=y -# CONFIG_VIDEO_BPP8 is not set -# CONFIG_VIDEO_BPP32 is not set CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_VIDEO_MXS=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y -CONFIG_SPLASH_SOURCE=y CONFIG_VIDEO_BMP_RLE8=y CONFIG_BMP_16BPP=y CONFIG_BMP_24BPP=y -- 2.32.0

2 1

[PATCH] ARM: imx6: dh-imx6: Add update_sf script to install U-Boot into SF
by Marek Vasut 15 Jan '22

15 Jan '22

Add script to read U-Boot from SD card and write it to matching locations in the SPI NOR, thus making the SPI NOR bootable. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Christoph Niedermaier <cniedermaier(a)dh-electronics.com> Cc: Stefano Babic <sbabic(a)denx.de> --- include/configs/dh_imx6.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/configs/dh_imx6.h b/include/configs/dh_imx6.h index ee56eb691ad..8183e7debd4 100644 --- a/include/configs/dh_imx6.h +++ b/include/configs/dh_imx6.h @@ -82,6 +82,10 @@ "ramdisk_addr_r=0x18000000\0" \ "scriptaddr=0x14000000\0" \ "fdtfile=imx6q-dhcom-pdk2.dtb\0"\ + "update_sf=" /* Erase SPI NOR and install U-Boot from SD */ \ + "load mmc 0:1 ${loadaddr} /boot/u-boot-with-spl.imx && "\ + "sf probe && sf erase 0x0 0xa0000 && " \ + "sf write ${loadaddr} 0x400 ${filesize}\0" \ BOOTENV #define CONFIG_BOOTCOMMAND "run distro_bootcmd" -- 2.33.0

3 2

[PATCH v3] phy: Track power-on and init counts in uclass
by Alper Nebi Yasak 15 Jan '22

15 Jan '22

On boards using the RK3399 SoC, the USB OHCI and EHCI controllers share the same PHY device instance. While these controllers are being stopped they both attempt to power-off and deinitialize it, but trying to power-off the deinitialized PHY device results in a hang. This usually happens just before booting an OS, and can be explicitly triggered by running "usb start; usb stop" in the U-Boot shell. Implement a uclass-wide counting mechanism for PHY initialization and power state change requests, so that we don't power-off/deinitialize a PHY instance until all of its users want it done. The Allwinner A10 USB PHY driver does this counting in-driver, remove those parts in favour of this in-uclass implementation. The sandbox PHY operations test needs some changes since the uclass will no longer call into the drivers for actions matching its tracked state (e.g. powering-off a powered-off PHY). Update that test, and add a new one which simulates multiple users of a single PHY. The major complication here is that PHY handles aren't deduplicated per instance, so the obvious idea of putting the counts in the PHY handles don't immediately work. It seems possible to bind a child udevice per PHY instance to the PHY provider and deduplicate the handles in each child's uclass-private areas, like in the CLK framework. An alternative approach could be to use those bound child udevices themselves as the PHY handles. Instead, to avoid the architectural changes those would require, this patch solves things by dynamically allocating a list of structs (one per instance) in the provider's uclass-private area. Signed-off-by: Alper Nebi Yasak <alpernebiyasak(a)gmail.com> Reviewed-by: Simon Glass <sjg(a)chromium.org> --- Changes in v3: - Add tag: "Reviewed-by: Simon Glass <sjg(a)chromium.org>" - Add comment for phy_counts struct v2: https://patchwork.ozlabs.org/project/uboot/patch/20211224130549.20276-1-alp… Changes in v2: - Rename {phy_,}id_priv -> {phy_,}counts - Split phy_get_uclass_priv -> phy_{alloc,get}_counts - Allocate counts (or return error) in generic_phy_get_by_*() - Remove now-unnecessary null checks for counts of valid phy handles v1: https://patchwork.ozlabs.org/project/uboot/patch/20211210200124.19226-1-alp… drivers/phy/allwinner/phy-sun4i-usb.c | 9 -- drivers/phy/phy-uclass.c | 137 ++++++++++++++++++++++++++ test/dm/phy.c | 83 +++++++++++++++- 3 files changed, 215 insertions(+), 14 deletions(-) diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c index ab2a5d17fcff..86c589a65fd3 100644 --- a/drivers/phy/allwinner/phy-sun4i-usb.c +++ b/drivers/phy/allwinner/phy-sun4i-usb.c @@ -125,7 +125,6 @@ struct sun4i_usb_phy_info { struct sun4i_usb_phy_plat { void __iomem *pmu; - int power_on_count; int gpio_vbus; int gpio_vbus_det; int gpio_id_det; @@ -225,10 +224,6 @@ static int sun4i_usb_phy_power_on(struct phy *phy) initial_usb_scan_delay = 0; } - usb_phy->power_on_count++; - if (usb_phy->power_on_count != 1) - return 0; - if (usb_phy->gpio_vbus >= 0) gpio_set_value(usb_phy->gpio_vbus, SUNXI_GPIO_PULL_UP); @@ -240,10 +235,6 @@ static int sun4i_usb_phy_power_off(struct phy *phy) struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev); struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id]; - usb_phy->power_on_count--; - if (usb_phy->power_on_count != 0) - return 0; - if (usb_phy->gpio_vbus >= 0) gpio_set_value(usb_phy->gpio_vbus, SUNXI_GPIO_PULL_DISABLE); diff --git a/drivers/phy/phy-uclass.c b/drivers/phy/phy-uclass.c index 59683a080cd7..cec46c2c4103 100644 --- a/drivers/phy/phy-uclass.c +++ b/drivers/phy/phy-uclass.c @@ -11,12 +11,96 @@ #include <dm/device_compat.h> #include <dm/devres.h> #include <generic-phy.h> +#include <linux/list.h> + +/** + * struct phy_counts - Init and power-on counts of a single PHY port + * + * This structure is used to keep track of PHY initialization and power + * state change requests, so that we don't power off and deinitialize a + * PHY instance until all of its users want it done. Otherwise, multiple + * consumers using the same PHY port can cause problems (e.g. one might + * call power_off() after another's exit() and hang indefinitely). + * + * @id: The PHY ID within a PHY provider + * @power_on_count: Times generic_phy_power_on() was called for this ID + * without a matching generic_phy_power_off() afterwards + * @init_count: Times generic_phy_init() was called for this ID + * without a matching generic_phy_exit() afterwards + * @list: Handle for a linked list of these structures corresponding to + * ports of the same PHY provider + */ +struct phy_counts { + unsigned long id; + int power_on_count; + int init_count; + struct list_head list; +}; static inline struct phy_ops *phy_dev_ops(struct udevice *dev) { return (struct phy_ops *)dev->driver->ops; } +static struct phy_counts *phy_get_counts(struct phy *phy) +{ + struct list_head *uc_priv; + struct phy_counts *counts; + + if (!generic_phy_valid(phy)) + return NULL; + + uc_priv = dev_get_uclass_priv(phy->dev); + list_for_each_entry(counts, uc_priv, list) + if (counts->id == phy->id) + return counts; + + return NULL; +} + +static int phy_alloc_counts(struct phy *phy) +{ + struct list_head *uc_priv; + struct phy_counts *counts; + + if (!generic_phy_valid(phy)) + return 0; + if (phy_get_counts(phy)) + return 0; + + uc_priv = dev_get_uclass_priv(phy->dev); + counts = kzalloc(sizeof(*counts), GFP_KERNEL); + if (!counts) + return -ENOMEM; + + counts->id = phy->id; + counts->power_on_count = 0; + counts->init_count = 0; + list_add(&counts->list, uc_priv); + + return 0; +} + +static int phy_uclass_pre_probe(struct udevice *dev) +{ + struct list_head *uc_priv = dev_get_uclass_priv(dev); + + INIT_LIST_HEAD(uc_priv); + + return 0; +} + +static int phy_uclass_pre_remove(struct udevice *dev) +{ + struct list_head *uc_priv = dev_get_uclass_priv(dev); + struct phy_counts *counts, *next; + + list_for_each_entry_safe(counts, next, uc_priv, list) + kfree(counts); + + return 0; +} + static int generic_phy_xlate_offs_flags(struct phy *phy, struct ofnode_phandle_args *args) { @@ -88,6 +172,12 @@ int generic_phy_get_by_index_nodev(ofnode node, int index, struct phy *phy) goto err; } + ret = phy_alloc_counts(phy); + if (ret) { + debug("phy_alloc_counts() failed: %d\n", ret); + goto err; + } + return 0; err: @@ -118,6 +208,7 @@ int generic_phy_get_by_name(struct udevice *dev, const char *phy_name, int generic_phy_init(struct phy *phy) { + struct phy_counts *counts; struct phy_ops const *ops; int ret; @@ -126,10 +217,19 @@ int generic_phy_init(struct phy *phy) ops = phy_dev_ops(phy->dev); if (!ops->init) return 0; + + counts = phy_get_counts(phy); + if (counts->init_count > 0) { + counts->init_count++; + return 0; + } + ret = ops->init(phy); if (ret) dev_err(phy->dev, "PHY: Failed to init %s: %d.\n", phy->dev->name, ret); + else + counts->init_count = 1; return ret; } @@ -154,6 +254,7 @@ int generic_phy_reset(struct phy *phy) int generic_phy_exit(struct phy *phy) { + struct phy_counts *counts; struct phy_ops const *ops; int ret; @@ -162,16 +263,28 @@ int generic_phy_exit(struct phy *phy) ops = phy_dev_ops(phy->dev); if (!ops->exit) return 0; + + counts = phy_get_counts(phy); + if (counts->init_count == 0) + return 0; + if (counts->init_count > 1) { + counts->init_count--; + return 0; + } + ret = ops->exit(phy); if (ret) dev_err(phy->dev, "PHY: Failed to exit %s: %d.\n", phy->dev->name, ret); + else + counts->init_count = 0; return ret; } int generic_phy_power_on(struct phy *phy) { + struct phy_counts *counts; struct phy_ops const *ops; int ret; @@ -180,16 +293,26 @@ int generic_phy_power_on(struct phy *phy) ops = phy_dev_ops(phy->dev); if (!ops->power_on) return 0; + + counts = phy_get_counts(phy); + if (counts->power_on_count > 0) { + counts->power_on_count++; + return 0; + } + ret = ops->power_on(phy); if (ret) dev_err(phy->dev, "PHY: Failed to power on %s: %d.\n", phy->dev->name, ret); + else + counts->power_on_count = 1; return ret; } int generic_phy_power_off(struct phy *phy) { + struct phy_counts *counts; struct phy_ops const *ops; int ret; @@ -198,10 +321,21 @@ int generic_phy_power_off(struct phy *phy) ops = phy_dev_ops(phy->dev); if (!ops->power_off) return 0; + + counts = phy_get_counts(phy); + if (counts->power_on_count == 0) + return 0; + if (counts->power_on_count > 1) { + counts->power_on_count--; + return 0; + } + ret = ops->power_off(phy); if (ret) dev_err(phy->dev, "PHY: Failed to power off %s: %d.\n", phy->dev->name, ret); + else + counts->power_on_count = 0; return ret; } @@ -316,4 +450,7 @@ int generic_phy_power_off_bulk(struct phy_bulk *bulk) UCLASS_DRIVER(phy) = { .id = UCLASS_PHY, .name = "phy", + .pre_probe = phy_uclass_pre_probe, + .pre_remove = phy_uclass_pre_remove, + .per_device_auto = sizeof(struct list_head), }; diff --git a/test/dm/phy.c b/test/dm/phy.c index ecbd47bf12fd..df4c73fc701f 100644 --- a/test/dm/phy.c +++ b/test/dm/phy.c @@ -79,12 +79,15 @@ static int dm_test_phy_ops(struct unit_test_state *uts) ut_assertok(generic_phy_power_off(&phy1)); /* - * test operations after exit(). - * The sandbox phy driver does not allow it. + * Test power_on() failure after exit(). + * The sandbox phy driver does not allow power-on/off after + * exit, but the uclass counts power-on/init calls and skips + * calling the driver's ops when e.g. powering off an already + * powered-off phy. */ ut_assertok(generic_phy_exit(&phy1)); ut_assert(generic_phy_power_on(&phy1) != 0); - ut_assert(generic_phy_power_off(&phy1) != 0); + ut_assertok(generic_phy_power_off(&phy1)); /* * test normal operations again (after re-init) @@ -99,6 +102,17 @@ static int dm_test_phy_ops(struct unit_test_state *uts) */ ut_assertok(generic_phy_reset(&phy1)); + /* + * Test power_off() failure after exit(). + * For this we need to call exit() while the phy is powered-on, + * so that the uclass actually calls the driver's power-off() + * and reports the resulting failure. + */ + ut_assertok(generic_phy_power_on(&phy1)); + ut_assertok(generic_phy_exit(&phy1)); + ut_assert(generic_phy_power_off(&phy1) != 0); + ut_assertok(generic_phy_power_on(&phy1)); + /* PHY2 has a known problem with power off */ ut_assertok(generic_phy_init(&phy2)); ut_assertok(generic_phy_power_on(&phy2)); @@ -106,8 +120,8 @@ static int dm_test_phy_ops(struct unit_test_state *uts) /* PHY3 has a known problem with power off and power on */ ut_assertok(generic_phy_init(&phy3)); - ut_asserteq(-EIO, generic_phy_power_off(&phy3)); - ut_asserteq(-EIO, generic_phy_power_off(&phy3)); + ut_asserteq(-EIO, generic_phy_power_on(&phy3)); + ut_assertok(generic_phy_power_off(&phy3)); return 0; } @@ -145,3 +159,62 @@ static int dm_test_phy_bulk(struct unit_test_state *uts) return 0; } DM_TEST(dm_test_phy_bulk, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT); + +static int dm_test_phy_multi_exit(struct unit_test_state *uts) +{ + struct phy phy1_method1; + struct phy phy1_method2; + struct phy phy1_method3; + struct udevice *parent; + + /* Get the same phy instance in 3 different ways. */ + ut_assertok(uclass_get_device_by_name(UCLASS_SIMPLE_BUS, + "gen_phy_user", &parent)); + ut_assertok(generic_phy_get_by_name(parent, "phy1", &phy1_method1)); + ut_asserteq(0, phy1_method1.id); + ut_assertok(generic_phy_get_by_name(parent, "phy1", &phy1_method2)); + ut_asserteq(0, phy1_method2.id); + ut_asserteq_ptr(phy1_method1.dev, phy1_method1.dev); + + ut_assertok(uclass_get_device_by_name(UCLASS_SIMPLE_BUS, + "gen_phy_user1", &parent)); + ut_assertok(generic_phy_get_by_name(parent, "phy1", &phy1_method3)); + ut_asserteq(0, phy1_method3.id); + ut_asserteq_ptr(phy1_method1.dev, phy1_method3.dev); + + /* + * Test using the same PHY from different handles. + * In non-test code these could be in different drivers. + */ + + /* + * These must only call the driver's ops at the first init() + * and power_on(). + */ + ut_assertok(generic_phy_init(&phy1_method1)); + ut_assertok(generic_phy_init(&phy1_method2)); + ut_assertok(generic_phy_power_on(&phy1_method1)); + ut_assertok(generic_phy_power_on(&phy1_method2)); + ut_assertok(generic_phy_init(&phy1_method3)); + ut_assertok(generic_phy_power_on(&phy1_method3)); + + /* + * These must not call the driver's ops as other handles still + * want the PHY powered-on and initialized. + */ + ut_assertok(generic_phy_power_off(&phy1_method3)); + ut_assertok(generic_phy_exit(&phy1_method3)); + + /* + * We would get an error here if the generic_phy_exit() above + * actually called the driver's exit(), as the sandbox driver + * doesn't allow power-off() after exit(). + */ + ut_assertok(generic_phy_power_off(&phy1_method1)); + ut_assertok(generic_phy_power_off(&phy1_method2)); + ut_assertok(generic_phy_exit(&phy1_method1)); + ut_assertok(generic_phy_exit(&phy1_method2)); + + return 0; +} +DM_TEST(dm_test_phy_multi_exit, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT); -- 2.34.1

3 2

[PATCH 0/1] [PATCH] ARM: qemu-arm: Fix build fail with boot devices disabled
by Piotr Kubik 15 Jan '22

15 Jan '22

BOOT_TARGET_DEVICES should only be added if the corresponding u-boot command is enabled otherwise the build will fail like: include/config_distro_bootcmd.h:241:2: error: expected '}' before 'BOOT_TARGET_DEVICES_references_SCSI_without_CONFIG_SCSI' BOOT_TARGET_DEVICES_references_SCSI_without_CONFIG_SCSI ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ include/config_distro_bootcmd.h:241:2: note: in definition of macro 'BOOTENV_DEV_NAME_SCSI' BOOT_TARGET_DEVICES_references_SCSI_without_CONFIG_SCSI ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ include/configs/qemu-arm.h:26:2: note: in expansion of macro 'BOOTENV_DEV_NAME' func(SCSI, scsi, 0) \ ^~~~ Tested with CONFIG_USB and CONFIG_SCSI disabled & enabled. Piotr Kubik (1): ARM: qemu-arm: Fix build fail with boot devices disabled include/configs/qemu-arm.h | 32 ++++++++++++++++++++++++++++---- 1 file changed, 28 insertions(+), 4 deletions(-) -- 2.25.1

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[PATCH] phy: nop-phy: Enable reset-gpios support
by Adam Ford 15 Jan '22

15 Jan '22

Some usb-nop-xceiv devices use a gpio to put them in and out of reset. Add a reset function to put them into that state. This is similar to how Linux handles the usb-nop-xceiv driver. Signed-off-by: Adam Ford <aford173(a)gmail.com> diff --git a/drivers/phy/nop-phy.c b/drivers/phy/nop-phy.c index 9f12ebc062..be993a764f 100644 --- a/drivers/phy/nop-phy.c +++ b/drivers/phy/nop-phy.c @@ -10,11 +10,24 @@ #include <dm/device.h> #include <dm/device_compat.h> #include <generic-phy.h> +#include <asm-generic/gpio.h> struct nop_phy_priv { struct clk_bulk bulk; + struct gpio_desc reset_gpio; }; +static int nop_phy_reset(struct phy *phy) +{ + struct nop_phy_priv *priv = dev_get_priv(phy->dev); + + /* Return if there is no gpio since it's optional */ + if (!dm_gpio_is_valid(&priv->reset_gpio)) + return 0; + + return dm_gpio_set_value(&priv->reset_gpio, false); +} + static int nop_phy_init(struct phy *phy) { struct nop_phy_priv *priv = dev_get_priv(phy->dev); @@ -22,7 +35,12 @@ static int nop_phy_init(struct phy *phy) if (CONFIG_IS_ENABLED(CLK)) return clk_enable_bulk(&priv->bulk); - return 0; + /* Return if there is no gpio since it's optional */ + if (!dm_gpio_is_valid(&priv->reset_gpio)) + return 0; + + /* If there is a reset gpio, take it out of reset */ + return dm_gpio_set_value(&priv->reset_gpio, true); } static int nop_phy_probe(struct udevice *dev) @@ -38,6 +56,12 @@ static int nop_phy_probe(struct udevice *dev) } } + ret = gpio_request_by_name(dev, "reset-gpios", 0, + &priv->reset_gpio, + GPIOD_IS_OUT); + if (ret != -ENOENT) + return ret; + return 0; } @@ -49,6 +73,7 @@ static const struct udevice_id nop_phy_ids[] = { static struct phy_ops nop_phy_ops = { .init = nop_phy_init, + .reset = nop_phy_reset, }; U_BOOT_DRIVER(nop_phy) = { -- 2.32.0

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