November 2021 - U-Boot

Please pull u-boot-marvell/master
by Stefan Roese 30 Nov '21

30 Nov '21

Hi Tom, please pull these 2 Marvell MVEBU related fixes: ---------------------------------------------------------------- - turris_omnia: enable A385 watchdog before disabling MCU watchdog (Pali) - a37xx: Reset whole UART when changing parent clock from TBG to XTAL (Pali) ---------------------------------------------------------------- Here the Azure build, without any issues: https://dev.azure.com/sr0718/u-boot/_build/results?buildId=137 Thanks, Stefan The following changes since commit ade37460a944aed36ae6ee634c4d4a9a22690461: Prepare v2022.01-rc3 (2021-11-29 11:16:03 -0500) are available in the Git repository at: git@source.denx.de:u-boot/custodians/u-boot-marvell.git for you to fetch changes up to 5db5815e997ae8cf0a3bba6a25652d8b6fd5edd1: serial: a37xx: Reset whole UART when changing parent clock from TBG to XTAL (2021-11-30 08:31:04 +0100) ---------------------------------------------------------------- Pali Rohár (2): arm: mvebu: turris_omnia: enable A385 watchdog before disabling MCU watchdog serial: a37xx: Reset whole UART when changing parent clock from TBG to XTAL board/CZ.NIC/turris_omnia/turris_omnia.c | 65 +++++++++++++++++++++++++++++++- drivers/serial/serial_mvebu_a3700.c | 13 ++++++- 2 files changed, 75 insertions(+), 3 deletions(-) Viele Grüße, Stefan Roese -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: sr(a)denx.de

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TPM subsystem pull
by Ilias Apalodimas 30 Nov '21

30 Nov '21

Prepare v2022.01-rc3 (2021-11-29 11:16:03 -0500) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-tpm/ tags/tpm-30112021 for you to fetch changes up to c3de051c411e024f9e63ab338071584b9460e8b3: tis: fix tpm_tis_remove() (2021-11-30 14:11:05 +0200) ---------------------------------------------------------------- TPM2 API fixes ---------------------------------------------------------------- Heinrich Schuchardt (1): tis: fix tpm_tis_remove() drivers/tpm/tpm2_tis_core.c | 6 ++++++ drivers/tpm/tpm2_tis_mmio.c | 5 ++++- 2 files changed, 10 insertions(+), 1 deletion(-)

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Pull request for efi-2022-01-rc4
by Heinrich Schuchardt 30 Nov '21

30 Nov '21

Hello Tom, now that you have merged running swtpm via u-boot-test-hooks this pull request finally finishes of making TPMs and the EFI_TCG2_PROTOCOL on ARM testable. The following changes since commit ade37460a944aed36ae6ee634c4d4a9a22690461: Prepare v2022.01-rc3 (2021-11-29 11:16:03 -0500) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-efi.git tags/efi-2022-01-rc4 for you to fetch changes up to c0d9bb0b4a747a7ec481b2369391ca8f53e50bc9: efi_loader: Extend PCR's for firmware measurements (2021-11-30 09:23:49 +0100) Gitlab CI showed no problems: https://source.denx.de/u-boot/custodians/u-boot-efi/-/pipelines/10033 ---------------------------------------------------------------- Pull request for efi-2022-01-rc4 Documentation: * describe how to enable Virtio RNG on QEMU ARM UEFI: * enable testing the TCG2 protocol * support TPM event log passed from firmware ---------------------------------------------------------------- Heinrich Schuchardt (3): doc: qemu-arm peripherials configs: enable CMD_TPM on QEMU ARM test: unit test for the EFI_TCG2_PROTOCOL Ruchika Gupta (3): efi_loader: Add check for event log passed from firmware tpm: use more algorithms than sha256 on pcr_read efi_loader: Extend PCR's for firmware measurements cmd/tpm-v2.c | 3 +- configs/qemu_arm64_defconfig | 1 + configs/qemu_arm_defconfig | 1 + doc/board/emulation/qemu-arm.rst | 9 +- drivers/tpm/tpm2_tis_mmio.c | 5 +- include/efi_loader.h | 2 + include/tpm-v2.h | 5 +- lib/efi_loader/efi_tcg2.c | 545 ++++++++++++++++++++++++++++++++----- lib/tpm-v2.c | 12 +- test/py/tests/test_efi_selftest.py | 20 ++ test/py/tests/test_tpm2.py | 1 + 11 files changed, 526 insertions(+), 78 deletions(-)

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[PATCH] Fix MMC numbering issue for Raspberry Pi 3
by karels＠FreeBSD.org 30 Nov '21

30 Nov '21

From: Mike Karels <karels(a)FreeBSD.org> Using mmc.dtbo from rpi-firmware to switch the controller for the SD card slot from sdhci to sdhost causes the numbering to change; the SD card is then not recognized at boot. Add to the range checked. --- include/configs/rpi.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/configs/rpi.h b/include/configs/rpi.h index 55768a46da..4c5c1ac31f 100644 --- a/include/configs/rpi.h +++ b/include/configs/rpi.h @@ -137,7 +137,8 @@ #if CONFIG_IS_ENABLED(CMD_MMC) #define BOOT_TARGET_MMC(func) \ func(MMC, mmc, 0) \ - func(MMC, mmc, 1) + func(MMC, mmc, 1) \ + func(MMC, mmc, 2) #else #define BOOT_TARGET_MMC(func) #endif -- 2.32.0

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[PATCH 1/2] rpi: Update the Raspberry Pi doucmentation URL
by Peter Robinson 30 Nov '21

30 Nov '21

The Raspberry Pi Foundation has updated their documentation so update the URL to the latest place to find the HW device revision codes. Signed-off-by: Peter Robinson <pbrobinson(a)gmail.com> --- board/raspberrypi/rpi/rpi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c index 55afaa54d9..e7bcee3746 100644 --- a/board/raspberrypi/rpi/rpi.c +++ b/board/raspberrypi/rpi/rpi.c @@ -72,7 +72,7 @@ struct msg_get_clock_rate { #endif /* - * https://www.raspberrypi.org/documentation/hardware/raspberrypi/revision-cod… + * https://www.raspberrypi.com/documentation/computers/raspberry-pi.html#raspb… */ struct rpi_model { const char *name; -- 2.33.1

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[PATCH] ARM: stm32: Increase USB power-good delay on DHSOM
by Marek Vasut 30 Nov '21

30 Nov '21

The USB hub on STM32MP1 DHCOM boards needs to wait a bit longer until the USB Vbus is stable. Increase the USB power-good delay to 1 s. This adds default-undefined STM32MP_BOARD_EXTRA_ENV variable into stm32mp15_common.h to reduce duplication in board-specific config files adding custom environment. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Patrice Chotard <patrice.chotard(a)foss.st.com> Cc: Patrick Delaunay <patrick.delaunay(a)foss.st.com> --- include/configs/stm32mp15_common.h | 3 ++- include/configs/stm32mp15_dh_dhsom.h | 3 +++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/include/configs/stm32mp15_common.h b/include/configs/stm32mp15_common.h index 4e2cabff2e7..be22d3ea7f1 100644 --- a/include/configs/stm32mp15_common.h +++ b/include/configs/stm32mp15_common.h @@ -169,7 +169,8 @@ STM32MP_BOOTCMD \ STM32MP_PARTS_DEFAULT \ BOOTENV \ - STM32MP_EXTRA + STM32MP_EXTRA \ + STM32MP_BOARD_EXTRA_ENV #endif /* ifndef CONFIG_SPL_BUILD */ #endif /* ifdef CONFIG_DISTRO_DEFAULTS*/ diff --git a/include/configs/stm32mp15_dh_dhsom.h b/include/configs/stm32mp15_dh_dhsom.h index c559cd72da7..bac9e8388a7 100644 --- a/include/configs/stm32mp15_dh_dhsom.h +++ b/include/configs/stm32mp15_dh_dhsom.h @@ -8,6 +8,9 @@ #ifndef __CONFIG_STM32MP15_DH_DHSOM_H__ #define __CONFIG_STM32MP15_DH_DHSOM_H__ +#define STM32MP_BOARD_EXTRA_ENV \ + "usb_pgood_delay=1000\0" + #include <configs/stm32mp15_common.h> #define CONFIG_SPL_TARGET "u-boot.itb" -- 2.33.0

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[PATCH] serial: a37xx: Reset whole UART when changing parent clock from TBG to XTAL
by Pali Rohár 30 Nov '21

30 Nov '21

Sometimes UART stops transmitting characters after UART clock is changed back to XTAL. In this state UART fifo is always full. Kernel during early boot wants to print output on UART and is waiting for non-empty UART fifo. Which leads to CPU hangup without any (debug) output on UART. Marvell Armada 3700 Functional Specifications says that for programming fractional divisor registers it is required to disable UART, enable loopback mode, reset fifos, program registers, disable loopback mode, release reset of fifos and enable UART. But these steps do not fix above mentioned issue that UART hangup. Also gating UART clock does not help. And even resetting UART state machines do not help. Experiments showed that UART fifo is unblocked after board is being reset (during board reset UART HW transmit UART fifo even CPU is not executing kernel/bootloader anymore). And another experiments showed that same workaround can be achieved also by external reset of UART HW (without need to reset board). So do not implement any of "Marvell recommended" steps from Functional Specifications as they do not work. And rather prior changing parent clock back to XTAL, do external reset of UART HW. This operation also resets all UART registers, so basically it also sets UART clock to default, which is XTAL. It is unknown why UART hangups and enters such broken state. Signed-off-by: Pali Rohár <pali(a)kernel.org> --- drivers/serial/serial_mvebu_a3700.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/serial/serial_mvebu_a3700.c b/drivers/serial/serial_mvebu_a3700.c index 6bca8e4b7e2d..93e4d38d34c7 100644 --- a/drivers/serial/serial_mvebu_a3700.c +++ b/drivers/serial/serial_mvebu_a3700.c @@ -9,6 +9,7 @@ #include <serial.h> #include <asm/io.h> #include <asm/arch/cpu.h> +#include <mach/soc.h> struct mvebu_plat { void __iomem *base; @@ -213,6 +214,7 @@ static int mvebu_serial_remove(struct udevice *dev) u32 new_oversampling; u32 oversampling; u32 d1, d2; + u32 nb_rst; /* * Switch UART base clock back to XTAL because older Linux kernel @@ -260,12 +262,22 @@ static int mvebu_serial_remove(struct udevice *dev) return 0; } + /* wait until TX empty */ while (!(readl(base + UART_STATUS_REG) & UART_STATUS_TX_EMPTY)) ; + /* external reset of UART via North Bridge Peripheral */ + nb_rst = readl(MVEBU_REGISTER(0x12400)); + writel(nb_rst & ~BIT(3), MVEBU_REGISTER(0x12400)); + writel(nb_rst | BIT(3), MVEBU_REGISTER(0x12400)); + + /* set baudrate and oversampling */ writel(new_divider, base + UART_BAUD_REG); writel(new_oversampling, base + UART_POSSR_REG); + /* No Parity, 1 Stop */ + writel(0, base + UART_CTRL_REG); + return 0; } @@ -305,7 +317,6 @@ U_BOOT_DRIVER(serial_mvebu) = { #ifdef CONFIG_DEBUG_MVEBU_A3700_UART #include <debug_uart.h> -#include <mach/soc.h> static inline void _debug_uart_init(void) { -- 2.20.1

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[PATCH] board: stm32mp1: add support of nor1 device in dfu command
by Patrick Delaunay 30 Nov '21

30 Nov '21

Add support of mtd backend for nor1 when this device is present on the board, on STM32MP157C-EV1 for example, as the support of several MTD spi-nor instance are now supported with commit b7f060565e31 ("mtd: spi-nor: allow registering multiple MTDs when DM is enabled"). Signed-off-by: Patrick Delaunay <patrick.delaunay(a)foss.st.com> --- board/st/common/stm32mp_dfu.c | 4 ++++ doc/board/st/stm32mp1.rst | 18 ++++++++++-------- 2 files changed, 14 insertions(+), 8 deletions(-) diff --git a/board/st/common/stm32mp_dfu.c b/board/st/common/stm32mp_dfu.c index 00d1fb8f59..a3f0da5b5b 100644 --- a/board/st/common/stm32mp_dfu.c +++ b/board/st/common/stm32mp_dfu.c @@ -132,6 +132,10 @@ void set_dfu_alt_info(char *interface, char *devstr) mtd = get_mtd_device_nm("nor0"); if (!IS_ERR_OR_NULL(mtd)) board_get_alt_info_mtd(mtd, buf); + + mtd = get_mtd_device_nm("nor1"); + if (!IS_ERR_OR_NULL(mtd)) + board_get_alt_info_mtd(mtd, buf); } mtd = get_mtd_device_nm("nand0"); diff --git a/doc/board/st/stm32mp1.rst b/doc/board/st/stm32mp1.rst index 42bb94148d..0c5d3a90f0 100644 --- a/doc/board/st/stm32mp1.rst +++ b/doc/board/st/stm32mp1.rst @@ -645,16 +645,18 @@ On EV1 board, booting from SD card, without OP-TEE_:: dev: eMMC alt: 15 name: mmc1_rootfs layout: RAW_ADDR dev: eMMC alt: 16 name: mmc1_userfs layout: RAW_ADDR dev: MTD alt: 17 name: nor0 layout: RAW_ADDR - dev: MTD alt: 18 name: nand0 layout: RAW_ADDR - dev: VIRT alt: 19 name: OTP layout: RAW_ADDR - dev: VIRT alt: 20 name: PMIC layout: RAW_ADDR + dev: MTD alt: 18 name: nor1 layout: RAW_ADDR + dev: MTD alt: 19 name: nand0 layout: RAW_ADDR + dev: VIRT alt: 20 name: OTP layout: RAW_ADDR + dev: VIRT alt: 21 name: PMIC layout: RAW_ADDR All the supported device are exported for dfu-util tool:: $> dfu-util -l - Found DFU: [0483:df11] ver=9999, devnum=99, cfg=1, intf=0, alt=20, name="PMIC", serial="002700333338511934383330" - Found DFU: [0483:df11] ver=9999, devnum=99, cfg=1, intf=0, alt=19, name="OTP", serial="002700333338511934383330" - Found DFU: [0483:df11] ver=9999, devnum=99, cfg=1, intf=0, alt=18, name="nand0", serial="002700333338511934383330" + Found DFU: [0483:df11] ver=9999, devnum=99, cfg=1, intf=0, alt=21, name="PMIC", serial="002700333338511934383330" + Found DFU: [0483:df11] ver=9999, devnum=99, cfg=1, intf=0, alt=20, name="OTP", serial="002700333338511934383330" + Found DFU: [0483:df11] ver=9999, devnum=99, cfg=1, intf=0, alt=19, name="nand0", serial="002700333338511934383330" + Found DFU: [0483:df11] ver=9999, devnum=99, cfg=1, intf=0, alt=18, name="nor1", serial="002700333338511934383330" Found DFU: [0483:df11] ver=9999, devnum=99, cfg=1, intf=0, alt=17, name="nor0", serial="002700333338511934383330" Found DFU: [0483:df11] ver=9999, devnum=99, cfg=1, intf=0, alt=16, name="mmc1_userfs", serial="002700333338511934383330" Found DFU: [0483:df11] ver=9999, devnum=99, cfg=1, intf=0, alt=15, name="mmc1_rootfs", serial="002700333338511934383330" @@ -705,12 +707,12 @@ You can update the boot device: When the board is booting for nor0 or nand0, only the MTD partition on the boot devices are available, for example: -- NOR (nor0 = alt 20) & NAND (nand0 = alt 26) :: +- NOR (nor0 = alt 20, nor1 = alt 26) & NAND (nand0 = alt 27) : $> dfu-util -d 0483:5720 -a 21 -D tf-a-stm32mp157c-ev1.stm32 $> dfu-util -d 0483:5720 -a 22 -D tf-a-stm32mp157c-ev1.stm32 $> dfu-util -d 0483:5720 -a 23 -D fip-stm32mp157c-ev1.bin - $> dfu-util -d 0483:5720 -a 27 -D st-image-weston-openstlinux-weston-stm32mp1_nand_4_256_multivolume.ubi + $> dfu-util -d 0483:5720 -a 28 -D st-image-weston-openstlinux-weston-stm32mp1_nand_4_256_multivolume.ubi - NAND (nand0 = alt 21):: -- 2.25.1

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[PATCH u-boot-marvell] arm: mvebu: turris_omnia: enable A385 watchdog before disabling MCU watchdog
by Marek Behún 30 Nov '21

30 Nov '21

From: Pali Rohár <pali(a)kernel.org> Commit aeb0ca64dbb5 ("arm: mvebu: turris_omnia: disable MCU watchdog in SPL when booting over UART") disabled MCU watchdog when booting over UART to ensure that watchdog does not reboot the board before UART transfer finishes. But if UART transfer fails for some reason, or if U-Boot binary crashes, then board hangs forever as there is no watchdog running which could reset it. To fix this issue, enable A385 watchdog with very high timeout before disabling MCU watchdog to ensure that even slow transfer can finish successfully before watchdog timer expires and also to ensure that if board hangs for some reason, watchdog will reset it. Omnia's MCU watchdog has fixed 120 seconds timer and it cannot be changed (without updating MCU firmware). A385 watchdog by default uses 25 MHz input clock and so the largest timeout value (2^32-1) can be just 171 seconds. But A385 watchdog can be switched to use NBCLK (L2) as input clock (on Turris Omnia it is 800 MHz clock) and in this case final watchdog clock frequency is calculated as: freq = NBCLK / 2 / (2 ^ R) So A385 watchdog on Turris Omnia can be configured to at most 1374 seconds (about 22 minutes). We set it to 10 minutes, which should be enough even for bigger U-Boot binaries or slower UART transfers. Both U-Boot and Linux kernel, when initializing A385 watchdog, switch watchdog timer to 25 MHz input clock, so usage of NBCLK input clock in U-Boot SPL does not cause any issues. Fixes: aeb0ca64dbb5 ("arm: mvebu: turris_omnia: disable MCU watchdog in SPL when booting over UART") Signed-off-by: Pali Rohár <pali(a)kernel.org> Signed-off-by: Marek Behún <marek.behun(a)nic.cz> --- board/CZ.NIC/turris_omnia/turris_omnia.c | 65 +++++++++++++++++++++++- 1 file changed, 63 insertions(+), 2 deletions(-) diff --git a/board/CZ.NIC/turris_omnia/turris_omnia.c b/board/CZ.NIC/turris_omnia/turris_omnia.c index 36c596efc5..ae24d14b76 100644 --- a/board/CZ.NIC/turris_omnia/turris_omnia.c +++ b/board/CZ.NIC/turris_omnia/turris_omnia.c @@ -43,6 +43,23 @@ DECLARE_GLOBAL_DATA_PTR; #define OMNIA_I2C_EEPROM_CHIP_LEN 2 #define OMNIA_I2C_EEPROM_MAGIC 0x0341a034 +#define SYS_RSTOUT_MASK MVEBU_REGISTER(0x18260) +#define SYS_RSTOUT_MASK_WD BIT(10) + +#define A385_WDT_GLOBAL_CTRL MVEBU_REGISTER(0x20300) +#define A385_WDT_GLOBAL_RATIO_MASK GENMASK(18, 16) +#define A385_WDT_GLOBAL_RATIO_SHIFT 16 +#define A385_WDT_GLOBAL_25MHZ BIT(10) +#define A385_WDT_GLOBAL_ENABLE BIT(8) + +#define A385_WDT_GLOBAL_STATUS MVEBU_REGISTER(0x20304) +#define A385_WDT_GLOBAL_EXPIRED BIT(31) + +#define A385_WDT_DURATION MVEBU_REGISTER(0x20334) + +#define A385_WD_RSTOUT_UNMASK MVEBU_REGISTER(0x20704) +#define A385_WD_RSTOUT_UNMASK_GLOBAL BIT(8) + enum mcu_commands { CMD_GET_STATUS_WORD = 0x01, CMD_GET_RESET = 0x09, @@ -141,6 +158,47 @@ static int omnia_mcu_write(u8 cmd, const void *buf, int len) return dm_i2c_write(chip, cmd, buf, len); } +static void enable_a385_watchdog(unsigned int timeout_minutes) +{ + struct sar_freq_modes sar_freq; + u32 watchdog_freq; + + printf("Enabling A385 watchdog with %u minutes timeout...\n", + timeout_minutes); + + /* + * Use NBCLK clock (a.k.a. L2 clock) as watchdog input clock with + * its maximal ratio 7 instead of default fixed 25 MHz clock. + * It allows to set watchdog duration up to the 22 minutes. + */ + clrsetbits_32(A385_WDT_GLOBAL_CTRL, + A385_WDT_GLOBAL_25MHZ | A385_WDT_GLOBAL_RATIO_MASK, + 7 << A385_WDT_GLOBAL_RATIO_SHIFT); + + /* + * Calculate watchdog clock frequency. It is defined by formula: + * freq = NBCLK / 2 / (2 ^ ratio) + * We set ratio to the maximal possible value 7. + */ + get_sar_freq(&sar_freq); + watchdog_freq = sar_freq.nb_clk * 1000000 / 2 / (1 << 7); + + /* Set watchdog duration */ + writel(timeout_minutes * 60 * watchdog_freq, A385_WDT_DURATION); + + /* Clear the watchdog expiration bit */ + clrbits_32(A385_WDT_GLOBAL_STATUS, A385_WDT_GLOBAL_EXPIRED); + + /* Enable watchdog timer */ + setbits_32(A385_WDT_GLOBAL_CTRL, A385_WDT_GLOBAL_ENABLE); + + /* Enable reset on watchdog */ + setbits_32(A385_WD_RSTOUT_UNMASK, A385_WD_RSTOUT_UNMASK_GLOBAL); + + /* Unmask reset for watchdog */ + clrbits_32(SYS_RSTOUT_MASK, SYS_RSTOUT_MASK_WD); +} + static bool disable_mcu_watchdog(void) { int ret; @@ -423,10 +481,13 @@ void spl_board_init(void) { /* * If booting from UART, disable MCU watchdog in SPL, since uploading - * U-Boot proper can take too much time and trigger it. + * U-Boot proper can take too much time and trigger it. Instead enable + * A385 watchdog with very high timeout (10 minutes) to prevent hangup. */ - if (get_boot_device() == BOOT_DEVICE_UART) + if (get_boot_device() == BOOT_DEVICE_UART) { + enable_a385_watchdog(10); disable_mcu_watchdog(); + } } int board_init(void) -- 2.32.0

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[PATCH 1/2] ram: stm32mp1: compute DDR size from DDRCTL registers
by Patrick Delaunay 30 Nov '21

30 Nov '21

Compute the DDR size from DDR controller register (mstr and addrmap) in U-Boot proper as the DDR information are useful only for SPL but not for U-Boot proper, for example with TFABOOT. This patch simplify U-Boot DT when several DDR size are supported and support of next SOC in STM32MP family. Signed-off-by: Patrick Delaunay <patrick.delaunay(a)st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay(a)foss.st.com> --- drivers/ram/stm32mp1/stm32mp1_ddr_regs.h | 1 + drivers/ram/stm32mp1/stm32mp1_ram.c | 192 ++++++++++++++++++++++- 2 files changed, 190 insertions(+), 3 deletions(-) diff --git a/drivers/ram/stm32mp1/stm32mp1_ddr_regs.h b/drivers/ram/stm32mp1/stm32mp1_ddr_regs.h index 3c8885a965..d6b9a76a76 100644 --- a/drivers/ram/stm32mp1/stm32mp1_ddr_regs.h +++ b/drivers/ram/stm32mp1/stm32mp1_ddr_regs.h @@ -238,6 +238,7 @@ struct stm32mp1_ddrphy { #define DDRCTRL_MSTR_LPDDR2 BIT(2) #define DDRCTRL_MSTR_LPDDR3 BIT(3) #define DDRCTRL_MSTR_DATA_BUS_WIDTH_MASK GENMASK(13, 12) +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_SHIFT 12 #define DDRCTRL_MSTR_DATA_BUS_WIDTH_FULL (0 << 12) #define DDRCTRL_MSTR_DATA_BUS_WIDTH_HALF (1 << 12) #define DDRCTRL_MSTR_DATA_BUS_WIDTH_QUARTER (2 << 12) diff --git a/drivers/ram/stm32mp1/stm32mp1_ram.c b/drivers/ram/stm32mp1/stm32mp1_ram.c index 98fa1f4f11..c9335e59df 100644 --- a/drivers/ram/stm32mp1/stm32mp1_ram.c +++ b/drivers/ram/stm32mp1/stm32mp1_ram.c @@ -16,6 +16,12 @@ #include <asm/io.h> #include <dm/device_compat.h> #include "stm32mp1_ddr.h" +#include "stm32mp1_ddr_regs.h" + +/* DDR subsystem configuration */ +struct stm32mp1_ddr_cfg { + u8 nb_bytes; /* MEMC_DRAM_DATA_WIDTH */ +}; static const char *const clkname[] = { "ddrc1", @@ -183,6 +189,182 @@ static __maybe_unused int stm32mp1_ddr_setup(struct udevice *dev) return 0; } +static u8 get_data_bus_width(struct stm32mp1_ddrctl *ctl) +{ + u32 reg = readl(&ctl->mstr) & DDRCTRL_MSTR_DATA_BUS_WIDTH_MASK; + u8 data_bus_width = reg >> DDRCTRL_MSTR_DATA_BUS_WIDTH_SHIFT; + + return data_bus_width; +} + +static u8 get_nb_bank(struct stm32mp1_ddrctl *ctl) +{ + /* Count bank address bits */ + u8 bits = 0; + u32 reg, val; + + reg = readl(&ctl->addrmap1); + /* addrmap1.addrmap_bank_b1 */ + val = (reg & GENMASK(5, 0)) >> 0; + if (val <= 31) + bits++; + /* addrmap1.addrmap_bank_b2 */ + val = (reg & GENMASK(13, 8)) >> 8; + if (val <= 31) + bits++; + /* addrmap1.addrmap_bank_b3 */ + val = (reg & GENMASK(21, 16)) >> 16; + if (val <= 31) + bits++; + + return bits; +} + +static u8 get_nb_col(struct stm32mp1_ddrctl *ctl, u8 data_bus_width) +{ + u8 bits; + u32 reg, val; + + /* Count column address bits, start at 2 for b0 and b1 (fixed) */ + bits = 2; + + reg = readl(&ctl->addrmap2); + /* addrmap2.addrmap_col_b2 */ + val = (reg & GENMASK(3, 0)) >> 0; + if (val <= 7) + bits++; + /* addrmap2.addrmap_col_b3 */ + val = (reg & GENMASK(11, 8)) >> 8; + if (val <= 7) + bits++; + /* addrmap2.addrmap_col_b4 */ + val = (reg & GENMASK(19, 16)) >> 16; + if (val <= 7) + bits++; + /* addrmap2.addrmap_col_b5 */ + val = (reg & GENMASK(27, 24)) >> 24; + if (val <= 7) + bits++; + + reg = readl(&ctl->addrmap3); + /* addrmap3.addrmap_col_b6 */ + val = (reg & GENMASK(3, 0)) >> 0; + if (val <= 7) + bits++; + /* addrmap3.addrmap_col_b7 */ + val = (reg & GENMASK(11, 8)) >> 8; + if (val <= 7) + bits++; + /* addrmap3.addrmap_col_b8 */ + val = (reg & GENMASK(19, 16)) >> 16; + if (val <= 7) + bits++; + /* addrmap3.addrmap_col_b9 */ + val = (reg & GENMASK(27, 24)) >> 24; + if (val <= 7) + bits++; + + reg = readl(&ctl->addrmap4); + /* addrmap4.addrmap_col_b10 */ + val = (reg & GENMASK(3, 0)) >> 0; + if (val <= 7) + bits++; + /* addrmap4.addrmap_col_b11 */ + val = (reg & GENMASK(11, 8)) >> 8; + if (val <= 7) + bits++; + + /* column bits shift up: + * 1 when half the data bus is used (data_bus_width = 1) + * 2 when a quarter the data bus is used (data_bus_width = 2) + * nothing to do for full data bus (data_bus_width = 0) + */ + bits += data_bus_width; + + return bits; +} + +static u8 get_nb_row(struct stm32mp1_ddrctl *ctl) +{ + /* Count row address bits */ + u8 bits = 0; + u32 reg, val; + + reg = readl(&ctl->addrmap5); + /* addrmap5.addrmap_row_b0 */ + val = (reg & GENMASK(3, 0)) >> 0; + if (val <= 11) + bits++; + /* addrmap5.addrmap_row_b1 */ + val = (reg & GENMASK(11, 8)) >> 8; + if (val <= 11) + bits++; + /* addrmap5.addrmap_row_b2_10 */ + val = (reg & GENMASK(19, 16)) >> 16; + if (val <= 11) + bits += 9; + else + printf("warning: addrmap5.addrmap_row_b2_10 not supported\n"); + /* addrmap5.addrmap_row_b11 */ + val = (reg & GENMASK(27, 24)) >> 24; + if (val <= 11) + bits++; + + reg = readl(&ctl->addrmap6); + /* addrmap6.addrmap_row_b12 */ + val = (reg & GENMASK(3, 0)) >> 0; + if (val <= 7) + bits++; + /* addrmap6.addrmap_row_b13 */ + val = (reg & GENMASK(11, 8)) >> 8; + if (val <= 7) + bits++; + /* addrmap6.addrmap_row_b14 */ + val = (reg & GENMASK(19, 16)) >> 16; + if (val <= 7) + bits++; + /* addrmap6.addrmap_row_b15 */ + val = (reg & GENMASK(27, 24)) >> 24; + if (val <= 7) + bits++; + + return bits; +} + +/* + * stm32mp1_ddr_size + * + * Get the current DRAM size from the DDR CTL registers + * + * @return: DRAM size + */ +u32 stm32mp1_ddr_size(struct udevice *dev) +{ + u8 nb_bit; + u32 ddr_size; + u8 data_bus_width; + struct ddr_info *priv = dev_get_priv(dev); + struct stm32mp1_ddrctl *ctl = priv->ctl; + struct stm32mp1_ddr_cfg *cfg = (struct stm32mp1_ddr_cfg *)dev_get_driver_data(dev); + const u8 nb_bytes = cfg->nb_bytes; + + data_bus_width = get_data_bus_width(ctl); + nb_bit = get_nb_bank(ctl) + get_nb_col(ctl, data_bus_width) + + get_nb_row(ctl); + if (nb_bit > 32) { + nb_bit = 32; + debug("invalid DDR configuration: %d bits\n", nb_bit); + } + + ddr_size = (nb_bytes >> data_bus_width) << nb_bit; + if (ddr_size > STM32_DDR_SIZE) { + ddr_size = STM32_DDR_SIZE; + debug("invalid DDR configuration: size = %x\n", ddr_size); + } + + return ddr_size; +} + static int stm32mp1_ddr_probe(struct udevice *dev) { struct ddr_info *priv = dev_get_priv(dev); @@ -209,8 +391,8 @@ static int stm32mp1_ddr_probe(struct udevice *dev) return log_ret(ret); } - ofnode node = stm32mp1_ddr_get_ofnode(dev); - priv->info.size = ofnode_read_u32_default(node, "st,mem-size", 0); + priv->info.size = stm32mp1_ddr_size(dev); + return 0; } @@ -227,8 +409,12 @@ static struct ram_ops stm32mp1_ddr_ops = { .get_info = stm32mp1_ddr_get_info, }; +static const struct stm32mp1_ddr_cfg stm32mp15x_ddr_cfg = { + .nb_bytes = 4, +}; + static const struct udevice_id stm32mp1_ddr_ids[] = { - { .compatible = "st,stm32mp1-ddr" }, + { .compatible = "st,stm32mp1-ddr", .data = (ulong)&stm32mp15x_ddr_cfg}, { } }; -- 2.25.1

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