October 2021 - U-Boot

[PATCH v6 1/2] arm: dts: imx8mq: Add Kontron pitx-imx8m
by Heiko Thiery 24 Oct '21

24 Oct '21

This adds the device tree for the Kontron pitx-imx8m Board. It is a copy of the device tree from the linux kernel sources. Signed-off-by: Heiko Thiery <heiko.thiery(a)gmail.com> --- v6: - no change v5: - no change v4: - no change v3: - no change v2: - no change arch/arm/dts/Makefile | 3 +- arch/arm/dts/imx8mq-kontron-pitx-imx8m.dts | 613 +++++++++++++++++++++ 2 files changed, 615 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/imx8mq-kontron-pitx-imx8m.dts diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 9438bf735a..9228b1d6c1 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -887,7 +887,8 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mq-phanbell.dtb \ imx8mp-evk.dtb \ imx8mp-phyboard-pollux-rdk.dtb \ - imx8mq-pico-pi.dtb + imx8mq-pico-pi.dtb \ + imx8mq-kontron-pitx-imx8m.dtb dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb \ imxrt1020-evk.dtb diff --git a/arch/arm/dts/imx8mq-kontron-pitx-imx8m.dts b/arch/arm/dts/imx8mq-kontron-pitx-imx8m.dts new file mode 100644 index 0000000000..f593e4ff62 --- /dev/null +++ b/arch/arm/dts/imx8mq-kontron-pitx-imx8m.dts @@ -0,0 +1,613 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree File for the Kontron pitx-imx8m board. + * + * Copyright (C) 2021 Heiko Thiery <heiko.thiery(a)gmail.com> + */ + +/dts-v1/; + +#include "imx8mq.dtsi" +#include <dt-bindings/net/ti-dp83867.h> + +/ { + model = "Kontron pITX-imx8m"; + compatible = "kontron,pitx-imx8m", "fsl,imx8mq"; + + aliases { + i2c0 = &i2c1; + i2c1 = &i2c2; + i2c2 = &i2c3; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + spi0 = &qspi0; + spi1 = &ecspi2; + }; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + pcie0_refclk: pcie0-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + pcie1_refclk: pcie1-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + reg_usdhc2_vmmc: regulator-usdhc2-vmmc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2>; + regulator-name = "V_3V3_SD"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <20000>; + enable-active-high; + }; +}; + +&ecspi2 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + status = "okay"; + + tpm@0 { + compatible = "infineon,slb9670"; + reg = <0>; + spi-max-frequency = <43000000>; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + phy-handle = <&ethphy0>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; + ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; + reset-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; + reset-assert-us = <10>; + reset-deassert-us = <280>; + }; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic@8 { + compatible = "fsl,pfuze100"; + fsl,pfuze-support-disable-sw; + reg = <0x8>; + + regulators { + sw1a_reg: sw1ab { + regulator-name = "V_0V9_GPU"; + regulator-min-microvolt = <825000>; + regulator-max-microvolt = <1100000>; + }; + + sw1c_reg: sw1c { + regulator-name = "V_0V9_VPU"; + regulator-min-microvolt = <825000>; + regulator-max-microvolt = <1100000>; + }; + + sw2_reg: sw2 { + regulator-name = "V_1V1_NVCC_DRAM"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + sw3a_reg: sw3ab { + regulator-name = "V_1V0_DRAM"; + regulator-min-microvolt = <825000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-name = "V_1V8_S0"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-name = "NC"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-name = "V_0V9_SNVS"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-name = "V_0V55_VREF_DDR"; + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-name = "V_1V5_CSI"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen2_reg: vgen2 { + regulator-name = "V_0V9_PHY"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <975000>; + regulator-always-on; + }; + + vgen3_reg: vgen3 { + regulator-name = "V_1V8_PHY"; + regulator-min-microvolt = <1675000>; + regulator-max-microvolt = <1975000>; + regulator-always-on; + }; + + vgen4_reg: vgen4 { + regulator-name = "V_1V8_VDDA"; + regulator-min-microvolt = <1625000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-name = "V_3V3_PHY"; + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3625000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-name = "V_2V8_CAM"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + + fan-controller@1b { + compatible = "maxim,max6650"; + reg = <0x1b>; + maxim,fan-microvolt = <5000000>; + }; + + rtc@32 { + compatible = "microcrystal,rv8803"; + reg = <0x32>; + }; + + sensor@4b { + compatible = "national,lm75b"; + reg = <0x4b>; + }; + + eeprom@51 { + compatible = "atmel,24c32"; + reg = <0x51>; + pagesize = <32>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +/* M.2 B-key slot */ +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + reset-gpio = <&gpio1 9 GPIO_ACTIVE_LOW>; + clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>, + <&clk IMX8MQ_CLK_PCIE1_AUX>, + <&clk IMX8MQ_CLK_PCIE1_PHY>, + <&pcie0_refclk>; + clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + status = "okay"; +}; + +/* Intel Ethernet Controller I210/I211 */ +&pcie1 { + clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, + <&clk IMX8MQ_CLK_PCIE2_AUX>, + <&clk IMX8MQ_CLK_PCIE2_PHY>, + <&pcie1_refclk>; + clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + fsl,max-link-speed = <1>; + status = "okay"; +}; + +&pgc_gpu { + power-supply = <&sw1a_reg>; +}; + +&pgc_vpu { + power-supply = <&sw1c_reg>; +}; + +&qspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + m25p,fast-read; + spi-max-frequency = <50000000>; + }; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clk IMX8MQ_CLK_UART1>; + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + assigned-clocks = <&clk IMX8MQ_CLK_UART2>; + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + fsl,uart-has-rtscts; + assigned-clocks = <&clk IMX8MQ_CLK_UART3>; + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>; + status = "okay"; +}; + +&usb3_phy0 { + status = "okay"; +}; + +&usb3_phy1 { + status = "okay"; +}; + +&usb_dwc3_0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0>; + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + maximum-speed = "high-speed"; + status = "okay"; +}; + +&usb_dwc3_1 { + dr_mode = "host"; + status = "okay"; +}; + +&usdhc1 { + assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>; + assigned-clock-rates = <400000000>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + vqmmc-supply = <&sw4_reg>; + bus-width = <8>; + non-removable; + no-sd; + no-sdio; + status = "okay"; +}; + +&usdhc2 { + assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>; + assigned-clock-rates = <200000000>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; + vmmc-supply = <&reg_usdhc2_vmmc>; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX8MQ_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x19 /* TPM Reset */ + MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x19 /* USB2 Hub Reset */ + >; + }; + + pinctrl_gpio: gpiogrp { + fsl,pins = < + MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x19 /* GPIO0 */ + MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x19 /* GPIO1 */ + MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17 0x19 /* GPIO2 */ + MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18 0x19 /* GPIO3 */ + MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 /* GPIO4 */ + MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x19 /* GPIO5 */ + MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x19 /* GPIO6 */ + MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x19 /* GPIO7 */ + >; + }; + + pinctrl_pcie0: pcie0grp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x16 /* PCIE_PERST */ + MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29 0x16 /* W_DISABLE */ + >; + }; + + pinctrl_reg_usdhc2: regusdhc2gpiogrp { + fsl,pins = < + MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 + MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x16 + MX8MQ_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x16 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f + MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f + MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000007f + MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000007f + >; + }; + + pinctrl_qspi: qspigrp { + fsl,pins = < + MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82 + MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 + MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 + MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 + MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 + MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX8MQ_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x19 + MX8MQ_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x19 + MX8MQ_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x19 + >; + }; + + pinctrl_ecspi2_cs: ecspi2csgrp { + fsl,pins = < + MX8MQ_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x19 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49 + MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49 + MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49 + MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49 + MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x49 + MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x49 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100grp { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200grp { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 + MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x19 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100grp { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200grp { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xdf + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xdf + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xdf + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xdf + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xdf + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usb0: usb0grp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x19 + MX8MQ_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x19 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; +}; -- 2.30.2

3 11

[PATCH v2 01/16] sandbox: net: Ensure host name is always a valid string
by Simon Glass 24 Oct '21

24 Oct '21

At present if ifname is exactly IFNAMSIZ characters then it will result in an unterminated string. Fix this by using strlcpy() instead. Signed-off-by: Simon Glass <sjg(a)chromium.org> Reported-by: Coverity (CID: 316358) --- Changes in v2: - Put 'Reported-by:' after the sign-off drivers/net/sandbox-raw.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/sandbox-raw.c b/drivers/net/sandbox-raw.c index ce66ff781ff..99eb7a3bbff 100644 --- a/drivers/net/sandbox-raw.c +++ b/drivers/net/sandbox-raw.c @@ -161,7 +161,7 @@ static int sb_eth_raw_of_to_plat(struct udevice *dev) ifname = dev_read_string(dev, "host-raw-interface"); if (ifname) { - strncpy(priv->host_ifname, ifname, IFNAMSIZ); + strlcpy(priv->host_ifname, ifname, IFNAMSIZ); printf(": Using %s from DT\n", priv->host_ifname); } if (dev_read_u32(dev, "host-raw-interface-idx", -- 2.31.1.751.gd2f1c929bd-goog

5 35

[PATCH v6 0/7] env: Allow environment in text files
by Simon Glass 24 Oct '21

24 Oct '21

One barrier to completing the 7-year-long Kconfig migration is that the default environment is implemented using ad-hoc CONFIG options. At present U-Boot environment variables, and thus scripts, are defined by CONFIG_EXTRA_ENV_SETTINGS. It is not really feasible to move the environment to Kconfig as it is hundreds of lines of text in some cases. Even considering the current situation, it is painful to add large amounts of text to the config-header file and dealing with quoting and newlines is harder than it should be. It would be better if we could just type the script into a text file and have it included by U-Boot. Add a feature that brings in a .env file associated with the board config, if present. To use it, create a file in a board/<vendor>/env directory called <board>.env (or common.env if you want the same environment for all boards). The environment variables should be of the form "var=value". Values can extend to multiple lines. This series converts the existing environment documentation to rST and updates it to explain how to use this. Note: this series was originally sent eight years ago: https://patchwork.ozlabs.org/project/uboot/patch/1382763695-2849-4-git-send… It has been updated to work with Kconfig, etc. Some review comments in that patch were infeasible so I have not addressed them. I would like this series to be considered independently, on its merits. Rather than deal with the complexity of rewriting the distro-boot script, this is disabled for sandbox. The forthcoming bootmethod approach should provide the same functionality without needing the complex scripting in the environment. Migration needs more thought, although it can be done later. It may be possible to do migrate automatically, using buildman to extract the built-in environmnent from the ELF file. This would produce a pretty ugly conversion though, since it would drop all the intermediate variables used to create the environment. Better would be to parse the config.h file, figure out the components of CONFIG_EXTRA_ENV_SETTINGS then output these as separate pieces in the file. It is not clear how easy that would be, nor whether the result would be very pretty. Also the __stringify() macro needs to be handled somehow. This series is available at u-boot-dm/env-working Comments welcome. Changes in v6: - Move all updates to a separate patch - Combine the two env2string.awk patches into one - Move all updates to a separate patch - More updates and improvements - Add new patch to tidy up use of autostart env var Changes in v5: - Minor updates as suggested by Wolfgang - Explain how to include the common.env file - Explain why variables starting with _ , and / are not supported - Expand the definition of how to declare an environment variable - Explain what happens to empty variables - Update maintainer - Move use of += to this patch - Explain that environment variables may not end in + - Minor updates as suggested by Wolfgang Changes in v4: - Add new patch to move environment documentation to rST - Move this from being part of configuring U-Boot to part of building it - Don't put the environment in autoconf.mk as it is not needed - Add documentation in rST format instead of README - Drop mention of import/export - Update awk script to ignore blank lines, as generated by clang - Add documentation in rST format instead of README - Add new patch to move environment documentation to rST Changes in v3: - Adjust Makefile to generate the .inc and .h files in separate fules - Add more detail in the README about the format of .env files - Improve the comment about " in the awk script - Correctly terminate environment files with \n - Define __UBOOT_CONFIG__ when collecting environment files - Add new patch to use a text-based environment for sandbox Changes in v2: - Move .env file from include/configs to board/ - Use awk script to process environment since it is much easier on the brain - Add information and updated example script to README - Add dependency rule so that the environment is rebuilt when it changes - Add separate patch to enable C preprocessor for environment files - Enable var+=value form to simplify composing variables in multiple steps Simon Glass (7): binman: Allow timeout to occur in the image or its section sandbox: Drop distro_boot doc: Move environment documentation to rST env: Allow U-Boot scripts to be placed in a .env file sandbox: Use a text-based environment doc: Improve environment documentation bootm: Tidy up use of autostart env var MAINTAINERS | 7 + Makefile | 39 ++- README | 328 ------------------------ board/sandbox/env/sandbox.env | 25 ++ cmd/bootm.c | 4 +- cmd/elf.c | 3 +- common/bootm_os.c | 5 +- config.mk | 2 + doc/usage/environment.rst | 453 ++++++++++++++++++++++++++++++++++ doc/usage/index.rst | 1 + env/common.c | 7 + env/embedded.c | 1 + include/configs/sandbox.h | 40 --- include/env.h | 7 + include/env_default.h | 8 + scripts/env2string.awk | 56 +++++ tools/binman/ftest.py | 3 +- 17 files changed, 609 insertions(+), 380 deletions(-) create mode 100644 board/sandbox/env/sandbox.env create mode 100644 doc/usage/environment.rst create mode 100644 scripts/env2string.awk -- 2.33.0.1079.g6e70778dc9-goog

3 23

[PATCH v2 0/9] usb: dwc3: add Layerscape SoC support
by Michael Walle 24 Oct '21

24 Oct '21

Primarily, this will add support for peripheral mode on Layerscape SoCs. For this to work, we have to backport two fixes from linux and fix the fixup code for the DWC3 controller (which enables snooping because the SoC has wrong startup defaults). As a first user of the driver, enable it on the Kontron SL28 board, where both host and peripheral mode was tested. OTG mode is not supported. For this to work, one would need to read the hardware status of the OTG pin in the bind() op. But it isn't allowed to access the hardware in the bind() op (if I understand Simon correctly). changes since v1: - added test case for the new ofnode_for_each_compatible_node() Michael Walle (9): dm: core: add ofnode_for_each_compatible_node() test: dm: add test for ofnode_for_each_compatible_node() armv8: fsl-layerscape: rework the dwc3 snooping enable code usb: common: silence dubious errors usb: dwc3: Add frame length adjustment quirk usb: dwc3: Enable undefined length INCR burst type usb: dwc3: add layerscape support board: sl28: switch to dwc3 driver board: sl28: enable USB periheral support and gadgets arch/arm/cpu/armv8/fsl-layerscape/soc.c | 28 ++- configs/kontron_sl28_defconfig | 9 +- drivers/usb/common/common.c | 4 +- drivers/usb/dwc3/Kconfig | 10 ++ drivers/usb/dwc3/Makefile | 1 + drivers/usb/dwc3/core.c | 95 ++++++++++ drivers/usb/dwc3/core.h | 22 +++ drivers/usb/dwc3/dwc3-layerscape.c | 222 ++++++++++++++++++++++++ include/dm/ofnode.h | 24 +++ test/dm/ofnode.c | 18 ++ 10 files changed, 415 insertions(+), 18 deletions(-) create mode 100644 drivers/usb/dwc3/dwc3-layerscape.c -- 2.30.2

2 12

[PATCH 1/2] cmd: kaslrseed: add command to generate value from hwrng
by Chris Morgan 24 Oct '21

24 Oct '21

From: Chris Morgan <macromorgan(a)hotmail.com> Allow the kaslr-seed value in the chosen node to be set from a hardware rng source. Tested on a Rockchip PX30 (Odroid Go Advance), you must have loaded the devicetree first and prepared it for editing. On my device the workflow goes as follows: setenv dtb_loadaddr "0x01f00000" load mmc 0:1 ${dtb_loadaddr} rk3326-odroid-go2.dtb fdt addr ${dtb_loadaddr} fdt resize kaslrseed and the output can be seen here: fdt print /chosen chosen { kaslr-seed = <0x6f61df74 0x6f7b996c>; stdout-path = "serial2:115200n8"; }; Signed-off-by: Chris Morgan <macromorgan(a)hotmail.com> --- cmd/Kconfig | 7 +++++ cmd/Makefile | 1 + cmd/kaslrseed.c | 81 +++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 89 insertions(+) create mode 100644 cmd/kaslrseed.c diff --git a/cmd/Kconfig b/cmd/Kconfig index ffef3cc76c..e62adff939 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -1790,6 +1790,13 @@ config CMD_RNG help Print bytes from the hardware random number generator. +config CMD_KASLRSEED + bool "kaslrseed" + depends on DM_RNG + help + Set the kaslr-seed in the chosen node with entropy provided by a + hardware random number generator. + config CMD_SLEEP bool "sleep" default y diff --git a/cmd/Makefile b/cmd/Makefile index ed3669411e..34cbda72f5 100644 --- a/cmd/Makefile +++ b/cmd/Makefile @@ -131,6 +131,7 @@ obj-$(CONFIG_CMD_REGINFO) += reginfo.o obj-$(CONFIG_CMD_REISER) += reiser.o obj-$(CONFIG_CMD_REMOTEPROC) += remoteproc.o obj-$(CONFIG_CMD_RNG) += rng.o +obj-$(CONFIG_CMD_KASLRSEED) += kaslrseed.o obj-$(CONFIG_CMD_ROCKUSB) += rockusb.o obj-$(CONFIG_CMD_RTC) += rtc.o obj-$(CONFIG_SANDBOX) += host.o diff --git a/cmd/kaslrseed.c b/cmd/kaslrseed.c new file mode 100644 index 0000000000..27c2648c91 --- /dev/null +++ b/cmd/kaslrseed.c @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * The 'kaslrseed' command takes bytes from the hardware random number + * generator and uses them to set the kaslr-seed value in the chosen node. + * + * Copyright (c) 2021, Chris Morgan <macromorgan(a)hotmail.com> + */ + +#include <common.h> +#include <command.h> +#include <dm.h> +#include <hexdump.h> +#include <malloc.h> +#include <rng.h> +#include <fdt_support.h> + +static int do_kaslr_seed(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +{ + size_t n = 0x8; + struct udevice *dev; + u64 *buf; + int nodeoffset; + int ret = CMD_RET_SUCCESS; + + if (uclass_get_device(UCLASS_RNG, 0, &dev) || !dev) { + printf("No RNG device\n"); + return CMD_RET_FAILURE; + } + + buf = malloc(n); + if (!buf) { + printf("Out of memory\n"); + return CMD_RET_FAILURE; + } + + if (dm_rng_read(dev, buf, n)) { + printf("Reading RNG failed\n"); + return CMD_RET_FAILURE; + } + + if (!working_fdt) { + printf("No FDT memory address configured. Please configure\n" + "the FDT address via \"fdt addr <address>\" command.\n" + "Aborting!\n"); + return CMD_RET_FAILURE; + } + + ret = fdt_check_header(working_fdt); + if (ret < 0) { + printf("fdt_chosen: %s\n", fdt_strerror(ret)); + return CMD_RET_FAILURE; + } + + nodeoffset = fdt_find_or_add_subnode(working_fdt, 0, "chosen"); + if (nodeoffset < 0) { + printf("Reading chosen node failed\n"); + return CMD_RET_FAILURE; + } + + ret = fdt_setprop(working_fdt, nodeoffset, "kaslr-seed", buf, sizeof(buf)); + if (ret < 0) { + printf("Unable to set kaslr-seed on chosen node: %s\n", fdt_strerror(ret)); + return CMD_RET_FAILURE; + } + + free(buf); + + return ret; +} + +#ifdef CONFIG_SYS_LONGHELP +static char kaslrseed_help_text[] = + "[n]\n" + " - append random bytes to chosen kaslr-seed node\n"; +#endif + +U_BOOT_CMD( + kaslrseed, 1, 0, do_kaslr_seed, + "feed bytes from the hardware random number generator to the kaslr-seed", + kaslrseed_help_text +); -- 2.25.1

4 3

[PATCH 1/1] Revert "arm64: Layerscape: Survive LPI one-way reset workaround"
by Tom Rini 24 Oct '21

24 Oct '21

Ad-hoc bindings that are not part of the upstream device tree / bindings are not allowed in-tree. Only bindings that are in-progress with upstream and then re-synced once agreed upon are. This reverts commit af288cb291da3abef6be0875527729296f7de7a0. Cc: Hou Zhiqiang <Zhiqiang.Hou(a)nxp.com> Cc: Priyanka Jain <priyanka.jain(a)nxp.com> Reported-by: Michael Walle <michael(a)walle.cc> Signed-off-by: Tom Rini <trini(a)konsulko.com> --- arch/arm/cpu/armv8/fsl-layerscape/soc.c | 17 +---------------- arch/arm/dts/fsl-ls1028a.dtsi | 6 ------ arch/arm/dts/fsl-ls1088a.dtsi | 6 ------ arch/arm/dts/fsl-ls2080a.dtsi | 6 ------ arch/arm/dts/fsl-lx2160a.dtsi | 6 ------ 5 files changed, 1 insertion(+), 40 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 42a096854629..166662a64baf 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -43,22 +43,7 @@ DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_GIC_V3_ITS int ls_gic_rd_tables_init(void *blob) { - struct fdt_memory lpi_base; - fdt_addr_t addr; - fdt_size_t size; - int offset, ret; - - offset = fdt_path_offset(gd->fdt_blob, "/syscon@0x80000000"); - addr = fdtdec_get_addr_size_auto_noparent(gd->fdt_blob, offset, "reg", - 0, &size, false); - - lpi_base.start = addr; - lpi_base.end = addr + size - 1; - ret = fdtdec_add_reserved_memory(blob, "lpi_rd_table", &lpi_base, NULL, false); - if (ret) { - debug("%s: failed to add reserved memory\n", __func__); - return ret; - } + int ret; ret = gic_lpi_tables_init(); if (ret) diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi index 50f9b527cde1..53b052ed3271 100644 --- a/arch/arm/dts/fsl-ls1028a.dtsi +++ b/arch/arm/dts/fsl-ls1028a.dtsi @@ -44,12 +44,6 @@ IRQ_TYPE_LEVEL_LOW)>; }; - gic_lpi_base: syscon@0x80000000 { - compatible = "gic-lpi-base"; - reg = <0x0 0x80000000 0x0 0x100000>; - max-gic-redistributors = <2>; - }; - timer { compatible = "arm,armv8-timer"; interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi index 64caa600ad77..3a5a50fb8313 100644 --- a/arch/arm/dts/fsl-ls1088a.dtsi +++ b/arch/arm/dts/fsl-ls1088a.dtsi @@ -27,12 +27,6 @@ interrupts = <1 9 0x4>; }; - gic_lpi_base: syscon@0x80000000 { - compatible = "gic-lpi-base"; - reg = <0x0 0x80000000 0x0 0x100000>; - max-gic-redistributors = <8>; - }; - timer { compatible = "arm,armv8-timer"; interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */ diff --git a/arch/arm/dts/fsl-ls2080a.dtsi b/arch/arm/dts/fsl-ls2080a.dtsi index 7374d580e07e..278daeeb6eea 100644 --- a/arch/arm/dts/fsl-ls2080a.dtsi +++ b/arch/arm/dts/fsl-ls2080a.dtsi @@ -27,12 +27,6 @@ interrupts = <1 9 0x4>; }; - gic_lpi_base: syscon@0x80000000 { - compatible = "gic-lpi-base"; - reg = <0x0 0x80000000 0x0 0x100000>; - max-gic-redistributors = <8>; - }; - timer { compatible = "arm,armv8-timer"; interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */ diff --git a/arch/arm/dts/fsl-lx2160a.dtsi b/arch/arm/dts/fsl-lx2160a.dtsi index a6f0e9bc56be..3b5f0d119e76 100644 --- a/arch/arm/dts/fsl-lx2160a.dtsi +++ b/arch/arm/dts/fsl-lx2160a.dtsi @@ -43,12 +43,6 @@ interrupts = <1 9 0x4>; }; - gic_lpi_base: syscon@0x80000000 { - compatible = "gic-lpi-base"; - reg = <0x0 0x80000000 0x0 0x200000>; - max-gic-redistributors = <16>; - }; - timer { compatible = "arm,armv8-timer"; interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */ -- 2.17.1

5 5

[PATCH] imx8mm-cl-iot-gate-optee: align config with Kconfig
by Stefano Babic 24 Oct '21

24 Oct '21

Due to missing configs, CI goes in deadlock until an OOM is tracked. Add CONFIG_SYS_LOAD_ADDR and replace CONFIG_SYS_EXTRA_OPTIONS with CONFIG_IMX_CONFIG. Signed-off-by: Stefano Babic <sbabic(a)denx.de> CC: Ying-Chun Liu (PaulLiu)" <paul.liu(a)linaro.org> CC: Fabio Estevam <festevam(a)denx.de> --- configs/imx8mm-cl-iot-gate-optee_defconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/configs/imx8mm-cl-iot-gate-optee_defconfig b/configs/imx8mm-cl-iot-gate-optee_defconfig index d918779960..d987328922 100644 --- a/configs/imx8mm-cl-iot-gate-optee_defconfig +++ b/configs/imx8mm-cl-iot-gate-optee_defconfig @@ -21,13 +21,14 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x40480000 CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_FIT_SIGNATURE=y CONFIG_SPL_LOAD_FIT=y # CONFIG_USE_SPL_FIT_GENERATOR is not set CONFIG_OF_SYSTEM_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/compulab/imx8mm-cl-iot-gate/imximage-8mm-lpddr4.cfg" +CONFIG_IMX_CONFIG="board/compulab/imx8mm-cl-iot-gate/imximage-8mm-lpddr4.cfg" CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SEPARATE_BSS=y -- 2.25.1

2 1

[PATCH] kontron-sl-mx8mm: fix missing configs and deadlock in CI
by Stefano Babic 24 Oct '21

24 Oct '21

Even if board can be successfuly built, CI goes in deadlock (see thread on https://www.mail-archive.com/u-boot@lists.denx.de/msg419663.html). This is caused by SYS_CONFIG set in header file and because defconfig for the board is out of sync with Kconfig. As result, buildman goes on to read from stdin until an OOM is reached. Signed-off-by: Stefano Babic <sbabic(a)denx.de> CC: Frieder Schrempf <frieder.schrempf(a)kontron.de> --- configs/kontron-sl-mx8mm_defconfig | 4 +++- include/configs/kontron-sl-mx8mm.h | 3 --- 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/configs/kontron-sl-mx8mm_defconfig b/configs/kontron-sl-mx8mm_defconfig index 06c57b7555..02897818d9 100644 --- a/configs/kontron-sl-mx8mm_defconfig +++ b/configs/kontron-sl-mx8mm_defconfig @@ -8,6 +8,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x10000 CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x1f0000 CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_DM_GPIO=y CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="imx8mm-kontron-n801x-s" @@ -17,6 +18,7 @@ CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_SPL=y +CONFIG_SYS_LOAD_ADDR=0x40480000 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_DISTRO_DEFAULTS=y @@ -25,7 +27,7 @@ CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y # CONFIG_USE_SPL_FIT_GENERATOR is not set CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/kontron/sl-mx8mm/imximage.cfg" +CONFIG_IMX_CONFIG="board/kontron/sl-mx8mm/imximage.cfg" CONFIG_BOARD_TYPES=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SEPARATE_BSS=y diff --git a/include/configs/kontron-sl-mx8mm.h b/include/configs/kontron-sl-mx8mm.h index 4909b3679d..0d9ab3b755 100644 --- a/include/configs/kontron-sl-mx8mm.h +++ b/include/configs/kontron-sl-mx8mm.h @@ -22,7 +22,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x200000 -#define CONFIG_SYS_MALLOC_LEN SZ_64M #define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_INIT_SP_OFFSET \ @@ -55,8 +54,6 @@ #define BOOTENV #endif -#define CONFIG_LOADADDR 0x40480000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_BOOTM_LEN SZ_64M #define CONFIG_SPL_MAX_SIZE (148 * SZ_1K) #define CONFIG_FSL_USDHC -- 2.25.1

2 1

[PATCH] video: mxsfb: fix clk_get_by_name() return value check
by Giulio Benetti 24 Oct '21

24 Oct '21

If clk_get_by_name() returns 0 it means it executed successfully while now we consider it as an error. So let's check if return value is negative to be an error. Otherwise this prevents "axi" and "disp_axi" to be enabled. Signed-off-by: Giulio Benetti <giulio.benetti(a)benettiengineering.com> --- drivers/video/mxsfb.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c index 98d2965711..5f85c0c3eb 100644 --- a/drivers/video/mxsfb.c +++ b/drivers/video/mxsfb.c @@ -89,7 +89,7 @@ static void mxs_lcd_init(struct udevice *dev, u32 fb_addr, } ret = clk_get_by_name(dev, "axi", &clk); - if (!ret) { + if (ret < 0) { debug("%s: Failed to get mxs axi clk: %d\n", __func__, ret); } else { ret = clk_enable(&clk); @@ -100,7 +100,7 @@ static void mxs_lcd_init(struct udevice *dev, u32 fb_addr, } ret = clk_get_by_name(dev, "disp_axi", &clk); - if (!ret) { + if (ret < 0) { debug("%s: Failed to get mxs disp_axi clk: %d\n", __func__, ret); } else { ret = clk_enable(&clk); -- 2.25.1

1 0

Pull request: u-boot-spi/master
by Jagan Teki 23 Oct '21

23 Oct '21

Hi Tom, Please pull the PR. Summary: - Fix mtd erase with mtdpart (Marek Behún) - NXP fspi driver fixes (Kuldeep Singh) CI: https://source.denx.de/u-boot/custodians/u-boot-spi/-/pipelines/9582 thanks, Jagan. The following changes since commit 7a508a7245592ca44b3dc51c0293656dce60d658: Merge tag 'u-boot-amlogic-20211007' of https://source.denx.de/u-boot/custodians/u-boot-amlogic (2021-10-07 09:02:22 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-spi master for you to fetch changes up to b9cfd8b0911209e2ebec887e497510ee42f9e788: spi: nxp_fspi: Implement errata workaround for LS1028A (2021-10-23 15:56:47 +0530) ---------------------------------------------------------------- Haolin Li (1): mtd: spinand: macronix: Fix ECC Status Read Kris Chaplin (2): mtd: spi-nor-ids: Add is25lp512 and is25wp512 devices mtd: spi-nor-ids: Add SECT_4K to mt25qu512a Kuldeep Singh (2): spi: nxp-fspi: Add support for IP read only spi: nxp_fspi: Implement errata workaround for LS1028A Marek Behún (10): mtd: spi-nor-core: Try cleaning up in case writing BAR failed mtd: spi-nor-core: Check return value of write_enable() in spi_nor_erase() mtd: spi-nor-core: Don't overwrite return value if it is non-zero mtd: spi-nor-core: Check return value of write_disable() in spi_nor_erase() mtd: spi-flash: Check for zero length in legacy spi_flash_*() mtd: spi-nor-core: Don't check for zero length in spi_nor_write() / spi_nor_erase() mtd: spi-nor-core: Call mtd_erase_callback() from spi_nor_erase() mtd: spi-nor-core: Check for ctrlc() in spi_nor_erase() mtd: mtdpart: Make mtdpart's _erase method sane mtd: Remove mtd_erase_callback() entirely Marek Vasut (1): mtd: spi-nor-ids: Reinstate Micron MT25QL02G Takahiro Kuwano (1): mtd: spi-nor: Add support for Spansion S25FL256L Yanhong Wang (1): mtd: spi-nor-ids: Add GD25LQ256D Chip cmd/onenand.c | 9 +---- drivers/mtd/altera_qspi.c | 3 -- drivers/mtd/cfi_mtd.c | 1 - drivers/mtd/mtdconcat.c | 11 ------ drivers/mtd/mtdcore.c | 8 ---- drivers/mtd/mtdpart.c | 23 +++--------- drivers/mtd/nand/raw/nand_base.c | 4 -- drivers/mtd/nand/spi/macronix.c | 10 ++++- drivers/mtd/onenand/onenand_base.c | 3 -- drivers/mtd/spi/sf_mtd.c | 1 - drivers/mtd/spi/spi-nor-core.c | 65 +++++++++++++++++++++++++------- drivers/mtd/spi/spi-nor-ids.c | 13 ++++++- drivers/mtd/ubi/io.c | 13 ------- drivers/spi/nxp_fspi.c | 77 +++++++++++++++++++++++++++++++++----- env/onenand.c | 4 +- fs/yaffs2/yaffs_mtdif.c | 1 - include/linux/mtd/mtd.h | 11 ------ include/nand.h | 1 - include/spi_flash.h | 9 +++++ 19 files changed, 159 insertions(+), 108 deletions(-)

2 1