January 2021 - U-Boot

[PATCH] drivers: mmc: support secure erase.
by dennis 05 Jan '21

05 Jan '21

According to the JEDEC Standard, eMMC v4.4 cards can supoort secure erase. the first bit in ext_csd[EXT_CSD_SEC_FEATURE_SUPPORT] - EXT_CSD_SEC_ER_EN is used to check if secure erase supoort by the device. Signed-off-by: dennis <dennislaplacian1(a)gmail.com> --- drivers/mmc/Kconfig | 8 ++++++++ drivers/mmc/mmc.c | 4 ++++ drivers/mmc/mmc_write.c | 16 +++++++++++++--- include/mmc.h | 5 ++++- 4 files changed, 29 insertions(+), 4 deletions(-) diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 14d7913986..6105cbe960 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -18,6 +18,14 @@ config MMC_WRITE help Enable write access to MMC and SD Cards +config MMC_SECURE_ERASE + bool "Enable secure erase for eMMC" + depends on MMC_WRITE + default n + help + This option replace the default erase with secure erase in eMMC v4.4 + and above cards. + config MMC_BROKEN_CD bool "Poll for broken card detection case" help diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index a6394bcf30..56b17070e7 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -2272,6 +2272,10 @@ static int mmc_startup_v4(struct mmc *mmc) if ((capacity >> 20) > 2 * 1024) mmc->capacity_user = capacity; } +#if CONFIG_IS_ENABLED(MMC_SECURE_ERASE) + if (mmc->version >= MMC_VERSION_4_4 && IS_MMC(mmc)) + mmc->sec_feature_support = ext_csd[EXT_CSD_SEC_FEATURE_SUPPORT]; +#endif if (mmc->version >= MMC_VERSION_4_5) mmc->gen_cmd6_time = ext_csd[EXT_CSD_GENERIC_CMD6_TIME]; diff --git a/drivers/mmc/mmc_write.c b/drivers/mmc/mmc_write.c index 6a4453ca02..0b720ccf7e 100644 --- a/drivers/mmc/mmc_write.c +++ b/drivers/mmc/mmc_write.c @@ -15,7 +15,7 @@ #include <linux/math64.h> #include "mmc_private.h" -static ulong mmc_erase_t(struct mmc *mmc, ulong start, lbaint_t blkcnt) +static ulong mmc_erase_t(struct mmc *mmc, ulong start, lbaint_t blkcnt, uint arg) { struct mmc_cmd cmd; ulong end; @@ -52,7 +52,7 @@ static ulong mmc_erase_t(struct mmc *mmc, ulong start, lbaint_t blkcnt) goto err_out; cmd.cmdidx = MMC_CMD_ERASE; - cmd.cmdarg = MMC_ERASE_ARG; + cmd.cmdarg = arg; cmd.resp_type = MMC_RSP_R1b; err = mmc_send_cmd(mmc, &cmd, NULL); @@ -81,6 +81,7 @@ ulong mmc_berase(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt) struct mmc *mmc = find_mmc_device(dev_num); lbaint_t blk = 0, blk_r = 0; int timeout_ms = 1000; + uint arg = MMC_ERASE_ARG; if (!mmc) return -1; @@ -105,6 +106,15 @@ ulong mmc_berase(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt) ((start + blkcnt + mmc->erase_grp_size) & ~(mmc->erase_grp_size - 1)) - 1); +#if CONFIG_IS_ENABLED(MMC_SECURE_ERASE) + if (!(mmc->sec_feature_support & EXT_CSD_SEC_ER_EN)) { + printf("secure erase not supported on device\n" + "perform insecure erase\n"); + } else { + arg = MMC_SECURE_ERASE_ARG; + } +#endif + while (blk < blkcnt) { if (IS_SD(mmc) && mmc->ssr.au) { blk_r = ((blkcnt - blk) > mmc->ssr.au) ? @@ -113,7 +123,7 @@ ulong mmc_berase(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt) blk_r = ((blkcnt - blk) > mmc->erase_grp_size) ? mmc->erase_grp_size : (blkcnt - blk); } - err = mmc_erase_t(mmc, start + blk, blk_r); + err = mmc_erase_t(mmc, start + blk, blk_r, arg); if (err) break; diff --git a/include/mmc.h b/include/mmc.h index 1d377e0281..bfdc712bdd 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -80,7 +80,6 @@ struct bd_info; #define MMC_MODE_1BIT BIT(28) #define MMC_MODE_SPI BIT(27) - #define SD_DATA_4BIT 0x00040000 #define IS_SD(x) ((x)->version & SD_VERSION_SD) @@ -240,6 +239,7 @@ static inline bool mmc_is_tuning_cmd(uint cmdidx) #define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */ #define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */ #define EXT_CSD_BOOT_MULT 226 /* RO */ +#define EXT_CSD_SEC_FEATURE_SUPPORT 231 /* RO */ #define EXT_CSD_GENERIC_CMD6_TIME 248 /* RO */ #define EXT_CSD_BKOPS_SUPPORT 502 /* RO */ @@ -247,6 +247,8 @@ static inline bool mmc_is_tuning_cmd(uint cmdidx) * EXT_CSD field definitions */ +#define EXT_CSD_SEC_ER_EN BIT(0) + #define EXT_CSD_CMD_SET_NORMAL (1 << 0) #define EXT_CSD_CMD_SET_SECURE (1 << 1) #define EXT_CSD_CMD_SET_CPSECURE (1 << 2) @@ -690,6 +692,7 @@ struct mmc { uint tran_speed; uint legacy_speed; /* speed for the legacy mode provided by the card */ uint read_bl_len; + u8 sec_feature_support; #if CONFIG_IS_ENABLED(MMC_WRITE) uint write_bl_len; uint erase_grp_size; /* in 512-byte sectors */ -- 2.17.1

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Pull request for UEFI sub-system for next
by Heinrich Schuchardt 04 Jan '21

04 Jan '21

Dear Tom, please, merge into origin/next. @Takahiro, Ilias, Sughosh *Thanks a lot for all your contributions this year.* The following changes since commit 958b9e2482538ebfeb2e1161257603d4dec498cb: Merge tag 'dm-next-23dec20' of git://git.denx.de/u-boot-dm into next (2020-12-23 18:10:15 -0500) are available in the Git repository at: https://gitlab.denx.de/u-boot/custodians/u-boot-efi.git tags/efi-next for you to fetch changes up to c35df7c9e43eaf5f8bf2113a58ea257291988589: qemu: arm64: Add documentation for capsule update (2020-12-31 14:41:31 +0100) Gitlab CI showed no problems: https://gitlab.denx.de/u-boot/custodians/u-boot-efi/-/pipelines/5718 ---------------------------------------------------------------- Pull request for UEFI sub-system for next * UEFI capsule authentication * UEFI capsule update on QEMU ARM * fsuuid command for FAT file system * bug fixes ---------------------------------------------------------------- Heinrich Schuchardt (10): efi_loader: make variable store size customizable fs: fat: eliminate DIRENTSPERBLOCK() macro fs/fat: implement fsuuid command efi_loader: missing parentheses after if efi_loader: escape key handling efi_loader: avoid invalid free efi_loader: efi_signal_event() fix comment typos efi_loader: describe struct efi_loaded_image_obj efi_loader: use after free in efi_exit() efi_loader: event queueing Ilias Apalodimas (4): efi_loader: Extra checks while opening an OPTEE session efi_loader: Remove unused headers from efi_load_initrd.c efi_loader: Remove unconditional installation of file2 protocol for initrd efi_loader: Add size checks to efi_create_indexed_name() Sughosh Ganu (14): mkeficapsule: Add support for embedding public key in a dtb qemu: arm: Initialise virtio devices in board_late_init crypto: Fix the logic to calculate hash with authattributes set qemu: common: Add support for dynamic mtdparts for the platform qemu: common: Set dfu_alt_info variable for the platform fsp: Move and rename fsp_types.h file efi_loader: Add logic to parse EDKII specific fmp payload header dfu_mtd: Add provision to unlock mtd device efi_loader: Make the pkcs7 header parsing function an extern efi_loader: Re-factor code to build the signature store from efi signature list efi: capsule: Add support for uefi capsule authentication efi_loader: Enable uefi capsule authentication efidebug: capsule: Add a command to update capsule on disk qemu: arm64: Add documentation for capsule update arch/arm/mach-qemu/Kconfig | 2 + arch/x86/include/asm/fsp/fsp_support.h | 3 +- board/emulation/common/Kconfig | 15 ++ board/emulation/common/Makefile | 5 + board/emulation/common/qemu_capsule.c | 48 +++++ board/emulation/common/qemu_dfu.c | 68 ++++++ board/emulation/common/qemu_mtdparts.c | 82 ++++++++ board/emulation/qemu-arm/Kconfig | 8 + board/emulation/qemu-arm/qemu-arm.c | 5 + cmd/efidebug.c | 14 ++ doc/board/emulation/index.rst | 1 + doc/board/emulation/qemu_capsule_update.rst | 210 +++++++++++++++++++ drivers/dfu/dfu_mtd.c | 20 +- fs/fat/fat.c | 23 +- fs/fs.c | 2 +- include/efi_api.h | 18 ++ include/efi_loader.h | 23 +- include/efi_variable.h | 2 +- include/fat.h | 13 +- .../asm/fsp/fsp_types.h => include/signatures.h | 6 +- lib/crypto/pkcs7_verify.c | 37 +++- lib/efi_loader/Kconfig | 31 +++ lib/efi_loader/efi_bootmgr.c | 2 +- lib/efi_loader/efi_boottime.c | 25 ++- lib/efi_loader/efi_capsule.c | 129 +++++++++++- lib/efi_loader/efi_console.c | 12 ++ lib/efi_loader/efi_firmware.c | 77 ++++++- lib/efi_loader/efi_load_initrd.c | 8 +- lib/efi_loader/efi_setup.c | 5 - lib/efi_loader/efi_signature.c | 192 +++++++++++++---- lib/efi_loader/efi_string.c | 10 +- lib/efi_loader/efi_variable.c | 93 +------- lib/efi_loader/efi_variable_tee.c | 20 +- test/unicode_ut.c | 2 +- tools/Makefile | 1 + tools/mkeficapsule.c | 233 +++++++++++++++++++-- 36 files changed, 1240 insertions(+), 205 deletions(-) create mode 100644 board/emulation/common/Kconfig create mode 100644 board/emulation/common/Makefile create mode 100644 board/emulation/common/qemu_capsule.c create mode 100644 board/emulation/common/qemu_dfu.c create mode 100644 board/emulation/common/qemu_mtdparts.c create mode 100644 doc/board/emulation/qemu_capsule_update.rst rename arch/x86/include/asm/fsp/fsp_types.h => include/signatures.h (95%)

3 4

[PATCH V2 01/12] imx: imx8mp_evk: enable eth support
by Peng Fan (OSS) 04 Jan '21

04 Jan '21

From: Peng Fan <peng.fan(a)nxp.com> Add board code to configure the network interface Add net defconfig Signed-off-by: Peng Fan <peng.fan(a)nxp.com> --- V2: Use phy-reset-gpios Use void for setup_fec Drop empty lines arch/arm/dts/imx8mp-evk-u-boot.dtsi | 4 ++ arch/arm/include/asm/arch-imx8m/imx-regs.h | 2 + board/freescale/imx8mp_evk/imx8mp_evk.c | 65 +++++++++++++++++++++- configs/imx8mp_evk_defconfig | 9 ++- include/configs/imx8mp_evk.h | 16 ++++++ 5 files changed, 94 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/imx8mp-evk-u-boot.dtsi b/arch/arm/dts/imx8mp-evk-u-boot.dtsi index 24a93ac2d6..47100da567 100644 --- a/arch/arm/dts/imx8mp-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-evk-u-boot.dtsi @@ -131,3 +131,7 @@ &wdog1 { u-boot,dm-spl; }; + +&fec { + phy-reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; +}; diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h index f1c410ec78..f5711155b7 100644 --- a/arch/arm/include/asm/arch-imx8m/imx-regs.h +++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h @@ -62,6 +62,8 @@ #define DDRC_IPS_BASE_ADDR(X) (0x3d400000 + ((X) * 0x2000000)) #define DDR_CSD1_BASE_ADDR 0x40000000 +#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK 0x70000 + #if !defined(__ASSEMBLY__) #include <asm/types.h> #include <linux/bitops.h> diff --git a/board/freescale/imx8mp_evk/imx8mp_evk.c b/board/freescale/imx8mp_evk/imx8mp_evk.c index 034a349236..330b47fa5f 100644 --- a/board/freescale/imx8mp_evk/imx8mp_evk.c +++ b/board/freescale/imx8mp_evk/imx8mp_evk.c @@ -7,9 +7,13 @@ #include <env.h> #include <errno.h> #include <init.h> +#include <miiphy.h> +#include <netdev.h> +#include <linux/delay.h> #include <asm/mach-imx/iomux-v3.h> #include <asm-generic/gpio.h> #include <asm/arch/imx8mp_pins.h> +#include <asm/arch/clock.h> #include <asm/arch/sys_proto.h> #include <asm/mach-imx/gpio.h> @@ -40,10 +44,69 @@ int board_early_init_f(void) return 0; } -int board_init(void) +static void setup_fec(void) +{ + struct iomuxc_gpr_base_regs *gpr = + (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; + + /* Enable RGMII TX clk output */ + setbits_le32(&gpr->gpr[1], BIT(22)); +} + +#define EQOS_RST_PAD IMX_GPIO_NR(4, 22) +static iomux_v3_cfg_t const eqos_rst_pads[] = { + MX8MP_PAD_SAI2_RXC__GPIO4_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_iomux_eqos(void) { + imx_iomux_v3_setup_multiple_pads(eqos_rst_pads, + ARRAY_SIZE(eqos_rst_pads)); + + gpio_request(EQOS_RST_PAD, "eqos_rst"); + gpio_direction_output(EQOS_RST_PAD, 0); + mdelay(15); + gpio_direction_output(EQOS_RST_PAD, 1); + mdelay(100); +} + +static int setup_eqos(void) +{ + struct iomuxc_gpr_base_regs *gpr = + (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; + + setup_iomux_eqos(); + + /* set INTF as RGMII, enable RGMII TXC clock */ + clrsetbits_le32(&gpr->gpr[1], + IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK, BIT(16)); + setbits_le32(&gpr->gpr[1], BIT(19) | BIT(21)); + + return set_clk_eqos(ENET_125MHZ); +} + +#if CONFIG_IS_ENABLED(NET) +int board_phy_config(struct phy_device *phydev) +{ + if (phydev->drv->config) + phydev->drv->config(phydev); return 0; } +#endif + +int board_init(void) +{ + int ret = 0; + + if (CONFIG_IS_ENABLED(FEC_MXC)) { + setup_fec(); + + if (CONFIG_IS_ENABLED(DWC_ETH_QOS)) + ret = setup_eqos(); + } + + return ret; +} int board_late_init(void) { diff --git a/configs/imx8mp_evk_defconfig b/configs/imx8mp_evk_defconfig index cd5724e811..538d0c0ef2 100644 --- a/configs/imx8mp_evk_defconfig +++ b/configs/imx8mp_evk_defconfig @@ -45,6 +45,9 @@ CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT2=y @@ -71,8 +74,12 @@ CONFIG_DM_MMC=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_IO_VOLTAGE=y CONFIG_FSL_ESDHC_IMX=y -CONFIG_PHYLIB=y +CONFIG_PHY_REALTEK=y CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_DWC_ETH_QOS=y +CONFIG_FEC_MXC=y +CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_IMX8M=y diff --git a/include/configs/imx8mp_evk.h b/include/configs/imx8mp_evk.h index 8253c6aa2f..7abaf5ff84 100644 --- a/include/configs/imx8mp_evk.h +++ b/include/configs/imx8mp_evk.h @@ -44,6 +44,22 @@ #endif +#if defined(CONFIG_CMD_NET) +#define CONFIG_ETHPRIME "eth1" /* Set eqos to primary since we use its MDIO */ + +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_FEC_MXC_PHYADDR 1 +#define FEC_QUIRK_ENET_MAC + +#define DWC_NET_PHYADDR 1 +#ifdef CONFIG_DWC_ETH_QOS +#define CONFIG_SYS_NONCACHED_MEMORY (1 * SZ_1M) /* 1M */ +#endif + +#define PHY_ANEG_TIMEOUT 20000 + +#endif + /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ -- 2.28.0

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[PATCH 1/2] ARM: zynq: add Digilent Zynq PYNQ Board(s)
by Florian Klink 04 Jan '21

04 Jan '21

This adds the dts and entry in CONFIG_OF_LIST for the Digilent Zynq PYNQ Board(s). They're Zynq 7000 - based boards, the Z1 is from Digilent, the Z2 from TUL. They have a slightly different audio system, and a different pin header, but these aren't really accessible from the PS, only from the PL, so the DTB is the same. Co-authored-by: Thomas Heijligen <src(a)posteo.de> Signed-off-by: Florian Klink <flokli(a)flokli.de> Signed-off-by: Thomas Heijligen <src(a)posteo.de> --- arch/arm/dts/Makefile | 1 + arch/arm/dts/zynq-pynq.dts | 68 ++++++++++++++++++++++++++++++ configs/xilinx_zynq_virt_defconfig | 2 +- 3 files changed, 70 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/zynq-pynq.dts diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index fd47e408f8..0631404dbd 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -267,6 +267,7 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \ zynq-microzed.dtb \ zynq-minized.dtb \ zynq-picozed.dtb \ + zynq-pynq.dtb \ zynq-syzygy-hub.dtb \ zynq-topic-miami.dtb \ zynq-topic-miamilite.dtb \ diff --git a/arch/arm/dts/zynq-pynq.dts b/arch/arm/dts/zynq-pynq.dts new file mode 100644 index 0000000000..04ac0f7cdc --- /dev/null +++ b/arch/arm/dts/zynq-pynq.dts @@ -0,0 +1,68 @@ +// SPDX-License-Identifier: GPL-2.0+ +/dts-v1/; +#include "zynq-7000.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "Digilent/TUL Zynq PYNQ"; + compatible = "digilent,zynq-pynq", "digilent,zynq-pynq-z1", "tul,zynq-pynq", "tul,zynq-pynq-z2", "xlnx,zynq-7000"; + + aliases { + ethernet0 = &gem0; + serial0 = &uart0; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x20000000>; + }; + + chosen { + bootargs = ""; + stdout-path = "serial0:115200n8"; + }; + + gpio-leds { + compatible = "gpio-leds"; + + ld4 { + label = "zynq-pynq:green:ld4"; + gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>; + }; + }; + + usb_phy0: phy0 { + #phy-cells = <0>; + compatible = "usb-nop-xceiv"; + reset-gpios = <&gpio0 46 GPIO_ACTIVE_LOW>; + }; +}; + +&clkc { + ps-clk-frequency = <50000000>; +}; + +&gem0 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <&ethernet_phy>; + + ethernet_phy: ethernet-phy@0 { + reg = <0>; + device_type = "ethernet-phy"; + }; +}; + +&sdhci0 { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; + usb-phy = <&usb_phy0>; +}; diff --git a/configs/xilinx_zynq_virt_defconfig b/configs/xilinx_zynq_virt_defconfig index 552f1b4dfb..c46f531d4d 100644 --- a/configs/xilinx_zynq_virt_defconfig +++ b/configs/xilinx_zynq_virt_defconfig @@ -52,7 +52,7 @@ CONFIG_CMD_MTDPARTS=y CONFIG_CMD_MTDPARTS_SPREAD=y CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES=y CONFIG_CMD_UBI=y -CONFIG_OF_LIST="zynq-zc702 zynq-zc706 zynq-zc770-xm010 zynq-zc770-xm011 zynq-zc770-xm011-x16 zynq-zc770-xm012 zynq-zc770-xm013 zynq-cc108 zynq-microzed zynq-minized zynq-picozed zynq-zed zynq-zturn zynq-zturn-v5 zynq-zybo zynq-zybo-z7 zynq-dlc20-rev1.0" +CONFIG_OF_LIST="zynq-zc702 zynq-zc706 zynq-zc770-xm010 zynq-zc770-xm011 zynq-zc770-xm011-x16 zynq-zc770-xm012 zynq-zc770-xm013 zynq-cc108 zynq-microzed zynq-minized zynq-picozed zynq-pynq zynq-zed zynq-zturn zynq-zturn-v5 zynq-zybo zynq-zybo-z7 zynq-dlc20-rev1.0" CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y -- 2.29.2

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Re: [PATCH v7 1/7] riscv: Add DMA 64-bit address support
by Rick Chen 04 Jan '21

04 Jan '21

> From: Padmarao Begari [mailto:padmarao.begari@microchip.com] > Sent: Tuesday, December 22, 2020 9:12 PM > To: u-boot(a)lists.denx.de; bmeng.cn(a)gmail.com; Rick Jian-Zhi Chen(陳建志); anup.patel(a)wdc.com; lukas.auer(a)aisec.fraunhofer.de; joe.hershberger(a)ni.com; lukma(a)denx.de; atish.patra(a)wdc.com > Cc: cyril.jean(a)microchip.com; lewis.hanly(a)microchip.com; ivan.griffin(a)emdalo.com; daire.mcnamara(a)emdalo.com; conor.dooley(a)microchip.com; Padmarao Begari > Subject: [PATCH v7 1/7] riscv: Add DMA 64-bit address support > > dma_addr_t holds any valid DMA address. If the DMA API only uses 32/64-bit > addresses, dma_addr_t need only be 32/64 bits wide. > > Signed-off-by: Padmarao Begari <padmarao.begari(a)microchip.com> > Reviewed-by: Anup Patel <anup.patel(a)wdc.com> > Reviewed-by: Bin Meng <bin.meng(a)windriver.com> > --- > arch/riscv/Kconfig | 4 ++++ > arch/riscv/include/asm/types.h | 4 ++++ > 2 files changed, 8 insertions(+) > Reviewed-by: Rick Chen <rick(a)andestech.com>

1 0

[PATCH 1/1] fru: ops: avoid out of bounds access
by Heinrich Schuchardt 04 Jan '21

04 Jan '21

Building xilinx_zynq_virt_defconfig fails on origin/next as reported by GCC 10.2 (as provided by Debian Bullseye): CC board/xilinx/common/fru_ops.o board/xilinx/common/fru_ops.c: In function ‘fru_capture’: board/xilinx/common/fru_ops.c:173:8: error: array subscript 284 is outside array bounds of ‘struct fru_table[1]’ [-Werror=array-bounds] 173 | limit = data + sizeof(struct fru_board_data); | ~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ board/xilinx/common/fru_ops.c:17:18: note: while referencing ‘fru_data’ 17 | struct fru_table fru_data __section(.data); | ^~~~~~~~ When using sizeof(struct fru_board_data) to find the end of the structure you should add it to the start of the structure. Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- board/xilinx/common/fru_ops.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/xilinx/common/fru_ops.c b/board/xilinx/common/fru_ops.c index b4cd3d4998..44f0913f2e 100644 --- a/board/xilinx/common/fru_ops.c +++ b/board/xilinx/common/fru_ops.c @@ -170,7 +170,7 @@ static int fru_parse_board(unsigned long addr) data = (u8 *)&fru_data.brd.manufacturer_type_len; /* Record max structure limit not to write data over allocated space */ - limit = data + sizeof(struct fru_board_data); + limit = (u8 *)&fru_data.brd + sizeof(struct fru_board_data); for (i = 0; ; i++, data += FRU_BOARD_MAX_LEN) { len = fru_check_type_len(*(u8 *)addr, fru_data.brd.lang_code, -- 2.29.2

2 1

[PATCH 1/1] zynq: mtd: nand: remove superfluous if
by Heinrich Schuchardt 04 Jan '21

04 Jan '21

This sort of code does not make much sense: if (ondie_ecc_enabled) { if (ondie_ecc_enabled) { Remove the inner if. The problem was indicated by cppcheck. Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- drivers/mtd/nand/raw/zynq_nand.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/drivers/mtd/nand/raw/zynq_nand.c b/drivers/mtd/nand/raw/zynq_nand.c index 92db2aa19c..65817ea7f2 100644 --- a/drivers/mtd/nand/raw/zynq_nand.c +++ b/drivers/mtd/nand/raw/zynq_nand.c @@ -1206,12 +1206,10 @@ static int zynq_nand_probe(struct udevice *dev) nand_chip->options |= NAND_SUBPAGE_READ; /* On-Die ECC spare bytes offset 8 is used for ECC codes */ - if (ondie_ecc_enabled) { - nand_chip->ecc.layout = &ondie_nand_oob_64; - /* Use the BBT pattern descriptors */ - nand_chip->bbt_td = &bbt_main_descr; - nand_chip->bbt_md = &bbt_mirror_descr; - } + nand_chip->ecc.layout = &ondie_nand_oob_64; + /* Use the BBT pattern descriptors */ + nand_chip->bbt_td = &bbt_main_descr; + nand_chip->bbt_md = &bbt_mirror_descr; } else { /* Hardware ECC generates 3 bytes ECC code for each 512 bytes */ nand_chip->ecc.mode = NAND_ECC_HW; -- 2.29.2

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[PATCH v2 1/2] phy: mv88e61xx: add support for RGMII TX/RX delay
by Pawel Dembicki 04 Jan '21

04 Jan '21

Clock delay in RGMII is required for some boards. Clock delay is read from phy-mode dts property. Delay is configured via proper bits in PORT_REG_PHYS_CTRL register. Cc: Chris Packham <judge.packham(a)gmail.com> Cc: Joe Hershberger <joe.hershberger(a)ni.com> Cc: Anatolij Gustschin <agust(a)denx.de> Cc: Tim Harvey <tharvey(a)gateworks.com> Cc: Tom Rini <trini(a)konsulko.com> Signed-off-by: Pawel Dembicki <paweldembicki(a)gmail.com> --- Changes in v2: - change source info about delay: from hardcode to phy-mode propoperty in dts drivers/net/phy/mv88e61xx.c | 62 ++++++++++++++++++++++++++++++++++++- 1 file changed, 61 insertions(+), 1 deletion(-) diff --git a/drivers/net/phy/mv88e61xx.c b/drivers/net/phy/mv88e61xx.c index 7eff37b244..70adec6578 100644 --- a/drivers/net/phy/mv88e61xx.c +++ b/drivers/net/phy/mv88e61xx.c @@ -97,6 +97,8 @@ #define PORT_REG_STATUS_CMODE_1000BASE_X 0x9 #define PORT_REG_STATUS_CMODE_SGMII 0xa +#define PORT_REG_PHYS_CTRL_RGMII_RX_DELAY BIT(15) +#define PORT_REG_PHYS_CTRL_RGMII_TX_DELAY BIT(14) #define PORT_REG_PHYS_CTRL_PCS_AN_EN BIT(10) #define PORT_REG_PHYS_CTRL_PCS_AN_RST BIT(9) #define PORT_REG_PHYS_CTRL_FC_VALUE BIT(7) @@ -729,7 +731,45 @@ unforce: static int mv88e61xx_fixed_port_setup(struct phy_device *phydev, u8 port) { struct mv88e61xx_phy_priv *priv = phydev->priv; - int val; + ofnode node; + const char *str; + int val, phy_mode; + u32 phy_handle; + + if (!ofnode_valid(phydev->node)) { + node = dev_ofnode(phydev->dev); + phy_handle = ofnode_read_u32_default(node, "phy-handle", -ENXIO); + + if (phy_handle == -ENXIO) { + node = ofnode_first_subnode(node); + + while (ofnode_valid(node)) { + phy_handle = ofnode_read_u32_default(node, "phy-handle", -ENXIO); + if (phy_handle != -ENXIO) + break; + node = ofnode_next_subnode(node); + } + } + + if (phy_handle != -ENXIO) + node = ofnode_get_by_phandle(phy_handle); + else + node = ofnode_null(); + } else { + node = phy_get_ofnode(phydev); + } + + node = ofnode_find_subnode(node, "ports"); + node = ofnode_first_subnode(node); + + while (ofnode_valid(node)) { + u8 port_no = (u8)ofnode_read_u32_default(node, "reg", -1); + + if (port_no == port) + break; + + node = ofnode_next_subnode(node); + } val = mv88e61xx_port_read(phydev, port, PORT_REG_PHYS_CTRL); if (val < 0) @@ -754,6 +794,26 @@ static int mv88e61xx_fixed_port_setup(struct phy_device *phydev, u8 port) val |= PORT_REG_PHYS_CTRL_LINK_VALUE | PORT_REG_PHYS_CTRL_LINK_FORCE; + if (ofnode_valid(node)) { + str = ofnode_read_string(node, "phy-mode"); + if (str) + phy_mode = phy_get_interface_by_name(str); + switch (phy_mode) { + case PHY_INTERFACE_MODE_RGMII_ID: + val |= PORT_REG_PHYS_CTRL_RGMII_RX_DELAY; + val |= PORT_REG_PHYS_CTRL_RGMII_TX_DELAY; + break; + case PHY_INTERFACE_MODE_RGMII_RXID: + val |= PORT_REG_PHYS_CTRL_RGMII_RX_DELAY; + break; + case PHY_INTERFACE_MODE_RGMII_TXID: + val |= PORT_REG_PHYS_CTRL_RGMII_TX_DELAY; + break; + default: + break; + } + } + return mv88e61xx_port_write(phydev, port, PORT_REG_PHYS_CTRL, val); } -- 2.25.1

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EFI System Resource Table
by Heinrich Schuchardt 04 Jan '21

04 Jan '21

Hello Sughosh, hello Takahiro, do you plan to expose the U-Boot firmware in the EFI System Resource Table so that Linux fwupd will be able to detect that a capsule update is possible? Best regards Heinrich

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[PATCH 0/2] sunxi: add support for Tanix TX6
by Jernej Skrabec 03 Jan '21

03 Jan '21

This series introduces Tanix TX6 TV box support based on Allwinner H6 SoC. First patch syncs H6 DT files from Linux 5.11-rc1 release and second one adds support for Tanix TX6 board. Please take a look. Best regards, Jernej Jernej Skrabec (2): ARM: dts: sunxi: h6: Update DT files sunxi: Add support for Tanix TX6 arch/arm/dts/Makefile | 3 +- arch/arm/dts/sun50i-h6-beelink-gs1.dts | 70 +++- arch/arm/dts/sun50i-h6-cpu-opp.dtsi | 117 +++++++ arch/arm/dts/sun50i-h6-orangepi-lite2.dts | 71 +++- arch/arm/dts/sun50i-h6-orangepi.dtsi | 72 +++- arch/arm/dts/sun50i-h6-pine-h64.dts | 102 ++++-- arch/arm/dts/sun50i-h6-tanix-tx6.dts | 124 +++++++ arch/arm/dts/sun50i-h6.dtsi | 394 ++++++++++++++++++++-- board/sunxi/MAINTAINERS | 6 + 9 files changed, 890 insertions(+), 69 deletions(-) create mode 100644 arch/arm/dts/sun50i-h6-cpu-opp.dtsi create mode 100644 arch/arm/dts/sun50i-h6-tanix-tx6.dts -- 2.30.0

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