January 2021 - U-Boot

[PATCH 1/1] tools: add mkeficapsule to .gitignore
by Heinrich Schuchardt 28 Jan '21

28 Jan '21

mkeficapsule is a build product. Add it to .gitignore Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- tools/.gitignore | 1 + 1 file changed, 1 insertion(+) diff --git a/tools/.gitignore b/tools/.gitignore index a021ea95cd..a88453f64d 100644 --- a/tools/.gitignore +++ b/tools/.gitignore @@ -20,6 +20,7 @@ /kwboot /lib/ /mips-relocs +/mkeficapsule /mkenvimage /mkexynosspl /mkimage -- 2.29.2

1 0

[PATCH v3] arm: fsl: common: Improve NXP VID driver PMBus support
by Stephen Carlson 28 Jan '21

28 Jan '21

This patch adds support for more PMBus compatible devices to the NXP drivers for its QorIQ family devices. At runtime, the voltage regulator is queried over I2C, and the required voltage multiplier determined. This change supports the DIRECT and LINEAR PMBus voltage reporting modes. Previously, the driver only supported a few specific devices such as the IR36021 and LTC3882, so this change allows the QorIQ series to be used with a much larger variety of core voltage regulator devices. checkpatch warning "Use if (IS_DEFINED (...))" was ignored to maintain consistency with the existing code. Signed-off-by: Stephen Carlson <stcarlso(a)linux.microsoft.com> --- board/freescale/common/Kconfig | 27 +- board/freescale/common/vid.c | 814 ++++++++++++------------------ board/freescale/common/vid.h | 7 +- board/freescale/ls1028a/ls1028a.c | 42 ++ board/freescale/ls1088a/ls1088a.c | 40 ++ board/freescale/ls2080a/ls2080a.c | 49 ++ board/freescale/lx2160a/lx2160a.c | 42 ++ include/configs/ls1088aqds.h | 6 - include/configs/ls1088ardb.h | 8 +- 9 files changed, 519 insertions(+), 516 deletions(-) diff --git a/board/freescale/common/Kconfig b/board/freescale/common/Kconfig index 1b1fd69cb2..17db755951 100644 --- a/board/freescale/common/Kconfig +++ b/board/freescale/common/Kconfig @@ -21,18 +21,37 @@ config CMD_ESBC_VALIDATE esbc_validate - validate signature using RSA verification esbc_halt - put the core in spin loop (Secure Boot Only) +config VID + depends on DM_I2C + bool "Enable Freescale VID" + help + This option enables setting core voltage based on individual + values saved in SoC fuses. + config VOL_MONITOR_LTC3882_READ depends on VID bool "Enable the LTC3882 voltage monitor read" - default n help This option enables LTC3882 voltage monitor read - functionality. It is used by common VID driver. + functionality. It is used by the common VID driver. config VOL_MONITOR_LTC3882_SET depends on VID bool "Enable the LTC3882 voltage monitor set" - default n help This option enables LTC3882 voltage monitor set - functionality. It is used by common VID driver. + functionality. It is used by the common VID driver. + +config VOL_MONITOR_ISL68233_READ + depends on VID + bool "Enable the ISL68233 voltage monitor read" + help + This option enables ISL68233 voltage monitor read + functionality. It is used by the common VID driver. + +config VOL_MONITOR_ISL68233_SET + depends on VID + bool "Enable the ISL68233 voltage monitor set" + help + This option enables ISL68233 voltage monitor set + functionality. It is used by the common VID driver. diff --git a/board/freescale/common/vid.c b/board/freescale/common/vid.c index 2617f61520..d155582006 100644 --- a/board/freescale/common/vid.c +++ b/board/freescale/common/vid.c @@ -2,6 +2,7 @@ /* * Copyright 2014 Freescale Semiconductor, Inc. * Copyright 2020 NXP + * Copyright 2020 Stephen Carlson <stcarlso(a)linux.microsoft.com> */ #include <common.h> @@ -21,14 +22,22 @@ #include <linux/delay.h> #include "vid.h" +/* Voltages are generally handled in mV to keep them as integers */ +#define MV_PER_V 1000 + +/* + * Select the channel on the I2C mux (on some NXP boards) that contains + * the voltage regulator to use for VID. Return 0 for success or nonzero + * for failure. + */ int __weak i2c_multiplexer_select_vid_channel(u8 channel) { return 0; } /* - * Compensate for a board specific voltage drop between regulator and SoC - * return a value in mV + * Compensate for a board specific voltage drop between regulator and SoC. + * Returns the voltage offset in mV. */ int __weak board_vdd_drop_compensation(void) { @@ -36,13 +45,90 @@ int __weak board_vdd_drop_compensation(void) } /* - * Board specific settings for specific voltage value + * Performs any board specific adjustments after the VID voltage has been + * set. Return 0 for success or nonzero for failure. */ int __weak board_adjust_vdd(int vdd) { return 0; } +/* + * Processor specific method of converting the fuse value read from VID + * registers into the core voltage to supply. Return the voltage in mV. + */ +u16 __weak soc_get_fuse_vid(int vid_index) +{ + /* Default VDD for Layerscape Chassis 1 devices */ + static const u16 vdd[32] = { + 0, /* unused */ + 9875, /* 0.9875V */ + 9750, + 9625, + 9500, + 9375, + 9250, + 9125, + 9000, + 8875, + 8750, + 8625, + 8500, + 8375, + 8250, + 8125, + 10000, /* 1.0000V */ + 10125, + 10250, + 10375, + 10500, + 10625, + 10750, + 10875, + 11000, + 0, /* reserved */ + }; + return vdd[vid_index]; +} + +#ifdef CONFIG_DM_I2C +#define DEVICE_HANDLE_T struct udevice * + +#ifndef I2C_VOL_MONITOR_BUS +#define I2C_VOL_MONITOR_BUS 0 +#endif + +/* If DM is in use, retrieve the udevice chip for the specified bus number */ +static int vid_get_device(int address, DEVICE_HANDLE_T *dev) +{ + int ret = i2c_get_chip_for_busnum(I2C_VOL_MONITOR_BUS, address, 1, dev); + + if (ret) + printf("VID: Bus %d has no device with address 0x%02X\n", + I2C_VOL_MONITOR_BUS, address); + return ret; +} + +#define I2C_READ(dev, register, data, length) \ + dm_i2c_read(dev, register, data, length) +#define I2C_WRITE(dev, register, data, length) \ + dm_i2c_write(dev, register, data, length) +#else +#define DEVICE_HANDLE_T int + +/* If DM is not in use, I2C addresses are passed directly */ +static int vid_get_device(int address, DEVICE_HANDLE_T *dev) +{ + *dev = address; + return 0; +} + +#define I2C_READ(dev, register, data, length) \ + i2c_read(dev, register, 1, data, length) +#define I2C_WRITE(dev, register, data, length) \ + i2c_write(dev, register, 1, data, length) +#endif + #if defined(CONFIG_VOL_MONITOR_IR36021_SET) || \ defined(CONFIG_VOL_MONITOR_IR36021_READ) /* @@ -60,30 +146,22 @@ int __weak board_adjust_vdd(int vdd) */ static int find_ir_chip_on_i2c(void) { - int i2caddress; - int ret; - u8 byte; - int i; + int i2caddress, ret, i; + u8 mfrID; const int ir_i2c_addr[] = {0x38, 0x08, 0x09}; -#ifdef CONFIG_DM_I2C - struct udevice *dev; -#endif + DEVICE_HANDLE_T dev; /* Check all the address */ for (i = 0; i < (sizeof(ir_i2c_addr)/sizeof(ir_i2c_addr[0])); i++) { i2caddress = ir_i2c_addr[i]; -#ifndef CONFIG_DM_I2C - ret = i2c_read(i2caddress, - IR36021_MFR_ID_OFFSET, 1, (void *)&byte, - sizeof(byte)); -#else - ret = i2c_get_chip_for_busnum(0, i2caddress, 1, &dev); - if (!ret) - ret = dm_i2c_read(dev, IR36021_MFR_ID_OFFSET, - (void *)&byte, sizeof(byte)); -#endif - if ((ret >= 0) && (byte == IR36021_MFR_ID)) - return i2caddress; + ret = vid_get_device(i2caddress, &dev); + if (!ret) { + ret = I2C_READ(dev, IR36021_MFR_ID_OFFSET, + (void *)&mfrID, sizeof(mfrID)); + /* If manufacturer ID matches the IR36021 */ + if (!ret && byte == IR36021_MFR_ID) + return i2caddress; + } } return -1; } @@ -117,35 +195,33 @@ static int read_voltage_from_INA220(int i2caddress) int i, ret, voltage_read = 0; u16 vol_mon; u8 buf[2]; -#ifdef CONFIG_DM_I2C - struct udevice *dev; -#endif + DEVICE_HANDLE_T dev; + + /* Open device handle */ + ret = vid_get_device(i2caddress, &dev); + if (ret) + return ret; for (i = 0; i < NUM_READINGS; i++) { -#ifndef CONFIG_DM_I2C - ret = i2c_read(I2C_VOL_MONITOR_ADDR, - I2C_VOL_MONITOR_BUS_V_OFFSET, 1, - (void *)&buf, 2); -#else - ret = i2c_get_chip_for_busnum(0, I2C_VOL_MONITOR_ADDR, 1, &dev); - if (!ret) - ret = dm_i2c_read(dev, I2C_VOL_MONITOR_BUS_V_OFFSET, - (void *)&buf, 2); -#endif + ret = I2C_READ(dev, I2C_VOL_MONITOR_BUS_V_OFFSET, + (void *)&buf[0], sizeof(buf)); if (ret) { printf("VID: failed to read core voltage\n"); return ret; } + vol_mon = (buf[0] << 8) | buf[1]; if (vol_mon & I2C_VOL_MONITOR_BUS_V_OVF) { printf("VID: Core voltage sensor error\n"); return -1; } + debug("VID: bus voltage reads 0x%04x\n", vol_mon); /* LSB = 4mv */ voltage_read += (vol_mon >> I2C_VOL_MONITOR_BUS_V_SHIFT) * 4; udelay(WAIT_FOR_ADC); } + /* calculate the average */ voltage_read /= NUM_READINGS; @@ -153,30 +229,25 @@ static int read_voltage_from_INA220(int i2caddress) } #endif -/* read voltage from IR */ #ifdef CONFIG_VOL_MONITOR_IR36021_READ +/* read voltage from IR */ static int read_voltage_from_IR(int i2caddress) { int i, ret, voltage_read = 0; u16 vol_mon; u8 buf; -#ifdef CONFIG_DM_I2C - struct udevice *dev; -#endif + DEVICE_HANDLE_T dev; + + /* Open device handle */ + ret = vid_get_device(i2caddress, &dev); + if (ret) + return ret; for (i = 0; i < NUM_READINGS; i++) { -#ifndef CONFIG_DM_I2C - ret = i2c_read(i2caddress, - IR36021_LOOP1_VOUT_OFFSET, - 1, (void *)&buf, 1); -#else - ret = i2c_get_chip_for_busnum(0, i2caddress, 1, &dev); - if (!ret) - ret = dm_i2c_read(dev, IR36021_LOOP1_VOUT_OFFSET, - (void *)&buf, 1); -#endif + ret = I2C_READ(dev, IR36021_LOOP1_VOUT_OFFSET, (void *)&buf, + sizeof(buf)); if (ret) { - printf("VID: failed to read vcpu\n"); + printf("VID: failed to read core voltage\n"); return ret; } vol_mon = buf; @@ -188,7 +259,7 @@ static int read_voltage_from_IR(int i2caddress) /* Resolution is 1/128V. We scale up here to get 1/128mV * and divide at the end */ - voltage_read += vol_mon * 1000; + voltage_read += vol_mon * MV_PER_V; udelay(WAIT_FOR_ADC); } /* Scale down to the real mV as IR resolution is 1/128V, rounding up */ @@ -206,49 +277,94 @@ static int read_voltage_from_IR(int i2caddress) } #endif -#ifdef CONFIG_VOL_MONITOR_LTC3882_READ -/* read the current value of the LTC Regulator Voltage */ -static int read_voltage_from_LTC(int i2caddress) -{ - int ret, vcode = 0; - u8 chan = PWM_CHANNEL0; +#if defined(CONFIG_VOL_MONITOR_ISL68233_READ) || \ + defined(CONFIG_VOL_MONITOR_LTC3882_READ) || \ + defined(CONFIG_VOL_MONITOR_ISL68233_SET) || \ + defined(CONFIG_VOL_MONITOR_LTC3882_SET) -#ifndef CONFIG_DM_I2C - /* select the PAGE 0 using PMBus commands PAGE for VDD*/ - ret = i2c_write(I2C_VOL_MONITOR_ADDR, - PMBUS_CMD_PAGE, 1, &chan, 1); -#else - struct udevice *dev; +/* + * The message displayed if the VOUT exponent causes a resolution + * worse than 1.0 V (if exponent is >= 0). + */ +#define VOUT_WARNING "VID: VOUT_MODE exponent has resolution worse than 1 V!\n" - ret = i2c_get_chip_for_busnum(0, I2C_VOL_MONITOR_ADDR, 1, &dev); - if (!ret) - ret = dm_i2c_write(dev, PMBUS_CMD_PAGE, &chan, 1); -#endif +/* Checks the PMBus voltage monitor for the format used for voltage values */ +static int get_pmbus_multiplier(DEVICE_HANDLE_T dev) +{ + u8 mode; + int exponent, multiplier, ret; + + ret = I2C_READ(dev, PMBUS_CMD_VOUT_MODE, &mode, sizeof(mode)); if (ret) { - printf("VID: failed to select VDD Page 0\n"); + printf("VID: unable to determine voltage multiplier\n"); + return 1; + } + + /* Upper 3 bits is mode, lower 5 bits is exponent */ + exponent = (int)mode & 0x1F; + mode >>= 5; + switch (mode) { + case 0: + /* Linear, 5 bit twos component exponent */ + if (exponent & 0x10) { + multiplier = 1 << (16 - (exponent & 0xF)); + } else { + /* If exponent is >= 0, then resolution is 1 V! */ + printf(VOUT_WARNING); + multiplier = 1; + } + break; + case 1: + /* VID code identifier */ + printf("VID: custom VID codes are not supported\n"); + multiplier = MV_PER_V; + break; + default: + /* Direct, in mV */ + multiplier = MV_PER_V; + break; + } + + debug("VID: calculated multiplier is %d\n", multiplier); + return multiplier; +} +#endif + +#if defined(CONFIG_VOL_MONITOR_ISL68233_READ) || \ + defined(CONFIG_VOL_MONITOR_LTC3882_READ) +static int read_voltage_from_pmbus(int i2caddress) +{ + int ret, multiplier, vout; + u8 channel = PWM_CHANNEL0; + u16 vcode; + DEVICE_HANDLE_T dev; + + /* Open device handle */ + ret = vid_get_device(i2caddress, &dev); + if (ret) return ret; - } -#ifndef CONFIG_DM_I2C - /*read the output voltage using PMBus command READ_VOUT*/ - ret = i2c_read(I2C_VOL_MONITOR_ADDR, - PMBUS_CMD_READ_VOUT, 1, (void *)&vcode, 2); -#else - ret = dm_i2c_read(dev, PMBUS_CMD_READ_VOUT, (void *)&vcode, 2); + /* Select the right page */ + ret = I2C_WRITE(dev, PMBUS_CMD_PAGE, &channel, sizeof(channel)); if (ret) { - printf("VID: failed to read the volatge\n"); + printf("VID: failed to select VDD page %d\n", channel); return ret; } -#endif + + /* VOUT is little endian */ + ret = I2C_READ(dev, PMBUS_CMD_READ_VOUT, (void *)&vcode, sizeof(vcode)); if (ret) { - printf("VID: failed to read the volatge\n"); + printf("VID: failed to read core voltage\n"); return ret; } - /* Scale down to the real mV as LTC resolution is 1/4096V,rounding up */ - vcode = DIV_ROUND_UP(vcode * 1000, 4096); - - return vcode; + /* Scale down to the real mV */ + multiplier = get_pmbus_multiplier(dev); + vout = (int)vcode; + /* Multiplier 1000 (direct mode) requires no change to convert */ + if (multiplier != MV_PER_V) + vout = DIV_ROUND_UP(vout * MV_PER_V, multiplier); + return vout - board_vdd_drop_compensation(); } #endif @@ -259,10 +375,11 @@ static int read_voltage(int i2caddress) voltage_read = read_voltage_from_INA220(i2caddress); #elif defined CONFIG_VOL_MONITOR_IR36021_READ voltage_read = read_voltage_from_IR(i2caddress); -#elif defined CONFIG_VOL_MONITOR_LTC3882_READ - voltage_read = read_voltage_from_LTC(i2caddress); +#elif defined(CONFIG_VOL_MONITOR_ISL68233_READ) || \ + defined(CONFIG_VOL_MONITOR_LTC3882_READ) + voltage_read = read_voltage_from_pmbus(i2caddress); #else - return -1; + voltage_read = -1; #endif return voltage_read; } @@ -300,7 +417,7 @@ static int wait_for_new_voltage(int vdd, int i2caddress) } /* - * this function keeps reading the voltage until it is stable or until the + * Blocks and reads the VID voltage until it stabilizes, or the * timeout expires */ static int wait_for_voltage_stable(int i2caddress) @@ -310,9 +427,9 @@ static int wait_for_voltage_stable(int i2caddress) vdd = read_voltage(i2caddress); udelay(NUM_READINGS * WAIT_FOR_ADC); - /* wait until voltage is stable */ vdd_current = read_voltage(i2caddress); - /* The maximum timeout is + /* + * The maximum timeout is * MAX_LOOP_WAIT_VOL_STABLE * NUM_READINGS * WAIT_FOR_ADC */ for (timeout = MAX_LOOP_WAIT_VOL_STABLE; @@ -327,12 +444,18 @@ static int wait_for_voltage_stable(int i2caddress) return vdd_current; } -/* Set the voltage to the IR chip */ +/* Sets the VID voltage using the IR36021 */ static int set_voltage_to_IR(int i2caddress, int vdd) { int wait, vdd_last; int ret; u8 vid; + DEVICE_HANDLE_T dev; + + /* Open device handle */ + ret = vid_get_device(i2caddress, &dev); + if (ret) + return ret; /* Compensate for a board specific voltage drop between regulator and * SoC before converting into an IR VID value @@ -344,20 +467,10 @@ static int set_voltage_to_IR(int i2caddress, int vdd) vid = DIV_ROUND_UP(vdd - 245, 5); #endif -#ifndef CONFIG_DM_I2C - ret = i2c_write(i2caddress, IR36021_LOOP1_MANUAL_ID_OFFSET, - 1, (void *)&vid, sizeof(vid)); -#else - struct udevice *dev; - - ret = i2c_get_chip_for_busnum(0, i2caddress, 1, &dev); - if (!ret) - ret = dm_i2c_write(dev, IR36021_LOOP1_MANUAL_ID_OFFSET, - (void *)&vid, sizeof(vid)); - -#endif + ret = I2C_WRITE(dev, IR36021_LOOP1_MANUAL_ID_OFFSET, (void *)&vid, + sizeof(vid)); if (ret) { - printf("VID: failed to write VID\n"); + printf("VID: failed to write new voltage\n"); return -1; } wait = wait_for_new_voltage(vdd, i2caddress); @@ -371,81 +484,59 @@ static int set_voltage_to_IR(int i2caddress, int vdd) debug("VID: Current voltage is %d mV\n", vdd_last); return vdd_last; } - #endif -#ifdef CONFIG_VOL_MONITOR_LTC3882_SET -/* this function sets the VDD and returns the value set */ -static int set_voltage_to_LTC(int i2caddress, int vdd) +#if defined(CONFIG_VOL_MONITOR_ISL68233_SET) || \ + defined(CONFIG_VOL_MONITOR_LTC3882_SET) +static int set_voltage_to_pmbus(int i2caddress, int vdd) { int ret, vdd_last, vdd_target = vdd; - int count = 100, temp = 0; + int count = MAX_LOOP_WAIT_NEW_VOL, temp = 0, multiplier; unsigned char value; - /* Scale up to the LTC resolution is 1/4096V */ - vdd = (vdd * 4096) / 1000; + /* The data to be sent with the PMBus command PAGE_PLUS_WRITE */ + u8 buffer[5] = { 0x04, PWM_CHANNEL0, PMBUS_CMD_VOUT_COMMAND, 0, 0 }; + DEVICE_HANDLE_T dev; - /* 5-byte buffer which needs to be sent following the - * PMBus command PAGE_PLUS_WRITE. - */ - u8 buff[5] = {0x04, PWM_CHANNEL0, PMBUS_CMD_VOUT_COMMAND, - vdd & 0xFF, (vdd & 0xFF00) >> 8}; + /* Open device handle */ + ret = vid_get_device(i2caddress, &dev); + if (ret) + return ret; + + /* Scale up to the proper value for the VOUT command, little endian */ + multiplier = get_pmbus_multiplier(dev); + vdd += board_vdd_drop_compensation(); + if (multiplier != MV_PER_V) + vdd = DIV_ROUND_UP(vdd * multiplier, MV_PER_V); + buffer[3] = vdd & 0xFF; + buffer[4] = (vdd & 0xFF00) >> 8; - /* Write the desired voltage code to the regulator */ -#ifndef CONFIG_DM_I2C /* Check write protect state */ - ret = i2c_read(I2C_VOL_MONITOR_ADDR, - PMBUS_CMD_WRITE_PROTECT, 1, - (void *)&value, sizeof(value)); + ret = I2C_READ(dev, PMBUS_CMD_WRITE_PROTECT, (void *)&value, + sizeof(value)); if (ret) goto exit; if (value != EN_WRITE_ALL_CMD) { value = EN_WRITE_ALL_CMD; - ret = i2c_write(I2C_VOL_MONITOR_ADDR, - PMBUS_CMD_WRITE_PROTECT, 1, + ret = I2C_WRITE(dev, PMBUS_CMD_WRITE_PROTECT, (void *)&value, sizeof(value)); if (ret) goto exit; } - ret = i2c_write(I2C_VOL_MONITOR_ADDR, - PMBUS_CMD_PAGE_PLUS_WRITE, 1, - (void *)&buff, sizeof(buff)); -#else - struct udevice *dev; - - ret = i2c_get_chip_for_busnum(0, I2C_VOL_MONITOR_ADDR, 1, &dev); - if (!ret) { - /* Check write protect state */ - ret = dm_i2c_read(dev, - PMBUS_CMD_WRITE_PROTECT, - (void *)&value, sizeof(value)); - if (ret) - goto exit; - - if (value != EN_WRITE_ALL_CMD) { - value = EN_WRITE_ALL_CMD; - ret = dm_i2c_write(dev, - PMBUS_CMD_WRITE_PROTECT, - (void *)&value, sizeof(value)); - if (ret) - goto exit; - } - - ret = dm_i2c_write(dev, PMBUS_CMD_PAGE_PLUS_WRITE, - (void *)&buff, sizeof(buff)); - } -#endif -exit: + /* Write the desired voltage code to the regulator */ + ret = I2C_WRITE(dev, PMBUS_CMD_PAGE_PLUS_WRITE, (void *)&buffer[0], + sizeof(buffer)); if (ret) { - printf("VID: I2C failed to write to the volatge regulator\n"); + printf("VID: I2C failed to write to the voltage regulator\n"); return -1; } - /* Wait for the volatge to get to the desired value */ +exit: + /* Wait for the voltage to get to the desired value */ do { - vdd_last = read_voltage_from_LTC(i2caddress); + vdd_last = read_voltage_from_pmbus(i2caddress); if (vdd_last < 0) { printf("VID: Couldn't read sensor abort VID adjust\n"); return -1; @@ -464,325 +555,80 @@ static int set_voltage(int i2caddress, int vdd) #ifdef CONFIG_VOL_MONITOR_IR36021_SET vdd_last = set_voltage_to_IR(i2caddress, vdd); -#elif defined CONFIG_VOL_MONITOR_LTC3882_SET - vdd_last = set_voltage_to_LTC(i2caddress, vdd); +#elif defined(CONFIG_VOL_MONITOR_ISL68233_SET) || \ + defined(CONFIG_VOL_MONITOR_LTC3882_SET) + vdd_last = set_voltage_to_pmbus(i2caddress, vdd); #else #error Specific voltage monitor must be defined #endif return vdd_last; } -#ifdef CONFIG_FSL_LSCH3 int adjust_vdd(ulong vdd_override) { int re_enable = disable_interrupts(); +#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); - u32 fusesr; -#if defined(CONFIG_VOL_MONITOR_IR36021_SET) || \ - defined(CONFIG_VOL_MONITOR_IR36021_READ) - u8 vid, buf; #else - u8 vid; + ccsr_gur_t __iomem *gur = + (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); #endif - int vdd_target, vdd_current, vdd_last; - int ret, i2caddress = 0; + u8 vid; + u32 fusesr; + int vdd_current, vdd_last, vdd_target; + int ret, i2caddress = I2C_VOL_MONITOR_ADDR; unsigned long vdd_string_override; char *vdd_string; -#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) - static const u16 vdd[32] = { - 8250, - 7875, - 7750, - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 8000, - 8125, - 8250, - 0, /* reserved */ - 8500, - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - }; -#else -#ifdef CONFIG_ARCH_LS1088A - static const uint16_t vdd[32] = { - 10250, - 9875, - 9750, - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 9000, - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 10000, /* 1.0000V */ - 10125, - 10250, - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - }; -#else - static const uint16_t vdd[32] = { - 10500, - 0, /* reserved */ - 9750, - 0, /* reserved */ - 9500, - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 9000, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 10000, /* 1.0000V */ - 0, /* reserved */ - 10250, - 0, /* reserved */ - 10500, - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - }; -#endif -#endif - struct vdd_drive { - u8 vid; - unsigned voltage; - }; - - ret = i2c_multiplexer_select_vid_channel(I2C_MUX_CH_VOL_MONITOR); - if (ret) { - debug("VID: I2C failed to switch channel\n"); - ret = -1; - goto exit; - } #if defined(CONFIG_VOL_MONITOR_IR36021_SET) || \ defined(CONFIG_VOL_MONITOR_IR36021_READ) - ret = find_ir_chip_on_i2c(); - if (ret < 0) { - printf("VID: Could not find voltage regulator on I2C.\n"); - ret = -1; - goto exit; - } else { - i2caddress = ret; - debug("VID: IR Chip found on I2C address 0x%02x\n", i2caddress); - } - - /* check IR chip work on Intel mode*/ -#ifndef CONFIG_DM_I2C - ret = i2c_read(i2caddress, - IR36021_INTEL_MODE_OOFSET, - 1, (void *)&buf, 1); -#else - struct udevice *dev; - - ret = i2c_get_chip_for_busnum(0, i2caddress, 1, &dev); - if (!ret) - ret = dm_i2c_read(dev, IR36021_INTEL_MODE_OOFSET, - (void *)&buf, 1); -#endif - if (ret) { - printf("VID: failed to read IR chip mode.\n"); - ret = -1; - goto exit; - } - - if ((buf & IR36021_MODE_MASK) != IR36021_INTEL_MODE) { - printf("VID: IR Chip is not used in Intel mode.\n"); - ret = -1; - goto exit; - } + u8 buf; + DEVICE_HANDLE_T dev; #endif - /* get the voltage ID from fuse status register */ + /* + * VID is used according to the table below + * --------------------------------------- + * | DA_V | + * |-------------------------------------| + * | 5b00000 | 5b00001-5b11110 | 5b11111 | + * ---------------+---------+-----------------+---------| + * | D | 5b00000 | NO VID | VID = DA_V | NO VID | + * | A |----------+---------+-----------------+---------| + * | _ | 5b00001 |VID = | VID = |VID = | + * | V | ~ | DA_V_ALT| DA_V_ALT | DA_A_VLT| + * | _ | 5b11110 | | | | + * | A |----------+---------+-----------------+---------| + * | L | 5b11111 | No VID | VID = DA_V | NO VID | + * | T | | | | | + * ------------------------------------------------------ + */ +#if defined(CONFIG_FSL_LSCH3) fusesr = in_le32(&gur->dcfg_fusesr); vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT) & - FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK; - if ((vid == 0) || (vid == FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK)) { + FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK; + if (vid == 0 || vid == FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK) { vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT) & - FSL_CHASSIS3_DCFG_FUSESR_VID_MASK; - } - vdd_target = vdd[vid]; - - /* check override variable for overriding VDD */ - vdd_string = env_get(CONFIG_VID_FLS_ENV); - if (vdd_override == 0 && vdd_string && - !strict_strtoul(vdd_string, 10, &vdd_string_override)) - vdd_override = vdd_string_override; - - if (vdd_override >= VDD_MV_MIN && vdd_override <= VDD_MV_MAX) { - vdd_target = vdd_override * 10; /* convert to 1/10 mV */ - debug("VDD override is %lu\n", vdd_override); - } else if (vdd_override != 0) { - printf("Invalid value.\n"); - } - - /* divide and round up by 10 to get a value in mV */ - vdd_target = DIV_ROUND_UP(vdd_target, 10); - if (vdd_target == 0) { - debug("VID: VID not used\n"); - ret = 0; - goto exit; - } else if (vdd_target < VDD_MV_MIN || vdd_target > VDD_MV_MAX) { - /* Check vdd_target is in valid range */ - printf("VID: Target VID %d mV is not in range.\n", - vdd_target); - ret = -1; - goto exit; - } else { - debug("VID: vid = %d mV\n", vdd_target); + FSL_CHASSIS3_DCFG_FUSESR_VID_MASK; } - - /* - * Read voltage monitor to check real voltage. - */ - vdd_last = read_voltage(i2caddress); - if (vdd_last < 0) { - printf("VID: Couldn't read sensor abort VID adjustment\n"); - ret = -1; - goto exit; +#elif defined(CONFIG_FSL_LSCH2) + fusesr = in_be32(&gur->dcfg_fusesr); + vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT) & + FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK; + if (vid == 0 || vid == FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK) { + vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT) & + FSL_CHASSIS2_DCFG_FUSESR_VID_MASK; } - vdd_current = vdd_last; - debug("VID: Core voltage is currently at %d mV\n", vdd_last); - -#ifdef CONFIG_VOL_MONITOR_LTC3882_SET - /* Set the target voltage */ - vdd_last = vdd_current = set_voltage(i2caddress, vdd_target); #else - /* - * Adjust voltage to at or one step above target. - * As measurements are less precise than setting the values - * we may run through dummy steps that cancel each other - * when stepping up and then down. - */ - while (vdd_last > 0 && - vdd_last < vdd_target) { - vdd_current += IR_VDD_STEP_UP; - vdd_last = set_voltage(i2caddress, vdd_current); - } - while (vdd_last > 0 && - vdd_last > vdd_target + (IR_VDD_STEP_DOWN - 1)) { - vdd_current -= IR_VDD_STEP_DOWN; - vdd_last = set_voltage(i2caddress, vdd_current); + fusesr = in_be32(&gur->dcfg_fusesr); + vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT) & + FSL_CORENET_DCFG_FUSESR_ALTVID_MASK; + if (vid == 0 || vid == FSL_CORENET_DCFG_FUSESR_ALTVID_MASK) { + vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_VID_SHIFT) & + FSL_CORENET_DCFG_FUSESR_VID_MASK; } - #endif - if (board_adjust_vdd(vdd_target) < 0) { - ret = -1; - goto exit; - } - - if (vdd_last > 0) - printf("VID: Core voltage after adjustment is at %d mV\n", - vdd_last); - else - ret = -1; -exit: - if (re_enable) - enable_interrupts(); - i2c_multiplexer_select_vid_channel(I2C_MUX_CH_DEFAULT); - return ret; -} -#else /* !CONFIG_FSL_LSCH3 */ -int adjust_vdd(ulong vdd_override) -{ - int re_enable = disable_interrupts(); -#if defined(CONFIG_FSL_LSCH2) - struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); -#else - ccsr_gur_t __iomem *gur = - (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); -#endif - u32 fusesr; - u8 vid, buf; - int vdd_target, vdd_current, vdd_last; - int ret, i2caddress; - unsigned long vdd_string_override; - char *vdd_string; - static const uint16_t vdd[32] = { - 0, /* unused */ - 9875, /* 0.9875V */ - 9750, - 9625, - 9500, - 9375, - 9250, - 9125, - 9000, - 8875, - 8750, - 8625, - 8500, - 8375, - 8250, - 8125, - 10000, /* 1.0000V */ - 10125, - 10250, - 10375, - 10500, - 10625, - 10750, - 10875, - 11000, - 0, /* reserved */ - }; - struct vdd_drive { - u8 vid; - unsigned voltage; - }; + vdd_target = soc_get_fuse_vid((int)vid); ret = i2c_multiplexer_select_vid_channel(I2C_MUX_CH_VOL_MONITOR); if (ret) { @@ -790,6 +636,7 @@ int adjust_vdd(ulong vdd_override) ret = -1; goto exit; } + #if defined(CONFIG_VOL_MONITOR_IR36021_SET) || \ defined(CONFIG_VOL_MONITOR_IR36021_READ) ret = find_ir_chip_on_i2c(); @@ -802,19 +649,13 @@ int adjust_vdd(ulong vdd_override) debug("VID: IR Chip found on I2C address 0x%02x\n", i2caddress); } - /* check IR chip work on Intel mode*/ -#ifndef CONFIG_DM_I2C - ret = i2c_read(i2caddress, - IR36021_INTEL_MODE_OOFSET, - 1, (void *)&buf, 1); -#else - struct udevice *dev; + ret = vid_get_device(i2caddress, &dev); + if (ret) + return ret; - ret = i2c_get_chip_for_busnum(0, i2caddress, 1, &dev); - if (!ret) - ret = dm_i2c_read(dev, IR36021_INTEL_MODE_OOFSET, - (void *)&buf, 1); -#endif + /* check IR chip work on Intel mode */ + ret = I2C_READ(dev, IR36021_INTEL_MODE_OFFSET, (void *)&buf, + sizeof(buf)); if (ret) { printf("VID: failed to read IR chip mode.\n"); ret = -1; @@ -827,52 +668,18 @@ int adjust_vdd(ulong vdd_override) } #endif - /* get the voltage ID from fuse status register */ - fusesr = in_be32(&gur->dcfg_fusesr); - /* - * VID is used according to the table below - * --------------------------------------- - * | DA_V | - * |-------------------------------------| - * | 5b00000 | 5b00001-5b11110 | 5b11111 | - * ---------------+---------+-----------------+---------| - * | D | 5b00000 | NO VID | VID = DA_V | NO VID | - * | A |----------+---------+-----------------+---------| - * | _ | 5b00001 |VID = | VID = |VID = | - * | V | ~ | DA_V_ALT| DA_V_ALT | DA_A_VLT| - * | _ | 5b11110 | | | | - * | A |----------+---------+-----------------+---------| - * | L | 5b11111 | No VID | VID = DA_V | NO VID | - * | T | | | | | - * ------------------------------------------------------ - */ -#ifdef CONFIG_FSL_LSCH2 - vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT) & - FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK; - if ((vid == 0) || (vid == FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK)) { - vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT) & - FSL_CHASSIS2_DCFG_FUSESR_VID_MASK; - } -#else - vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT) & - FSL_CORENET_DCFG_FUSESR_ALTVID_MASK; - if ((vid == 0) || (vid == FSL_CORENET_DCFG_FUSESR_ALTVID_MASK)) { - vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_VID_SHIFT) & - FSL_CORENET_DCFG_FUSESR_VID_MASK; - } -#endif - vdd_target = vdd[vid]; - /* check override variable for overriding VDD */ vdd_string = env_get(CONFIG_VID_FLS_ENV); + debug("VID: Initial VDD value is %d mV\n", + DIV_ROUND_UP(vdd_target, 10)); if (vdd_override == 0 && vdd_string && !strict_strtoul(vdd_string, 10, &vdd_string_override)) vdd_override = vdd_string_override; if (vdd_override >= VDD_MV_MIN && vdd_override <= VDD_MV_MAX) { vdd_target = vdd_override * 10; /* convert to 1/10 mV */ - debug("VDD override is %lu\n", vdd_override); + debug("VID: VDD override is %lu\n", vdd_override); } else if (vdd_override != 0) { - printf("Invalid value.\n"); + printf("VID: Invalid VDD value.\n"); } if (vdd_target == 0) { debug("VID: VID not used\n"); @@ -895,6 +702,13 @@ int adjust_vdd(ulong vdd_override) } vdd_current = vdd_last; debug("VID: Core voltage is currently at %d mV\n", vdd_last); + +#if defined(CONFIG_VOL_MONITOR_LTC3882_SET) || \ + defined(CONFIG_VOL_MONITOR_ISL68233_SET) + /* Set the target voltage */ + vdd_current = set_voltage(i2caddress, vdd_target); + vdd_last = vdd_current; +#else /* * Adjust voltage to at or one step above target. * As measurements are less precise than setting the values @@ -911,6 +725,13 @@ int adjust_vdd(ulong vdd_override) vdd_current -= IR_VDD_STEP_DOWN; vdd_last = set_voltage(i2caddress, vdd_current); } +#endif + + /* Board specific adjustments */ + if (board_adjust_vdd(vdd_target) < 0) { + ret = -1; + goto exit; + } if (vdd_last > 0) printf("VID: Core voltage after adjustment is at %d mV\n", @@ -925,11 +746,10 @@ exit: return ret; } -#endif static int print_vdd(void) { - int vdd_last, ret, i2caddress = 0; + int vdd_last, ret, i2caddress = I2C_VOL_MONITOR_ADDR; ret = i2c_multiplexer_select_vid_channel(I2C_MUX_CH_VOL_MONITOR); if (ret) { diff --git a/board/freescale/common/vid.h b/board/freescale/common/vid.h index 5bbaecace4..da6f018391 100644 --- a/board/freescale/common/vid.h +++ b/board/freescale/common/vid.h @@ -7,16 +7,17 @@ #ifndef __VID_H_ #define __VID_H_ +/* IR36021 command codes */ #define IR36021_LOOP1_MANUAL_ID_OFFSET 0x6A #define IR36021_LOOP1_VOUT_OFFSET 0x9A #define IR36021_MFR_ID_OFFSET 0x92 #define IR36021_MFR_ID 0x43 -#define IR36021_INTEL_MODE_OOFSET 0x14 +#define IR36021_INTEL_MODE_OFFSET 0x14 #define IR36021_MODE_MASK 0x20 #define IR36021_INTEL_MODE 0x00 #define IR36021_AMD_MODE 0x20 -/* step the IR regulator in 5mV increments */ +/* Step the IR regulator in 5mV increments */ #define IR_VDD_STEP_DOWN 5 #define IR_VDD_STEP_UP 5 @@ -56,6 +57,7 @@ defined(CONFIG_TARGET_LX2160ARDB) #define PWM_CHANNEL0 0x0 #define PMBUS_CMD_PAGE 0x0 #define PMBUS_CMD_READ_VOUT 0x8B +#define PMBUS_CMD_VOUT_MODE 0x20 #define PMBUS_CMD_VOUT_COMMAND 0x21 #define PMBUS_CMD_PAGE_PLUS_WRITE 0x05 @@ -68,5 +70,6 @@ defined(CONFIG_TARGET_LX2160ARDB) #endif int adjust_vdd(ulong vdd_override); +u16 soc_get_fuse_vid(int vid_index); #endif /* __VID_H_ */ diff --git a/board/freescale/ls1028a/ls1028a.c b/board/freescale/ls1028a/ls1028a.c index e37e3a3c16..a2d2e15787 100644 --- a/board/freescale/ls1028a/ls1028a.c +++ b/board/freescale/ls1028a/ls1028a.c @@ -130,6 +130,48 @@ int misc_init_r(void) } #endif +#ifdef CONFIG_VID +u16 soc_get_fuse_vid(int vid_index) +{ + static const u16 vdd[32] = { + 10500, + 0, /* reserved */ + 9750, + 0, /* reserved */ + 9500, + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 9000, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 10000, /* 1.0000V */ + 0, /* reserved */ + 10250, + 0, /* reserved */ + 10500, + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + }; + + return vdd[vid_index]; +}; +#endif + int board_early_init_f(void) { #ifdef CONFIG_LPUART diff --git a/board/freescale/ls1088a/ls1088a.c b/board/freescale/ls1088a/ls1088a.c index 5d19702a05..2dba62c524 100644 --- a/board/freescale/ls1088a/ls1088a.c +++ b/board/freescale/ls1088a/ls1088a.c @@ -185,6 +185,46 @@ int init_func_vid(void) return 0; } + +u16 soc_get_fuse_vid(int vid_index) +{ + static const u16 vdd[32] = { + 10250, + 9875, + 9750, + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 9000, + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 10000, /* 1.0000V */ + 10125, + 10250, + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + }; + + return vdd[vid_index]; +}; #endif int is_pb_board(void) diff --git a/board/freescale/ls2080a/ls2080a.c b/board/freescale/ls2080a/ls2080a.c index 62da2a7af1..fec3f7a835 100644 --- a/board/freescale/ls2080a/ls2080a.c +++ b/board/freescale/ls2080a/ls2080a.c @@ -50,6 +50,55 @@ void detail_board_ddr_info(void) #endif } +#if defined(CONFIG_ARCH_MISC_INIT) +int arch_misc_init(void) +{ + return 0; +} +#endif + +#ifdef CONFIG_VID +u16 soc_get_fuse_vid(int vid_index) +{ + static const u16 vdd[32] = { + 10500, + 0, /* reserved */ + 9750, + 0, /* reserved */ + 9500, + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 9000, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 10000, /* 1.0000V */ + 0, /* reserved */ + 10250, + 0, /* reserved */ + 10500, + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + }; + + return vdd[vid_index]; +}; +#endif + int board_eth_init(struct bd_info *bis) { int error = 0; diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c index ea027bec56..5ac6d0e746 100644 --- a/board/freescale/lx2160a/lx2160a.c +++ b/board/freescale/lx2160a/lx2160a.c @@ -648,6 +648,48 @@ int misc_init_r(void) } #endif +#ifdef CONFIG_VID +u16 soc_get_fuse_vid(int vid_index) +{ + static const u16 vdd[32] = { + 8250, + 7875, + 7750, + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 8000, + 8125, + 8250, + 0, /* reserved */ + 8500, + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + }; + + return vdd[vid_index]; +}; +#endif + #ifdef CONFIG_FSL_MC_ENET extern int fdt_fixup_board_phy(void *fdt); diff --git a/include/configs/ls1088aqds.h b/include/configs/ls1088aqds.h index b92ec14c69..a2b21c697f 100644 --- a/include/configs/ls1088aqds.h +++ b/include/configs/ls1088aqds.h @@ -326,12 +326,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_VOL_MONITOR_LTC3882_SET #define CONFIG_VOL_MONITOR_LTC3882_READ -/* PM Bus commands code for LTC3882*/ -#define PMBUS_CMD_PAGE 0x0 -#define PMBUS_CMD_READ_VOUT 0x8B -#define PMBUS_CMD_PAGE_PLUS_WRITE 0x05 -#define PMBUS_CMD_VOUT_COMMAND 0x21 - #define PWM_CHANNEL0 0x0 /* diff --git a/include/configs/ls1088ardb.h b/include/configs/ls1088ardb.h index f59a9f5574..6f36dd417a 100644 --- a/include/configs/ls1088ardb.h +++ b/include/configs/ls1088ardb.h @@ -203,7 +203,7 @@ #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 -#define I2C_MUX_CH_VOL_MONITOR 0xA +#define I2C_MUX_CH_VOL_MONITOR 0xA /* Voltage monitor on channel 2*/ #define I2C_VOL_MONITOR_ADDR 0x63 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 @@ -221,12 +221,6 @@ #define CONFIG_VOL_MONITOR_LTC3882_SET #define CONFIG_VOL_MONITOR_LTC3882_READ -/* PM Bus commands code for LTC3882*/ -#define PMBUS_CMD_PAGE 0x0 -#define PMBUS_CMD_READ_VOUT 0x8B -#define PMBUS_CMD_PAGE_PLUS_WRITE 0x05 -#define PMBUS_CMD_VOUT_COMMAND 0x21 - #define PWM_CHANNEL0 0x0 /* -- 2.17.1

1 0

[PATCH 00/30] test: Refactor tests to have a single test runner
by Simon Glass 28 Jan '21

28 Jan '21

At present U-Boot has two broad sets of tests in the C code: driver model tests which do a lot of pre-/post-init and command tests which do not. This separation makes it slightly harder to write a test, since there are two different test-state structures and different rules for running the two different test types. At present these rules are determined by where the test is (actually its prefix). All unit tests can be run from the command line with the 'ut' command. Since SPL does not have commands, it currently calls the test runner directly and offers no control of which tests are run. This seems like a good time to refactor the tests into a unified test runner, allowing U-Boot proper and SPL to use the same path, perhaps with some different conditions along the way. This series sets up a unified runner called ut_run_list(), which runs a set of tests from a linker_list. Driver model tests are distinguished by a new UT_TESTF_DM flag so that the necessary init and cleanup can still be done. This should make it easier to add SPL tests. A future series may tweak those as well. This series is available at u-boot-dm/test-working Simon Glass (30): doc: Tidy up testing section doc: Document make tcheck sandbox: Drop the 'starting...' message unless testing doc: Explain how to run tests without pytest doc: Document how sandbox_spl_tests are run test: Correct setexpr test prefix test: Mark all driver model tests with a flag test: Rename test-main.c to test-dm.c test: Add an overall test runner test: Create pre/post-run functions test: Call test_pre/post_run() from driver model tests test: Move dm_extended_scan() to test_pre_run() test: Move do_autoprobe() to test_pre_run() test: Move dm_scan_plat() to test_pre_run() test: Drop mallinfo() work-around test: Move console silencing to test_pre_run() test: Move delay skipping to test_pre_run() test: Handle driver model reinit in test_pre_run() test: Drop struct dm_test_state test: Move dm_test_init() into test-main.c test: Move dm_test_destroy() into test-main.c test: Move test running into a separate function test: Use ut_run_test() to run driver model tests test: Drop dm_do_test() test: Add ut_run_test_live_flat() to run tests twice test: Use a local variable for test state test: Run driver-model tests using ut_run_list() test: Use return values in dm_test_run() test: Move the devicetree check into ut_run_list() test: Move restoring of driver model state to ut_run_list() arch/sandbox/cpu/spl.c | 2 +- arch/sandbox/cpu/start.c | 15 +- arch/sandbox/include/asm/state.h | 1 + doc/develop/index.rst | 1 + doc/develop/testing.rst | 34 ++- doc/develop/tests_under.rst | 138 ++++++++++ include/dm/test.h | 20 +- include/test/test.h | 18 +- include/test/ut.h | 45 ++++ test/Makefile | 2 + test/cmd/setexpr.c | 23 +- test/cmd_ut.c | 38 +-- test/dm/Makefile | 2 +- test/dm/core.c | 47 ++-- test/dm/test-dm.c | 41 +++ test/dm/test-driver.c | 12 +- test/dm/test-main.c | 229 ----------------- test/dm/test-uclass.c | 10 +- test/py/tests/test_log.py | 2 +- test/test-main.c | 416 +++++++++++++++++++++++++++++++ test/ut.c | 7 + 21 files changed, 767 insertions(+), 336 deletions(-) create mode 100644 doc/develop/tests_under.rst create mode 100644 test/dm/test-dm.c delete mode 100644 test/dm/test-main.c create mode 100644 test/test-main.c -- 2.30.0.280.ga3ce27912f-goog

2 33

[PATCH v1 6/7] fix sst26_process_bpr check
by Bernhard Kirchen 28 Jan '21

28 Jan '21

the sst26_process_bpr function is supposed to check whether a particular protection bit is set (write-lock active). the caller always returns with EACCES when sst26_process_bpr returns true. the previous implementation (double negation) causes the caller to abort checking protection bits when the first bit expected to be set is set. in order to check whether a particular region is (completely) write-protected, all bits enabling write-protection for all relevant blocks (blocks within the region) must be set. checking for bits can be aborted if a required bit is NOT set, i.e., if sst26_process_bpr returns true. the test whether the region is locked then fails, indicated by (positive) return value EACCES. checking for bits must continue while the required bits are found to be set. only if all expected bits were found to be set, return value 0 indicates that no error occurred and all relevant bits are set. Signed-off-by: Bernhard Kirchen <bernhard.kirchen(a)mbconnectline.com> --- drivers/mtd/spi/spi-nor-core.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index b3873aaf6e..0b48e068be 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -982,6 +982,9 @@ enum lock_ctl { SST26_CTL_CHECK }; +/* + * returns false for "no error" and true for "expected protection bit is NOT set" + */ static bool sst26_process_bpr(u32 bpr_size, u8 *cmd, u32 bit, enum lock_ctl ctl) { switch (ctl) { @@ -992,7 +995,7 @@ static bool sst26_process_bpr(u32 bpr_size, u8 *cmd, u32 bit, enum lock_ctl ctl) cmd[bpr_size - (bit / 8) - 1] &= ~BIT(bit % 8); break; case SST26_CTL_CHECK: - return !!(cmd[bpr_size - (bit / 8) - 1] & BIT(bit % 8)); + return !(cmd[bpr_size - (bit / 8) - 1] & BIT(bit % 8)); } return false; @@ -1071,6 +1074,11 @@ static int sst26_hardware_write_protection(struct spi_nor *nor, bool lock) /* * Lock, unlock or check lock status of the flash region of the flash (depending * on the lock_ctl value) + * + * if lock_ctl == SST26_CTL_CHECK, returns EACCES (positive value) if region is + * NOT locked, 0 if region is locked, and negative on errors. + * + * otherwise returns 0 on success, negative value on error. */ static int sst26_lock_ctl(struct spi_nor *nor, loff_t ofs, uint64_t len, enum lock_ctl ctl) { @@ -1200,10 +1208,6 @@ static int sst26_lock(struct spi_nor *nor, loff_t ofs, uint64_t len) return sst26_lock_ctl(nor, ofs, len, SST26_CTL_LOCK); } -/* - * Returns EACCES (positive value) if region is locked, 0 if region is unlocked, - * and negative on errors. - */ static int sst26_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len) { /* -- 2.29.2

1 0

[PATCH v1 5/7] sf protect (un)lock for SST26*: test BPR values
by Bernhard Kirchen 28 Jan '21

28 Jan '21

after writing new block protection bits, read back the block protection bit register and test whether the desired settings were accepted. fail with error message otherwise. this adjusts the behavior of "sf protect (un)lock" for SST26* chips to be similar to the (un)locking behavior of Micron-compatible chips, where the statur register is read back and checked after writing it with the new block protection bit setting. comparing the desired and current values fails if hardware write protection is enabled (SRWD (Micron) or WPEN (SST26*) bit set), and the WP# pin is not asserted, as the respective registers are write-protected in that case. Signed-off-by: Bernhard Kirchen <bernhard.kirchen(a)mbconnectline.com> --- drivers/mtd/spi/spi-nor-core.c | 55 +++++++++++++++++++++++++++++----- 1 file changed, 48 insertions(+), 7 deletions(-) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 10c01cf20e..b3873aaf6e 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -998,6 +998,47 @@ static bool sst26_process_bpr(u32 bpr_size, u8 *cmd, u32 bit, enum lock_ctl ctl) return false; } +static int sst26_read_bpr(struct spi_nor *nor, u8 *buff, u32 *len) +{ + struct mtd_info *mtd = &nor->mtd; + u32 bpr_size; + int ret; + + bpr_size = 2 + (mtd->size / SZ_64K / 8); + + if (*len < bpr_size) { + dev_err(nor->dev, "block-protection register buffer too small\n"); + return -EINVAL; + } + + ret = nor->read_reg(nor, SPINOR_OP_READ_BPR, buff, bpr_size); + if (ret < 0) { + dev_err(nor->dev, "failed to read block-protection register\n"); + return ret; + } + + *len = bpr_size; + return 0; +} + +static int sst26_check_bpr(struct spi_nor *nor, u8 *expected_buf, u32 expected_len) +{ + u8 actual_buf[SST26_MAX_BPR_REG_LEN] = {}; + u32 actual_len = SST26_MAX_BPR_REG_LEN; + int ret; + + ret = sst26_read_bpr(nor, actual_buf, &actual_len); + if (ret < 0) + return ret; + + if (expected_len != actual_len || memcmp(expected_buf, actual_buf, actual_len)) { + dev_err(nor->dev, "device did not accept new block protection bits\n"); + return -EACCES; + } + + return 0; +} + static int sst26_hardware_write_protection(struct spi_nor *nor, bool lock) { int ret; @@ -1034,7 +1075,7 @@ static int sst26_hardware_write_protection(struct spi_nor *nor, bool lock) static int sst26_lock_ctl(struct spi_nor *nor, loff_t ofs, uint64_t len, enum lock_ctl ctl) { struct mtd_info *mtd = &nor->mtd; - u32 i, bpr_ptr, rptr_64k, lptr_64k, bpr_size; + u32 i, bpr_ptr, rptr_64k, lptr_64k, bpr_size = SST26_MAX_BPR_REG_LEN; bool lower_64k = false, upper_64k = false; u8 bpr_buff[SST26_MAX_BPR_REG_LEN] = {}; int ret; @@ -1057,13 +1098,9 @@ static int sst26_lock_ctl(struct spi_nor *nor, loff_t ofs, uint64_t len, enum lo mtd->size != SZ_8M) return -EINVAL; - bpr_size = 2 + (mtd->size / SZ_64K / 8); - - ret = nor->read_reg(nor, SPINOR_OP_READ_BPR, bpr_buff, bpr_size); - if (ret < 0) { - dev_err(nor->dev, "fail to read block-protection register\n"); + ret = sst26_read_bpr(nor, bpr_buff, &bpr_size); + if (ret < 0) return ret; - } rptr_64k = min_t(u32, ofs + len, mtd->size - SST26_BOUND_REG_SIZE); lptr_64k = max_t(u32, ofs, SST26_BOUND_REG_SIZE); @@ -1134,6 +1171,10 @@ static int sst26_lock_ctl(struct spi_nor *nor, loff_t ofs, uint64_t len, enum lo return ret; } + ret = sst26_check_bpr(nor, bpr_buff, bpr_size); + if (ret < 0) + return ret; + // enable hardware write protection iff any protection bit is set for (i = 0; i < bpr_size; ++i) if (bpr_buff[i] != 0) -- 2.29.2

1 0

[PATCH v2 0/3] sunxi: OrangePi Zero 2: Ethernet support
by Andre Przywara 28 Jan '21

28 Jan '21

The first two patches prepare the sun8i-emac driver to deal with the EMAC as integrated into the H616 SoC. This IP block is compatible with the A64 version, but the current driver prevents us from using that: - The EPHY syscon register needs to have a bit cleared to select the external PHY. On the A64 it is cleared on reset, but we should not rely on that. The Linux driver does so as well. Fixed in patch 1/3. - The pinmux setting is tied to the compatible string, but the H616 requires a different value. Fixed in patch 2/3. The final patch enables Ethernet support for the OrangePi Zero 2 board, which now works without further ado. Cheers, Andre Andre Przywara (3): net: sun8i-emac: Always clear syscon EPHY register net: sun8i-emac: Determine pinmux based on SoC, not EMAC type sunxi: OrangePi Zero 2: Enable Ethernet configs/orangepi_zero2_defconfig | 2 ++ drivers/net/sun8i_emac.c | 59 ++++++++++++++++++-------------- 2 files changed, 35 insertions(+), 26 deletions(-) -- 2.17.5

2 4

[PATCH 1/1] doc: describe load command
by Heinrich Schuchardt 28 Jan '21

28 Jan '21

Man-page for load command. Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- doc/usage/index.rst | 1 + doc/usage/load.rst | 74 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 75 insertions(+) create mode 100644 doc/usage/load.rst diff --git a/doc/usage/index.rst b/doc/usage/index.rst index 83cfbafd90..5754958d7e 100644 --- a/doc/usage/index.rst +++ b/doc/usage/index.rst @@ -23,6 +23,7 @@ Shell commands exit false for + load loady mbr pstore diff --git a/doc/usage/load.rst b/doc/usage/load.rst new file mode 100644 index 0000000000..1efee77317 --- /dev/null +++ b/doc/usage/load.rst @@ -0,0 +1,74 @@ +.. SPDX-License-Identifier: GPL-2.0+: + +load command +============ + +Synopsis +-------- + +:: + + load <interface> [<dev[:part]> [<addr> [<filename> [bytes [pos]]]]] + +Description +----------- + +The load command is used to read a file from a filesystem into memory. + +The number of transferred bytes is saved in the environment variable filesize. +The load address is saved in the environment variable fileaddr. + +interface + interface for accessing the block device (mmc, sata, scsi, usb, ....) + +dev + device number + +part + partition number, defaults to 0 (whole device) + +addr + load address, defaults to environment variable loadaddr or if loadaddr is + not set to configuration variable CONFIG_SYS_LOAD_ADDR + +filename + path to file, defaults to environment variable bootfile + +bytes + maximum number of bytes to load + +pos + number of bytes to skip + +addr, bytes, pos are hexadecimal numbers. + +Example +------- + +:: + + => load mmc 0:1 ${kernel_addr_r} snp.efi + 149280 bytes read in 11 ms (12.9 MiB/s) + => + => load mmc 0:1 ${kernel_addr_r} snp.efi 1000000 + 149280 bytes read in 9 ms (15.8 MiB/s) + => + => load mmc 0:1 ${kernel_addr_r} snp.efi 1000000 100 + 149024 bytes read in 10 ms (14.2 MiB/s) + => + => load mmc 0:1 ${kernel_addr_r} snp.efi 10 + 16 bytes read in 1 ms (15.6 KiB/s) + => + +Configuration +------------- + +The load command is only available if CONFIG_CMD_FS_GENERIC=y. + +Return value +------------ + +The return value $? is set to 0 (true) if the file was successfully loaded +even if the number of bytes is less then the specified length. + +If an error occurs, the return value $? is set to 1 (false). -- 2.29.2

2 1

arm64: rk3399: add support NanoPi R4S
by alex tian 28 Jan '21

28 Jan '21

>From d67b0ea0d3ebd53896146c651dbb4b35db4d073e Mon Sep 17 00:00:00 2001 From: Xiaobo Tian <peterwillcn(a)gmail.com> Date: Thu, 28 Jan 2021 21:30:40 +0800 Subject: [PATCH] arm64: rk3399: Add support NanoPi R4s NanoPi R4s [1] is SBC base on Rockchip RK3399 hexa-core processor with dual-Core Cortex-A72 and Mali-T864 GPU with 4GiB(LPDDR4) of RAM, SD card support, including 2 gigabit ethernet(RTL8211E 1Gbps - RTL8111H 1Gbps) and 2 USB 3.0 port. port.It also has two GPIO headers which allows further peripherals to be used. The devicetree file is taken of the rk3399 nanopi4 Linux kernel [2]. [1] https://wiki.friendlyarm.com/wiki/index.php/NanoPi_R4S [2] https://github.com/torvalds/linux/blob/master/arch/arm64/boot/dts/rockchip/… Cc: Tom Rini <trini(a)konsulko.com> Cc: Kever Yang <kever.yang(a)rock-chips.com> Reviewed-by: Kever Yang <kever.yang(a)rock-chips.com> Signed-off-by: Xiaobo Tian <peterwillcn(a)gmail.com> --- arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3399-nanopi-r4s-u-boot.dtsi | 7 ++ arch/arm/dts/rk3399-nanopi-r4s.dts | 126 +++++++++++++++++++++ configs/nanopi-r4s-rk3399_defconfig | 62 ++++++++++ 4 files changed, 196 insertions(+) create mode 100644 arch/arm/dts/rk3399-nanopi-r4s-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-nanopi-r4s.dts create mode 100644 configs/nanopi-r4s-rk3399_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 858b79ac97..528dfe069e 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -92,6 +92,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3288) += \ rk3288-evb.dtb \ rk3288-firefly.dtb \ rk3288-miqi.dtb \ + rk3399-nanopi-r4s.dtb \ rk3288-phycore-rdk.dtb \ rk3288-popmetal.dtb \ rk3288-rock2-square.dtb \ diff --git a/arch/arm/dts/rk3399-nanopi-r4s-u-boot.dtsi b/arch/arm/dts/rk3399-nanopi-r4s-u-boot.dtsi new file mode 100644 index 0000000000..df193f0e64 --- /dev/null +++ b/arch/arm/dts/rk3399-nanopi-r4s-u-boot.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020 Xiaobo <peterwillcn(a)gmail.com> + */ + +#include "rk3399-nanopi4-u-boot.dtsi" +#include "rk3399-sdram-lpddr4-100.dtsi" diff --git a/arch/arm/dts/rk3399-nanopi-r4s.dts b/arch/arm/dts/rk3399-nanopi-r4s.dts new file mode 100644 index 0000000000..8f3e9cc48f --- /dev/null +++ b/arch/arm/dts/rk3399-nanopi-r4s.dts @@ -0,0 +1,126 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyarm.com) + * + * Copyright (C) 2020 Xiaobo <peterwillcn(a)gmail.com> + */ + +/dts-v1/; +#include "rk3399-nanopi4.dtsi" + +/ { + model = "FriendlyElec NanoPi R4S"; + compatible = "friendlyarm,nanopi-r4s", "rockchip,rk3399"; + + clkin_gmac: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "clkin_gmac"; + #clock-cells = <0>; + }; + + vdd_5v: vdd-5v { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v"; + regulator-always-on; + regulator-boot-on; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + cooling-levels = <0 12 18 255>; + #cooling-cells = <2>; + fan-supply = <&vdd_5v>; + pwms = <&pwm1 0 50000 0>; + }; +}; + +&cpu_thermal { + trips { + cpu_warm: cpu_warm { + temperature = <55000>; + hysteresis = <2000>; + type = "active"; + }; + + cpu_hot: cpu_hot { + temperature = <65000>; + hysteresis = <2000>; + type = "active"; + }; + }; + + cooling-maps { + map2 { + trip = <&cpu_warm>; + cooling-device = <&fan THERMAL_NO_LIMIT 1>; + }; + + map3 { + trip = <&cpu_hot>; + cooling-device = <&fan 2 THERMAL_NO_LIMIT>; + }; + }; +}; + +&emmc_phy { + status = "disabled"; +}; + +&fusb0 { + status = "disabled"; +}; + +&leds { + lan_led: led-1 { + gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>; + label = "nanopi-r4s:green:lan"; + }; + + wan_led: led-2 { + gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; + label = "nanopi-r4s:green:wan"; + }; +}; + +&leds_gpio { + rockchip,pins = + <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>, + <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>, + <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; +}; + +&pcie0 { + max-link-speed = <1>; + num-lanes = <1>; + vpcie3v3-supply = <&vcc3v3_sys>; +}; + +&sdhci { + status = "disabled"; +}; + +&sdio0 { + status = "disabled"; +}; + +&sdmmc { + host-index-min = <1>; +}; + +&u2phy0_host { + phy-supply = <&vdd_5v>; +}; + +&u2phy1_host { + status = "disabled"; +}; + +&usbdrd_dwc3_0 { + dr_mode = "host"; +}; + +&vcc3v3_sys { + vin-supply = <&vcc5v0_sys>; +}; diff --git a/configs/nanopi-r4s-rk3399_defconfig b/configs/nanopi-r4s-rk3399_defconfig new file mode 100644 index 0000000000..0a3c28b012 --- /dev/null +++ b/configs/nanopi-r4s-rk3399_defconfig @@ -0,0 +1,62 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_ENV_OFFSET=0x3F8000 +CONFIG_ROCKCHIP_RK3399=y +CONFIG_TARGET_EVB_RK3399=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEBUG_UART_BASE=0xFF1A0000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-r4s.dtb" +CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_TPL=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-r4s" +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM_RK3399_LPDDR4=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_KEYBOARD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_DM_VIDEO=y +CONFIG_DISPLAY=y +CONFIG_VIDEO_ROCKCHIP=y +CONFIG_DISPLAY_ROCKCHIP_HDMI=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_ERRNO_STR=y -- 2.30.0

1 0

[RFC 0/2] Add ESRT and test ESRT creation
by Jose Marinho 28 Jan '21

28 Jan '21

The following 2 commits add the ESRT and provide some intial testing. The first commit adds the ESRT as defined in the UEFI 2.8 specification. The ESRT is created during the execution of the efi_init_obj_list(). The ESRT will, during initialization, look for FMP instances already present in the system and populate the corresponding FW image entries. When a new FMP is added, via efi_add_protocol(), the method esrt_add_from_fmp() is called to populate the corresponding ESRT entries. The second commit creates a fake FMP instance with the intent of testing the code populating the ESRT entries. CC: Heinrich Schuchardt <xypron.glpki(a)gmx.de> CC: Sughosh Ganu <sughosh.ganu(a)linaro.org> CC: AKASHI Takahiro <takahiro.akashi(a)linaro.org> CC: Andre Przywara <andre.przywara(a)arm.com> CC: Alexander Graf <agraf(a)csgraf.de> CC: nd(a)arm.com Jose Marinho (2): efi: Add ESRT to the EFI system table efi: Add fake FMP instance to test ESRT creation include/efi_api.h | 21 +++ include/efi_loader.h | 22 +++ lib/efi_loader/Makefile | 2 + lib/efi_loader/efi_boottime.c | 12 ++ lib/efi_loader/efi_esrt.c | 294 ++++++++++++++++++++++++++++++++++ lib/efi_loader/efi_fake_fmp.c | 172 ++++++++++++++++++++ lib/efi_loader/efi_setup.c | 4 + 7 files changed, 527 insertions(+) create mode 100644 lib/efi_loader/efi_esrt.c create mode 100644 lib/efi_loader/efi_fake_fmp.c -- 2.17.1

1 2

arm64: rk3399: add support NanoPi R4S
by alex tian 28 Jan '21

28 Jan '21

>From bc4d38377b8f745b39f3028a14dff23203ee39d3 Mon Sep 17 00:00:00 2001 From: Xiaobo Tian <peterwillcn(a)gmail.com> Date: Thu, 28 Jan 2021 20:58:52 +0800 Subject: [PATCH] arm64: rk3399: Add support NanoPi R4s NanoPi R4s [1] is SBC base on Rockchip RK3399 hexa-core processor with dual-Core Cortex-A72 and Mali-T864 GPU with 4GiB(LPDDR4) of RAM, SD card support, including 2 gigabit ethernet(RTL8211E 1Gbps - RTL8111H 1Gbps) and 2 USB 3.0 port. port.It also has two GPIO headers which allows further peripherals to be used. The devicetree file is taken of the rk3399 nanopi4 Linux kernel [2]. [1] https://wiki.friendlyarm.com/wiki/index.php/NanoPi_R4S [2] https://github.com/torvalds/linux/blob/master/arch/arm64/boot/dts/rockchip/… Cc: Tom Rini <trini(a)konsulko.com> Cc: Kever Yang <kever.yang(a)rock-chips.com> Reviewed-by: Kever Yang <kever.yang(a)rock-chips.com> Signed-off-by: Xiaobo Tian <peterwillcn(a)gmail.com> --- arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3399-nanopi-r4s-u-boot.dtsi | 7 ++ arch/arm/dts/rk3399-nanopi-r4s.dts | 120 +++++++++++++++++++++ configs/nanopi-r4s-rk3399_defconfig | 62 +++++++++++ 4 files changed, 190 insertions(+) create mode 100644 arch/arm/dts/rk3399-nanopi-r4s-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-nanopi-r4s.dts create mode 100644 configs/nanopi-r4s-rk3399_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 858b79ac97..528dfe069e 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -92,6 +92,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3288) += \ rk3288-evb.dtb \ rk3288-firefly.dtb \ rk3288-miqi.dtb \ + rk3399-nanopi-r4s.dtb \ rk3288-phycore-rdk.dtb \ rk3288-popmetal.dtb \ rk3288-rock2-square.dtb \ diff --git a/arch/arm/dts/rk3399-nanopi-r4s-u-boot.dtsi b/arch/arm/dts/rk3399-nanopi-r4s-u-boot.dtsi new file mode 100644 index 0000000000..05f785e662 --- /dev/null +++ b/arch/arm/dts/rk3399-nanopi-r4s-u-boot.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020 Xiaobo <tianxiaobo(a)gelaxy.io> + */ + +#include "rk3399-nanopi4-u-boot.dtsi" +#include "rk3399-sdram-lpddr4-100.dtsi" diff --git a/arch/arm/dts/rk3399-nanopi-r4s.dts b/arch/arm/dts/rk3399-nanopi-r4s.dts new file mode 100644 index 0000000000..5c65447f0e --- /dev/null +++ b/arch/arm/dts/rk3399-nanopi-r4s.dts @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyarm.com) + * + * Copyright (C) 2020 Xiaobo <tianxiaobo(a)gelaxy.io> + */ + +/dts-v1/; +#include "rk3399-nanopi4.dtsi" + +/ { + model = "FriendlyElec NanoPi R4S"; + compatible = "friendlyarm,nanopi-r4s", "rockchip,rk3399"; + + vdd_5v: vdd-5v { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v"; + regulator-always-on; + regulator-boot-on; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + /* FIXME: adjust leveles for the connected fan */ + cooling-levels = <0 12 18 255>; + #cooling-cells = <2>; + fan-supply = <&vdd_5v>; + pwms = <&pwm1 0 50000 0>; + }; +}; + +&cpu_thermal { + trips { + cpu_warm: cpu_warm { + temperature = <55000>; + hysteresis = <2000>; + type = "active"; + }; + + cpu_hot: cpu_hot { + temperature = <65000>; + hysteresis = <2000>; + type = "active"; + }; + }; + + cooling-maps { + map2 { + trip = <&cpu_warm>; + cooling-device = <&fan THERMAL_NO_LIMIT 1>; + }; + + map3 { + trip = <&cpu_hot>; + cooling-device = <&fan 2 THERMAL_NO_LIMIT>; + }; + }; +}; + +&emmc_phy { + status = "disabled"; +}; + +&fusb0 { + status = "disabled"; +}; + +&leds { + lan_led: led-1 { + gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>; + label = "nanopi-r4s:green:lan"; + }; + + wan_led: led-2 { + gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; + label = "nanopi-r4s:green:wan"; + }; +}; + +&leds_gpio { + rockchip,pins = + <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>, + <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>, + <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; +}; + +&pcie0 { + max-link-speed = <1>; + num-lanes = <1>; + vpcie3v3-supply = <&vcc3v3_sys>; +}; + +&sdhci { + status = "disabled"; +}; + +&sdio0 { + status = "disabled"; +}; + +&sdmmc { + host-index-min = <1>; +}; + +&u2phy0_host { + phy-supply = <&vdd_5v>; +}; + +&u2phy1_host { + status = "disabled"; +}; + +&usbdrd_dwc3_0 { + dr_mode = "host"; +}; + +&vcc3v3_sys { + vin-supply = <&vcc5v0_sys>; +}; diff --git a/configs/nanopi-r4s-rk3399_defconfig b/configs/nanopi-r4s-rk3399_defconfig new file mode 100644 index 0000000000..0a3c28b012 --- /dev/null +++ b/configs/nanopi-r4s-rk3399_defconfig @@ -0,0 +1,62 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_ENV_OFFSET=0x3F8000 +CONFIG_ROCKCHIP_RK3399=y +CONFIG_TARGET_EVB_RK3399=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEBUG_UART_BASE=0xFF1A0000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-r4s.dtb" +CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_TPL=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-r4s" +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM_RK3399_LPDDR4=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_KEYBOARD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_DM_VIDEO=y +CONFIG_DISPLAY=y +CONFIG_VIDEO_ROCKCHIP=y +CONFIG_DISPLAY_ROCKCHIP_HDMI=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_ERRNO_STR=y -- 2.30.0

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