September 2020 - U-Boot

make_fit_atf.py and multiple U-Boot ELF segments
by Tom Rini 08 Sep '20

08 Sep '20

Hey all, As part of reviewing http://patchwork.ozlabs.org/project/uboot/list/?series=187450&state=* I've run in to an odd problem. With patch 4/7 of that series, building firefly-rk3399 fails on the make_fit_atf.py step as those changes end up with a U-Boot ELF that has len(segments) of 2, rather than 1, and the generator blows up. It's not clear to me if we can just check for non-zero number of segments here or what. Thanks! -- Tom

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[PATCH] ARM: at91: common: guard ATMEL_PIT code by ifdef
by Eugen Hristev 08 Sep '20

08 Sep '20

Atmel PIT timer is not available for next products that have another timer hardware block. To be able to use the common at91 code, guard the code that uses PIT by ifdefs. Signed-off-by: Eugen Hristev <eugen.hristev(a)microchip.com> --- arch/arm/mach-at91/armv7/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-at91/armv7/cpu.c b/arch/arm/mach-at91/armv7/cpu.c index a8f4356ce9..8b7355042b 100644 --- a/arch/arm/mach-at91/armv7/cpu.c +++ b/arch/arm/mach-at91/armv7/cpu.c @@ -29,6 +29,7 @@ int arch_cpu_init(void) void arch_preboot_os(void) { +#if (IS_ENABLED(CONFIG_ATMEL_PIT_TIMER)) ulong cpiv; at91_pit_t *pit = (at91_pit_t *)ATMEL_BASE_PIT; @@ -40,6 +41,7 @@ void arch_preboot_os(void) * without waiting for wrapping back to 0 */ writel(cpiv + 0x1000, &pit->mr); +#endif } #if defined(CONFIG_DISPLAY_CPUINFO) -- 2.25.1

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[PATCH] board: atmel: common: introduce at91_set_eth1addr for second interface
by Eugen Hristev 08 Sep '20

08 Sep '20

We already have a function to retrieve the mac address from one EEPROM. For boards with a second Ethernet interface, however, we would require another EEPROM with a second unique MAC address. Introduce at91_set_eth1addr which will look for a second EEPROM and set the 'eth1addr' variable with the obtained MAC address. Signed-off-by: Eugen Hristev <eugen.hristev(a)microchip.com> --- arch/arm/mach-at91/include/mach/at91_common.h | 1 + board/atmel/common/mac_eeprom.c | 33 +++++++++++++++++++ 2 files changed, 34 insertions(+) diff --git a/arch/arm/mach-at91/include/mach/at91_common.h b/arch/arm/mach-at91/include/mach/at91_common.h index 01e00c508a..f7b411cf7d 100644 --- a/arch/arm/mach-at91/include/mach/at91_common.h +++ b/arch/arm/mach-at91/include/mach/at91_common.h @@ -40,6 +40,7 @@ void configure_ddrcfg_input_buffers(bool open); #endif int at91_set_ethaddr(int offset); +int at91_set_eth1addr(int offset); void at91_spi_nor_set_ethaddr(void); int at91_video_show_board_info(void); diff --git a/board/atmel/common/mac_eeprom.c b/board/atmel/common/mac_eeprom.c index 050aa51ee1..0f038beee6 100644 --- a/board/atmel/common/mac_eeprom.c +++ b/board/atmel/common/mac_eeprom.c @@ -35,3 +35,36 @@ int at91_set_ethaddr(int offset) return 0; } + +/* this function will set eth1addr from a second eeprom, if available */ +int at91_set_eth1addr(int offset) +{ + const int ETH_ADDR_LEN = 6; + unsigned char ethaddr[ETH_ADDR_LEN]; + /* configure eth1addr for second interface */ + const char *ETHADDR_NAME = "eth1addr"; + struct udevice *dev; + int ret; + + if (env_get(ETHADDR_NAME)) + return 0; + + /* first eeprom is retrieved, this is for the first interface */ + ret = uclass_first_device_err(UCLASS_I2C_EEPROM, &dev); + if (ret) + return ret; + + /* attempt to obtain a second eeprom device */ + ret = uclass_next_device(&dev); + if (ret) + return ret; + + ret = i2c_eeprom_read(dev, offset, ethaddr, 6); + if (ret) + return ret; + + if (is_valid_ethaddr(ethaddr)) + eth_env_set_enetaddr(ETHADDR_NAME, ethaddr); + + return 0; +} -- 2.25.1

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[PATCH v3 00/21] clk: at91: add sama7g5 support
by Claudiu Beznea 08 Sep '20

08 Sep '20

The purpose of this series is to add clock support for SAMA7G5. Along with this, clock drivers were switched to CCF and aligned with their corresponding versions present in Linux. Some changes were done for CCF, patches 1, 3, 4, 5 (I don't know if they were as is by intention of a fixes tag is needed in there). Also patch 3/21 has been added to support clock re-reparenting (this is minimal support and hope it doesn't break anything if used). Thank you, Claudiu Beznea Changes in v3: - collected remaining Reviewed-by tags - rebase on top of latest master branch: e5df264e7aac ("Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvell") to adapt patch 8/21 at changes from commit 702e57e113d8 ("treewide: convert devfdt_get_addr_ptr() to dev_read_addr_ptr()") Changes in v2: - use assert() in patch 1/21 - drop patch 2/22 from previous series - add sandbox tests for clock reparenting, device reparenting and critical clocks - adapt review comments - collected Reviewed-by tags Claudiu Beznea (21): clk: check hw and hw->dev before dereference it dm: core: add support for device re-parenting clk: bind clk to new parent device clk: do not disable clock if it is critical clk: get clock pointer before proceeding clk: at91: add pre-requisite headers for AT91 clock architecture clk: at91: pmc: add helpers for clock drivers clk: at91: move clock code to compat.c clk: at91: sckc: add driver compatible with ccf clk: at91: clk-main: add driver compatible with ccf clk: at91: sam9x60-pll: add driver compatible with ccf clk: at91: clk-master: add driver compatible with ccf clk: at91: clk-master: add support for sama7g5 clk: at91: clk-utmi: add driver compatible with ccf clk: at91: clk-utmi: add support for sama7g5 clk: at91: clk-programmable: add driver compatible with ccf clk: at91: clk-system: add driver compatible with ccf clk: at91: clk-peripheral: add driver compatible with ccf clk: at91: clk-generic: add driver compatible with ccf clk: at91: pmc: add generic clock ops clk: at91: sama7g5: add clock support drivers/clk/at91/Kconfig | 7 + drivers/clk/at91/Makefile | 15 +- drivers/clk/at91/clk-generated.c | 178 ----- drivers/clk/at91/clk-generic.c | 202 +++++ drivers/clk/at91/clk-h32mx.c | 56 -- drivers/clk/at91/clk-main.c | 381 +++++++++- drivers/clk/at91/clk-master.c | 331 ++++++++- drivers/clk/at91/clk-peripheral.c | 291 ++++++-- drivers/clk/at91/clk-plla.c | 54 -- drivers/clk/at91/clk-plladiv.c | 85 --- drivers/clk/at91/clk-programmable.c | 208 ++++++ drivers/clk/at91/clk-sam9x60-pll.c | 442 +++++++++++ drivers/clk/at91/clk-slow.c | 36 - drivers/clk/at91/clk-system.c | 143 ++-- drivers/clk/at91/clk-usb.c | 147 ---- drivers/clk/at91/clk-utmi.c | 234 ++++-- drivers/clk/at91/compat.c | 1023 +++++++++++++++++++++++++ drivers/clk/at91/pmc.c | 218 +++--- drivers/clk/at91/pmc.h | 140 +++- drivers/clk/at91/sama7g5.c | 1401 +++++++++++++++++++++++++++++++++++ drivers/clk/at91/sckc.c | 169 ++++- drivers/clk/clk-uclass.c | 51 +- drivers/clk/clk.c | 3 + drivers/core/device.c | 22 + include/dm/device-internal.h | 9 + include/dt-bindings/clk/at91.h | 22 + include/linux/clk/at91_pmc.h | 247 ++++++ test/dm/clk_ccf.c | 57 ++ test/dm/core.c | 160 ++++ 29 files changed, 5407 insertions(+), 925 deletions(-) delete mode 100644 drivers/clk/at91/clk-generated.c create mode 100644 drivers/clk/at91/clk-generic.c delete mode 100644 drivers/clk/at91/clk-h32mx.c delete mode 100644 drivers/clk/at91/clk-plla.c delete mode 100644 drivers/clk/at91/clk-plladiv.c create mode 100644 drivers/clk/at91/clk-programmable.c create mode 100644 drivers/clk/at91/clk-sam9x60-pll.c delete mode 100644 drivers/clk/at91/clk-slow.c delete mode 100644 drivers/clk/at91/clk-usb.c create mode 100644 drivers/clk/at91/compat.c create mode 100644 drivers/clk/at91/sama7g5.c create mode 100644 include/dt-bindings/clk/at91.h create mode 100644 include/linux/clk/at91_pmc.h -- 2.7.4

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[PATCH v3 0/7] riscv: Clean up timer drivers
by Sean Anderson 08 Sep '20

08 Sep '20

This series cleans up the timer drivers in RISC-V and converts them to DM. This series depends on [1]. This series needs to be tested! I have only tested it on QEMU and the K210. Notably, this means that the HiFive and anything Andes is completely untested. CI for this series is located at [2]. [1] https://patchwork.ozlabs.org/project/uboot/list/?series=190862 [2] https://dev.azure.com/seanga2/u-boot/_build/results?buildId=4 Changes in v3: - Don't initialize the IPI in spl_invoke_opensbi. Further testing has revealed it to be unnecessary. - Rebase Changes in v2: - Remove RISCV_RDTIME KConfig option - Split Kendryte binding changes into their own commit - Fix SiFive CLINT not getting tick-rate from rtcclk Sean Anderson (7): riscv: Rework riscv timer driver to only support S-mode riscv: Rework Andes PLMT as a UCLASS_TIMER driver riscv: Clean up initialization in Andes PLIC riscv: Rework Sifive CLINT as UCLASS_TIMER driver riscv: clk: Add CLINT clock to kendryte clock driver riscv: Update Kendryte device tree for new CLINT driver riscv: Update SiFive device tree for new CLINT driver arch/riscv/Kconfig | 16 ---- arch/riscv/dts/ae350_32.dts | 1 + arch/riscv/dts/ae350_64.dts | 1 + arch/riscv/dts/fu540-c000-u-boot.dtsi | 8 +- .../dts/hifive-unleashed-a00-u-boot.dtsi | 4 + arch/riscv/dts/k210.dtsi | 9 +- arch/riscv/include/asm/global_data.h | 3 - arch/riscv/lib/Makefile | 1 - arch/riscv/lib/andes_plic.c | 58 ++++++------- arch/riscv/lib/andes_plmt.c | 42 +++++---- arch/riscv/lib/rdtime.c | 38 -------- arch/riscv/lib/sifive_clint.c | 87 ++++++++++++------- drivers/clk/kendryte/clk.c | 4 + drivers/ram/sifive/Kconfig | 2 + drivers/timer/Kconfig | 6 +- drivers/timer/riscv_timer.c | 39 +++++---- include/dt-bindings/clock/k210-sysctl.h | 1 + 17 files changed, 150 insertions(+), 170 deletions(-) delete mode 100644 arch/riscv/lib/rdtime.c -- 2.28.0

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Changing U-boot relocation addres to SRAM (instead of DRAM)
by Yusuf Altıparmak 08 Sep '20

08 Sep '20

Hello, I want to modify U-boot to relocate itself to on-board SRAM of chip (T1042 demo board) instead of DRAM. At first, there is call list in u-boot/common/board_f.c and it has a line to call dram_init. I will change this line with my custom sram_init function. [image: Capture.PNG] The function board_f() is being called in start.S which is located at u-boot/arch/powerpc/cpu/mpc85xx/ start.S file also includes a region to relocate itself by changing Link Register. Code region is: */** ** void relocate_code(addr_sp, gd, addr_moni)* *** ** This "function" does not return, instead it continues in RAM* ** after relocating the monitor code.* *** ** r3 = dest* ** r4 = src* ** r5 = length in bytes* ** r6 = cachelinesize* **/* *.globl relocate_code* *relocate_code:* *mr r1,r3 /* Set new stack pointer */* *mr r9,r4 /* Save copy of Init Data pointer */* *mr r10,r5 /* Save copy of Destination Address */* *GET_GOT* *#ifndef CONFIG_SPL_SKIP_RELOCATE* *mr r3,r5 /* Destination Address */* *lis r4,CONFIG_SYS_MONITOR_BASE@h /* Source Address */* *ori r4,r4,CONFIG_SYS_MONITOR_BASE@l* *lwz r5,GOT(__init_end)* *sub r5,r5,r4* *li r6,CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */* My question is, in above code, how relocate_code() function is calculating the jump address of Link Register (CONFIG_SYS_MONITOR_BASE@h). What should be done to change it to point SRAM of t1042 after we initialize it in board_init_f() function. ? Thanks.

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[PATCH 1/1] efi_loader: efi_var_mem_notify_exit_boot_services
by Heinrich Schuchardt 08 Sep '20

08 Sep '20

efi_var_mem_notify_exit_boot_services() is invoked when ExitBootServices() is called by the UEFI payload. efi_var_mem_notify_exit_boot_services() should not be defined as __efi_runtime as it is invoking EFI_ENTRY() and EFI_EXIT() which themselves are not __efi_runtime. Fixes: f1f990a8c958 ("efi_loader: memory buffer for variables") Fixes: e01aed47d6a0 ("efi_loader: Enable run-time variable support for tee based variables") Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- lib/efi_loader/efi_var_mem.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/efi_loader/efi_var_mem.c b/lib/efi_loader/efi_var_mem.c index 8f4a5a5e47..1d2b44580f 100644 --- a/lib/efi_loader/efi_var_mem.c +++ b/lib/efi_loader/efi_var_mem.c @@ -211,7 +211,7 @@ static void efi_var_mem_bs_del(void) * @event: callback event * @context: callback context */ -static void EFIAPI __efi_runtime +static void EFIAPI efi_var_mem_notify_exit_boot_services(struct efi_event *event, void *context) { EFI_ENTRY("%p, %p", event, context); -- 2.20.1

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[PATCH v4 1/9] usb: xhci: add a member hci_version in xhci_ctrl struct
by Chunfeng Yun 08 Sep '20

08 Sep '20

Add a member to save xHCI version, it's used some times. Signed-off-by: Chunfeng Yun <chunfeng.yun(a)mediatek.com> Reviewed-by: Bin Meng <bmeng.cn(a)gmail.com> --- v4: no changes v3: add reviewed-by Bin v2: no changes --- drivers/usb/host/xhci-ring.c | 4 ++-- drivers/usb/host/xhci.c | 1 + include/usb/xhci.h | 1 + 3 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c index 092ed6e..79bfc34 100644 --- a/drivers/usb/host/xhci-ring.c +++ b/drivers/usb/host/xhci-ring.c @@ -682,7 +682,7 @@ int xhci_bulk_tx(struct usb_device *udev, unsigned long pipe, field |= TRB_ISP; /* Set the TRB length, TD size, and interrupter fields. */ - if (HC_VERSION(xhci_readl(&ctrl->hccr->cr_capbase)) < 0x100) + if (ctrl->hci_version < 0x100) remainder = xhci_td_remainder(length - running_total); else remainder = xhci_v1_0_td_remainder(running_total, @@ -830,7 +830,7 @@ int xhci_ctrl_tx(struct usb_device *udev, unsigned long pipe, field |= 0x1; /* xHCI 1.0 6.4.1.2.1: Transfer Type field */ - if (HC_VERSION(xhci_readl(&ctrl->hccr->cr_capbase)) >= 0x100) { + if (ctrl->hci_version >= 0x100) { if (length > 0) { if (req->requesttype & USB_DIR_IN) field |= (TRB_DATA_IN << TRB_TX_TYPE_SHIFT); diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c index 126dabc..4be1411 100644 --- a/drivers/usb/host/xhci.c +++ b/drivers/usb/host/xhci.c @@ -1283,6 +1283,7 @@ static int xhci_lowlevel_init(struct xhci_ctrl *ctrl) reg = HC_VERSION(xhci_readl(&hccr->cr_capbase)); printf("USB XHCI %x.%02x\n", reg >> 8, reg & 0xff); + ctrl->hci_version = reg; return 0; } diff --git a/include/usb/xhci.h b/include/usb/xhci.h index 7d34103..a3e5914 100644 --- a/include/usb/xhci.h +++ b/include/usb/xhci.h @@ -1227,6 +1227,7 @@ struct xhci_ctrl { struct xhci_scratchpad *scratchpad; struct xhci_virt_device *devs[MAX_HC_SLOTS]; int rootdev; + u16 hci_version; }; unsigned long trb_addr(struct xhci_segment *seg, union xhci_trb *trb); -- 1.9.1

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[PATCH v1] arm: socfpga: soc64: Disable CONFIG_PSCI_RESET
by Chee Hong Ang 08 Sep '20

08 Sep '20

Don't invoke 'SYSTEM_RESET' PSCI function because PSCI function calls are not supported by u-boot running in EL3. Signed-off-by: Chee Hong Ang <chee.hong.ang(a)intel.com> --- configs/socfpga_agilex_defconfig | 1 + configs/socfpga_stratix10_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/socfpga_agilex_defconfig b/configs/socfpga_agilex_defconfig index a08f66e248..feaab00249 100644 --- a/configs/socfpga_agilex_defconfig +++ b/configs/socfpga_agilex_defconfig @@ -12,6 +12,7 @@ CONFIG_TARGET_SOCFPGA_AGILEX_SOCDK=y CONFIG_IDENT_STRING="socfpga_agilex" CONFIG_SPL_FS_FAT=y CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex_socdk" +# CONFIG_PSCI_RESET is not set CONFIG_BOOTDELAY=5 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="earlycon" diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig index 04e354f59e..e7c7550112 100644 --- a/configs/socfpga_stratix10_defconfig +++ b/configs/socfpga_stratix10_defconfig @@ -14,6 +14,7 @@ CONFIG_SPL_FS_FAT=y CONFIG_DEFAULT_DEVICE_TREE="socfpga_stratix10_socdk" CONFIG_OPTIMIZE_INLINING=y CONFIG_SPL_OPTIMIZE_INLINING=y +# CONFIG_PSCI_RESET is not set CONFIG_BOOTDELAY=5 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="earlycon" -- 2.19.0

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[BUG] rsa: crash in br_i32_decode() called from rsa_gen_key_prop()
by Heinrich Schuchardt 08 Sep '20

08 Sep '20

Hello Takahiro, on the 32bit Wandboard (with i.mx6 CPU) running the lib_asn1_pkcs7 unit test results in a crash due to an unaligned access occurring when br_i32_decode() is called by rsa_gen_key_prop(). Please, check the alignment assumptions for src when calling br_i32_decode(). If src is only 1 byte aligned, you should neither call be32_to_cpup() nor be16_to_cpup() which assume 32bit and 16bit alignment. ----Running lib tests---- Running 14 lib tests Test: lib_asn1_pkcs7 data abort pc : [<8efb3a8e>] lr : [<8efb3bbd>] reloc pc : [<17845a8e>] lr : [<17845bbd>] sp : 8e561330 ip : 00000001 fp : 8efd9d66 r10: 8e58f040 r9 : 8e56dec0 r8 : 8e588748 r7 : 00000001 r6 : 8e58f350 r5 : 8e58f350 r4 : 8e58f350 r3 : 000000fc r2 : 00000100 r1 : 8e58ee49 r0 : 8e58f350 Flags: nzCv IRQs off FIQs off Mode SVC_32 (T) Code: ea43 4302 e7a2 3b04 (58c8) ba00 Resetting CPU ... resetting ... br_i32_decode(): return be16_to_cpup(src); 17845a84: b29b uxth r3, r3 w = ((uint32_t)buf[0] << 16) 17845a86: ea43 4302 orr.w r3, r3, r2, lsl #16 17845a8a: e7a2 b.n 178459d2 <br_i32_decode+0x24> u -= 4; 17845a8c: 3b04 subs r3, #4 return __arch__swab32p(x); 17845a8e: 58c8 ldr r0, [r1, r3] <<<<<<<<<<<<<< 17845a90: ba00 rev r0, r0 x[v ++] = br_dec32be(buf + u); 17845a92: f845 0f04 str.w r0, [r5, #4]! if (u < 4) { 17845a96: e78f b.n 178459b8 <br_i32_decode+0xa> return y ^ (-ctl & (x ^ y)); rsa_gen_key_prop(): /* n0 inverse */ br_i32_decode(n, &rsa_key.n[i], rsa_key.n_sz - i); 17845bac: 9910 ldr r1, [sp, #64] ; 0x40 (*prop)->exp_len = sizeof(uint64_t); 17845bae: 615a str r2, [r3, #20] br_i32_decode(n, &rsa_key.n[i], rsa_key.n_sz - i); 17845bb0: 9a18 ldr r2, [sp, #96] ; 0x60 17845bb2: 4439 add r1, r7 17845bb4: 1bd2 subs r2, r2, r7 17845bb6: 4630 mov r0, r6 17845bb8: f7ff fef9 bl 178459ae <br_i32_decode> <<<<<< (*prop)->n0inv = br_i32_ninv32(n[1]); 17845bbc: 6873 ldr r3, [r6, #4] 17845bbe: 682a ldr r2, [r5, #0] y = 2 - x; 17845bc0: f1c3 0102 rsb r1, r3, #2 Best regards Heinrich

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