August 2020 - U-Boot

[PATCH] xilinx: kconfig: Change Kconfig dependencies for Xilinx drivers
by Michal Simek 20 Aug '20

20 Aug '20

Zynq/ZynqMP/Versal IPs should be possible to called also from Microblaze in PL and vice versa. That's why change dependencies and do not limit enabling just for some platforms. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- drivers/gpio/Kconfig | 4 ++-- drivers/i2c/Kconfig | 2 +- drivers/mmc/Kconfig | 1 - drivers/net/Kconfig | 6 +++--- 4 files changed, 6 insertions(+), 7 deletions(-) diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 11e9a17f9729..202fcc6f4759 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -381,8 +381,8 @@ config MVEBU_GPIO config ZYNQ_GPIO bool "Zynq GPIO driver" - depends on DM_GPIO && (ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL) - default y + depends on DM_GPIO + default y if ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL help Supports GPIO access on Zynq SoC. diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index dec6dc9dfa4d..8ae54e1e93b0 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -88,7 +88,7 @@ config SYS_I2C_FSL config SYS_I2C_CADENCE tristate "Cadence I2C Controller" - depends on DM_I2C && (ARCH_ZYNQ || ARM64) + depends on DM_I2C help Say yes here to select Cadence I2C Host Controller. This controller is e.g. used by Xilinx Zynq. diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 556b3ac48978..c29d1ea680ef 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -653,7 +653,6 @@ config TEGRA124_MMC_DISABLE_EXT_LOOPBACK config MMC_SDHCI_ZYNQ bool "Arasan SDHCI controller support" - depends on ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL depends on DM_MMC && OF_CONTROL && BLK depends on MMC_SDHCI help diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index ecd779d979e4..039f9fb05899 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -519,7 +519,7 @@ config TULIP This driver supports DEC DC2114x Fast ethernet chips. config XILINX_AXIEMAC - depends on DM_ETH && (MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP) + depends on DM_ETH select PHYLIB select MII bool "Xilinx AXI Ethernet" @@ -527,7 +527,7 @@ config XILINX_AXIEMAC This MAC is present in Xilinx Microblaze, Zynq and ZynqMP SoCs. config XILINX_EMACLITE - depends on DM_ETH && (MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP || MIPS) + depends on DM_ETH select PHYLIB select MII bool "Xilinx Ethernetlite" @@ -535,7 +535,7 @@ config XILINX_EMACLITE This MAC is present in Xilinx Microblaze, Zynq and ZynqMP SoCs. config ZYNQ_GEM - depends on DM_ETH && (ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL) + depends on DM_ETH select PHYLIB bool "Xilinx Ethernet GEM" help -- 2.28.0

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Re: [PATCH 2/2] ram: sifive: Fix compiler warnings for 32-bit
by Rick Chen 20 Aug '20

20 Aug '20

> From: Bin Meng [mailto:bmeng.cn@gmail.com] > Sent: Tuesday, August 18, 2020 4:09 PM > To: Rick Jian-Zhi Chen(陳建志); Pragnesh Patel; U-Boot Mailing List > Cc: Bin Meng > Subject: [PATCH 2/2] ram: sifive: Fix compiler warnings for 32-bit > > From: Bin Meng <bin.meng(a)windriver.com> > > priv->info.size is of type 'size_t' but the length modifier is l. > Fix this by casting priv->info.size. Note 'z' cannot be used as > the modifier as SPL does not support that. > > Signed-off-by: Bin Meng <bin.meng(a)windriver.com> > --- > > drivers/ram/sifive/fu540_ddr.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) Reviewed-by: Rick Chen <rick(a)andestech.com>

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Re: [PATCH 1/2] riscv: fu540: Use correct API to get L2 cache controller base address
by Rick Chen 20 Aug '20

20 Aug '20

> From: Bin Meng [mailto:bmeng.cn@gmail.com] > Sent: Tuesday, August 18, 2020 4:09 PM > To: Rick Jian-Zhi Chen(陳建志); Pragnesh Patel; U-Boot Mailing List > Cc: Bin Meng > Subject: [PATCH 1/2] riscv: fu540: Use correct API to get L2 cache controller base address > > From: Bin Meng <bin.meng(a)windriver.com> > > At present fdtdec_get_addr() is used to get L2 cache controller base > address. This only works for a fixed #address-cells and #size-cells. > Change to use fdtdec_get_addr_size_auto_parent() instead. > > Signed-off-by: Bin Meng <bin.meng(a)windriver.com> > --- > > arch/riscv/cpu/fu540/cache.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) Reviewed-by: Rick Chen <rick(a)andestech.com>

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[PATCH v2 00/11] Add MTK AHCI driver, BPI-R64 dts and USB-Nodes for mt7622/mt7623
by Frank Wunderlich 20 Aug '20

20 Aug '20

From: Frank Wunderlich <frank-w(a)public-files.de> This series adds Mediatek AHCI driver, makes neccessary phy modifications creates new dts for bananapi-r64 (because it's a bit different to rfb) and adds all DTS nodes to get SATA and USB working on mt7622 and mt7623 they are based on top of this: Add PCIe and its clock support for mt7622 https://patchwork.ozlabs.org/project/uboot/list/?series=194888 and to get USB working (no hard depency, ports get enumerated without it): usb: xhci: add a member hci_version in xhci_ctrl struct https://patchwork.ozlabs.org/project/uboot/list/?series=195331 v1->v2: - made register of phy optional for tphy v1 and remove it in dts Frank Wunderlich (11): arm: dts: mt7622: add SATA reset constants phy: mtk-tphy: add PHY_TYPE_SATA phy: mtk-tphy: make shared reg optional for v1 reset: add basic reset controller for pciesys ahci: mediatek: add ahci driver clk: mt7622: add needed clocks for ssusb-node arm: dts: add watchdog-reboot node for mt7622 arm: dts: add dts for Bananapi-R64 arm: dts: mt7622: add sata- and asm_sel nodes arm: dts: mt7622: add USB nodes arm: dts: mt7623: add USB nodes arch/arm/dts/Makefile | 1 + arch/arm/dts/mt7622-bananapi-bpi-r64.dts | 223 +++++++++++++++++++++++ arch/arm/dts/mt7622-rfb.dts | 8 + arch/arm/dts/mt7622.dtsi | 92 ++++++++++ arch/arm/dts/mt7623.dtsi | 46 +++++ arch/arm/dts/mt7623n-bananapi-bpi-r2.dts | 16 ++ drivers/ata/Kconfig | 8 + drivers/ata/Makefile | 1 + drivers/ata/mtk_ahci.c | 130 +++++++++++++ drivers/clk/mediatek/clk-mt7622.c | 57 ++++++ drivers/phy/phy-mtk-tphy.c | 110 ++++++++++- include/dt-bindings/reset/mt7629-reset.h | 5 +- 12 files changed, 693 insertions(+), 4 deletions(-) create mode 100644 arch/arm/dts/mt7622-bananapi-bpi-r64.dts create mode 100644 drivers/ata/mtk_ahci.c -- 2.25.1

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[PATCH v3 1/1] cmd: provide command sbi
by Heinrich Schuchardt 20 Aug '20

20 Aug '20

Provide a command to display information about the SBI implementation. The output might look like: => sbi SBI 0.2 OpenSBI Extensions: sbi_set_timer sbi_console_putchar sbi_console_getchar sbi_clear_ipi sbi_send_ipi sbi_remote_fence_i sbi_remote_sfence_vma sbi_remote_sfence_vma_asid sbi_shutdown SBI Base Functionality Timer Extension IPI Extension RFENCE Extension Hart State Management Extension The command can be used to construct a unit test checking that the communication with the SEE is working. Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- v3: add dependency on CONFIG_SBI_V02 use lower case for sbi in Kconfig v2: provide a non-blank long help text --- arch/riscv/include/asm/sbi.h | 2 + arch/riscv/lib/sbi.c | 36 ++++++++++++++++ cmd/Kconfig | 6 +++ cmd/riscv/Makefile | 1 + cmd/riscv/sbi.c | 82 ++++++++++++++++++++++++++++++++++++ 5 files changed, 127 insertions(+) create mode 100644 cmd/riscv/sbi.c diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index 08e1ac0c0e..53ca316180 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -115,6 +115,8 @@ void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask, unsigned long asid); #endif void sbi_set_timer(uint64_t stime_value); +long sbi_get_spec_version(void); +int sbi_get_impl_id(void); int sbi_probe_extension(int ext); #endif diff --git a/arch/riscv/lib/sbi.c b/arch/riscv/lib/sbi.c index 8fbc23839d..920889ed13 100644 --- a/arch/riscv/lib/sbi.c +++ b/arch/riscv/lib/sbi.c @@ -53,6 +53,42 @@ void sbi_set_timer(uint64_t stime_value) #endif } +/** + * sbi_get_spec_version() - get current SBI specification version + * + * Return: version id + */ +long sbi_get_spec_version(void) +{ + struct sbiret ret; + + ret = sbi_ecall(SBI_EXT_BASE, SBI_EXT_BASE_GET_SPEC_VERSION, + 0, 0, 0, 0, 0, 0); + if (!ret.error) + if (ret.value) + return ret.value; + + return -ENOTSUPP; +} + +/** + * sbi_get_impl_id() - get SBI implemenation ID + * + * Return: implementation ID + */ +int sbi_get_impl_id(void) +{ + struct sbiret ret; + + ret = sbi_ecall(SBI_EXT_BASE, SBI_EXT_BASE_GET_IMP_ID, + 0, 0, 0, 0, 0, 0); + if (!ret.error) + if (ret.value) + return ret.value; + + return -ENOTSUPP; +} + /** * sbi_probe_extension() - Check if an SBI extension ID is supported or not. * @extid: The extension ID to be probed. diff --git a/cmd/Kconfig b/cmd/Kconfig index 9ad511aa17..8feeb0ddb0 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -270,6 +270,12 @@ config SPL_CMD_TLV_EEPROM help Read system EEPROM data block in ONIE Tlvinfo format from SPL. +config CMD_SBI + bool "sbi information" + depends on RISCV_SMODE && SBI_V02 + help + Display information about the SBI implementation. + endmenu menu "Boot commands" diff --git a/cmd/riscv/Makefile b/cmd/riscv/Makefile index 24df023ece..1e6ac364e3 100644 --- a/cmd/riscv/Makefile +++ b/cmd/riscv/Makefile @@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0+ obj-$(CONFIG_CMD_EXCEPTION) += exception.o +obj-$(CONFIG_CMD_SBI) += sbi.o diff --git a/cmd/riscv/sbi.c b/cmd/riscv/sbi.c new file mode 100644 index 0000000000..7c9151f436 --- /dev/null +++ b/cmd/riscv/sbi.c @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * The 'sbi' command displays information about the SBI implementation. + * + * Copyright (c) 2020, Heinrich Schuchardt <xypron.glpk(a)gmx.de> + */ + +#include <common.h> +#include <command.h> +#include <asm/sbi.h> + +struct sbi_ext { + const u32 id; + const char *name; +}; + +static struct sbi_ext extensions[] = { + { 0x00000000, "sbi_set_timer" }, + { 0x00000001, "sbi_console_putchar" }, + { 0x00000002, "sbi_console_getchar" }, + { 0x00000003, "sbi_clear_ipi" }, + { 0x00000004, "sbi_send_ipi" }, + { 0x00000005, "sbi_remote_fence_i" }, + { 0x00000006, "sbi_remote_sfence_vma" }, + { 0x00000007, "sbi_remote_sfence_vma_asid" }, + { 0x00000008, "sbi_shutdown" }, + { 0x00000010, "SBI Base Functionality" }, + { 0x54494D45, "Timer Extension" }, + { 0x00735049, "IPI Extension" }, + { 0x52464E43, "RFENCE Extension" }, + { 0x0048534D, "Hart State Management Extension" }, +}; + +static int do_sbi(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + int i; + long ret; + + ret = sbi_get_spec_version(); + if (ret >= 0) + printf("SBI %ld.%ld\n", ret >> 24, ret &0xffffff); + ret = sbi_get_impl_id(); + if (ret >= 0) { + switch (ret) { + case 0: + printf("Berkeley Boot Loader (BBL)\n"); + break; + case 1: + printf("OpenSBI\n"); + break; + case 2: + printf("Xvisor\n"); + break; + case 3: + printf("KVM\n"); + break; + default: + printf("Unknown implementation\n"); + break; + } + } + printf("Extensions:\n"); + for (i = 0; i < ARRAY_SIZE(extensions); ++i) { + ret = sbi_probe_extension(extensions[i].id); + if (ret > 0) + printf(" %s\n", extensions[i].name); + } + return 0; +} + +#ifdef CONFIG_SYS_LONGHELP +static char sbi_help_text[] = + "- display SBI spec version, implementation, and available extensions"; + +#endif + +U_BOOT_CMD_COMPLETE( + sbi, 2, 0, do_sbi, + "display SBI information", + sbi_help_text, NULL +); -- 2.28.0

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[PATCH] arm: imx6q_logic: Enable I2C PMIC
by Adam Ford 19 Aug '20

19 Aug '20

The PMIC which powers the whole board is connected to the I2C1 bus. This patch enables I2C. With this enabled, the PMIC needs to told to keep the rail enabled, or it gets shutdown before the system boots. Signed-off-by: Adam Ford <aford173(a)gmail.com> diff --git a/arch/arm/dts/imx6q-logicpd-u-boot.dtsi b/arch/arm/dts/imx6q-logicpd-u-boot.dtsi index ee44ed91fe..94b53d569d 100644 --- a/arch/arm/dts/imx6q-logicpd-u-boot.dtsi +++ b/arch/arm/dts/imx6q-logicpd-u-boot.dtsi @@ -28,3 +28,7 @@ &pinctrl_usdhc2 { u-boot,dm-spl; }; + +&sw2_reg { + regulator-always-on; +}; diff --git a/configs/imx6q_logic_defconfig b/configs/imx6q_logic_defconfig index 35dfd8a303..d02c81449c 100644 --- a/configs/imx6q_logic_defconfig +++ b/configs/imx6q_logic_defconfig @@ -9,6 +9,7 @@ CONFIG_ENV_SIZE=0x100000 CONFIG_ENV_OFFSET=0x400000 CONFIG_MX6_OCRAM_256KB=y CONFIG_TARGET_MX6LOGICPD=y +CONFIG_SYS_I2C_MXC_I2C1=y CONFIG_SPL_TEXT_BASE=0x00908000 CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y @@ -70,6 +71,7 @@ CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_OF_TRANSLATE=y CONFIG_PCF8575_GPIO=y +CONFIG_SYS_I2C_MXC=y CONFIG_LED=y CONFIG_LED_GPIO=y CONFIG_FSL_USDHC=y -- 2.25.1

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[PATCH v1 0/8] mips/usb: Add Octeon xHCI USB support
by Stefan Roese 19 Aug '20

19 Aug '20

This patchset adds xHCI USB support for MIPS Octeon. After the xHCI code has been fixed to support mapped addresses (virt != phys), this patchset now adds the missing code pieces to enable USB support on Octeon. This is mainly the USB glue code for Octeon and the MIPS platform specific changes (cache fixes, platform specific swapping based on address areas, DT & defcopnfig changes). Thanks, Stefan Stefan Roese (8): usb: xhci: xhci-dwc3.c: Use dev_remap_addr() instead of dev_get_addr() usb: xhci: xhci_bulk_tx: Don't "BUG" when comparing addresses on Octeon usb: xhci: octeon: Add DWC3 glue layer for Octeon mips: octeon: cpu.c: Add table for selective swapping mips: octeon: Add mangle-port.h mips: octeon: cache.c: Flush all pending writes in flush_dcache_range() mips: octeon: Add USB DT nodes mips: octeon: octeon_ebb7304_defconfig: Enable USB support arch/mips/dts/mrvl,cn73xx.dtsi | 58 +++ arch/mips/dts/mrvl,octeon-ebb7304.dts | 22 ++ arch/mips/mach-octeon/cache.c | 12 +- arch/mips/mach-octeon/cpu.c | 21 ++ arch/mips/mach-octeon/include/mangle-port.h | 58 +++ configs/octeon_ebb7304_defconfig | 17 + drivers/usb/host/Kconfig | 9 + drivers/usb/host/Makefile | 1 + drivers/usb/host/dwc3-octeon-glue.c | 396 ++++++++++++++++++++ drivers/usb/host/xhci-dwc3.c | 2 +- drivers/usb/host/xhci-ring.c | 7 +- 11 files changed, 594 insertions(+), 9 deletions(-) create mode 100644 arch/mips/mach-octeon/include/mangle-port.h create mode 100644 drivers/usb/host/dwc3-octeon-glue.c -- 2.28.0

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[PATCH] armv8: MMU: Mark code memory Executable, any other Non-Executable
by marek.bykowski＠gmail.com 19 Aug '20

19 Aug '20

From: Marek Bykowski <marek.bykowski(a)gmail.com> If the location the ARM CPU is accessing is executable (translation table descriptor Execute-Never attribute bit cleared) then the ARM CPU fetches a number of instructions from that location all at the same time. For example, Cortex-A57 can source up to 128 bits per fetch depending on alignment. If the CPU mispredicts to the Execute-Never region, it creates the memory fault but it actually never uses the instructions mispredicted. The CPU branches away elsewhere. So, as long as we program the MMU correctly these mispredictions will only affect the performance. However if we fail programming so and the instruction fetch logic goes mispredict to non-instruction memory it may eventually perturb it, eg. corrupt the FIFO, or the control registers, load the unified cache the data side memory system hits into subsequently. U-Boot adheres into attributing the device regions to Execute-Never but it actually fails doing so for data regions. Data as well as Device Regions should be Execute-Never. This patch enables attributing data memory regions to Non-Executable, and code region to Executable, additionally to Read-Only. Read-Only ensures the code region is only Readable resulting in Instruction Abort, Permission Fault exception on a write. To use the updated attributes the DDR memory of interest should be Non-Executable, it is by default Read-Write Access Permission as well with an example as follows: static struct mm_region axxia_mem_map[] = { { .virt = 0x0UL, /* DDR */ .phys = 0x0UL, .size = 0x400000000ULL, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, { .virt = AXXIA_CCN_512_BASE, .phys = AXXIA_CCN_512_BASE, .size = AXXIA_CCN_512_SIZE, .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, { .virt = AXI_MMAP_BASE, .phys = AXI_MMAP_BASE, .size = AXI_MMAP_SIZE, .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, { .virt = AXI_PERIPH_BASE, .phys = AXI_PERIPH_BASE, .size = AXI_PERIPH_SIZE, .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, { /* List terminator */ 0, } }; add_text_map() routine in cache_v8.c locates then the code region in it and modifies its attributes to Executable, Read-Only. The HW Debugger views the Memory Map set then as: EL2N:0x00000000-0x3FD35FFF NP:0x00000000-0x3FD35FFF Normal RW C S XN EL2N:0x3FD36000-0x3FD86FFF NP:0x3FD36000-0x3FD86FFF Normal RO C S EL2N:0x3FD87000-0x3FFFFFFFF NP:0x3FD87000-0x3FFFFFFFF Normal RW C S XN EL2N:0x400000000-0x3FFFFFFFFF <unmapped> EL2N:0x4000000000-0x403FFFFFFF NP:0x4000000000-0x403FFFFFFF Device-nGnRnE RW NC XN EL2N:0x4040000000-0x7FFFFFFFFF <unmapped> EL2N:0x8000000000-0x803FFFFFFF NP:0x8000000000-0x803FFFFFFF Device-nGnRnE RW NC XN EL2N:0x8040000000-0x807FFFFFFF <unmapped> EL2N:0x8080000000-0x80BFFFFFFF NP:0x8080000000-0x80BFFFFFFF Device-nGnRnE RW NC XN EL2N:0x80C0000000-0xFFFFFFFFFF <unmapped> where: C, NC is Cacheable, Non-Cacheable respectively, S, NS - Shareable and Non-Shareable, XN - Execute-Never, if XN isn't present it is Executable. May be worth to add that Shareability is of no matter to Non-Cacheable as it concerns only the Cacheable Regions. Signed-off-by: Marek Bykowski <marek.bykowski(a)gmail.com> --- arch/arm/cpu/armv8/cache_v8.c | 21 +++++++++++++++++++++ arch/arm/cpu/armv8/u-boot.lds | 6 ++++-- arch/arm/include/asm/armv8/mmu.h | 6 ++++++ arch/arm/lib/sections.c | 1 + include/asm-generic/sections.h | 1 + 5 files changed, 33 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index c1a08fb4ac..cb25fc0c8a 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -11,6 +11,7 @@ #include <cpu_func.h> #include <asm/system.h> #include <asm/armv8/mmu.h> +#include <asm/sections.h> DECLARE_GLOBAL_DATA_PTR; @@ -361,6 +362,24 @@ __weak u64 get_page_table_size(void) return size; } +__weak void add_text_map(void) +{ + if (!(gd->flags & GD_FLG_RELOC)) + return; + + /* Text is always XN=0, read-only region. */ + struct mm_region text = { + .virt = (unsigned long)__image_copy_start, + .phys = (unsigned long)__image_copy_start, + .size = (unsigned long)__text_end - (unsigned long)__image_copy_start, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE | + PTE_BLOCK_AP_RO + }; + + add_map(&text); +} + void setup_pgtables(void) { int i; @@ -378,6 +397,8 @@ void setup_pgtables(void) /* Now add all MMU table entries one after another to the table */ for (i = 0; mem_map[i].size || mem_map[i].attrs; i++) add_map(&mem_map[i]); + + add_text_map(); } static void setup_all_pgtables(void) diff --git a/arch/arm/cpu/armv8/u-boot.lds b/arch/arm/cpu/armv8/u-boot.lds index 2554980595..20f98ae74d 100644 --- a/arch/arm/cpu/armv8/u-boot.lds +++ b/arch/arm/cpu/armv8/u-boot.lds @@ -20,8 +20,8 @@ SECTIONS #endif . = 0x00000000; - . = ALIGN(8); - .text : + /* Align .text to the page size */ + .text ALIGN(0x1000): { *(.__image_copy_start) CPUDIR/start.o (.text*) @@ -39,6 +39,8 @@ SECTIONS .text_rest : { *(.text*) + . = NEXT(0x1000); + KEEP(*(.__text_end)) } #ifdef CONFIG_ARMV8_PSCI diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h index 4a573208df..4bd15c7e08 100644 --- a/arch/arm/include/asm/armv8/mmu.h +++ b/arch/arm/include/asm/armv8/mmu.h @@ -58,6 +58,12 @@ */ #define PTE_BLOCK_MEMTYPE(x) ((x) << 2) #define PTE_BLOCK_NS (1 << 5) +/* + * AP[1] bit is ignored by hardware and is + * treated as if it was One in EL2/EL3 + */ +#define PTE_BLOCK_AP_RO (1 << 7) +#define PTE_BLOCK_AP_RW (0 << 7) #define PTE_BLOCK_NON_SHARE (0 << 8) #define PTE_BLOCK_OUTER_SHARE (2 << 8) #define PTE_BLOCK_INNER_SHARE (3 << 8) diff --git a/arch/arm/lib/sections.c b/arch/arm/lib/sections.c index 3bb2d8468c..a76f2d3049 100644 --- a/arch/arm/lib/sections.c +++ b/arch/arm/lib/sections.c @@ -18,6 +18,7 @@ * aliasing warnings. */ +char __text_end[0] __attribute__((section(".__text_end"))); char __bss_start[0] __attribute__((section(".__bss_start"))); char __bss_end[0] __attribute__((section(".__bss_end"))); char __image_copy_start[0] __attribute__((section(".__image_copy_start"))); diff --git a/include/asm-generic/sections.h b/include/asm-generic/sections.h index 17a31ec788..1487e16432 100644 --- a/include/asm-generic/sections.h +++ b/include/asm-generic/sections.h @@ -70,6 +70,7 @@ extern void _start(void); */ #ifdef CONFIG_ARM +extern char __text_end[]; extern char __bss_start[]; extern char __bss_end[]; extern char __image_copy_start[]; -- 2.21.0.896.g6a6c0f1

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[GIT PULL] UniPhier SoC updates for v2020.10-rc3
by Masahiro Yamada 19 Aug '20

19 Aug '20

Hi Tom, Please pull a little more for v2020.10. Thanks. The following changes since commit 789bfb52668ee609b2043de645e2f94bbd24fd1f: Merge tag 'efi-2020-10-rc3-2' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi (2020-08-15 09:01:01 -0400) are available in the Git repository at: https://gitlab.denx.de/u-boot/custodians/u-boot-uniphier.git tags/uniphier-v2020.10-2 for you to fetch changes up to 65282edbdf2f30e97c1680e856e6e9fb7af26f8b: ARM: dts: uniphier: resync DT with Linux 5.9-rc1 (2020-08-18 02:01:14 +0900) ---------------------------------------------------------------- UniPhier SoC updates for v2020.10 (2nd) - minor code cleanups - sync DT with Linux ---------------------------------------------------------------- Masahiro Yamada (6): ARM: uniphier: rename include guard of include/configs/uniphier.h ARM: uniphier: remove unused uniphier_pin_init() ARM: uniphier: remove unneeded header inclusion from board_late_init.c serial: uniphier: fix typo in comment ARM: uniphier: use FIELD_GET() to get access to revision register fields ARM: dts: uniphier: resync DT with Linux 5.9-rc1 arch/arm/dts/uniphier-ld11-global.dts | 2 +- arch/arm/dts/uniphier-ld11-ref.dts | 8 +- arch/arm/dts/uniphier-ld20-global.dts | 2 +- arch/arm/dts/uniphier-ld20-ref.dts | 8 +- arch/arm/dts/uniphier-ld20.dtsi | 2 + arch/arm/dts/uniphier-ld4-ref.dts | 6 +- arch/arm/dts/uniphier-ld6b-ref.dts | 7 +- arch/arm/dts/uniphier-pinctrl.dtsi | 5 + arch/arm/dts/uniphier-pro4-ace.dts | 2 +- arch/arm/dts/uniphier-pro4-ref.dts | 8 +- arch/arm/dts/uniphier-pro4-sanji.dts | 3 +- arch/arm/dts/uniphier-pro5.dtsi | 190 +++++++++++++++--- arch/arm/dts/uniphier-pxs2-gentil.dts | 2 +- arch/arm/dts/uniphier-pxs2-vodka.dts | 2 +- arch/arm/dts/uniphier-pxs3-ref.dts | 10 +- arch/arm/dts/uniphier-pxs3.dtsi | 2 + arch/arm/dts/uniphier-sld8-ref.dts | 6 +- arch/arm/dts/uniphier-support-card.dtsi | 31 ++- arch/arm/mach-uniphier/Makefile | 1 - arch/arm/mach-uniphier/board_late_init.c | 3 +- arch/arm/mach-uniphier/init.h | 1 - arch/arm/mach-uniphier/pinctrl-glue.c | 30 --- arch/arm/mach-uniphier/sg-regs.h | 5 + arch/arm/mach-uniphier/soc-info.c | 21 +- drivers/serial/serial_uniphier.c | 2 +- include/configs/uniphier.h | 6 +- 26 files changed, 255 insertions(+), 110 deletions(-) delete mode 100644 arch/arm/mach-uniphier/pinctrl-glue.c

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[PATCH v2 1/1] configs: defconfig for Sipeed Maix in S-mode
by Heinrich Schuchardt 19 Aug '20

19 Aug '20

Provide a defconfig that can be used to build U-Boot for the Maix boards running upon OpenSBI. Update the documentation. Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- v2: adjust MAINTAINERS --- board/sipeed/maix/MAINTAINERS | 2 +- configs/sipeed_maix_smode_defconfig | 10 ++++++ doc/board/sipeed/maix.rst | 49 +++++++++++++++++++++++++++++ 3 files changed, 60 insertions(+), 1 deletion(-) create mode 100644 configs/sipeed_maix_smode_defconfig diff --git a/board/sipeed/maix/MAINTAINERS b/board/sipeed/maix/MAINTAINERS index e7bb9ec433..969a0afbad 100644 --- a/board/sipeed/maix/MAINTAINERS +++ b/board/sipeed/maix/MAINTAINERS @@ -4,7 +4,7 @@ S: Maintained F: arch/riscv/dts/k210.dtsi F: arch/riscv/dts/k210-maix-bit.dts F: board/sipeed/maix/ -F: configs/sipeed_maix_bitm_defconfig +F: configs/sipeed_maix*_defconfig F: doc/board/sipeed/ F: include/configs/sipeed-maix.h F: include/dt-bindings/*/k210-sysctl.h diff --git a/configs/sipeed_maix_smode_defconfig b/configs/sipeed_maix_smode_defconfig new file mode 100644 index 0000000000..2516bb7258 --- /dev/null +++ b/configs/sipeed_maix_smode_defconfig @@ -0,0 +1,10 @@ +CONFIG_RISCV=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_TARGET_SIPEED_MAIX=y +CONFIG_ARCH_RV64I=y +CONFIG_RISCV_SMODE=y +CONFIG_STACK_SIZE=0x100000 +# CONFIG_NET is not set +# CONFIG_INPUT is not set +# CONFIG_DM_ETH is not set +# CONFIG_EFI_UNICODE_CAPITALIZATION is not set diff --git a/doc/board/sipeed/maix.rst b/doc/board/sipeed/maix.rst index b1894f3a6f..efcde9aebf 100644 --- a/doc/board/sipeed/maix.rst +++ b/doc/board/sipeed/maix.rst @@ -75,6 +75,49 @@ console shall be opened immediately. Boot output should look like the following: Err: serial@38000000 => +OpenSBI +^^^^^^^ + +OpenSBI is an open source supervisor execution environment implementing the +RISC-V Supervisor Binary Interface Specification [1]. One of its features is +to intercept run-time exceptions, e.g. for unaligned access or illegal +instructions, and to emulate the failing instructions. + +The OpenSBI source can be downloaded via: + +.. code-block:: bash + + git clone https://github.com/riscv/opensbi + +As OpenSBI will be loaded at 0x80000000 we have to adjust the U-Boot text base. +Furthermore we have to enable building U-Boot for S-mode:: + + CONFIG_SYS_TEXT_BASE=0x80020000 + CONFIG_RISCV_SMODE=y + +Both settings are contained in sipeed_maix_smode_defconfig so we can build +U-Boot with: + +.. code-block:: bash + + make sipeed_maix_smode_defconfig + make + +To build OpenSBI with U-Boot as a payload: + +.. code-block:: bash + + cd opensbi + make \ + PLATFORM=kendryte/k210 \ + FW_PAYLOAD=y \ + FW_PAYLOAD_OFFSET=0x20000 \ + FW_PAYLOAD_PATH=<path to U-Boot>/u-boot-dtb.bin + +The value of FW_PAYLOAD_OFFSET must match CONFIG_SYS_TEXT_BASE - 0x80000000. + +The file to flash is build/platform/kendryte/k210/firmware/fw_payload.bin. + Loading Images ^^^^^^^^^^^^^^ @@ -363,3 +406,9 @@ Address Size Description interrupts) 0x8801f000 0x1000 credits ========== ========= =========== + +Links +----- + +[1] https://github.com/riscv/riscv-sbi-doc + RISC-V Supervisor Binary Interface Specification -- 2.28.0

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