August 2020 - U-Boot

[ANN] U-Boot v2020.10-rc3 released
by Tom Rini 26 Aug '20

26 Aug '20

Hey all, I know it's a few days past the scheduled release but we had several PRs come in and my general cycle for PRs (for a while now) is take one, throw it at CI and world build before/after, repeat. If it's likely to be fairly localized I will queue a few together, but usually I don't. So here we are, sorry for the delay and I have now tagged v2020.10-rc3. Once again, for a changelog, git log --merges v2020.10-rc2..v2020.10-rc3 and as always, I ask for more details in the PRs people send me so I can put them in the merge commit. I'm going to get back on track with every-other-week RCs on Mondays and release on October 5th, and I'll open the -next branch with the next -rc. I'll queue up PRs for that until then and deal with merges as needed. Thanks all! -- Tom

1 0

[PATCH 1/1] fs: convert error and debug messages to log
by Heinrich Schuchardt 26 Aug '20

26 Aug '20

Use log functions for error and debug messages of the file-system. Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- fs/fs.c | 16 +++++++++------- fs/fs_internal.c | 16 +++++++++------- 2 files changed, 18 insertions(+), 14 deletions(-) diff --git a/fs/fs.c b/fs/fs.c index 17e4bc33f7..29ad4d1a69 100644 --- a/fs/fs.c +++ b/fs/fs.c @@ -3,6 +3,8 @@ * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. */ +#define LOG_CATEGORY LOGC_CORE + #include <command.h> #include <config.h> #include <errno.h> @@ -34,7 +36,7 @@ static int fs_type = FS_TYPE_ANY; static inline int fs_probe_unsupported(struct blk_desc *fs_dev_desc, struct disk_partition *fs_partition) { - printf("** Unrecognized filesystem type **\n"); + log_err("** Unrecognized filesystem type **\n"); return -1; } @@ -508,7 +510,7 @@ static int fs_read_lmb_check(const char *filename, ulong addr, loff_t offset, if (lmb_alloc_addr(&lmb, addr, read_len) == addr) return 0; - printf("** Reading file would overwrite reserved memory **\n"); + log_err("** Reading file would overwrite reserved memory **\n"); return -ENOSPC; } #endif @@ -538,7 +540,7 @@ static int _fs_read(const char *filename, ulong addr, loff_t offset, loff_t len, /* If we requested a specific number of bytes, check we got it */ if (ret == 0 && len && *actread != len) - debug("** %s shorter than offset + len **\n", filename); + log_debug("** %s shorter than offset + len **\n", filename); fs_close(); return ret; @@ -562,7 +564,7 @@ int fs_write(const char *filename, ulong addr, loff_t offset, loff_t len, unmap_sysmem(buf); if (ret < 0 && len != *actwrite) { - printf("** Unable to write file %s **\n", filename); + log_err("** Unable to write file %s **\n", filename); ret = -1; } fs_close(); @@ -656,7 +658,7 @@ int fs_ln(const char *fname, const char *target) ret = info->ln(fname, target); if (ret < 0) { - printf("** Unable to create link %s -> %s **\n", fname, target); + log_err("** Unable to create link %s -> %s **\n", fname, target); ret = -1; } fs_close(); @@ -737,7 +739,7 @@ int do_load(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[], ret = _fs_read(filename, addr, pos, bytes, 1, &len_read); time = get_timer(time); if (ret < 0) { - printf("Failed to load '%s'\n", filename); + log_err("Failed to load '%s'\n", filename); return 1; } @@ -902,7 +904,7 @@ int do_mkdir(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[], ret = fs_mkdir(argv[3]); if (ret) { - printf("** Unable to create a directory \"%s\" **\n", argv[3]); + log_err("** Unable to create a directory \"%s\" **\n", argv[3]); return 1; } diff --git a/fs/fs_internal.c b/fs/fs_internal.c index 8b19811a63..bfc35c996c 100644 --- a/fs/fs_internal.c +++ b/fs/fs_internal.c @@ -5,6 +5,8 @@ * Derived from code in ext4/dev.c, which was based on reiserfs/dev.c */ +#define LOG_CATEGORY LOGC_CORE + #include <common.h> #include <blk.h> #include <compiler.h> @@ -19,7 +21,7 @@ int fs_devread(struct blk_desc *blk, struct disk_partition *partition, int log2blksz; ALLOC_CACHE_ALIGN_BUFFER(char, sec_buf, (blk ? blk->blksz : 0)); if (blk == NULL) { - printf("** Invalid Block Device Descriptor (NULL)\n"); + log_err("** Invalid Block Device Descriptor (NULL)\n"); return 0; } log2blksz = blk->log2blksz; @@ -27,8 +29,8 @@ int fs_devread(struct blk_desc *blk, struct disk_partition *partition, /* Check partition boundaries */ if ((sector + ((byte_offset + byte_len - 1) >> log2blksz)) >= partition->size) { - printf("%s read outside partition " LBAFU "\n", __func__, - sector); + log_err("%s read outside partition " LBAFU "\n", __func__, + sector); return 0; } @@ -36,14 +38,14 @@ int fs_devread(struct blk_desc *blk, struct disk_partition *partition, sector += byte_offset >> log2blksz; byte_offset &= blk->blksz - 1; - debug(" <" LBAFU ", %d, %d>\n", sector, byte_offset, byte_len); + log_debug(" <" LBAFU ", %d, %d>\n", sector, byte_offset, byte_len); if (byte_offset != 0) { int readlen; /* read first part which isn't aligned with start of sector */ if (blk_dread(blk, partition->start + sector, 1, (void *)sec_buf) != 1) { - printf(" ** %s read error **\n", __func__); + log_err(" ** %s read error **\n", __func__); return 0; } readlen = min((int)blk->blksz - byte_offset, @@ -73,7 +75,7 @@ int fs_devread(struct blk_desc *blk, struct disk_partition *partition, if (blk_dread(blk, partition->start + sector, block_len >> log2blksz, (void *)buf) != block_len >> log2blksz) { - printf(" ** %s read error - block\n", __func__); + log_err(" ** %s read error - block\n", __func__); return 0; } block_len = byte_len & ~(blk->blksz - 1); @@ -85,7 +87,7 @@ int fs_devread(struct blk_desc *blk, struct disk_partition *partition, /* read rest of data which are not in whole sector */ if (blk_dread(blk, partition->start + sector, 1, (void *)sec_buf) != 1) { - printf("* %s read error - last part\n", __func__); + log_err("* %s read error - last part\n", __func__); return 0; } memcpy(buf, sec_buf, byte_len); -- 2.28.0

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[PATCH 1/6] ARM: mach-at91: add support for new SoC sama7g5
by Eugen Hristev 26 Aug '20

26 Aug '20

Add support for new SoC sama7g5 Signed-off-by: Eugen Hristev <eugen.hristev(a)microchip.com> --- arch/arm/dts/sama7g5-pinfunc.h | 924 +++++++++++++++++++++ arch/arm/mach-at91/Kconfig | 5 + arch/arm/mach-at91/armv7/Makefile | 1 + arch/arm/mach-at91/armv7/sama7g5_devices.c | 11 + arch/arm/mach-at91/include/mach/hardware.h | 2 + arch/arm/mach-at91/include/mach/sama7g5.h | 74 ++ 6 files changed, 1017 insertions(+) create mode 100644 arch/arm/dts/sama7g5-pinfunc.h create mode 100644 arch/arm/mach-at91/armv7/sama7g5_devices.c create mode 100644 arch/arm/mach-at91/include/mach/sama7g5.h diff --git a/arch/arm/dts/sama7g5-pinfunc.h b/arch/arm/dts/sama7g5-pinfunc.h new file mode 100644 index 0000000000..89293e5470 --- /dev/null +++ b/arch/arm/dts/sama7g5-pinfunc.h @@ -0,0 +1,924 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#define PINMUX_PIN(no, func, ioset) \ +(((no) & 0xffff) | (((func) & 0xf) << 16) | (((ioset) & 0xff) << 20)) + +#define PIN_PA0 0 +#define PIN_PA0__GPIO PINMUX_PIN(PIN_PA0, 0, 0) +#define PIN_PA0__SDMMC0_CK PINMUX_PIN(PIN_PA0, 1, 1) +#define PIN_PA0__FLEXCOM0_IO0 PINMUX_PIN(PIN_PA0, 2, 1) +#define PIN_PA0__CANTX3 PINMUX_PIN(PIN_PA0, 3, 1) +#define PIN_PA0__PWML0 PINMUX_PIN(PIN_PA0, 5, 2) +#define PIN_PA1 1 +#define PIN_PA1__GPIO PINMUX_PIN(PIN_PA1, 0, 0) +#define PIN_PA1__SDMMC0_CMD PINMUX_PIN(PIN_PA1, 1, 1) +#define PIN_PA1__FLEXCOM0_IO1 PINMUX_PIN(PIN_PA1, 2, 1) +#define PIN_PA1__CANRX3 PINMUX_PIN(PIN_PA1, 3, 1) +#define PIN_PA1__D14 PINMUX_PIN(PIN_PA1, 4, 1) +#define PIN_PA1__PWMH0 PINMUX_PIN(PIN_PA1, 5, 3) +#define PIN_PA2 2 +#define PIN_PA2__GPIO PINMUX_PIN(PIN_PA2, 0, 0) +#define PIN_PA2__SDMMC0_RSTN PINMUX_PIN(PIN_PA2, 1, 1) +#define PIN_PA2__FLEXCOM0_IO2 PINMUX_PIN(PIN_PA2, 2, 1) +#define PIN_PA2__PDMC1_CLK PINMUX_PIN(PIN_PA2, 3, 1) +#define PIN_PA2__D15 PINMUX_PIN(PIN_PA2, 4, 1) +#define PIN_PA2__PWMH1 PINMUX_PIN(PIN_PA2, 5, 3) +#define PIN_PA2__FLEXCOM1_IO0 PINMUX_PIN(PIN_PA2, 6, 3) +#define PIN_PA3 3 +#define PIN_PA3__GPIO PINMUX_PIN(PIN_PA3, 0, 0) +#define PIN_PA3__SDMMC0_DAT0 PINMUX_PIN(PIN_PA3, 1, 1) +#define PIN_PA3__FLEXCOM0_IO3 PINMUX_PIN(PIN_PA3, 2, 1) +#define PIN_PA3__PDMC1_DS0 PINMUX_PIN(PIN_PA3, 3, 1) +#define PIN_PA3__NWR1_NBS1 PINMUX_PIN(PIN_PA3, 4, 1) +#define PIN_PA3__PWML3 PINMUX_PIN(PIN_PA3, 5, 3) +#define PIN_PA3__FLEXCOM1_IO1 PINMUX_PIN(PIN_PA3, 6, 3) +#define PIN_PA4 4 +#define PIN_PA4__GPIO PINMUX_PIN(PIN_PA4, 0, 0) +#define PIN_PA4__SDMMC0_DAT1 PINMUX_PIN(PIN_PA4, 1, 1) +#define PIN_PA4__FLEXCOM0_IO4 PINMUX_PIN(PIN_PA4, 2, 1) +#define PIN_PA4__PDMC1_DS1 PINMUX_PIN(PIN_PA4, 3, 1) +#define PIN_PA4__NCS2 PINMUX_PIN(PIN_PA4, 4, 1) +#define PIN_PA4__PWMH3 PINMUX_PIN(PIN_PA4, 5, 3) +#define PIN_PA4__FLEXCOM2_IO0 PINMUX_PIN(PIN_PA4, 6, 3) +#define PIN_PA5 5 +#define PIN_PA5__GPIO PINMUX_PIN(PIN_PA5, 0, 0) +#define PIN_PA5__SDMMC0_DAT2 PINMUX_PIN(PIN_PA5, 1, 1) +#define PIN_PA5__FLEXCOM1_IO0 PINMUX_PIN(PIN_PA5, 2, 1) +#define PIN_PA5__CANTX2 PINMUX_PIN(PIN_PA5, 3, 1) +#define PIN_PA5__A23 PINMUX_PIN(PIN_PA5, 4, 1) +#define PIN_PA5__PWMEXTRG0 PINMUX_PIN(PIN_PA5, 5, 3) +#define PIN_PA5__FLEXCOM2_IO1 PINMUX_PIN(PIN_PA5, 6, 3) +#define PIN_PA6 6 +#define PIN_PA6__GPIO PINMUX_PIN(PIN_PA6, 0, 0) +#define PIN_PA6__SDMMC0_DAT3 PINMUX_PIN(PIN_PA6, 1, 1) +#define PIN_PA6__FLEXCOM1_IO1 PINMUX_PIN(PIN_PA6, 2, 1) +#define PIN_PA6__CANRX2 PINMUX_PIN(PIN_PA6, 3, 1) +#define PIN_PA6__A24 PINMUX_PIN(PIN_PA6, 4, 1) +#define PIN_PA6__PWMEXTRG1 PINMUX_PIN(PIN_PA6, 5, 3) +#define PIN_PA6__FLEXCOM3_IO0 PINMUX_PIN(PIN_PA6, 6, 3) +#define PIN_PA7 7 +#define PIN_PA7__GPIO PINMUX_PIN(PIN_PA7, 0, 0) +#define PIN_PA7__SDMMC0_DAT4 PINMUX_PIN(PIN_PA7, 1, 1) +#define PIN_PA7__FLEXCOM2_IO0 PINMUX_PIN(PIN_PA7, 2, 1) +#define PIN_PA7__CANTX1 PINMUX_PIN(PIN_PA7, 3, 1) +#define PIN_PA7__NWAIT PINMUX_PIN(PIN_PA7, 4, 1) +#define PIN_PA7__PWMFI0 PINMUX_PIN(PIN_PA7, 5, 3) +#define PIN_PA7__FLEXCOM3_IO1 PINMUX_PIN(PIN_PA7, 6, 3) +#define PIN_PA8 8 +#define PIN_PA8__GPIO PINMUX_PIN(PIN_PA8, 0, 0) +#define PIN_PA8__SDMMC0_DAT5 PINMUX_PIN(PIN_PA8, 1, 1) +#define PIN_PA8__FLEXCOM2_IO1 PINMUX_PIN(PIN_PA8, 2, 1) +#define PIN_PA8__CANRX1 PINMUX_PIN(PIN_PA8, 3, 1) +#define PIN_PA8__NCS0 PINMUX_PIN(PIN_PA8, 4, 1) +#define PIN_PA8__PWMIF1 PINMUX_PIN(PIN_PA8, 5, 3) +#define PIN_PA8__FLEXCOM4_IO0 PINMUX_PIN(PIN_PA8, 6, 3) +#define PIN_PA9 9 +#define PIN_PA9__GPIO PINMUX_PIN(PIN_PA9, 0, 0) +#define PIN_PA9__SDMMC0_DAT6 PINMUX_PIN(PIN_PA9, 1, 1) +#define PIN_PA9__FLEXCOM2_IO2 PINMUX_PIN(PIN_PA9, 2, 1) +#define PIN_PA9__CANTX0 PINMUX_PIN(PIN_PA9, 3, 1) +#define PIN_PA9__SMCK PINMUX_PIN(PIN_PA9, 4, 1) +#define PIN_PA9__SPDIF_RX PINMUX_PIN(PIN_PA9, 5, 1) +#define PIN_PA9__FLEXCOM4_IO1 PINMUX_PIN(PIN_PA9, 6, 3) +#define PIN_PA10 10 +#define PIN_PA10__GPIO PINMUX_PIN(PIN_PA10, 0, 0) +#define PIN_PA10__SDMMC0_DAT7 PINMUX_PIN(PIN_PA10, 1, 1) +#define PIN_PA10__FLEXCOM2_IO3 PINMUX_PIN(PIN_PA10, 2, 1) +#define PIN_PA10__CANRX0 PINMUX_PIN(PIN_PA10, 3, 1) +#define PIN_PA10__NCS1 PINMUX_PIN(PIN_PA10, 4, 1) +#define PIN_PA10__SPDIF_TX PINMUX_PIN(PIN_PA10, 5, 1) +#define PIN_PA10__FLEXCOM5_IO0 PINMUX_PIN(PIN_PA10, 6, 3) +#define PIN_PA11 11 +#define PIN_PA11__GPIO PINMUX_PIN(PIN_PA11, 0, 0) +#define PIN_PA11__SDMMC0_DS PINMUX_PIN(PIN_PA11, 1, 1) +#define PIN_PA11__FLEXCOM2_IO4 PINMUX_PIN(PIN_PA11, 2, 1) +#define PIN_PA11__A0_NBS0 PINMUX_PIN(PIN_PA11, 4, 1) +#define PIN_PA11__TIOA0 PINMUX_PIN(PIN_PA11, 5, 1) +#define PIN_PA11__FLEXCOM5_IO1 PINMUX_PIN(PIN_PA11, 6, 3) +#define PIN_PA12 12 +#define PIN_PA12__GPIO PINMUX_PIN(PIN_PA12, 0, 0) +#define PIN_PA12__SDMMC0_WP PINMUX_PIN(PIN_PA12, 1, 1) +#define PIN_PA12__FLEXCOM1_IO3 PINMUX_PIN(PIN_PA12, 2, 1) +#define PIN_PA12__FLEXCOM3_IO5 PINMUX_PIN(PIN_PA12, 4, 1) +#define PIN_PA12__PWML2 PINMUX_PIN(PIN_PA12, 5, 3) +#define PIN_PA12__FLEXCOM6_IO0 PINMUX_PIN(PIN_PA12, 6, 3) +#define PIN_PA13 13 +#define PIN_PA13__GPIO PINMUX_PIN(PIN_PA13, 0, 0) +#define PIN_PA13__SDMMC0_1V8SEL PINMUX_PIN(PIN_PA13, 1, 1) +#define PIN_PA13__FLEXCOM1_IO2 PINMUX_PIN(PIN_PA13, 2, 1) +#define PIN_PA13__FLEXCOM3_IO6 PINMUX_PIN(PIN_PA13, 4, 1) +#define PIN_PA13__PWMH2 PINMUX_PIN(PIN_PA13, 5, 3) +#define PIN_PA13__FLEXCOM6_IO1 PINMUX_PIN(PIN_PA13, 6, 3) +#define PIN_PA14 14 +#define PIN_PA14__GPIO PINMUX_PIN(PIN_PA14, 0, 0) +#define PIN_PA14__SDMMC0_CD PINMUX_PIN(PIN_PA14, 1, 1) +#define PIN_PA14__FLEXCOM1_IO4 PINMUX_PIN(PIN_PA14, 2, 1) +#define PIN_PA14__A25 PINMUX_PIN(PIN_PA14, 4, 1) +#define PIN_PA14__PWML1 PINMUX_PIN(PIN_PA14, 5, 3) +#define PIN_PA15 15 +#define PIN_PA15__GPIO PINMUX_PIN(PIN_PA15, 0, 0) +#define PIN_PA15__G0_TXEN PINMUX_PIN(PIN_PA15, 1, 1) +#define PIN_PA15__FLEXCOM3_IO0 PINMUX_PIN(PIN_PA15, 2, 1) +#define PIN_PA15__ISC_MCK PINMUX_PIN(PIN_PA15, 3, 1) +#define PIN_PA15__A1 PINMUX_PIN(PIN_PA15, 4, 1) +#define PIN_PA15__TIOB0 PINMUX_PIN(PIN_PA15, 5, 1) +#define PIN_PA16 16 +#define PIN_PA16__GPIO PINMUX_PIN(PIN_PA16, 0, 0) +#define PIN_PA16__G0_TX0 PINMUX_PIN(PIN_PA16, 1, 1) +#define PIN_PA16__FLEXCOM3_IO1 PINMUX_PIN(PIN_PA16, 2, 1) +#define PIN_PA16__ISC_D0 PINMUX_PIN(PIN_PA16, 3, 1) +#define PIN_PA16__A2 PINMUX_PIN(PIN_PA16, 4, 1) +#define PIN_PA16__TCLK0 PINMUX_PIN(PIN_PA16, 5, 1) +#define PIN_PA17 17 +#define PIN_PA17__GPIO PINMUX_PIN(PIN_PA17, 0, 0) +#define PIN_PA17__G0_TX1 PINMUX_PIN(PIN_PA17, 1, 1) +#define PIN_PA17__FLEXCOM3_IO2 PINMUX_PIN(PIN_PA17, 2, 1) +#define PIN_PA17__ISC_D1 PINMUX_PIN(PIN_PA17, 3, 1) +#define PIN_PA17__A3 PINMUX_PIN(PIN_PA17, 4, 1) +#define PIN_PA17__TIOA1 PINMUX_PIN(PIN_PA17, 5, 1) +#define PIN_PA18 18 +#define PIN_PA18__GPIO PINMUX_PIN(PIN_PA18, 0, 0) +#define PIN_PA18__G0_RXDV PINMUX_PIN(PIN_PA18, 1, 1) +#define PIN_PA18__FLEXCOM3_IO3 PINMUX_PIN(PIN_PA18, 2, 1) +#define PIN_PA18__ISC_D2 PINMUX_PIN(PIN_PA18, 3, 1) +#define PIN_PA18__A4 PINMUX_PIN(PIN_PA18, 4, 1) +#define PIN_PA18__TIOB1 PINMUX_PIN(PIN_PA18, 5, 1) +#define PIN_PA19 19 +#define PIN_PA19__GPIO PINMUX_PIN(PIN_PA19, 0, 0) +#define PIN_PA19__G0_RX0 PINMUX_PIN(PIN_PA19, 1, 1) +#define PIN_PA19__FLEXCOM3_IO4 PINMUX_PIN(PIN_PA19, 2, 1) +#define PIN_PA19__ISC_D3 PINMUX_PIN(PIN_PA19, 3, 1) +#define PIN_PA19__A5 PINMUX_PIN(PIN_PA19, 4, 1) +#define PIN_PA19__TCLK1 PINMUX_PIN(PIN_PA19, 5, 1) +#define PIN_PA20 20 +#define PIN_PA20__GPIO PINMUX_PIN(PIN_PA20, 0, 0) +#define PIN_PA20__G0_RX1 PINMUX_PIN(PIN_PA20, 1, 1) +#define PIN_PA20__FLEXCOM4_IO0 PINMUX_PIN(PIN_PA20, 2, 1) +#define PIN_PA20__ISC_D4 PINMUX_PIN(PIN_PA20, 3, 1) +#define PIN_PA20__A6 PINMUX_PIN(PIN_PA20, 4, 1) +#define PIN_PA20__TIOA2 PINMUX_PIN(PIN_PA20, 5, 1) +#define PIN_PA21 21 +#define PIN_PA21__GPIO PINMUX_PIN(PIN_PA21, 0, 0) +#define PIN_PA21__G0_RXER PINMUX_PIN(PIN_PA21, 1, 1) +#define PIN_PA21__FLEXCOM4_IO1 PINMUX_PIN(PIN_PA21, 2, 1) +#define PIN_PA21__ISC_D5 PINMUX_PIN(PIN_PA21, 3, 1) +#define PIN_PA21__A7 PINMUX_PIN(PIN_PA21, 4, 1) +#define PIN_PA21__TIOB2 PINMUX_PIN(PIN_PA21, 5, 1) +#define PIN_PA22 22 +#define PIN_PA22__GPIO PINMUX_PIN(PIN_PA22, 0, 0) +#define PIN_PA22__G0_MDC PINMUX_PIN(PIN_PA22, 1, 1) +#define PIN_PA22__FLEXCOM4_IO2 PINMUX_PIN(PIN_PA22, 2, 1) +#define PIN_PA22__ISC_D6 PINMUX_PIN(PIN_PA22, 3, 1) +#define PIN_PA22__A8 PINMUX_PIN(PIN_PA22, 4, 1) +#define PIN_PA22__TCLK2 PINMUX_PIN(PIN_PA22, 5, 1) +#define PIN_PA23 23 +#define PIN_PA23__GPIO PINMUX_PIN(PIN_PA23, 0, 0) +#define PIN_PA23__G0_MDIO PINMUX_PIN(PIN_PA23, 1, 1) +#define PIN_PA23__FLEXCOM4_IO3 PINMUX_PIN(PIN_PA23, 2, 1) +#define PIN_PA23__ISC_D7 PINMUX_PIN(PIN_PA23, 3, 1) +#define PIN_PA23__A9 PINMUX_PIN(PIN_PA23, 4, 1) +#define PIN_PA24 24 +#define PIN_PA24__GPIO PINMUX_PIN(PIN_PA24, 0, 0) +#define PIN_PA24__G0_TXCK PINMUX_PIN(PIN_PA24, 1, 1) +#define PIN_PA24__FLEXCOM4_IO4 PINMUX_PIN(PIN_PA24, 2, 1) +#define PIN_PA24__ISC_HSYNC PINMUX_PIN(PIN_PA24, 3, 1) +#define PIN_PA24__A10 PINMUX_PIN(PIN_PA24, 4, 1) +#define PIN_PA24__FLEXCOM0_IO5 PINMUX_PIN(PIN_PA24, 5, 1) +#define PIN_PA25 25 +#define PIN_PA25__GPIO PINMUX_PIN(PIN_PA25, 0, 0) +#define PIN_PA25__G0_125CK PINMUX_PIN(PIN_PA25, 1, 1) +#define PIN_PA25__FLEXCOM5_IO4 PINMUX_PIN(PIN_PA25, 2, 1) +#define PIN_PA25__ISC_VSYNC PINMUX_PIN(PIN_PA25, 3, 1) +#define PIN_PA25__A11 PINMUX_PIN(PIN_PA25, 4, 1) +#define PIN_PA25__FLEXCOM0_IO6 PINMUX_PIN(PIN_PA25, 5, 1) +#define PIN_PA25__FLEXCOM7_IO0 PINMUX_PIN(PIN_PA25, 6, 3) +#define PIN_PA26 26 +#define PIN_PA26__GPIO PINMUX_PIN(PIN_PA26, 0, 0) +#define PIN_PA26__G0_TX2 PINMUX_PIN(PIN_PA26, 1, 1) +#define PIN_PA26__FLEXCOM5_IO2 PINMUX_PIN(PIN_PA26, 2, 1) +#define PIN_PA26__ISC_FIELD PINMUX_PIN(PIN_PA26, 3, 1) +#define PIN_PA26__A12 PINMUX_PIN(PIN_PA26, 4, 1) +#define PIN_PA26__TF0 PINMUX_PIN(PIN_PA26, 5, 1) +#define PIN_PA26__FLEXCOM7_IO1 PINMUX_PIN(PIN_PA26, 6, 3) +#define PIN_PA27 27 +#define PIN_PA27__GPIO PINMUX_PIN(PIN_PA27, 0, 0) +#define PIN_PA27__G0_TX3 PINMUX_PIN(PIN_PA27, 1, 1) +#define PIN_PA27__FLEXCOM5_IO3 PINMUX_PIN(PIN_PA27, 2, 1) +#define PIN_PA27__ISC_PCK PINMUX_PIN(PIN_PA27, 3, 1) +#define PIN_PA27__A13 PINMUX_PIN(PIN_PA27, 4, 1) +#define PIN_PA27__TK0 PINMUX_PIN(PIN_PA27, 5, 1) +#define PIN_PA27__FLEXCOM8_IO0 PINMUX_PIN(PIN_PA27, 6, 3) +#define PIN_PA28 28 +#define PIN_PA28__GPIO PINMUX_PIN(PIN_PA28, 0, 0) +#define PIN_PA28__G0_RX2 PINMUX_PIN(PIN_PA28, 1, 1) +#define PIN_PA28__FLEXCOM5_IO0 PINMUX_PIN(PIN_PA28, 2, 1) +#define PIN_PA28__ISC_D8 PINMUX_PIN(PIN_PA28, 3, 1) +#define PIN_PA28__A14 PINMUX_PIN(PIN_PA28, 4, 1) +#define PIN_PA28__RD0 PINMUX_PIN(PIN_PA28, 5, 1) +#define PIN_PA28__FLEXCOM8_IO1 PINMUX_PIN(PIN_PA28, 6, 3) +#define PIN_PA29 29 +#define PIN_PA29__GPIO PINMUX_PIN(PIN_PA29, 0, 0) +#define PIN_PA29__G0_RX3 PINMUX_PIN(PIN_PA29, 1, 1) +#define PIN_PA29__FLEXCOM5_IO1 PINMUX_PIN(PIN_PA29, 2, 1) +#define PIN_PA29__ISC_D9 PINMUX_PIN(PIN_PA29, 3, 1) +#define PIN_PA29__A15 PINMUX_PIN(PIN_PA29, 4, 1) +#define PIN_PA29__RF0 PINMUX_PIN(PIN_PA29, 5, 1) +#define PIN_PA29__FLEXCOM9_IO0 PINMUX_PIN(PIN_PA29, 6, 3) +#define PIN_PA30 30 +#define PIN_PA30__GPIO PINMUX_PIN(PIN_PA30, 0, 0) +#define PIN_PA30__G0_RXCK PINMUX_PIN(PIN_PA30, 1, 1) +#define PIN_PA30__FLEXCOM6_IO4 PINMUX_PIN(PIN_PA30, 2, 1) +#define PIN_PA30__ISC_D10 PINMUX_PIN(PIN_PA30, 3, 1) +#define PIN_PA30__A16 PINMUX_PIN(PIN_PA30, 4, 1) +#define PIN_PA30__RK0 PINMUX_PIN(PIN_PA30, 5, 1) +#define PIN_PA30__FLEXCOM9_IO1 PINMUX_PIN(PIN_PA30, 6, 3) +#define PIN_PA31 31 +#define PIN_PA31__GPIO PINMUX_PIN(PIN_PA31, 0, 0) +#define PIN_PA31__G0_TXER PINMUX_PIN(PIN_PA31, 1, 1) +#define PIN_PA31__FLEXCOM6_IO2 PINMUX_PIN(PIN_PA31, 2, 1) +#define PIN_PA31__ISC_D11 PINMUX_PIN(PIN_PA31, 3, 1) +#define PIN_PA31__A17 PINMUX_PIN(PIN_PA31, 4, 1) +#define PIN_PA31__TD0 PINMUX_PIN(PIN_PA31, 5, 1) +#define PIN_PA31__FLEXCOM10_IO0 PINMUX_PIN(PIN_PA31, 6, 3) +#define PIN_PB0 32 +#define PIN_PB0__GPIO PINMUX_PIN(PIN_PB0, 0, 0) +#define PIN_PB0__G0_COL PINMUX_PIN(PIN_PB0, 1, 1) +#define PIN_PB0__FLEXCOM6_IO3 PINMUX_PIN(PIN_PB0, 2, 2) +#define PIN_PB0__EXT_IRQ0 PINMUX_PIN(PIN_PB0, 3, 1) +#define PIN_PB0__A18 PINMUX_PIN(PIN_PB0, 4, 1) +#define PIN_PB0__SPDIF_RX PINMUX_PIN(PIN_PB0, 5, 2) +#define PIN_PB0__FLEXCOM10_IO1 PINMUX_PIN(PIN_PB0, 6, 3) +#define PIN_PB1 33 +#define PIN_PB1__GPIO PINMUX_PIN(PIN_PB1, 0, 0) +#define PIN_PB1__G0_CRS PINMUX_PIN(PIN_PB1, 1, 1) +#define PIN_PB1__FLEXCOM6_IO1 PINMUX_PIN(PIN_PB1, 2, 2) +#define PIN_PB1__EXT_IRQ1 PINMUX_PIN(PIN_PB1, 3, 1) +#define PIN_PB1__A19 PINMUX_PIN(PIN_PB1, 4, 1) +#define PIN_PB1__SPDIF_TX PINMUX_PIN(PIN_PB1, 5, 2) +#define PIN_PB1__FLEXCOM11_IO0 PINMUX_PIN(PIN_PB1, 6, 3) +#define PIN_PB2 34 +#define PIN_PB2__GPIO PINMUX_PIN(PIN_PB2, 0, 0) +#define PIN_PB2__G0_TSUCOMP PINMUX_PIN(PIN_PB2, 1, 1) +#define PIN_PB2__FLEXCOM6_IO0 PINMUX_PIN(PIN_PB2, 2, 1) +#define PIN_PB2__ADTRG PINMUX_PIN(PIN_PB2, 3, 1) +#define PIN_PB2__A20 PINMUX_PIN(PIN_PB2, 4, 1) +#define PIN_PB2__FLEXCOM11_IO0 PINMUX_PIN(PIN_PB2, 6, 3) +#define PIN_PB3 35 +#define PIN_PB3__GPIO PINMUX_PIN(PIN_PB3, 0, 0) +#define PIN_PB3__RF1 PINMUX_PIN(PIN_PB3, 1, 1) +#define PIN_PB3__FLEXCOM11_IO0 PINMUX_PIN(PIN_PB3, 2, 1) +#define PIN_PB3__PCK2 PINMUX_PIN(PIN_PB3, 3, 2) +#define PIN_PB3__D8 PINMUX_PIN(PIN_PB3, 4, 1) +#define PIN_PB4 36 +#define PIN_PB4__GPIO PINMUX_PIN(PIN_PB4, 0, 0) +#define PIN_PB4__TF1 PINMUX_PIN(PIN_PB4, 1, 1) +#define PIN_PB4__FLEXCOM11_IO1 PINMUX_PIN(PIN_PB4, 2, 1) +#define PIN_PB4__PCK3 PINMUX_PIN(PIN_PB4, 3, 2) +#define PIN_PB4__D9 PINMUX_PIN(PIN_PB4, 4, 1) +#define PIN_PB5 37 +#define PIN_PB5__GPIO PINMUX_PIN(PIN_PB5, 0, 0) +#define PIN_PB5__TK1 PINMUX_PIN(PIN_PB5, 1, 1) +#define PIN_PB5__FLEXCOM11_IO2 PINMUX_PIN(PIN_PB5, 2, 1) +#define PIN_PB5__PCK4 PINMUX_PIN(PIN_PB5, 3, 2) +#define PIN_PB5__D10 PINMUX_PIN(PIN_PB5, 4, 1) +#define PIN_PB6 38 +#define PIN_PB6__GPIO PINMUX_PIN(PIN_PB6, 0, 0) +#define PIN_PB6__RK1 PINMUX_PIN(PIN_PB6, 1, 1) +#define PIN_PB6__FLEXCOM11_IO3 PINMUX_PIN(PIN_PB6, 2, 1) +#define PIN_PB6__PCK5 PINMUX_PIN(PIN_PB6, 3, 2) +#define PIN_PB6__D11 PINMUX_PIN(PIN_PB6, 4, 1) +#define PIN_PB7 39 +#define PIN_PB7__GPIO PINMUX_PIN(PIN_PB7, 0, 0) +#define PIN_PB7__TD1 PINMUX_PIN(PIN_PB7, 1, 1) +#define PIN_PB7__FLEXCOM11_IO4 PINMUX_PIN(PIN_PB7, 2, 1) +#define PIN_PB7__FLEXCOM3_IO5 PINMUX_PIN(PIN_PB7, 3, 2) +#define PIN_PB7__D12 PINMUX_PIN(PIN_PB7, 4, 1) +#define PIN_PB8 40 +#define PIN_PB8__GPIO PINMUX_PIN(PIN_PB8, 0, 0) +#define PIN_PB8__RD1 PINMUX_PIN(PIN_PB8, 1, 1) +#define PIN_PB8__FLEXCOM8_IO0 PINMUX_PIN(PIN_PB8, 2, 1) +#define PIN_PB8__FLEXCOM3_IO6 PINMUX_PIN(PIN_PB8, 3, 2) +#define PIN_PB8__D13 PINMUX_PIN(PIN_PB8, 4, 1) +#define PIN_PB9 41 +#define PIN_PB9__GPIO PINMUX_PIN(PIN_PB9, 0, 0) +#define PIN_PB9__QSPI0_IO3 PINMUX_PIN(PIN_PB9, 1, 1) +#define PIN_PB9__FLEXCOM8_IO1 PINMUX_PIN(PIN_PB9, 2, 1) +#define PIN_PB9__PDMC0_CLK PINMUX_PIN(PIN_PB9, 3, 1) +#define PIN_PB9__NCS3_NANDCS PINMUX_PIN(PIN_PB9, 4, 1) +#define PIN_PB9__PWML0 PINMUX_PIN(PIN_PB9, 5, 2) +#define PIN_PB10 42 +#define PIN_PB10__GPIO PINMUX_PIN(PIN_PB10, 0, 0) +#define PIN_PB10__QSPI0_IO2 PINMUX_PIN(PIN_PB10, 1, 1) +#define PIN_PB10__FLEXCOM8_IO2 PINMUX_PIN(PIN_PB10, 2, 1) +#define PIN_PB10__PDMC0_DS0 PINMUX_PIN(PIN_PB10, 3, 1) +#define PIN_PB10__NWE_NWR0_NANDWE PINMUX_PIN(PIN_PB10, 4, 1) +#define PIN_PB10__PWMH0 PINMUX_PIN(PIN_PB10, 5, 2) +#define PIN_PB11 43 +#define PIN_PB11__GPIO PINMUX_PIN(PIN_PB11, 0, 0) +#define PIN_PB11__QSPI0_IO1 PINMUX_PIN(PIN_PB11, 1, 1) +#define PIN_PB11__FLEXCOM8_IO3 PINMUX_PIN(PIN_PB11, 2, 1) +#define PIN_PB11__PDMC0_DS1 PINMUX_PIN(PIN_PB11, 3, 1) +#define PIN_PB11__NRD_NANDOE PINMUX_PIN(PIN_PB11, 4, 1) +#define PIN_PB11__PWML1 PINMUX_PIN(PIN_PB11, 5, 2) +#define PIN_PB12 44 +#define PIN_PB12__GPIO PINMUX_PIN(PIN_PB12, 0, 0) +#define PIN_PB12__QSPI0_IO0 PINMUX_PIN(PIN_PB12, 1, 1) +#define PIN_PB12__FLEXCOM8_IO4 PINMUX_PIN(PIN_PB12, 2, 1) +#define PIN_PB12__FLEXCOM6_IO5 PINMUX_PIN(PIN_PB12, 3, 1) +#define PIN_PB12__A21_NANDALE PINMUX_PIN(PIN_PB12, 4, 1) +#define PIN_PB12__PWMH1 PINMUX_PIN(PIN_PB12, 5, 2) +#define PIN_PB13 45 +#define PIN_PB13__GPIO PINMUX_PIN(PIN_PB13, 0, 0) +#define PIN_PB13__QSPI0_CS PINMUX_PIN(PIN_PB13, 1, 1) +#define PIN_PB13__FLEXCOM9_IO0 PINMUX_PIN(PIN_PB13, 2, 1) +#define PIN_PB13__FLEXCOM6_IO6 PINMUX_PIN(PIN_PB13, 3, 1) +#define PIN_PB13__A22_NANDCLE PINMUX_PIN(PIN_PB13, 4, 1) +#define PIN_PB13__PWML2 PINMUX_PIN(PIN_PB13, 5, 2) +#define PIN_PB14 46 +#define PIN_PB14__GPIO PINMUX_PIN(PIN_PB14, 0, 0) +#define PIN_PB14__QSPI0_SCK PINMUX_PIN(PIN_PB14, 1, 1) +#define PIN_PB14__FLEXCOM9_IO1 PINMUX_PIN(PIN_PB14, 2, 1) +#define PIN_PB14__D0 PINMUX_PIN(PIN_PB14, 4, 1) +#define PIN_PB14__PWMH2 PINMUX_PIN(PIN_PB14, 5, 2) +#define PIN_PB15 47 +#define PIN_PB15__GPIO PINMUX_PIN(PIN_PB15, 0, 0) +#define PIN_PB15__QSPI0_SCKN PINMUX_PIN(PIN_PB15, 1, 1) +#define PIN_PB15__FLEXCOM9_IO2 PINMUX_PIN(PIN_PB15, 2, 1) +#define PIN_PB15__D1 PINMUX_PIN(PIN_PB15, 4, 1) +#define PIN_PB15__PWML3 PINMUX_PIN(PIN_PB15, 5, 2) +#define PIN_PB16 48 +#define PIN_PB16__GPIO PINMUX_PIN(PIN_PB16, 0, 0) +#define PIN_PB16__QSPI0_IO4 PINMUX_PIN(PIN_PB16, 1, 1) +#define PIN_PB16__FLEXCOM9_IO3 PINMUX_PIN(PIN_PB16, 2, 1) +#define PIN_PB16__PCK0 PINMUX_PIN(PIN_PB16, 3, 1) +#define PIN_PB16__D2 PINMUX_PIN(PIN_PB16, 4, 1) +#define PIN_PB16__PWMH3 PINMUX_PIN(PIN_PB16, 5, 2) +#define PIN_PB16__EXT_IRQ0 PINMUX_PIN(PIN_PB16, 6, 2) +#define PIN_PB17 49 +#define PIN_PB17__GPIO PINMUX_PIN(PIN_PB17, 0, 0) +#define PIN_PB17__QSPI0_IO5 PINMUX_PIN(PIN_PB17, 1, 1) +#define PIN_PB17__FLEXCOM9_IO4 PINMUX_PIN(PIN_PB17, 2, 1) +#define PIN_PB17__PCK1 PINMUX_PIN(PIN_PB17, 3, 1) +#define PIN_PB17__D3 PINMUX_PIN(PIN_PB17, 4, 1) +#define PIN_PB17__PWMEXTRG0 PINMUX_PIN(PIN_PB17, 5, 2) +#define PIN_PB17__EXT_IRQ1 PINMUX_PIN(PIN_PB17, 6, 2) +#define PIN_PB18 50 +#define PIN_PB18__GPIO PINMUX_PIN(PIN_PB18, 0, 0) +#define PIN_PB18__QSPI0_IO6 PINMUX_PIN(PIN_PB18, 1, 1) +#define PIN_PB18__FLEXCOM10_IO0 PINMUX_PIN(PIN_PB18, 2, 1) +#define PIN_PB18__PCK2 PINMUX_PIN(PIN_PB18, 3, 1) +#define PIN_PB18__D4 PINMUX_PIN(PIN_PB18, 4, 1) +#define PIN_PB18__PWMEXTRG1 PINMUX_PIN(PIN_PB18, 5, 2) +#define PIN_PB19 51 +#define PIN_PB19__GPIO PINMUX_PIN(PIN_PB19, 0, 0) +#define PIN_PB19__QSPI0_IO7 PINMUX_PIN(PIN_PB19, 1, 1) +#define PIN_PB19__FLEXCOM10_IO1 PINMUX_PIN(PIN_PB19, 2, 1) +#define PIN_PB19__PCK3 PINMUX_PIN(PIN_PB19, 3, 1) +#define PIN_PB19__D5 PINMUX_PIN(PIN_PB19, 4, 1) +#define PIN_PB19__PWMFI0 PINMUX_PIN(PIN_PB19, 5, 2) +#define PIN_PB20 52 +#define PIN_PB20__GPIO PINMUX_PIN(PIN_PB20, 0, 0) +#define PIN_PB20__QSPI0_DQS PINMUX_PIN(PIN_PB20, 1, 1) +#define PIN_PB20__FLEXCOM10_IO2 PINMUX_PIN(PIN_PB20, 2, 1) +#define PIN_PB20__D6 PINMUX_PIN(PIN_PB20, 4, 1) +#define PIN_PB20__PWMFI1 PINMUX_PIN(PIN_PB20, 5, 2) +#define PIN_PB21 53 +#define PIN_PB21__GPIO PINMUX_PIN(PIN_PB21, 0, 0) +#define PIN_PB21__QSPI0_INT PINMUX_PIN(PIN_PB21, 1, 1) +#define PIN_PB21__FLEXCOM10_IO3 PINMUX_PIN(PIN_PB21, 2, 1) +#define PIN_PB21__FLEXCOM9_IO5 PINMUX_PIN(PIN_PB21, 3, 1) +#define PIN_PB21__D7 PINMUX_PIN(PIN_PB21, 4, 1) +#define PIN_PB22 54 +#define PIN_PB22__GPIO PINMUX_PIN(PIN_PB22, 0, 0) +#define PIN_PB22__QSPI1_IO3 PINMUX_PIN(PIN_PB22, 1, 1) +#define PIN_PB22__FLEXCOM10_IO4 PINMUX_PIN(PIN_PB22, 2, 1) +#define PIN_PB22__FLEXCOM9_IO6 PINMUX_PIN(PIN_PB22, 3, 1) +#define PIN_PB22__NANDRDY PINMUX_PIN(PIN_PB22, 4, 1) +#define PIN_PB23 55 +#define PIN_PB23__GPIO PINMUX_PIN(PIN_PB23, 0, 0) +#define PIN_PB23__QSPI1_IO2 PINMUX_PIN(PIN_PB23, 1, 1) +#define PIN_PB23__FLEXCOM7_IO0 PINMUX_PIN(PIN_PB23, 2, 1) +#define PIN_PB23__I2SMCC0_CK PINMUX_PIN(PIN_PB23, 3, 1) +#define PIN_PB23__PCK4 PINMUX_PIN(PIN_PB23, 6, 1) +#define PIN_PB24 56 +#define PIN_PB24__GPIO PINMUX_PIN(PIN_PB24, 0, 0) +#define PIN_PB24__QSPI1_IO1 PINMUX_PIN(PIN_PB24, 1, 1) +#define PIN_PB24__FLEXCOM7_IO1 PINMUX_PIN(PIN_PB24, 2, 1) +#define PIN_PB24__I2SMCC0_WS PINMUX_PIN(PIN_PB24, 3, 1) +#define PIN_PB24__PCK5 PINMUX_PIN(PIN_PB24, 6, 1) +#define PIN_PB25 57 +#define PIN_PB25__GPIO PINMUX_PIN(PIN_PB25, 0, 0) +#define PIN_PB25__QSPI1_IO0 PINMUX_PIN(PIN_PB25, 1, 1) +#define PIN_PB25__FLEXCOM7_IO2 PINMUX_PIN(PIN_PB25, 2, 1) +#define PIN_PB25__I2SMCC0_DOUT1 PINMUX_PIN(PIN_PB25, 3, 1) +#define PIN_PB25__PCK6 PINMUX_PIN(PIN_PB25, 6, 1) +#define PIN_PB26 58 +#define PIN_PB26__GPIO PINMUX_PIN(PIN_PB26, 0, 0) +#define PIN_PB26__QSPI1_CS PINMUX_PIN(PIN_PB26, 1, 1) +#define PIN_PB26__FLEXCOM7_IO3 PINMUX_PIN(PIN_PB26, 2, 1) +#define PIN_PB26__I2SMCC0_DOUT0 PINMUX_PIN(PIN_PB26, 3, 1) +#define PIN_PB26__PWMEXTRG0 PINMUX_PIN(PIN_PB26, 5, 1) +#define PIN_PB26__PCK7 PINMUX_PIN(PIN_PB26, 6, 1) +#define PIN_PB27 59 +#define PIN_PB27__GPIO PINMUX_PIN(PIN_PB27, 0, 0) +#define PIN_PB27__QSPI1_SCK PINMUX_PIN(PIN_PB27, 1, 1) +#define PIN_PB27__FLEXCOM7_IO4 PINMUX_PIN(PIN_PB27, 2, 1) +#define PIN_PB27__I2SMCC0_MCK PINMUX_PIN(PIN_PB27, 3, 1) +#define PIN_PB27__PWMEXTRG1 PINMUX_PIN(PIN_PB27, 5, 1) +#define PIN_PB28 60 +#define PIN_PB28__GPIO PINMUX_PIN(PIN_PB28, 0, 0) +#define PIN_PB28__SDMMC1_RSTN PINMUX_PIN(PIN_PB28, 1, 1) +#define PIN_PB28__ADTRG PINMUX_PIN(PIN_PB28, 2, 2) +#define PIN_PB28__PWMFI0 PINMUX_PIN(PIN_PB28, 5, 1) +#define PIN_PB28__FLEXCOM7_IO0 PINMUX_PIN(PIN_PB28, 6, 4) +#define PIN_PB29 61 +#define PIN_PB29__GPIO PINMUX_PIN(PIN_PB29, 0, 0) +#define PIN_PB29__SDMMC1_CMD PINMUX_PIN(PIN_PB29, 1, 1) +#define PIN_PB29__FLEXCOM3_IO2 PINMUX_PIN(PIN_PB29, 2, 2) +#define PIN_PB29__FLEXCOM0_IO5 PINMUX_PIN(PIN_PB29, 3, 2) +#define PIN_PB29__TIOA3 PINMUX_PIN(PIN_PB29, 4, 2) +#define PIN_PB29__PWMFI1 PINMUX_PIN(PIN_PB29, 5, 1) +#define PIN_PB29__FLEXCOM7_IO1 PINMUX_PIN(PIN_PB29, 6, 4) +#define PIN_PB30 62 +#define PIN_PB30__GPIO PINMUX_PIN(PIN_PB30, 0, 0) +#define PIN_PB30__SDMMC1_CK PINMUX_PIN(PIN_PB30, 1, 1) +#define PIN_PB30__FLEXCOM3_IO3 PINMUX_PIN(PIN_PB30, 2, 2) +#define PIN_PB30__FLEXCOM0_IO6 PINMUX_PIN(PIN_PB30, 3, 2) +#define PIN_PB30__TIOB3 PINMUX_PIN(PIN_PB30, 4, 1) +#define PIN_PB30__PWMH0 PINMUX_PIN(PIN_PB30, 5, 1) +#define PIN_PB30__FLEXCOM8_IO0 PINMUX_PIN(PIN_PB30, 6, 4) +#define PIN_PB31 63 +#define PIN_PB31__GPIO PINMUX_PIN(PIN_PB31, 0, 0) +#define PIN_PB31__SDMMC1_DAT0 PINMUX_PIN(PIN_PB31, 1, 1) +#define PIN_PB31__FLEXCOM3_IO4 PINMUX_PIN(PIN_PB31, 2, 2) +#define PIN_PB31__FLEXCOM9_IO5 PINMUX_PIN(PIN_PB31, 3, 2) +#define PIN_PB31__TCLK3 PINMUX_PIN(PIN_PB31, 4, 1) +#define PIN_PB31__PWML0 PINMUX_PIN(PIN_PB31, 5, 1) +#define PIN_PB31__FLEXCOM8_IO1 PINMUX_PIN(PIN_PB31, 6, 4) +#define PIN_PC0 64 +#define PIN_PC0__GPIO PINMUX_PIN(PIN_PC0, 0, 0) +#define PIN_PC0__SDMMC1_DAT1 PINMUX_PIN(PIN_PC0, 1, 1) +#define PIN_PC0__FLEXCOM3_IO0 PINMUX_PIN(PIN_PC0, 2, 2) +#define PIN_PC0__TIOA4 PINMUX_PIN(PIN_PC0, 4, 1) +#define PIN_PC0__PWML1 PINMUX_PIN(PIN_PC0, 5, 1) +#define PIN_PC0__FLEXCOM9_IO0 PINMUX_PIN(PIN_PC0, 6, 4) +#define PIN_PC1 65 +#define PIN_PC1__GPIO PINMUX_PIN(PIN_PC1, 0, 0) +#define PIN_PC1__SDMMC1_DAT2 PINMUX_PIN(PIN_PC1, 1, 1) +#define PIN_PC1__FLEXCOM3_IO1 PINMUX_PIN(PIN_PC1, 2, 2) +#define PIN_PC1__TIOB4 PINMUX_PIN(PIN_PC1, 4, 1) +#define PIN_PC1__PWMH1 PINMUX_PIN(PIN_PC1, 5, 1) +#define PIN_PC1__FLEXCOM9_IO1 PINMUX_PIN(PIN_PC1, 6, 4) +#define PIN_PC2 66 +#define PIN_PC2__GPIO PINMUX_PIN(PIN_PC2, 0, 0) +#define PIN_PC2__SDMMC1_DAT3 PINMUX_PIN(PIN_PC2, 1, 1) +#define PIN_PC2__FLEXCOM4_IO0 PINMUX_PIN(PIN_PC2, 2, 2) +#define PIN_PC2__TCLK4 PINMUX_PIN(PIN_PC2, 4, 1) +#define PIN_PC2__PWML2 PINMUX_PIN(PIN_PC2, 5, 1) +#define PIN_PC2__FLEXCOM10_IO0 PINMUX_PIN(PIN_PC2, 6, 4) +#define PIN_PC3 67 +#define PIN_PC3__GPIO PINMUX_PIN(PIN_PC3, 0, 0) +#define PIN_PC3__SDMMC1_WP PINMUX_PIN(PIN_PC3, 1, 1) +#define PIN_PC3__FLEXCOM4_IO1 PINMUX_PIN(PIN_PC3, 2, 2) +#define PIN_PC3__TIOA5 PINMUX_PIN(PIN_PC3, 4, 1) +#define PIN_PC3__PWMH2 PINMUX_PIN(PIN_PC3, 5, 1) +#define PIN_PC3__FLEXCOM10_IO1 PINMUX_PIN(PIN_PC3, 6, 4) +#define PIN_PC4 68 +#define PIN_PC4__GPIO PINMUX_PIN(PIN_PC4, 0, 0) +#define PIN_PC4__SDMMC1_CD PINMUX_PIN(PIN_PC4, 1, 1) +#define PIN_PC4__FLEXCOM4_IO2 PINMUX_PIN(PIN_PC4, 2, 2) +#define PIN_PC4__FLEXCOM9_IO6 PINMUX_PIN(PIN_PC4, 3, 2) +#define PIN_PC4__TIOB5 PINMUX_PIN(PIN_PC4, 4, 1) +#define PIN_PC4__PWML3 PINMUX_PIN(PIN_PC4, 5, 1) +#define PIN_PC4__FLEXCOM11_IO0 PINMUX_PIN(PIN_PC4, 6, 4) +#define PIN_PC5 69 +#define PIN_PC5__GPIO PINMUX_PIN(PIN_PC5, 0, 0) +#define PIN_PC5__SDMMC1_1V8SEL PINMUX_PIN(PIN_PC5, 1, 1) +#define PIN_PC5__FLEXCOM4_IO3 PINMUX_PIN(PIN_PC5, 2, 2) +#define PIN_PC5__FLEXCOM6_IO5 PINMUX_PIN(PIN_PC5, 3, 2) +#define PIN_PC5__TCLK5 PINMUX_PIN(PIN_PC5, 4, 1) +#define PIN_PC5__PWMH3 PINMUX_PIN(PIN_PC5, 5, 1) +#define PIN_PC5__FLEXCOM11_IO1 PINMUX_PIN(PIN_PC5, 6, 4) +#define PIN_PC6 70 +#define PIN_PC6__GPIO PINMUX_PIN(PIN_PC6, 0, 0) +#define PIN_PC6__FLEXCOM4_IO4 PINMUX_PIN(PIN_PC6, 2, 2) +#define PIN_PC6__FLEXCOM6_IO6 PINMUX_PIN(PIN_PC6, 3, 2) +#define PIN_PC7 71 +#define PIN_PC7__GPIO PINMUX_PIN(PIN_PC7, 0, 0) +#define PIN_PC7__I2SMCC0_DIN0 PINMUX_PIN(PIN_PC7, 1, 1) +#define PIN_PC7__FLEXCOM7_IO0 PINMUX_PIN(PIN_PC7, 2, 2) +#define PIN_PC8 72 +#define PIN_PC8__GPIO PINMUX_PIN(PIN_PC8, 0, 0) +#define PIN_PC8__I2SMCC0_DIN1 PINMUX_PIN(PIN_PC8, 1, 1) +#define PIN_PC8__FLEXCOM7_IO1 PINMUX_PIN(PIN_PC8, 2, 2) +#define PIN_PC9 73 +#define PIN_PC9__GPIO PINMUX_PIN(PIN_PC9, 0, 0) +#define PIN_PC9__I2SMCC0_DOUT3 PINMUX_PIN(PIN_PC9, 1, 1) +#define PIN_PC9__FLEXCOM7_IO2 PINMUX_PIN(PIN_PC9, 2, 2) +#define PIN_PC9__FLEXCOM1_IO0 PINMUX_PIN(PIN_PC9, 6, 4) +#define PIN_PC10 74 +#define PIN_PC10__GPIO PINMUX_PIN(PIN_PC10, 0, 0) +#define PIN_PC10__I2SMCC0_DOUT2 PINMUX_PIN(PIN_PC10, 1, 1) +#define PIN_PC10__FLEXCOM7_IO3 PINMUX_PIN(PIN_PC10, 2, 2) +#define PIN_PC10__FLEXCOM1_IO1 PINMUX_PIN(PIN_PC10, 6, 4) +#define PIN_PC11 75 +#define PIN_PC11__GPIO PINMUX_PIN(PIN_PC11, 0, 0) +#define PIN_PC11__I2SMCC1_CK PINMUX_PIN(PIN_PC11, 1, 1) +#define PIN_PC11__FLEXCOM7_IO4 PINMUX_PIN(PIN_PC11, 2, 2) +#define PIN_PC11__FLEXCOM2_IO0 PINMUX_PIN(PIN_PC11, 6, 4) +#define PIN_PC12 76 +#define PIN_PC12__GPIO PINMUX_PIN(PIN_PC12, 0, 0) +#define PIN_PC12__I2SMCC1_WS PINMUX_PIN(PIN_PC12, 1, 1) +#define PIN_PC12__FLEXCOM8_IO2 PINMUX_PIN(PIN_PC12, 2, 2) +#define PIN_PC12__FLEXCOM2_IO1 PINMUX_PIN(PIN_PC12, 6, 4) +#define PIN_PC13 77 +#define PIN_PC13__GPIO PINMUX_PIN(PIN_PC13, 0, 0) +#define PIN_PC13__I2SMCC1_MCK PINMUX_PIN(PIN_PC13, 1, 1) +#define PIN_PC13__FLEXCOM8_IO1 PINMUX_PIN(PIN_PC13, 2, 2) +#define PIN_PC13__FLEXCOM3_IO0 PINMUX_PIN(PIN_PC13, 6, 4) +#define PIN_PC14 78 +#define PIN_PC14__GPIO PINMUX_PIN(PIN_PC14, 0, 0) +#define PIN_PC14__I2SMCC1_DOUT0 PINMUX_PIN(PIN_PC14, 1, 1) +#define PIN_PC14__FLEXCOM8_IO0 PINMUX_PIN(PIN_PC14, 2, 2) +#define PIN_PC14__FLEXCOM3_IO1 PINMUX_PIN(PIN_PC14, 6, 4) +#define PIN_PC15 79 +#define PIN_PC15__GPIO PINMUX_PIN(PIN_PC15, 0, 0) +#define PIN_PC15__I2SMCC1_DOUT1 PINMUX_PIN(PIN_PC15, 1, 1) +#define PIN_PC15__FLEXCOM8_IO3 PINMUX_PIN(PIN_PC15, 2, 2) +#define PIN_PC15__FLEXCOM4_IO0 PINMUX_PIN(PIN_PC15, 6, 4) +#define PIN_PC16 80 +#define PIN_PC16__GPIO PINMUX_PIN(PIN_PC16, 0, 0) +#define PIN_PC16__I2SMCC_DOUT2 PINMUX_PIN(PIN_PC16, 1, 1) +#define PIN_PC16__FLEXCOM8_IO4 PINMUX_PIN(PIN_PC16, 2, 2) +#define PIN_PC16__FLEXCOM3_IO1 PINMUX_PIN(PIN_PC16, 6, 4) +#define PIN_PC17 81 +#define PIN_PC17__GPIO PINMUX_PIN(PIN_PC17, 0, 0) +#define PIN_PC17__I2SMCC1_DOUT3 PINMUX_PIN(PIN_PC17, 1, 1) +#define PIN_PC17__EXT_IRQ0 PINMUX_PIN(PIN_PC17, 2, 3) +#define PIN_PC17__FLEXCOM5_IO0 PINMUX_PIN(PIN_PC17, 6, 4) +#define PIN_PC18 82 +#define PIN_PC18__GPIO PINMUX_PIN(PIN_PC18, 0, 0) +#define PIN_PC18__I2SMCC1_DIN0 PINMUX_PIN(PIN_PC18, 1, 1) +#define PIN_PC18__FLEXCOM9_IO0 PINMUX_PIN(PIN_PC18, 2, 2) +#define PIN_PC18__FLEXCOM5_IO1 PINMUX_PIN(PIN_PC18, 6, 4) +#define PIN_PC19 83 +#define PIN_PC19__GPIO PINMUX_PIN(PIN_PC19, 0, 0) +#define PIN_PC19__I2SMCC1_DIN1 PINMUX_PIN(PIN_PC19, 1, 1) +#define PIN_PC19__FLEXCOM9_IO1 PINMUX_PIN(PIN_PC19, 2, 2) +#define PIN_PC19__FLEXCOM6_IO0 PINMUX_PIN(PIN_PC19, 6, 4) +#define PIN_PC20 84 +#define PIN_PC20__GPIO PINMUX_PIN(PIN_PC20, 0, 0) +#define PIN_PC20__I2SMCC1_DIN2 PINMUX_PIN(PIN_PC20, 1, 1) +#define PIN_PC20__FLEXCOM9_IO4 PINMUX_PIN(PIN_PC20, 2, 2) +#define PIN_PC20__FLEXCOM6_IO1 PINMUX_PIN(PIN_PC20, 6, 4) +#define PIN_PC21 85 +#define PIN_PC21__GPIO PINMUX_PIN(PIN_PC21, 0, 0) +#define PIN_PC21__I2SMCC1_DIN3 PINMUX_PIN(PIN_PC21, 1, 1) +#define PIN_PC21__FLEXCOM9_IO2 PINMUX_PIN(PIN_PC21, 2, 2) +#define PIN_PC21__D3 PINMUX_PIN(PIN_PC21, 4, 2) +#define PIN_PC21__FLEXCOM6_IO0 PINMUX_PIN(PIN_PC21, 6, 5) +#define PIN_PC22 86 +#define PIN_PC22__GPIO PINMUX_PIN(PIN_PC22, 0, 0) +#define PIN_PC22__I2SMCC0_DIN2 PINMUX_PIN(PIN_PC22, 1, 1) +#define PIN_PC22__FLEXCOM9_IO3 PINMUX_PIN(PIN_PC22, 2, 2) +#define PIN_PC22__D4 PINMUX_PIN(PIN_PC22, 4, 2) +#define PIN_PC22__FLEXCOM6_IO1 PINMUX_PIN(PIN_PC22, 6, 5) +#define PIN_PC23 87 +#define PIN_PC23__GPIO PINMUX_PIN(PIN_PC23, 0, 0) +#define PIN_PC23__I2SMCC0_DIN3 PINMUX_PIN(PIN_PC23, 1, 1) +#define PIN_PC23__FLEXCOM0_IO5 PINMUX_PIN(PIN_PC23, 2, 3) +#define PIN_PC23__D5 PINMUX_PIN(PIN_PC23, 4, 2) +#define PIN_PC23__FLEXCOM7_IO0 PINMUX_PIN(PIN_PC23, 6, 5) +#define PIN_PC24 88 +#define PIN_PC24__GPIO PINMUX_PIN(PIN_PC24, 0, 0) +#define PIN_PC24__FLEXCOM0_IO6 PINMUX_PIN(PIN_PC24, 2, 3) +#define PIN_PC24__EXT_IRQ1 PINMUX_PIN(PIN_PC24, 3, 3) +#define PIN_PC24__D6 PINMUX_PIN(PIN_PC24, 4, 2) +#define PIN_PC24__FLEXCOM7_IO1 PINMUX_PIN(PIN_PC24, 6, 5) +#define PIN_PC25 89 +#define PIN_PC25__GPIO PINMUX_PIN(PIN_PC25, 0, 0) +#define PIN_PC25__NTRST PINMUX_PIN(PIN_PC25, 1, 1) +#define PIN_PC26 90 +#define PIN_PC26__GPIO PINMUX_PIN(PIN_PC26, 0, 0) +#define PIN_PC26__TCK_SWCLK PINMUX_PIN(PIN_PC26, 1, 1) +#define PIN_PC27 91 +#define PIN_PC27__GPIO PINMUX_PIN(PIN_PC27, 0, 0) +#define PIN_PC27__TMS_SWDIO PINMUX_PIN(PIN_PC27, 1, 1) +#define PIN_PC28 92 +#define PIN_PC28__GPIO PINMUX_PIN(PIN_PC28, 0, 0) +#define PIN_PC28__TDI PINMUX_PIN(PIN_PC28, 1, 1) +#define PIN_PC29 93 +#define PIN_PC29__GPIO PINMUX_PIN(PIN_PC29, 0, 0) +#define PIN_PC29__TDO PINMUX_PIN(PIN_PC29, 1, 1) +#define PIN_PC30 94 +#define PIN_PC30__GPIO PINMUX_PIN(PIN_PC30, 0, 0) +#define PIN_PC30__FLEXCOM10_IO0 PINMUX_PIN(PIN_PC30, 2, 2) +#define PIN_PC31 95 +#define PIN_PC31__GPIO PINMUX_PIN(PIN_PC31, 0, 0) +#define PIN_PC31__FLEXCOM10_IO1 PINMUX_PIN(PIN_PC31, 2, 2) +#define PIN_PD0 96 +#define PIN_PD0__GPIO PINMUX_PIN(PIN_PD0, 0, 0) +#define PIN_PD0__FLEXCOM11_IO0 PINMUX_PIN(PIN_PD0, 2, 2) +#define PIN_PD1 97 +#define PIN_PD1__GPIO PINMUX_PIN(PIN_PD1, 0, 0) +#define PIN_PD1__FLEXCOM11_IO1 PINMUX_PIN(PIN_PD1, 2, 2) +#define PIN_PD2 98 +#define PIN_PD2__GPIO PINMUX_PIN(PIN_PD2, 0, 0) +#define PIN_PD2__SDMMC2_RSTN PINMUX_PIN(PIN_PD2, 1, 1) +#define PIN_PD2__PCK0 PINMUX_PIN(PIN_PD2, 2, 2) +#define PIN_PD2__CANTX4 PINMUX_PIN(PIN_PD2, 3, 1) +#define PIN_PD2__D7 PINMUX_PIN(PIN_PD2, 4, 2) +#define PIN_PD2__TIOA0 PINMUX_PIN(PIN_PD2, 5, 2) +#define PIN_PD2__FLEXCOM8_IO0 PINMUX_PIN(PIN_PD2, 6, 5) +#define PIN_PD3 99 +#define PIN_PD3__GPIO PINMUX_PIN(PIN_PD3, 0, 0) +#define PIN_PD3__SDMMC2_CMD PINMUX_PIN(PIN_PD3, 1, 1) +#define PIN_PD3__FLEXCOM0_IO0 PINMUX_PIN(PIN_PD3, 2, 2) +#define PIN_PD3__CANRX4 PINMUX_PIN(PIN_PD3, 3, 1) +#define PIN_PD3__NANDRDY PINMUX_PIN(PIN_PD3, 4, 2) +#define PIN_PD3__TIOB0 PINMUX_PIN(PIN_PD3, 5, 2) +#define PIN_PD3__FLEXCOM8_IO1 PINMUX_PIN(PIN_PD3, 6, 5) +#define PIN_PD4 100 +#define PIN_PD4__GPIO PINMUX_PIN(PIN_PD4, 0, 0) +#define PIN_PD4__SDMMC2_CK PINMUX_PIN(PIN_PD4, 1, 1) +#define PIN_PD4__FLEXCOM0_IO1 PINMUX_PIN(PIN_PD4, 2, 2) +#define PIN_PD4__CANTX5 PINMUX_PIN(PIN_PD4, 3, 1) +#define PIN_PD4__NCS3_NANDCS PINMUX_PIN(PIN_PD4, 4, 2) +#define PIN_PD4__TCLK0 PINMUX_PIN(PIN_PD4, 5, 2) +#define PIN_PD4__FLEXCOM9_IO0 PINMUX_PIN(PIN_PD4, 6, 5) +#define PIN_PD5 101 +#define PIN_PD5__GPIO PINMUX_PIN(PIN_PD5, 0, 0) +#define PIN_PD5__SDMMC2_DAT0 PINMUX_PIN(PIN_PD5, 1, 1) +#define PIN_PD5__FLEXCOM0_IO2 PINMUX_PIN(PIN_PD5, 2, 2) +#define PIN_PD5__CANRX5 PINMUX_PIN(PIN_PD5, 3, 1) +#define PIN_PD5__NWE_NWR0_NANDWE PINMUX_PIN(PIN_PD5, 4, 2) +#define PIN_PD5__TIOA1 PINMUX_PIN(PIN_PD5, 5, 2) +#define PIN_PD5__FLEXCOM9_IO1 PINMUX_PIN(PIN_PD5, 6, 5) +#define PIN_PD6 102 +#define PIN_PD6__GPIO PINMUX_PIN(PIN_PD6, 0, 0) +#define PIN_PD6__SDMMC2_DAT1 PINMUX_PIN(PIN_PD6, 1, 1) +#define PIN_PD6__FLEXCOM0_IO3 PINMUX_PIN(PIN_PD6, 2, 2) +#define PIN_PD6__SPDIF_RX PINMUX_PIN(PIN_PD6, 3, 3) +#define PIN_PD6__NRD_NANDOE PINMUX_PIN(PIN_PD6, 4, 2) +#define PIN_PD6__TIOB1 PINMUX_PIN(PIN_PD6, 5, 2) +#define PIN_PD6__FLEXCOM10_IO0 PINMUX_PIN(PIN_PD6, 6, 5) +#define PIN_PD7 103 +#define PIN_PD7__GPIO PINMUX_PIN(PIN_PD7, 0, 0) +#define PIN_PD7__SDMMC2_DAT2 PINMUX_PIN(PIN_PD7, 1, 1) +#define PIN_PD7__FLEXCOM0_IO4 PINMUX_PIN(PIN_PD7, 2, 2) +#define PIN_PD7__SPDIF_TX PINMUX_PIN(PIN_PD7, 2, 2) +#define PIN_PD7__A21_NANDALE PINMUX_PIN(PIN_PD7, 4, 2) +#define PIN_PD7__TCLK1 PINMUX_PIN(PIN_PD7, 5, 2) +#define PIN_PD7__FLEXCOM10_IO1 PINMUX_PIN(PIN_PD7, 6, 5) +#define PIN_PD8 104 +#define PIN_PD8__GPIO PINMUX_PIN(PIN_PD8, 0, 0) +#define PIN_PD8__SDMMC2_DAT3 PINMUX_PIN(PIN_PD8, 1, 1) +#define PIN_PD8__I2SMCC0_DIN0 PINMUX_PIN(PIN_PD8, 3, 1) +#define PIN_PD8__A11_NANDCLE PINMUX_PIN(PIN_PD8, 4, 2) +#define PIN_PD8__TIOA2 PINMUX_PIN(PIN_PD8, 5, 2) +#define PIN_PD8__FLEXCOM11_IO0 PINMUX_PIN(PIN_PD8, 6, 5) +#define PIN_PD9 105 +#define PIN_PD9__GPIO PINMUX_PIN(PIN_PD9, 0, 0) +#define PIN_PD9__SDMMC2_WP PINMUX_PIN(PIN_PD9, 1, 1) +#define PIN_PD9__I2SMCC0_DIN1 PINMUX_PIN(PIN_PD9, 3, 2) +#define PIN_PD9__D0 PINMUX_PIN(PIN_PD9, 4, 2) +#define PIN_PD9__TIOB2 PINMUX_PIN(PIN_PD9, 5, 2) +#define PIN_PD9__FLEXCOM11_IO1 PINMUX_PIN(PIN_PD9, 6, 5) +#define PIN_PD10 106 +#define PIN_PD10__GPIO PINMUX_PIN(PIN_PD10, 0, 0) +#define PIN_PD10__SDMMC2_CD PINMUX_PIN(PIN_PD10, 1, 1) +#define PIN_PD10__PCK6 PINMUX_PIN(PIN_PD10, 2, 2) +#define PIN_PD10__I2SMCC0_DIN2 PINMUX_PIN(PIN_PD10, 3, 2) +#define PIN_PD10__D1 PINMUX_PIN(PIN_PD10, 4, 2) +#define PIN_PD10__TCLK2 PINMUX_PIN(PIN_PD10, 5, 2) +#define PIN_PD10__FLEXCOM0_IO0 PINMUX_PIN(PIN_PD10, 6, 3) +#define PIN_PD11 107 +#define PIN_PD11__GPIO PINMUX_PIN(PIN_PD11, 0, 0) +#define PIN_PD11__SDMMC2_1V8SEL PINMUX_PIN(PIN_PD11, 1, 1) +#define PIN_PD11__PCK7 PINMUX_PIN(PIN_PD11, 2, 2) +#define PIN_PD11__I2SMCC0_DIN3 PINMUX_PIN(PIN_PD11, 3, 2) +#define PIN_PD11__D2 PINMUX_PIN(PIN_PD11, 4, 2) +#define PIN_PD11__TIOA3 PINMUX_PIN(PIN_PD11, 5, 2) +#define PIN_PD11__FLEXCOM0_IO1 PINMUX_PIN(PIN_PD11, 6, 3) +#define PIN_PD12 108 +#define PIN_PD12__GPIO PINMUX_PIN(PIN_PD12, 0, 0) +#define PIN_PD12__PCK1 PINMUX_PIN(PIN_PD12, 1, 2) +#define PIN_PD12__FLEXCOM1_IO0 PINMUX_PIN(PIN_PD12, 2, 2) +#define PIN_PD12__CANTX0 PINMUX_PIN(PIN_PD12, 4, 2) +#define PIN_PD12__TIOB3 PINMUX_PIN(PIN_PD12, 5, 2) +#define PIN_PD13 109 +#define PIN_PD13__GPIO PINMUX_PIN(PIN_PD13, 0, 0) +#define PIN_PD13__I2SMCC0_CK PINMUX_PIN(PIN_PD13, 1, 2) +#define PIN_PD13__FLEXCOM1_IO1 PINMUX_PIN(PIN_PD13, 2, 2) +#define PIN_PD13__PWML0 PINMUX_PIN(PIN_PD13, 3, 4) +#define PIN_PD13__CANRX0 PINMUX_PIN(PIN_PD13, 4, 2) +#define PIN_PD13__TCLK3 PINMUX_PIN(PIN_PD13, 5, 2) +#define PIN_PD14 110 +#define PIN_PD14__GPIO PINMUX_PIN(PIN_PD14, 0, 0) +#define PIN_PD14__I2SMCC0_MCK PINMUX_PIN(PIN_PD14, 1, 2) +#define PIN_PD14__FLEXCOM1_IO2 PINMUX_PIN(PIN_PD14, 2, 2) +#define PIN_PD14__PWMH0 PINMUX_PIN(PIN_PD14, 3, 4) +#define PIN_PD14__CANTX1 PINMUX_PIN(PIN_PD14, 4, 2) +#define PIN_PD14__TIOA4 PINMUX_PIN(PIN_PD14, 5, 2) +#define PIN_PD14__FLEXCOM2_IO0 PINMUX_PIN(PIN_PD14, 6, 5) +#define PIN_PD15 111 +#define PIN_PD15__GPIO PINMUX_PIN(PIN_PD15, 0, 0) +#define PIN_PD15__I2SMCC0_WS PINMUX_PIN(PIN_PD15, 1, 2) +#define PIN_PD15__FLEXCOM1_IO3 PINMUX_PIN(PIN_PD15, 2, 2) +#define PIN_PD15__PWML1 PINMUX_PIN(PIN_PD15, 3, 4) +#define PIN_PD15__CANRX1 PINMUX_PIN(PIN_PD15, 4, 2) +#define PIN_PD15__TIOB4 PINMUX_PIN(PIN_PD15, 5, 2) +#define PIN_PD15__FLEXCOM2_IO1 PINMUX_PIN(PIN_PD15, 6, 5) +#define PIN_PD16 112 +#define PIN_PD16__GPIO PINMUX_PIN(PIN_PD16, 0, 0) +#define PIN_PD16__I2SMCC0_DOUT0 PINMUX_PIN(PIN_PD16, 1, 2) +#define PIN_PD16__FLEXCOM1_IO4 PINMUX_PIN(PIN_PD16, 2, 2) +#define PIN_PD16__PWMH1 PINMUX_PIN(PIN_PD16, 3, 4) +#define PIN_PD16__CANTX2 PINMUX_PIN(PIN_PD16, 4, 2) +#define PIN_PD16__TCLK4 PINMUX_PIN(PIN_PD16, 5, 2) +#define PIN_PD16__FLEXCOM3_IO0 PINMUX_PIN(PIN_PD16, 6, 5) +#define PIN_PD17 113 +#define PIN_PD17__GPIO PINMUX_PIN(PIN_PD17, 0, 0) +#define PIN_PD17__I2SMCC0_DOUT1 PINMUX_PIN(PIN_PD17, 1, 2) +#define PIN_PD17__FLEXCOM2_IO0 PINMUX_PIN(PIN_PD17, 2, 2) +#define PIN_PD17__PWML2 PINMUX_PIN(PIN_PD17, 3, 4) +#define PIN_PD17__CANRX2 PINMUX_PIN(PIN_PD17, 4, 2) +#define PIN_PD17__TIOA5 PINMUX_PIN(PIN_PD17, 5, 2) +#define PIN_PD17__FLEXCOM3_IO1 PINMUX_PIN(PIN_PD17, 6, 5) +#define PIN_PD18 114 +#define PIN_PD18__GPIO PINMUX_PIN(PIN_PD18, 0, 0) +#define PIN_PD18__I2SMCC0_DOUT2 PINMUX_PIN(PIN_PD18, 1, 2) +#define PIN_PD18__FLEXCOM2_IO1 PINMUX_PIN(PIN_PD18, 2, 2) +#define PIN_PD18__PWMH2 PINMUX_PIN(PIN_PD18, 3, 4) +#define PIN_PD18__CANTX3 PINMUX_PIN(PIN_PD18, 4, 2) +#define PIN_PD18__TIOB5 PINMUX_PIN(PIN_PD18, 5, 2) +#define PIN_PD18__FLEXCOM4_IO0 PINMUX_PIN(PIN_PD18, 6, 5) +#define PIN_PD19 115 +#define PIN_PD19__GPIO PINMUX_PIN(PIN_PD19, 0, 0) +#define PIN_PD19__I2SMCC0_DOUT3 PINMUX_PIN(PIN_PD19, 1, 2) +#define PIN_PD19__FLEXCOM2_IO2 PINMUX_PIN(PIN_PD19, 2, 2) +#define PIN_PD19__PWML3 PINMUX_PIN(PIN_PD19, 3, 4) +#define PIN_PD19__CANRX3 PINMUX_PIN(PIN_PD19, 4, 2) +#define PIN_PD19__TCLK5 PINMUX_PIN(PIN_PD19, 5, 2) +#define PIN_PD19__FLEXCOM4_IO1 PINMUX_PIN(PIN_PD19, 6, 5) +#define PIN_PD20 116 +#define PIN_PD20__GPIO PINMUX_PIN(PIN_PD20, 0, 0) +#define PIN_PD20__PCK0 PINMUX_PIN(PIN_PD20, 1, 3) +#define PIN_PD20__FLEXCOM2_IO3 PINMUX_PIN(PIN_PD20, 2, 2) +#define PIN_PD20__PWMH3 PINMUX_PIN(PIN_PD20, 3, 4) +#define PIN_PD20__CANTX4 PINMUX_PIN(PIN_PD20, 5, 2) +#define PIN_PD20__FLEXCOM5_IO0 PINMUX_PIN(PIN_PD20, 6, 5) +#define PIN_PD21 117 +#define PIN_PD21__GPIO PINMUX_PIN(PIN_PD21, 0, 0) +#define PIN_PD21__PCK1 PINMUX_PIN(PIN_PD21, 1, 3) +#define PIN_PD21__FLEXCOM2_IO4 PINMUX_PIN(PIN_PD21, 2, 2) +#define PIN_PD21__CANRX4 PINMUX_PIN(PIN_PD21, 4, 2) +#define PIN_PD21__FLEXCOM5_IO1 PINMUX_PIN(PIN_PD21, 6, 5) +#define PIN_PD21__G1_TXEN PINMUX_PIN(PIN_PD21, 7, 1) +#define PIN_PD22 118 +#define PIN_PD22__GPIO PINMUX_PIN(PIN_PD22, 0, 0) +#define PIN_PD22__PDMC0_CLK PINMUX_PIN(PIN_PD22, 1, 2) +#define PIN_PD22__PWMEXTRG0 PINMUX_PIN(PIN_PD22, 3, 4) +#define PIN_PD22__RD1 PINMUX_PIN(PIN_PD22, 4, 2) +#define PIN_PD22__CANTX5 PINMUX_PIN(PIN_PD22, 6, 2) +#define PIN_PD22__G1_TX0 PINMUX_PIN(PIN_PD22, 7, 1) +#define PIN_PD23 119 +#define PIN_PD23__GPIO PINMUX_PIN(PIN_PD23, 0, 0) +#define PIN_PD23__PDMC0_DS0 PINMUX_PIN(PIN_PD23, 1, 2) +#define PIN_PD23__PWMEXTRG1 PINMUX_PIN(PIN_PD23, 3, 4) +#define PIN_PD23__RF1 PINMUX_PIN(PIN_PD23, 4, 2) +#define PIN_PD23__ISC_MCK PINMUX_PIN(PIN_PD23, 5, 2) +#define PIN_PD23__CANRX5 PINMUX_PIN(PIN_PD23, 6, 2) +#define PIN_PD23__G1_TX1 PINMUX_PIN(PIN_PD23, 7, 1) +#define PIN_PD24 120 +#define PIN_PD24__GPIO PINMUX_PIN(PIN_PD24, 0, 0) +#define PIN_PD24__PDMC0_DS1 PINMUX_PIN(PIN_PD24, 1, 2) +#define PIN_PD24__PWMFI0 PINMUX_PIN(PIN_PD24, 3, 4) +#define PIN_PD24__RK1 PINMUX_PIN(PIN_PD24, 4, 2) +#define PIN_PD24__ISC_D0 PINMUX_PIN(PIN_PD24, 5, 2) +#define PIN_PD24__G1_RXDV PINMUX_PIN(PIN_PD24, 7, 1) +#define PIN_PD25 121 +#define PIN_PD25__GPIO PINMUX_PIN(PIN_PD25, 0, 0) +#define PIN_PD25__PDMC1_CLK PINMUX_PIN(PIN_PD25, 1, 2) +#define PIN_PD25__FLEXCOM5_IO0 PINMUX_PIN(PIN_PD25, 2, 2) +#define PIN_PD25__PWMFI1 PINMUX_PIN(PIN_PD25, 3, 4) +#define PIN_PD25__TD1 PINMUX_PIN(PIN_PD25, 4, 2) +#define PIN_PD25__ISC_D1 PINMUX_PIN(PIN_PD25, 5, 2) +#define PIN_PD25__G1_RX0 PINMUX_PIN(PIN_PD25, 7, 1) +#define PIN_PD26 122 +#define PIN_PD26__GPIO PINMUX_PIN(PIN_PD26, 0, 0) +#define PIN_PD26__PDMC1_DS0 PINMUX_PIN(PIN_PD26, 1, 2) +#define PIN_PD26__FLEXCOM5_IO1 PINMUX_PIN(PIN_PD26, 2, 2) +#define PIN_PD26__ADTRG PINMUX_PIN(PIN_PD26, 3, 3) +#define PIN_PD26__TF1 PINMUX_PIN(PIN_PD26, 4, 2) +#define PIN_PD26__ISC_D2 PINMUX_PIN(PIN_PD26, 5, 2) +#define PIN_PD26__G1_RX1 PINMUX_PIN(PIN_PD26, 7, 1) +#define PIN_PD27 123 +#define PIN_PD27__GPIO PINMUX_PIN(PIN_PD27, 0, 0) +#define PIN_PD27__PDMC1_DS1 PINMUX_PIN(PIN_PD27, 1, 2) +#define PIN_PD27__FLEXCOM5_IO2 PINMUX_PIN(PIN_PD27, 2, 2) +#define PIN_PD27__TIOA0 PINMUX_PIN(PIN_PD27, 3, 3) +#define PIN_PD27__TK1 PINMUX_PIN(PIN_PD27, 4, 2) +#define PIN_PD27__ISC_D3 PINMUX_PIN(PIN_PD27, 5, 2) +#define PIN_PD27__G1_RXER PINMUX_PIN(PIN_PD27, 7, 1) +#define PIN_PD28 124 +#define PIN_PD28__GPIO PINMUX_PIN(PIN_PD28, 0, 0) +#define PIN_PD28__RD0 PINMUX_PIN(PIN_PD28, 1, 2) +#define PIN_PD28__FLEXCOM5_IO3 PINMUX_PIN(PIN_PD28, 2, 2) +#define PIN_PD28__TIOB0 PINMUX_PIN(PIN_PD28, 3, 3) +#define PIN_PD28__I2SMCC1_CK PINMUX_PIN(PIN_PD28, 4, 2) +#define PIN_PD28__ISC_D4 PINMUX_PIN(PIN_PD28, 5, 2) +#define PIN_PD28__PWML3 PINMUX_PIN(PIN_PD28, 6, 5) +#define PIN_PD28__G1_MDC PINMUX_PIN(PIN_PD28, 7, 1) +#define PIN_PD29 125 +#define PIN_PD29__GPIO PINMUX_PIN(PIN_PD29, 0, 0) +#define PIN_PD29__RF0 PINMUX_PIN(PIN_PD29, 1, 2) +#define PIN_PD29__FLEXCOM5_IO4 PINMUX_PIN(PIN_PD29, 2, 2) +#define PIN_PD29__TCLK0 PINMUX_PIN(PIN_PD29, 3, 3) +#define PIN_PD29__I2SMCC1_WS PINMUX_PIN(PIN_PD29, 4, 2) +#define PIN_PD29__ISC_D5 PINMUX_PIN(PIN_PD29, 5, 2) +#define PIN_PD29__PWMH3 PINMUX_PIN(PIN_PD29, 6, 5) +#define PIN_PD29__G1_MDIO PINMUX_PIN(PIN_PD29, 7, 1) +#define PIN_PD30 126 +#define PIN_PD30__GPIO PINMUX_PIN(PIN_PD30, 0, 0) +#define PIN_PD30__RK0 PINMUX_PIN(PIN_PD30, 1, 2) +#define PIN_PD30__FLEXCOM6_IO0 PINMUX_PIN(PIN_PD30, 2, 2) +#define PIN_PD30__TIOA1 PINMUX_PIN(PIN_PD30, 3, 3) +#define PIN_PD30__I2SMCC1_MCK PINMUX_PIN(PIN_PD30, 4, 2) +#define PIN_PD30__ISC_D6 PINMUX_PIN(PIN_PD30, 5, 2) +#define PIN_PD30__PWMEXTRG0 PINMUX_PIN(PIN_PD30, 6, 5) +#define PIN_PD30__G1_TXCK PINMUX_PIN(PIN_PD30, 7, 1) +#define PIN_PD31 127 +#define PIN_PD31__GPIO PINMUX_PIN(PIN_PD31, 0, 0) +#define PIN_PD31__TD0 PINMUX_PIN(PIN_PD31, 1, 2) +#define PIN_PD31__FLEXCOM6_IO1 PINMUX_PIN(PIN_PD31, 2, 2) +#define PIN_PD31__TIOB1 PINMUX_PIN(PIN_PD31, 3, 3) +#define PIN_PD31__I2SMCC1_DOUT0 PINMUX_PIN(PIN_PD31, 4, 2) +#define PIN_PD31__ISC_D7 PINMUX_PIN(PIN_PD31, 5, 2) +#define PIN_PD31__PWM_EXTRG1 PINMUX_PIN(PIN_PD31, 6, 5) +#define PIN_PD31__G1_TX2 PINMUX_PIN(PIN_PD31, 7, 1) +#define PIN_PE0 128 +#define PIN_PE0__GPIO PINMUX_PIN(PIN_PE0, 0, 0) +#define PIN_PE0__TF0 PINMUX_PIN(PIN_PE0, 1, 2) +#define PIN_PE0__FLEXCOM6_IO2 PINMUX_PIN(PIN_PE0, 2, 2) +#define PIN_PE0__TCLK1 PINMUX_PIN(PIN_PE0, 3, 3) +#define PIN_PE0__I2SMCC1_DOUT1 PINMUX_PIN(PIN_PE0, 4, 2) +#define PIN_PE0__ISC_HSYNC PINMUX_PIN(PIN_PE0, 5, 2) +#define PIN_PE0__PWMFI0 PINMUX_PIN(PIN_PE0, 6, 5) +#define PIN_PE0__G1_TX3 PINMUX_PIN(PIN_PE0, 7, 1) +#define PIN_PE1 129 +#define PIN_PE1__GPIO PINMUX_PIN(PIN_PE1, 0, 0) +#define PIN_PE1__TK0 PINMUX_PIN(PIN_PE1, 1, 2) +#define PIN_PE1__FLEXCOM6_IO3 PINMUX_PIN(PIN_PE1, 2, 2) +#define PIN_PE1__TIOA2 PINMUX_PIN(PIN_PE1, 3, 3) +#define PIN_PE1__I2SMCC1_DOUT2 PINMUX_PIN(PIN_PE1, 4, 2) +#define PIN_PE1__ISC_VSYNC PINMUX_PIN(PIN_PE1, 5, 2) +#define PIN_PE1__PWMFI1 PINMUX_PIN(PIN_PE1, 6, 5) +#define PIN_PE1__G1_RX2 PINMUX_PIN(PIN_PE1, 7, 1) +#define PIN_PE2 130 +#define PIN_PE2__GPIO PINMUX_PIN(PIN_PE2, 0, 0) +#define PIN_PE2__PWML0 PINMUX_PIN(PIN_PE2, 1, 5) +#define PIN_PE2__FLEXCOM6_IO4 PINMUX_PIN(PIN_PE2, 2, 2) +#define PIN_PE2__TIOB2 PINMUX_PIN(PIN_PE2, 3, 3) +#define PIN_PE2__I2SMCC1_DOUT3 PINMUX_PIN(PIN_PE2, 4, 2) +#define PIN_PE2__ISC_FIELD PINMUX_PIN(PIN_PE2, 5, 2) +#define PIN_PE2__G1_RX3 PINMUX_PIN(PIN_PE2, 7, 1) +#define PIN_PE3 131 +#define PIN_PE3__GPIO PINMUX_PIN(PIN_PE3, 0, 0) +#define PIN_PE3__PWMH0 PINMUX_PIN(PIN_PE3, 1, 5) +#define PIN_PE3__FLEXCOM0_IO0 PINMUX_PIN(PIN_PE3, 2, 4) +#define PIN_PE3__TCLK2 PINMUX_PIN(PIN_PE3, 3, 3) +#define PIN_PE3__I2SMCC1_DIN0 PINMUX_PIN(PIN_PE3, 4, 2) +#define PIN_PE3__ISC_PCK PINMUX_PIN(PIN_PE3, 5, 2) +#define PIN_PE3__G1_RXCK PINMUX_PIN(PIN_PE3, 7, 1) +#define PIN_PE4 132 +#define PIN_PE4__GPIO PINMUX_PIN(PIN_PE4, 0, 0) +#define PIN_PE4__PWML1 PINMUX_PIN(PIN_PE4, 1, 5) +#define PIN_PE4__FLEXCOM0_IO1 PINMUX_PIN(PIN_PE4, 2, 4) +#define PIN_PE4__TIOA3 PINMUX_PIN(PIN_PE4, 3, 3) +#define PIN_PE4__I2SMCC1_DIN1 PINMUX_PIN(PIN_PE4, 4, 2) +#define PIN_PE4__ISC_D8 PINMUX_PIN(PIN_PE4, 5, 2) +#define PIN_PE4__G1_TXER PINMUX_PIN(PIN_PE4, 7, 1) +#define PIN_PE5 133 +#define PIN_PE5__GPIO PINMUX_PIN(PIN_PE5, 0, 0) +#define PIN_PE5__PWMH1 PINMUX_PIN(PIN_PE5, 1, 5) +#define PIN_PE5__FLEXCOM0_IO2 PINMUX_PIN(PIN_PE5, 2, 4) +#define PIN_PE5__TIOB3 PINMUX_PIN(PIN_PE5, 3, 3) +#define PIN_PE5__I2SMCC1_DIN2 PINMUX_PIN(PIN_PE5, 4, 2) +#define PIN_PE5__ISC_D9 PINMUX_PIN(PIN_PE5, 5, 2) +#define PIN_PE5__G1_COL PINMUX_PIN(PIN_PE5, 7, 1) +#define PIN_PE6 134 +#define PIN_PE6__GPIO PINMUX_PIN(PIN_PE6, 0, 0) +#define PIN_PE6__PWML2 PINMUX_PIN(PIN_PE6, 1, 5) +#define PIN_PE6__FLEXCOM0_IO3 PINMUX_PIN(PIN_PE6, 2, 4) +#define PIN_PE6__TCLK3 PINMUX_PIN(PIN_PE6, 3, 3) +#define PIN_PE6__I2SMCC1_DIN3 PINMUX_PIN(PIN_PE6, 4, 2) +#define PIN_PE6__ISC_D10 PINMUX_PIN(PIN_PE6, 5, 2) +#define PIN_PE6__G1_CRS PINMUX_PIN(PIN_PE6, 7, 1) +#define PIN_PE7 135 +#define PIN_PE7__GPIO PINMUX_PIN(PIN_PE7, 0, 0) +#define PIN_PE7__PWMH2 PINMUX_PIN(PIN_PE7, 1, 5) +#define PIN_PE7__FLEXCOM0_IO4 PINMUX_PIN(PIN_PE7, 2, 4) +#define PIN_PE7__TIOA4 PINMUX_PIN(PIN_PE7, 3, 3) +#define PIN_PE7__ISC_D11 PINMUX_PIN(PIN_PE7, 5, 2) +#define PIN_PE7__G1_TSUCOMP PINMUX_PIN(PIN_PE7, 7, 1) + diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 85524004f9..9e4392b793 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -47,6 +47,10 @@ config SAM9X60 bool select CPU_ARM926EJS +config SAMA7G5 + bool + select CPU_V7A + config SAMA5D2 bool select CPU_V7A @@ -323,6 +327,7 @@ source "board/atmel/at91sam9n12ek/Kconfig" source "board/atmel/at91sam9rlek/Kconfig" source "board/atmel/at91sam9x5ek/Kconfig" source "board/atmel/sam9x60ek/Kconfig" +source "board/atmel/sama7g5ek/Kconfig" source "board/atmel/sama5d2_ptc_ek/Kconfig" source "board/atmel/sama5d2_xplained/Kconfig" source "board/atmel/sama5d27_som1_ek/Kconfig" diff --git a/arch/arm/mach-at91/armv7/Makefile b/arch/arm/mach-at91/armv7/Makefile index 9ced3dc0c1..55477560a8 100644 --- a/arch/arm/mach-at91/armv7/Makefile +++ b/arch/arm/mach-at91/armv7/Makefile @@ -9,6 +9,7 @@ obj-$(CONFIG_SAMA5D2) += sama5d2_devices.o obj-$(CONFIG_SAMA5D3) += sama5d3_devices.o obj-$(CONFIG_SAMA5D4) += sama5d4_devices.o +obj-$(CONFIG_SAMA7G5) += sama7g5_devices.o obj-y += clock.o obj-y += cpu.o obj-y += reset.o diff --git a/arch/arm/mach-at91/armv7/sama7g5_devices.c b/arch/arm/mach-at91/armv7/sama7g5_devices.c new file mode 100644 index 0000000000..a58f671f72 --- /dev/null +++ b/arch/arm/mach-at91/armv7/sama7g5_devices.c @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020 Microchip Technology, Inc. + * Eugen Hristev <eugen.hristev(a)microchip.com> + */ + +char *get_cpu_name(void) +{ + return "SAMA7G5"; +} + diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h index 88acca8549..0a16c8ff08 100644 --- a/arch/arm/mach-at91/include/mach/hardware.h +++ b/arch/arm/mach-at91/include/mach/hardware.h @@ -24,6 +24,8 @@ # include <asm/arch/at91sam9x5.h> #elif defined(CONFIG_SAM9X60) # include <asm/arch/sam9x60.h> +#elif defined(CONFIG_SAMA7G5) +# include <asm/arch/sama7g5.h> #elif defined(CONFIG_SAMA5D2) # include <asm/arch/sama5d2.h> #elif defined(CONFIG_SAMA5D3) diff --git a/arch/arm/mach-at91/include/mach/sama7g5.h b/arch/arm/mach-at91/include/mach/sama7g5.h new file mode 100644 index 0000000000..ae43e8700b --- /dev/null +++ b/arch/arm/mach-at91/include/mach/sama7g5.h @@ -0,0 +1,74 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Chip-specific header file for the SAMA7G5 SoC + * + * Copyright (C) 2020 Microchip Technology, Inc. and its subsidiaries + * Eugen Hristev <eugen.hristev(a)microchip.com> + */ + +#ifndef __SAMA7G5_H__ +#define __SAMA7G5_H__ + +/* + * Peripheral identifiers/interrupts. + */ +#define ATMEL_ID_FLEXCOM0 38 +#define ATMEL_ID_FLEXCOM1 39 +#define ATMEL_ID_FLEXCOM2 40 +#define ATMEL_ID_FLEXCOM3 41 + +#define ATMEL_ID_SDMMC0 80 +#define ATMEL_ID_SDMMC1 81 + +#define ATMEL_ID_PIT64B0 70 +#define ATMEL_ID_PIT64B ATMEL_ID_PIT64B0 + +#define ATMEL_CHIPID_CIDR 0xe0020000 +#define ATMEL_CHIPID_EXID 0xe0020004 +/* + * User Peripherals physical base addresses. + */ +#define ATMEL_BASE_PIOA 0xe0014000 +#define ATMEL_BASE_PIOB (ATMEL_BASE_PIOA + 0x40) +#define ATMEL_BASE_PIOC (ATMEL_BASE_PIOB + 0x40) +#define ATMEL_BASE_PIOD (ATMEL_BASE_PIOC + 0x40) +#define ATMEL_BASE_PIOE (ATMEL_BASE_PIOD + 0x40) + +#define ATMEL_PIO_PORTS 5 + +#define CPU_HAS_PCR + +#define ATMEL_BASE_PMC 0xe0018000 + +#define ATMEL_BASE_WDT 0xe001c000 +#define ATMEL_BASE_RSTC 0xe001d000 +#define ATMEL_BASE_WDTS 0xe001d180 +#define ATMEL_BASE_SCKCR 0xe001d050 + +#define ATMEL_BASE_SDMMC0 0xe1204000 +#define ATMEL_BASE_SDMMC1 0xe1208000 + +#define ATMEL_BASE_PIT64B0 0xe1800000 + +#define ATMEL_BASE_FLEXCOM0 0xe1818000 +#define ATMEL_BASE_FLEXCOM1 0xe181c000 +#define ATMEL_BASE_FLEXCOM2 0xe1820000 +#define ATMEL_BASE_FLEXCOM3 0xe1824000 +#define ATMEL_BASE_FLEXCOM4 0xe2018000 + +#define ATMEL_BASE_TZC400 0xe3000000 + +#define ATMEL_BASE_UMCTL2 0xe3800000 +#define ATMEL_BASE_UMCTL2_MP 0xe38003f8 +#define ATMEL_BASE_PUBL 0xe3804000 + +#define ATMEL_NUM_FLEXCOM 12 +#define ATMEL_PIO_PORTS 5 + +#define ATMEL_BASE_PIT64BC ATMEL_BASE_PIT64B0 + +#ifndef __ASSEMBLY__ +char *get_cpu_name(void); +#endif + +#endif /* #ifndef __SAMA7G5_H__ */ -- 2.25.1

1 5

[GIT PULL] Pull request: u-boot-imx u-boot-imx-20200825
by Stefano Babic 26 Aug '20

26 Aug '20

Hi Tom, please pull from u-boot-imx, thanks ! The following changes since commit 789bfb52668ee609b2043de645e2f94bbd24fd1f: Merge tag 'efi-2020-10-rc3-2' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi (2020-08-15 09:01:01 -0400) are available in the Git repository at: https://gitlab.denx.de/u-boot/custodians/u-boot-imx.git tags/u-boot-imx-20200825 for you to fetch changes up to acbc1d86f16cc8372cccb7b862a0b9dc242f8fe5: imx8m: config: convert to bootm_size (2020-08-25 10:26:38 +0200) ---------------------------------------------------------------- For 2020.10 ----------- - mx6: SOCs user selectable Fix for imx6q_logic Some DM conversion - mx7: introduce secondary boot device Travis: https://travis-ci.org/github/sbabic/u-boot-imx/builds/720918010 ---------------------------------------------------------------- Adam Ford (1): ARM: imx6q_logic: Fix broken booting by moving fdt_addr_r address Fabio Estevam (1): pico-imx6: Remove unneeded CONFIG_DM_MDIO Grygorii Tertychnyi (1): imx8m: config: convert to bootm_size Marek Vasut (5): ARM: imx: Add bmode support for iMX7 ARM: imx: Add support for switching primary/secondary boot mode to bmode ARM: imx: Add support for reading out the primary/secondary bmode ARM: imx: Add support for reading out the primary/secondary bmode to MX7 ARM: imx: ddr: Add deskew register programming Matthias Schiffer (1): tools/imximage: fix DCD Blocks message output order Tom Rini (1): arm: mx6: Make all i.MX6 SoCs user-selectable Wig Cheng (3): configs: pico-imx6ul: convert DM_USB configs: pico-imx6ul: convert DM_VIDEO pico-imx6ul: convert ethernet function to DM_ETH arch/arm/include/asm/arch-mx7/mx7-ddr.h | 16 +++++++++++++--- arch/arm/include/asm/mach-imx/boot_mode.h | 2 ++ arch/arm/include/asm/mach-imx/sys_proto.h | 8 +++++++- arch/arm/mach-imx/Kconfig | 2 +- arch/arm/mach-imx/cmd_bmode.c | 12 ++++++++++++ arch/arm/mach-imx/init.c | 30 ++++++++++++++++++++++-------- arch/arm/mach-imx/mx6/Kconfig | 134 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-------------------------------------------------------------- arch/arm/mach-imx/mx7/ddr.c | 9 +++++++++ arch/arm/mach-imx/mx7/soc.c | 17 +++++++++++++++++ board/seco/Kconfig | 6 +++--- board/tbs/tbs2910/Kconfig | 3 --- board/technexion/pico-imx6ul/pico-imx6ul.c | 53 ----------------------------------------------------- board/tqc/tqma6/Kconfig | 6 +++--- configs/apalis_imx6_defconfig | 3 ++- configs/aristainetos2_defconfig | 1 + configs/aristainetos2b_defconfig | 1 + configs/aristainetos2bcsl_defconfig | 1 + configs/aristainetos2c_defconfig | 1 + configs/brppt2_defconfig | 1 + configs/cgtqmx6eval_defconfig | 1 + configs/cm_fx6_defconfig | 1 + configs/colibri-imx6ull_defconfig | 3 ++- configs/colibri_imx6_defconfig | 3 ++- configs/dh_imx6_defconfig | 1 + configs/display5_defconfig | 3 ++- configs/display5_factory_defconfig | 3 ++- configs/dms-ba16-1g_defconfig | 1 + configs/dms-ba16_defconfig | 1 + configs/ge_bx50v3_defconfig | 1 + configs/gwventana_emmc_defconfig | 1 + configs/gwventana_gw5904_defconfig | 1 + configs/gwventana_nand_defconfig | 1 + configs/imx6dl_icore_nand_defconfig | 1 + configs/imx6dl_mamoj_defconfig | 1 + configs/imx6q_icore_nand_defconfig | 1 + configs/imx6q_logic_defconfig | 1 + configs/imx6qdl_icore_mipi_defconfig | 1 + configs/imx6qdl_icore_mmc_defconfig | 1 + configs/imx6qdl_icore_nand_defconfig | 1 + configs/imx6qdl_icore_rqs_defconfig | 1 + configs/imx6ul_geam_mmc_defconfig | 1 + configs/imx6ul_geam_nand_defconfig | 1 + configs/imx6ul_isiot_emmc_defconfig | 1 + configs/imx6ul_isiot_nand_defconfig | 1 + configs/kp_imx6q_tpc_defconfig | 1 + configs/liteboard_defconfig | 1 + configs/marsboard_defconfig | 3 ++- configs/mccmon6_nor_defconfig | 1 + configs/mccmon6_sd_defconfig | 1 + configs/mx6cuboxi_defconfig | 1 + configs/mx6dlarm2_defconfig | 3 ++- configs/mx6dlarm2_lpddr2_defconfig | 3 ++- configs/mx6memcal_defconfig | 3 ++- configs/mx6qarm2_defconfig | 3 ++- configs/mx6qarm2_lpddr2_defconfig | 3 ++- configs/mx6qsabrelite_defconfig | 3 ++- configs/mx6sabreauto_defconfig | 1 + configs/mx6sabresd_defconfig | 1 + configs/mx6slevk_defconfig | 1 + configs/mx6slevk_spinor_defconfig | 1 + configs/mx6slevk_spl_defconfig | 1 + configs/mx6sllevk_defconfig | 1 + configs/mx6sllevk_plugin_defconfig | 1 + configs/mx6sxsabreauto_defconfig | 1 + configs/mx6sxsabresd_defconfig | 1 + configs/mx6ul_14x14_evk_defconfig | 1 + configs/mx6ul_9x9_evk_defconfig | 1 + configs/mx6ull_14x14_evk_defconfig | 1 + configs/mx6ull_14x14_evk_plugin_defconfig | 1 + configs/mx6ulz_14x14_evk_defconfig | 1 + configs/myir_mys_6ulx_defconfig | 1 + configs/nitrogen6dl2g_defconfig | 3 ++- configs/nitrogen6dl_defconfig | 3 ++- configs/nitrogen6q2g_defconfig | 3 ++- configs/nitrogen6q_defconfig | 3 ++- configs/nitrogen6s1g_defconfig | 3 ++- configs/nitrogen6s_defconfig | 3 ++- configs/novena_defconfig | 3 ++- configs/opos6uldev_defconfig | 1 + configs/ot1200_defconfig | 3 ++- configs/ot1200_spl_defconfig | 3 ++- configs/pcm058_defconfig | 3 ++- configs/pfla02_defconfig | 1 + configs/phycore_pcl063_defconfig | 1 + configs/phycore_pcl063_ull_defconfig | 1 + configs/pico-dwarf-imx6ul_defconfig | 1 + configs/pico-hobbit-imx6ul_defconfig | 1 + configs/pico-imx6_defconfig | 2 +- configs/pico-imx6ul_defconfig | 6 +++++- configs/pico-pi-imx6ul_defconfig | 1 + configs/platinum_picon_defconfig | 3 ++- configs/platinum_titanium_defconfig | 3 ++- configs/riotboard_defconfig | 3 ++- configs/riotboard_spl_defconfig | 3 ++- configs/secomx6quq7_defconfig | 1 + configs/sksimx6_defconfig | 3 ++- configs/somlabs_visionsom_6ull_defconfig | 1 + configs/tbs2910_defconfig | 1 + configs/titanium_defconfig | 1 + configs/tqma6dl_mba6_mmc_defconfig | 2 +- configs/tqma6dl_mba6_spi_defconfig | 2 +- configs/tqma6q_mba6_mmc_defconfig | 1 + configs/tqma6q_mba6_spi_defconfig | 1 + configs/tqma6s_mba6_mmc_defconfig | 2 +- configs/tqma6s_mba6_spi_defconfig | 2 +- configs/tqma6s_wru4_mmc_defconfig | 2 +- configs/udoo_defconfig | 1 + configs/udoo_neo_defconfig | 1 + configs/variscite_dart6ul_defconfig | 1 + configs/vining_2000_defconfig | 1 + configs/wandboard_defconfig | 1 + configs/warp_defconfig | 1 + configs/xpress_defconfig | 1 + configs/xpress_spl_defconfig | 1 + configs/zc5202_defconfig | 3 ++- configs/zc5601_defconfig | 3 ++- include/configs/imx6_logic.h | 4 ++-- include/configs/imx8mm_evk.h | 3 +-- include/configs/imx8mn_evk.h | 3 +-- include/configs/imx8mp_evk.h | 3 +-- include/configs/imx8mq_evk.h | 4 +--- include/configs/titanium.h | 2 -- tools/imximage.c | 2 +- 123 files changed, 304 insertions(+), 187 deletions(-) Best regards, Stefano -- ===================================================================== DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic(a)denx.de =====================================================================

2 1

u-boot 2015.4 & 2015.10 can't determine partition table on samsung emmc (error -19)
by Eugene Kruglikov 26 Aug '20

26 Aug '20

Hello. I've got the trouble with u-boot and samsung emmc: partition table can't be determined. U-Boot > mmc dev 2 ===> test_block_type error 1: (buffer[DOS_PART_MAGIC_OFFSET + 0] != 0x55) || (buffer[DOS_PART_MAGIC_OFFSET + 1] != 0xaa) bad MBR sector signature: 0x9966 ===> test_part_dos error: test_block_type(buffer) != DOS_MBR switch to partitions #0, OK mmc2(part 0) is current device CMD_TRACE: ... CMD_SEND:8 ARG 0x000001AA RET: -19 , 0xffffffed MMC_RSP_R1,5,6,7 0x2FF67610 CMD_SEND:55 ARG 0x00000000 RET: -19 , 0xffffffed MMC_RSP_R1,5,6,7 0x2FF67610 ... CMD_SEND:8 ARG 0x00000000 RET: -19 , 0xffffffed MMC_RSP_R1,5,6,7 0x00000900 ... U-Boot > mmc info Device: FSL_SDHC Manufacturer ID: 90 OEM: 14a Name: H8G1e Tran Speed: 52000000 Rd Block Len: 512 MMC version 5.0 High Capacity: Yes Capacity: 7.3 GiB Bus Width: 1-bit Erase Group Size: 512 KiB HC WP Group Size: 8 MiB User Capacity: 7.3 GiB WRREL Boot Capacity: 4 MiB ENH RPMB Capacity: 512 KiB ENH ------------------------------------------ In same time Linux kernel works fine with that emmc: # fdisk -l /dev/mmcblk3 Disk /dev/mmcblk3: 7.3 GiB, 7818182656 bytes, 15269888 sectors Units: sectors of 1 * 512 = 512 bytes Sector size (logical/physical): 512 bytes / 512 bytes I/O size (minimum/optimal): 512 bytes / 512 bytes Disklabel type: dos Disk identifier: 0x3f1bef1e Device Boot Start End Sectors Size Id Type /dev/mmcblk3p1 2048 133119 131072 64M 83 Linux ------------------------------------------ Does anyone have any idea? What is error code -19 ? Thanks! -- Regards, Eugene Kruglikov DMT TRADING 220020, Belarus, Minsk Pobeditelei av., 89/2-1 tel1: +375(17)379-63-41 tel2: +375(17)379-63-44 fax: ‎+375(17)351-42-01 skype:kruglikov.dmt kryglikov(a)dmt.by kruglikov.dmt(a)gmail.com

1 0

[PATCH v5 0/2] Basic Kontron SMARC-sAL28 board support
by Michael Walle 26 Aug '20

26 Aug '20

Add basic board support for the Kontron SMARC-sAL28 board. Please note, that this board doesn't support TF-a (yet). Therefore, the u-boot SPL is the first code which is run and it has to set up the RAM. changes since v4: - dropped "armv8: ls1028a: move FSL_LAYERSCAPE to kconfig" as it is already upstream - new patch "board: sl28: add board specific nvm command" - use binman - sync device trees with linux - use "<devicetree>-u-boot.dtsi" style - rebase to lastest master changes since v3: - rebase to latest master - use CONFIG_PCI_INIT_R - set fdtfile in default environment changes since v2: - add variant 4 support. Since the atheros PHY dt bindings were merged into master, we can now use them - add environment section in include/configs/kontron_sl28.h - add cover letter changes since v1: - fix watchdog device tree reference Michael Walle (2): board: kontron: add sl28 support board: sl28: add board specific nvm command arch/arm/Kconfig | 11 + arch/arm/dts/Makefile | 3 + .../dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi | 135 +++++++++++++ .../fsl-ls1028a-kontron-sl28-var3-u-boot.dtsi | 1 + .../arm/dts/fsl-ls1028a-kontron-sl28-var3.dts | 15 ++ .../fsl-ls1028a-kontron-sl28-var4-u-boot.dtsi | 1 + .../arm/dts/fsl-ls1028a-kontron-sl28-var4.dts | 48 +++++ arch/arm/dts/fsl-ls1028a-kontron-sl28.dts | 189 ++++++++++++++++++ board/kontron/sl28/Kconfig | 18 ++ board/kontron/sl28/MAINTAINERS | 6 + board/kontron/sl28/Makefile | 8 + board/kontron/sl28/README | 142 +++++++++++++ board/kontron/sl28/cmds.c | 176 ++++++++++++++++ board/kontron/sl28/common.c | 10 + board/kontron/sl28/ddr.c | 98 +++++++++ board/kontron/sl28/sl28.c | 75 +++++++ board/kontron/sl28/spl.c | 32 +++ configs/kontron_sl28_defconfig | 106 ++++++++++ include/configs/kontron_sl28.h | 125 ++++++++++++ 19 files changed, 1199 insertions(+) create mode 100644 arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi create mode 100644 arch/arm/dts/fsl-ls1028a-kontron-sl28-var3-u-boot.dtsi create mode 100644 arch/arm/dts/fsl-ls1028a-kontron-sl28-var3.dts create mode 100644 arch/arm/dts/fsl-ls1028a-kontron-sl28-var4-u-boot.dtsi create mode 100644 arch/arm/dts/fsl-ls1028a-kontron-sl28-var4.dts create mode 100644 arch/arm/dts/fsl-ls1028a-kontron-sl28.dts create mode 100644 board/kontron/sl28/Kconfig create mode 100644 board/kontron/sl28/MAINTAINERS create mode 100644 board/kontron/sl28/Makefile create mode 100644 board/kontron/sl28/README create mode 100644 board/kontron/sl28/cmds.c create mode 100644 board/kontron/sl28/common.c create mode 100644 board/kontron/sl28/ddr.c create mode 100644 board/kontron/sl28/sl28.c create mode 100644 board/kontron/sl28/spl.c create mode 100644 configs/kontron_sl28_defconfig create mode 100644 include/configs/kontron_sl28.h -- 2.20.1

2 3

Z-Turn board support on U-Boot 2020.10-rc2, got some errors.
by Alexandre GRIVEAUX 26 Aug '20

26 Aug '20

Hello, I've tried the u-boot 2020.10-rc2 and it's seem i've got some errors: U-Boot 2020.10-rc2-00204-gc84341f5ac (Aug 24 2020 - 09:49:25 +0200) CPU: Zynq 7z020 Silicon: v3.1 Model: Zynq Z-Turn MYIR Board DRAM: ECC disabled 1 GiB Flash: 0 Bytes NAND: 0 MiB MMC: mmc@e0100000: 0 Loading Environment from SPIFlash... Invalid bus 0 (err=-19) *** Warning - spi_flash_probe_bus_cs() failed, using default environment In: serial@e0001000 Out: serial@e0001000 Err: serial@e0001000 Net: ZYNQ GEM: e000b000, mdio bus e000b000, phyaddr 0, interface rgmii-id Could not get PHY for eth0: addr 0 No ethernet found. Hit any key to stop autoboot: 0 Zynq> According to [0] the board use a winbond W25Q128BVFIG but on the board it's seem to usea spansion FL128SAIF00. I've checked if FL128SAIF00 is registered on drivers/mtd/spi/spi-nor-ids.c: ({ INFO6("s25fl128s", 0x012018, 0x4d0180, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },) I've checked if flash manufacturer was enabled on configs/xilinx_zynq_virt_defconfig: CONFIG_SPI_FLASH_SPANSION=y I checked on [1] to see if the pinout is broken but not. I dont know how to correct this problem. For the ethernet it's seem CONFIG_PHY_MICREL_KSZ90X1=y and CONFIG_PHY_MICREL=y was not on configs/xilinx_zynq_virt_defconfig But adding it doesn't resolve it: ZYNQ GEM: e000b000, mdio bus e000b000, phyaddr 0, interface rgmii-id Could not get PHY for eth0: addr 0 No ethernet found. I dont (again) know how to correct this problem. Can you help me ? [0] http://www.myirtech.com/download/Zynq7000/Z-TURNBOARD_schematic.pdf [1] https://www.xilinx.com/support/documentation/boards_and_kits/zc702_zvik/ug8…

2 3

Re: [PATCH v2 1/3] fdtdec: optionally add property no-map to created reserved memory node
by Rick Chen 26 Aug '20

26 Aug '20

> From: Patrice Chotard [mailto:patrice.chotard@st.com] > Sent: Tuesday, August 25, 2020 7:29 PM > To: u-boot(a)lists.denx.de > Cc: Patrice CHOTARD; Patrick DELAUNAY; U-Boot STM32; Etienne Carriere; Atish Patra; Bin Meng; Bryan O'Donoghue; Heinrich Schuchardt; Rick Jian-Zhi Chen(陳建志); Simon Glass > Subject: [PATCH v2 1/3] fdtdec: optionally add property no-map to created reserved memory node > > From: Etienne Carriere <etienne.carriere(a)st.com> > > Add boolean input argument @no_map to helper function > fdtdec_add_reserved_memory() to add "no-map" property for an added > reserved memory node. This is needed for example when the reserved > memory relates to secure memory that the dear Linux kernel shall > not even map unless what non-secure world speculative accesses of the > CPU can violate the memory firmware configuration. > > No function change. A later change will update to OPTEE library to > add no-map property to OP-TEE reserved memory nodes. > > Signed-off-by: Etienne Carriere <etienne.carriere(a)st.com> > Signed-off-by: Patrice Chotard <patrice.chotard(a)st.com> > - fix dm fdtdec test and arch/riscv/lib/fdt_fixup.c with > fdtdec_add_reserved_memory() new parameter > > --- > > (no changes since v1) > > arch/riscv/lib/fdt_fixup.c | 2 +- > include/fdtdec.h | 5 +++-- > lib/fdtdec.c | 10 ++++++++-- > lib/optee/optee.c | 2 +- > test/dm/fdtdec.c | 6 +++--- > 5 files changed, 16 insertions(+), 9 deletions(-) Acked-by: Rick Chen <rick(a)andestech.com>

1 0

Please pull u-boot-marvell/master
by Stefan Roese 26 Aug '20

26 Aug '20

Hi Tom, please pull the Marvell Octeon TX / TX2 base support. I would have liked to send this pull request earlier in the release cycle, but it did not work out and I hope, that it's still possible to get this included in this rc2 phase. Most changes are located in the Octeon TX / TX2 platform code and some IF changes in the PCI uclass driver. As mentioned in my last mail, I've removed the bigger device drivers for NAND & ethernet for now. This way, they have a bit more time for reviews. I've also included the small QEMU x86 patch that I sent earlier today, as this patch fixes a CI QEMU failure. Here the summary log: ---------------------------------------------------------------- - Add basic Marvell/Cavium OcteonTX/TX2 support (Suneel) - Infrastructure changes to PCI uclass to support these SoC's (Suneel) - Add PCI, MMC & watchdog driver drivers for OcteonTX/TX2 (Suneel) - Increase CONFIG_SYS_MALLOC_F_LEN for qemu-x86 (Stefan) ---------------------------------------------------------------- Here the Azure build, without any issues: https://dev.azure.com/sr0718/u-boot/_build/results?buildId=45&view=results Thanks, Stefan The following changes since commit 1aa3966173fe92fa3c46638ee8eb8b8491f521d6: Merge tag 'u-boot-clk-24Aug2020' of https://gitlab.denx.de/u-boot/custodians/u-boot-clk (2020-08-24 09:06:02 -0400) are available in the Git repository at: git@gitlab.denx.de:u-boot/custodians/u-boot-marvell.git for you to fetch changes up to 6944937f9c4d21f39dd257bce7b677a0f6849cea: x86: qemu-x86_defconfig: Increase CONFIG_SYS_MALLOC_F_LEN (2020-08-25 11:37:57 +0200) ---------------------------------------------------------------- Stefan Roese (5): dm: core: Add API to read PCI bus-range property pci: pci-uclass: Remove #ifdef CONFIG_NR_DRAM_BANKS as its always set ARM: renesas: Drop unnecessary function ft_board_setup() pci: pci-uclass: Dynamically allocate the PCI regions x86: qemu-x86_defconfig: Increase CONFIG_SYS_MALLOC_F_LEN Suneel Garapati (18): fdtdec: Add API to read pci bus-range property pci: pci-uclass: Fix incorrect argument in map_physmem pci: pci-uclass: Make DT subnode parse optional pci: pci-uclass: Add multi entry support for memory regions pci: pci-uclass: Add support for Enhanced Allocation in Bridges pci: pci-uclass: Add support for Single-Root I/O Virtualization pci: pci-uclass: Add VF BAR map support for Enhanced Allocation pci: pci-uclass: Add support for Alternate-RoutingID capability pci: pci-uclass: Check validity of ofnode arm: include/asm/io.h: Add 64bit clrbits and setbits helpers arm: octeontx: Add headers for OcteonTX arm: octeontx2: Add headers for OcteonTX2 ata: ahci: Add BAR index quirk for Cavium PCI SATA device pci: Add PCI controller driver for OcteonTX / TX2 mmc: Add MMC controller driver for OcteonTX / TX2 watchdog: Add reset support for OcteonTX / TX2 arm: octeontx: Add support for OcteonTX SoC platforms arm: octeontx2: Add support for OcteonTX2 SoC platforms arch/arm/Kconfig | 24 + arch/arm/Makefile | 2 + arch/arm/include/asm/arch-octeontx/board.h | 123 + arch/arm/include/asm/arch-octeontx/clock.h | 25 + .../include/asm/arch-octeontx/csrs/csrs-mio_emm.h | 1193 +++ arch/arm/include/asm/arch-octeontx/csrs/csrs-xcv.h | 428 + arch/arm/include/asm/arch-octeontx/gpio.h | 6 + arch/arm/include/asm/arch-octeontx/smc.h | 20 + arch/arm/include/asm/arch-octeontx/soc.h | 33 + arch/arm/include/asm/arch-octeontx2/board.h | 128 + arch/arm/include/asm/arch-octeontx2/clock.h | 24 + .../arm/include/asm/arch-octeontx2/csrs/csrs-cgx.h | 7851 ++++++++++++++ .../arm/include/asm/arch-octeontx2/csrs/csrs-lmt.h | 60 + .../include/asm/arch-octeontx2/csrs/csrs-mio_emm.h | 1193 +++ .../arm/include/asm/arch-octeontx2/csrs/csrs-nix.h | 10404 +++++++++++++++++++ .../arm/include/asm/arch-octeontx2/csrs/csrs-npa.h | 2294 ++++ .../arm/include/asm/arch-octeontx2/csrs/csrs-npc.h | 1629 +++ .../arm/include/asm/arch-octeontx2/csrs/csrs-rvu.h | 2276 ++++ arch/arm/include/asm/arch-octeontx2/gpio.h | 6 + arch/arm/include/asm/arch-octeontx2/smc-id.h | 32 + arch/arm/include/asm/arch-octeontx2/smc.h | 18 + arch/arm/include/asm/arch-octeontx2/soc.h | 33 + arch/arm/include/asm/io.h | 16 + arch/arm/mach-octeontx/Kconfig | 23 + arch/arm/mach-octeontx/Makefile | 9 + arch/arm/mach-octeontx/clock.c | 35 + arch/arm/mach-octeontx/cpu.c | 76 + arch/arm/mach-octeontx/lowlevel_init.S | 33 + arch/arm/mach-octeontx2/Kconfig | 23 + arch/arm/mach-octeontx2/Makefile | 9 + arch/arm/mach-octeontx2/clock.c | 35 + arch/arm/mach-octeontx2/config.mk | 4 + arch/arm/mach-octeontx2/cpu.c | 72 + arch/arm/mach-octeontx2/lowlevel_init.S | 33 + arch/sandbox/dts/test.dts | 5 +- board/Marvell/octeontx/Kconfig | 14 + board/Marvell/octeontx/MAINTAINERS | 8 + board/Marvell/octeontx/Makefile | 9 + board/Marvell/octeontx/board-fdt.c | 311 + board/Marvell/octeontx/board.c | 152 + board/Marvell/octeontx/smc.c | 25 + board/Marvell/octeontx/soc-utils.c | 50 + board/Marvell/octeontx2/Kconfig | 14 + board/Marvell/octeontx2/MAINTAINERS | 8 + board/Marvell/octeontx2/Makefile | 9 + board/Marvell/octeontx2/board-fdt.c | 221 + board/Marvell/octeontx2/board.c | 247 + board/Marvell/octeontx2/smc.c | 58 + board/Marvell/octeontx2/soc-utils.c | 49 + board/renesas/rcar-common/common.c | 47 - configs/octeontx2_95xx_defconfig | 105 + configs/octeontx2_96xx_defconfig | 131 + configs/octeontx_81xx_defconfig | 130 + configs/octeontx_83xx_defconfig | 129 + configs/qemu-x86_defconfig | 1 + configs/sandbox_defconfig | 1 + configs/sandbox_flattree_defconfig | 1 + drivers/ata/ahci.c | 15 + drivers/core/read.c | 17 + drivers/mmc/Kconfig | 9 + drivers/mmc/Makefile | 1 + drivers/mmc/octeontx_hsmmc.c | 3897 +++++++ drivers/mmc/octeontx_hsmmc.h | 207 + drivers/pci/Kconfig | 37 + drivers/pci/Makefile | 1 + drivers/pci/pci-uclass.c | 288 +- drivers/pci/pci_octeontx.c | 364 + drivers/watchdog/Kconfig | 10 + drivers/watchdog/Makefile | 1 + drivers/watchdog/octeontx_wdt.c | 66 + include/configs/octeontx2_common.h | 72 + include/configs/octeontx_common.h | 89 + include/dm/read.h | 12 + include/fdtdec.h | 13 + include/pci.h | 45 +- lib/fdtdec.c | 16 + test/dm/pci.c | 22 + 77 files changed, 34983 insertions(+), 94 deletions(-) create mode 100644 arch/arm/include/asm/arch-octeontx/board.h create mode 100644 arch/arm/include/asm/arch-octeontx/clock.h create mode 100644 arch/arm/include/asm/arch-octeontx/csrs/csrs-mio_emm.h create mode 100644 arch/arm/include/asm/arch-octeontx/csrs/csrs-xcv.h create mode 100644 arch/arm/include/asm/arch-octeontx/gpio.h create mode 100644 arch/arm/include/asm/arch-octeontx/smc.h create mode 100644 arch/arm/include/asm/arch-octeontx/soc.h create mode 100644 arch/arm/include/asm/arch-octeontx2/board.h create mode 100644 arch/arm/include/asm/arch-octeontx2/clock.h create mode 100644 arch/arm/include/asm/arch-octeontx2/csrs/csrs-cgx.h create mode 100644 arch/arm/include/asm/arch-octeontx2/csrs/csrs-lmt.h create mode 100644 arch/arm/include/asm/arch-octeontx2/csrs/csrs-mio_emm.h create mode 100644 arch/arm/include/asm/arch-octeontx2/csrs/csrs-nix.h create mode 100644 arch/arm/include/asm/arch-octeontx2/csrs/csrs-npa.h create mode 100644 arch/arm/include/asm/arch-octeontx2/csrs/csrs-npc.h create mode 100644 arch/arm/include/asm/arch-octeontx2/csrs/csrs-rvu.h create mode 100644 arch/arm/include/asm/arch-octeontx2/gpio.h create mode 100644 arch/arm/include/asm/arch-octeontx2/smc-id.h create mode 100644 arch/arm/include/asm/arch-octeontx2/smc.h create mode 100644 arch/arm/include/asm/arch-octeontx2/soc.h create mode 100644 arch/arm/mach-octeontx/Kconfig create mode 100644 arch/arm/mach-octeontx/Makefile create mode 100644 arch/arm/mach-octeontx/clock.c create mode 100644 arch/arm/mach-octeontx/cpu.c create mode 100644 arch/arm/mach-octeontx/lowlevel_init.S create mode 100644 arch/arm/mach-octeontx2/Kconfig create mode 100644 arch/arm/mach-octeontx2/Makefile create mode 100644 arch/arm/mach-octeontx2/clock.c create mode 100644 arch/arm/mach-octeontx2/config.mk create mode 100644 arch/arm/mach-octeontx2/cpu.c create mode 100644 arch/arm/mach-octeontx2/lowlevel_init.S create mode 100644 board/Marvell/octeontx/Kconfig create mode 100644 board/Marvell/octeontx/MAINTAINERS create mode 100644 board/Marvell/octeontx/Makefile create mode 100644 board/Marvell/octeontx/board-fdt.c create mode 100644 board/Marvell/octeontx/board.c create mode 100644 board/Marvell/octeontx/smc.c create mode 100644 board/Marvell/octeontx/soc-utils.c create mode 100644 board/Marvell/octeontx2/Kconfig create mode 100644 board/Marvell/octeontx2/MAINTAINERS create mode 100644 board/Marvell/octeontx2/Makefile create mode 100644 board/Marvell/octeontx2/board-fdt.c create mode 100644 board/Marvell/octeontx2/board.c create mode 100644 board/Marvell/octeontx2/smc.c create mode 100644 board/Marvell/octeontx2/soc-utils.c create mode 100644 configs/octeontx2_95xx_defconfig create mode 100644 configs/octeontx2_96xx_defconfig create mode 100644 configs/octeontx_81xx_defconfig create mode 100644 configs/octeontx_83xx_defconfig create mode 100644 drivers/mmc/octeontx_hsmmc.c create mode 100644 drivers/mmc/octeontx_hsmmc.h create mode 100644 drivers/pci/pci_octeontx.c create mode 100644 drivers/watchdog/octeontx_wdt.c create mode 100644 include/configs/octeontx2_common.h create mode 100644 include/configs/octeontx_common.h

2 1

ext2ls zero-length directory entries?
by Joe Buehler 25 Aug '20

25 Aug '20

(This is a vendor-modified version of uboot 2011.03.) I am running into problems using ext2load, the command complains that the file of interest is not found. I know it's there though since it is fine under LINUX. Doing some poking around, I see that ext2ls is showing mostly zero length on the subdirs I am interested in loading files from -- thus the "not found" issues. Some of the directories have enormous lengths and crash uboot when attempting to list their content. I am attempting to load from a large SATA disk partitioned into two equal-size partitions that add up to the whole disk. No problems with the first partition, the second partition has the issue. Does this ring a bell with anyone? Perhaps it is a disk size issue and an old uboot? LINUX says the following about the disk: ata1: SATA link up 3.0 Gbps (SStatus 123 SControl 0) ata1.00: supports DRM functions and may not be fully accessable. ata1.00: ATA-10: Micron_1100_MTFDDAK256TBN, M0MU031, max UDMA/133 ata1.00: 500118192 sectors, multi 16: LBA48 NCQ (depth 31/32) ata1.00: supports DRM functions and may not be fully accessable. ata1.00: configured for UDMA/100 scsi 0:0:0:0: Direct-Access ATA Micron_1100_MTFD n/a PQ: 0 ANSI: 5 sd 0:0:0:0: [sda] 500118192 512-byte logical blocks: (256 GB/238 GiB) sd 0:0:0:0: [sda] Write Protect is off sd 0:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA sda: sda1 sda2 sd 0:0:0:0: [sda] Attached SCSI disk Joe Buehler

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