August 2020 - U-Boot

[PATCH 00/31] Add DM support for omap PWM backlight
by Dario Binacchi 05 Sep '20

05 Sep '20

The series was born from the need to manage the PWM backlight of the display connected to my beaglebone board. To hit the target, I had to develop drivers for PWM management which in turn relied on drivers for managing timers and clocks, all developed according to the driver model. My intention was to use the SoC-specific API only at strictly necessary points in the code. My previous patches for migrating the AM335x display driver to the driver model had required the implementation of additional functions outside the concerns of the driver, (settings for dividing the pixel clock rate, configuring the display DPLL rate, ....) not being able to use the API of the related clock drivers. This series shouldn't have repeated the same kind of mistake. Furthermore, I also wanted to fix that kind of forced choice. Almost everything should have been accessible via the driver model API. In the series there are also some patches that could be submitted separately, but which I have however inserted to avoid applying future patches to incorporate them. With this last consideration, I hope I have convincingly justified the large number of patches in the series. The patch enabling address translation into a CPU physical address from device-tree even in case of crossing levels with #size-cells = <0>, is crucial for the series. The previous implementation was unable to perform the address translation required by the am33xx device tree. I tried to apply in a conservative way as few changes as possible and to verify the execution of all the tests already developed, as well as the new ones I added for the new feature. Dario Binacchi (31): clk: remove a redundant header clk: export generic routines arch: sandbox: fix typo in clk.h clk: add clk_round_rate() clk: ti: add mux clock driver arm: ti: am33xx: add DPLL_EN_FAST_RELOCK_BYPASS macro clk: ti: am33xx: add DPLL clock drivers clk: ti: add divider clock driver clk: ti: refactor mux and divider clock drivers clk: ti: add gate clock driver ti: am33xx: fix do_enable_clocks() to accept NULL parameters clk: ti: add support for clkctrl clocks clk: ti: move drivers to 'ti' directory clk: ti: omap4: add clock manager driver clk: ti: am335x: add clock manager driver fdt: translate address if #size-cells = <0> omap: timer: fix the rate setting misc: am33xx: add control module driver pwm: ti: am33xx: add enhanced pwm driver pwm: ti: am33xx: add subsystem driver video: backlight: fix pwm's duty cycle calculation video: backlight: fix pwm data structure description dm: core: improve uclass_get_device_by_phandle_id() description gpio: fix gpio_request_by_name() description dm: core: add a function to decode display timings video: omap: add panel driver video: omap: enable LCD clock domain through DM API video: omap: set LCD clock rate through DM API video: omap: split the legacy code from the DM code video: omap: move drivers to 'ti' directory board: ti: am335x-ice: get CDCE913 clock device arch/arm/dts/am335x-brppt1-mmc.dts | 3 +- arch/arm/dts/am335x-brppt1-nand.dts | 3 +- arch/arm/dts/am335x-brppt1-spi.dts | 3 +- arch/arm/dts/am335x-brsmarc1.dts | 2 +- arch/arm/dts/am335x-brxre1.dts | 3 +- arch/arm/dts/am335x-evm-u-boot.dtsi | 7 +- arch/arm/dts/am335x-evmsk-u-boot.dtsi | 6 +- arch/arm/dts/am335x-guardian-u-boot.dtsi | 8 +- arch/arm/dts/am335x-pdu001-u-boot.dtsi | 8 +- arch/arm/dts/am335x-pxm50-u-boot.dtsi | 6 +- arch/arm/dts/am335x-rut-u-boot.dtsi | 6 +- arch/arm/dts/am33xx.dtsi | 12 + arch/arm/dts/da850-evm-u-boot.dtsi | 8 +- arch/arm/include/asm/arch-am33xx/clock.h | 1 + arch/arm/mach-omap2/am33xx/clock.c | 10 +- arch/arm/mach-omap2/am33xx/clock_am33xx.c | 2 +- arch/sandbox/dts/test.dts | 67 +++ arch/sandbox/include/asm/clk.h | 35 +- board/ti/am335x/board.c | 2 +- board/ti/am43xx/board.c | 2 +- common/fdt_support.c | 10 +- doc/device-tree-bindings/arm/omap,ctrl.txt | 82 +++ doc/device-tree-bindings/arm/omap,prcm.txt | 63 +++ .../clock/clock-bindings.txt | 186 +++++++ .../clock/gpio-gate-clock.txt | 21 + .../clock/ti,autoidle.txt | 39 ++ doc/device-tree-bindings/clock/ti,clkctrl.txt | 61 +++ .../clock/ti,clockdomain.txt | 24 + doc/device-tree-bindings/clock/ti,divider.txt | 117 +++++ doc/device-tree-bindings/clock/ti,dpll.txt | 85 ++++ doc/device-tree-bindings/clock/ti,gate.txt | 106 ++++ doc/device-tree-bindings/clock/ti,mux.txt | 79 +++ .../pinctrl/pinctrl-single.txt | 255 ++++++++++ doc/device-tree-bindings/pwm/ti,ehrpwm.txt | 49 ++ doc/device-tree-bindings/pwm/ti,pwmss.txt | 58 +++ drivers/clk/Kconfig | 9 +- drivers/clk/Makefile | 2 +- drivers/clk/clk-divider.c | 18 +- drivers/clk/clk-uclass.c | 15 + drivers/clk/clk_sandbox.c | 17 + drivers/clk/clk_sandbox_test.c | 10 + drivers/clk/ti/Kconfig | 42 ++ drivers/clk/ti/Makefile | 18 + drivers/clk/ti/am3-prcm.c | 73 +++ drivers/clk/ti/clk-am3-dpll-x2.c | 78 +++ drivers/clk/ti/clk-am3-dpll.c | 267 ++++++++++ drivers/clk/ti/clk-ctrl.c | 102 ++++ drivers/clk/ti/clk-divider.c | 380 ++++++++++++++ drivers/clk/ti/clk-gate.c | 92 ++++ drivers/clk/ti/clk-mux.c | 252 ++++++++++ drivers/clk/{clk-ti-sci.c => ti/clk-sci.c} | 0 drivers/clk/ti/clk.c | 34 ++ drivers/clk/ti/clk.h | 13 + drivers/clk/ti/omap4-cm.c | 22 + drivers/core/Kconfig | 12 + drivers/core/fdtaddr.c | 2 +- drivers/core/of_addr.c | 14 +- drivers/core/ofnode.c | 11 +- drivers/core/read.c | 6 + drivers/misc/Kconfig | 7 + drivers/misc/Makefile | 1 + drivers/misc/ti-am3-scm.c | 90 ++++ drivers/pwm/Kconfig | 13 + drivers/pwm/Makefile | 2 + drivers/pwm/pwm-ti-ehrpwm.c | 465 ++++++++++++++++++ drivers/pwm/pwm-ti-pwmss.c | 95 ++++ drivers/timer/omap-timer.c | 6 +- drivers/video/Kconfig | 5 +- drivers/video/Makefile | 2 +- drivers/video/pwm_backlight.c | 4 +- drivers/video/ti/Kconfig | 8 + drivers/video/ti/Makefile | 10 + drivers/video/{ => ti}/am335x-fb.c | 342 +------------ drivers/video/{ => ti}/am335x-fb.h | 4 - drivers/video/ti/tilcdc-panel.c | 171 +++++++ drivers/video/ti/tilcdc-panel.h | 14 + drivers/video/ti/tilcdc.c | 438 +++++++++++++++++ drivers/video/ti/tilcdc.h | 38 ++ include/asm-generic/gpio.h | 2 +- include/clk-uclass.h | 8 + include/clk.h | 29 ++ include/dm/read.h | 24 + include/dm/uclass.h | 3 +- include/linux/clk-provider.h | 11 +- test/dm/clk.c | 22 + test/dm/panel.c | 12 +- test/dm/test-fdt.c | 153 +++++- 87 files changed, 4459 insertions(+), 438 deletions(-) create mode 100644 doc/device-tree-bindings/arm/omap,ctrl.txt create mode 100644 doc/device-tree-bindings/arm/omap,prcm.txt create mode 100644 doc/device-tree-bindings/clock/clock-bindings.txt create mode 100644 doc/device-tree-bindings/clock/gpio-gate-clock.txt create mode 100644 doc/device-tree-bindings/clock/ti,autoidle.txt create mode 100644 doc/device-tree-bindings/clock/ti,clkctrl.txt create mode 100644 doc/device-tree-bindings/clock/ti,clockdomain.txt create mode 100644 doc/device-tree-bindings/clock/ti,divider.txt create mode 100644 doc/device-tree-bindings/clock/ti,dpll.txt create mode 100644 doc/device-tree-bindings/clock/ti,gate.txt create mode 100644 doc/device-tree-bindings/clock/ti,mux.txt create mode 100644 doc/device-tree-bindings/pinctrl/pinctrl-single.txt create mode 100644 doc/device-tree-bindings/pwm/ti,ehrpwm.txt create mode 100644 doc/device-tree-bindings/pwm/ti,pwmss.txt create mode 100644 drivers/clk/ti/Kconfig create mode 100644 drivers/clk/ti/Makefile create mode 100644 drivers/clk/ti/am3-prcm.c create mode 100644 drivers/clk/ti/clk-am3-dpll-x2.c create mode 100644 drivers/clk/ti/clk-am3-dpll.c create mode 100644 drivers/clk/ti/clk-ctrl.c create mode 100644 drivers/clk/ti/clk-divider.c create mode 100644 drivers/clk/ti/clk-gate.c create mode 100644 drivers/clk/ti/clk-mux.c rename drivers/clk/{clk-ti-sci.c => ti/clk-sci.c} (100%) create mode 100644 drivers/clk/ti/clk.c create mode 100644 drivers/clk/ti/clk.h create mode 100644 drivers/clk/ti/omap4-cm.c create mode 100644 drivers/misc/ti-am3-scm.c create mode 100644 drivers/pwm/pwm-ti-ehrpwm.c create mode 100644 drivers/pwm/pwm-ti-pwmss.c create mode 100644 drivers/video/ti/Kconfig create mode 100644 drivers/video/ti/Makefile rename drivers/video/{ => ti}/am335x-fb.c (54%) rename drivers/video/{ => ti}/am335x-fb.h (97%) create mode 100644 drivers/video/ti/tilcdc-panel.c create mode 100644 drivers/video/ti/tilcdc-panel.h create mode 100644 drivers/video/ti/tilcdc.c create mode 100644 drivers/video/ti/tilcdc.h -- 2.17.1

4 42

[PATCH 1/2] defconfig: espressobin: Include support for Gigadevice SPI
by Andre Heider 04 Sep '20

04 Sep '20

From: Konstantin Porotchkin <kostap(a)marvell.com> Include support for CONFIG_SPI_FLASH_GIGADEVICE for supporting newly produces EspressoBin boards (v7) Change-Id: I5d4b972cbe2ee5a9d52ce9908794ad4e1b59ee3b Signed-off-by: Konstantin Porotchkin <kostap(a)marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/61236 Tested-by: iSoC Platform CI <ykjenk(a)marvell.com> Reviewed-by: Igal Liberman <igall(a)marvell.com> --- configs/mvebu_espressobin-88f3720_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/mvebu_espressobin-88f3720_defconfig b/configs/mvebu_espressobin-88f3720_defconfig index 99f421d841..d07c67dbc8 100644 --- a/configs/mvebu_espressobin-88f3720_defconfig +++ b/configs/mvebu_espressobin-88f3720_defconfig @@ -54,6 +54,7 @@ CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_PHYLIB=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y -- 2.28.0

3 7

[PATCH] phy: marvell: a3700: add sata comphy on lane 2 with invert option
by Andre Heider 04 Sep '20

04 Sep '20

From: zachary <zhangzg(a)marvell.com> - This patch moves sata phy powerup from dedicate phy to compphy and adds invert option for sata powerup routine. Change-Id: I1b4e8753e2b2c14c6efa97bca2ffc7d2553d8a90 Signed-off-by: zachary <zhangzg(a)marvell.com> Signed-off-by: Ken Ma <make(a)marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/53601 Reviewed-by: Igal Liberman <igall(a)marvell.com> Tested-by: Igal Liberman <igall(a)marvell.com> [a.heider: adapt to mainline] Signed-off-by: Andre Heider <a.heider(a)gmail.com> --- This is based on the downstream patch: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/0a5b1598… Fixes SATA on my espressobin v5. drivers/phy/marvell/comphy_a3700.c | 33 +++++++++++++----------------- 1 file changed, 14 insertions(+), 19 deletions(-) diff --git a/drivers/phy/marvell/comphy_a3700.c b/drivers/phy/marvell/comphy_a3700.c index dc188c44e0..4606de6f48 100644 --- a/drivers/phy/marvell/comphy_a3700.c +++ b/drivers/phy/marvell/comphy_a3700.c @@ -273,16 +273,23 @@ static void reg_set_indirect(u32 reg, u16 data, u16 mask) * * return: 1 if PLL locked (OK), 0 otherwise (FAIL) */ -static int comphy_sata_power_up(void) +static int comphy_sata_power_up(u32 invert) { int ret; + u32 data = 0; debug_enter(); /* - * 0. Swap SATA TX lines + * 0. Check the Polarity invert bits */ - reg_set_indirect(vphy_sync_pattern_reg, bs_txd_inv, bs_txd_inv); + if (invert & PHY_POLARITY_TXD_INVERT) + data |= bs_txd_inv; + + if (invert & PHY_POLARITY_RXD_INVERT) + data |= bs_rxd_inv; + + reg_set_indirect(vphy_sync_pattern_reg, data, bs_txd_inv | bs_rxd_inv); /* * 1. Select 40-bit data width width @@ -924,22 +931,6 @@ void comphy_dedicated_phys_init(void) } } - node = fdt_node_offset_by_compatible(blob, -1, - "marvell,armada-3700-ahci"); - if (node > 0) { - if (fdtdec_get_is_enabled(blob, node)) { - ret = comphy_sata_power_up(); - if (!ret) - printf("Failed to initialize SATA PHY\n"); - else - debug("SATA PHY init succeed\n"); - } else { - debug("SATA node is disabled\n"); - } - } else { - debug("No SATA node in DT\n"); - } - node = fdt_node_offset_by_compatible(blob, -1, "marvell,armada-8k-sdhci"); if (node <= 0) { @@ -1007,6 +998,10 @@ int comphy_a3700_init(struct chip_serdes_phy_config *chip_cfg, comphy_map->invert); break; + case PHY_TYPE_SATA0: + ret = comphy_sata_power_up(comphy_map->invert); + break; + default: debug("Unknown SerDes type, skip initialize SerDes %d\n", lane); -- 2.28.0

3 3

[PATCH v1 0/5] SoCFPGA mailbox driver fixes and enhancements
by Chee Hong Ang 04 Sep '20

04 Sep '20

Fixes: - Proper timeout implementation - Always read mailbox response data before returning mailbox status to caller Enhancement: - Auto retry on mailbox sending - Send large mailbox message Chee Hong Ang (3): arm: socfpga: mailbox: Refactor mailbox timeout event handling arm: socfpga: mailbox: Always read mailbox responses before returning status arm: socfpga: mailbox: Support sending large mailbox command Ley Foon Tan (2): arm: socfpga: mailbox: Update mailbox response codes arm: socfpga: mailbox: Add mailbox retry support .../mach-socfpga/include/mach/mailbox_s10.h | 38 +++- arch/arm/mach-socfpga/mailbox_s10.c | 172 ++++++++++++------ 2 files changed, 156 insertions(+), 54 deletions(-) -- 2.19.0

2 8

[PATCH v3 1/3] fdtdec: optionally add property no-map to created reserved memory node
by Patrice Chotard 04 Sep '20

04 Sep '20

From: Etienne Carriere <etienne.carriere(a)st.com> Add boolean input argument @no_map to helper function fdtdec_add_reserved_memory() to add "no-map" property for an added reserved memory node. This is needed for example when the reserved memory relates to secure memory that the dear Linux kernel shall not even map unless what non-secure world speculative accesses of the CPU can violate the memory firmware configuration. No function change. A later change will update to OPTEE library to add no-map property to OP-TEE reserved memory nodes. Signed-off-by: Etienne Carriere <etienne.carriere(a)st.com> Signed-off-by: Patrice Chotard <patrice.chotard(a)st.com> --- (no changes since v2) Changes in v2: - fix dm fdtdec test and arch/riscv/lib/fdt_fixup.c with fdtdec_add_reserved_memory() new parameter arch/riscv/lib/fdt_fixup.c | 2 +- include/fdtdec.h | 5 +++-- lib/fdtdec.c | 10 ++++++++-- lib/optee/optee.c | 2 +- test/dm/fdtdec.c | 6 +++--- 5 files changed, 16 insertions(+), 9 deletions(-) diff --git a/arch/riscv/lib/fdt_fixup.c b/arch/riscv/lib/fdt_fixup.c index 5b2420243f..d02062fd5b 100644 --- a/arch/riscv/lib/fdt_fixup.c +++ b/arch/riscv/lib/fdt_fixup.c @@ -75,7 +75,7 @@ int riscv_fdt_copy_resv_mem_node(const void *src, void *dst) pmp_mem.start = addr; pmp_mem.end = addr + size - 1; err = fdtdec_add_reserved_memory(dst, basename, &pmp_mem, - &phandle); + &phandle, false); if (err < 0 && err != -FDT_ERR_EXISTS) { log_err("failed to add reserved memory: %d\n", err); return err; diff --git a/include/fdtdec.h b/include/fdtdec.h index bc79389260..f127c7d386 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -1016,7 +1016,7 @@ static inline int fdtdec_set_phandle(void *blob, int node, uint32_t phandle) * }; * uint32_t phandle; * - * fdtdec_add_reserved_memory(fdt, "framebuffer", &fb, &phandle); + * fdtdec_add_reserved_memory(fdt, "framebuffer", &fb, &phandle, false); * * This results in the following subnode being added to the top-level * /reserved-memory node: @@ -1043,11 +1043,12 @@ static inline int fdtdec_set_phandle(void *blob, int node, uint32_t phandle) * @param carveout information about the carveout region * @param phandlep return location for the phandle of the carveout region * can be NULL if no phandle should be added + * @param no_map add "no-map" property if true * @return 0 on success or a negative error code on failure */ int fdtdec_add_reserved_memory(void *blob, const char *basename, const struct fdt_memory *carveout, - uint32_t *phandlep); + uint32_t *phandlep, bool no_map); /** * fdtdec_get_carveout() - reads a carveout from an FDT diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 30a1c6a217..bf40d87cb3 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -1303,7 +1303,7 @@ static int fdtdec_init_reserved_memory(void *blob) int fdtdec_add_reserved_memory(void *blob, const char *basename, const struct fdt_memory *carveout, - uint32_t *phandlep) + uint32_t *phandlep, bool no_map) { fdt32_t cells[4] = {}, *ptr = cells; uint32_t upper, lower, phandle; @@ -1403,6 +1403,12 @@ int fdtdec_add_reserved_memory(void *blob, const char *basename, if (err < 0) return err; + if (no_map) { + err = fdt_setprop(blob, node, "no-map", NULL, 0); + if (err < 0) + return err; + } + /* return the phandle for the new node for the caller to use */ if (phandlep) *phandlep = phandle; @@ -1468,7 +1474,7 @@ int fdtdec_set_carveout(void *blob, const char *node, const char *prop_name, fdt32_t value; void *prop; - err = fdtdec_add_reserved_memory(blob, name, carveout, &phandle); + err = fdtdec_add_reserved_memory(blob, name, carveout, &phandle, false); if (err < 0) { debug("failed to add reserved memory: %d\n", err); return err; diff --git a/lib/optee/optee.c b/lib/optee/optee.c index 457d4cca8a..963c2ff430 100644 --- a/lib/optee/optee.c +++ b/lib/optee/optee.c @@ -192,7 +192,7 @@ int optee_copy_fdt_nodes(const void *old_blob, void *new_blob) ret = fdtdec_add_reserved_memory(new_blob, nodename, &carveout, - NULL); + NULL, false); free(oldname); if (ret < 0) diff --git a/test/dm/fdtdec.c b/test/dm/fdtdec.c index 716993f706..4119003041 100644 --- a/test/dm/fdtdec.c +++ b/test/dm/fdtdec.c @@ -80,7 +80,7 @@ static int dm_test_fdtdec_add_reserved_memory(struct unit_test_state *uts) resv.start = 0x1000; resv.end = 0x1fff; ut_assertok(fdtdec_add_reserved_memory(blob, "rsvd_region", - &resv, &phandle)); + &resv, &phandle, false)); /* Test /reserve-memory and its subnode should exist */ parent = fdt_path_offset(blob, "/reserved-memory"); @@ -101,7 +101,7 @@ static int dm_test_fdtdec_add_reserved_memory(struct unit_test_state *uts) resv.start = 0x2000; resv.end = 0x2fff; ut_assertok(fdtdec_add_reserved_memory(blob, "rsvd_region1", - &resv, &phandle1)); + &resv, &phandle1, false)); subnode = fdt_path_offset(blob, "/reserved-memory/rsvd_region1"); ut_assert(subnode > 0); @@ -115,7 +115,7 @@ static int dm_test_fdtdec_add_reserved_memory(struct unit_test_state *uts) resv.start = 0x1000; resv.end = 0x1fff; ut_assertok(fdtdec_add_reserved_memory(blob, "rsvd_region2", - &resv, &phandle1)); + &resv, &phandle1, false)); subnode = fdt_path_offset(blob, "/reserved-memory/rsvd_region2"); ut_assert(subnode < 0); -- 2.17.1

4 5

[PATCH v2 0/7] riscv: Clean up timer drivers
by Sean Anderson 03 Sep '20

03 Sep '20

This series cleans up the timer drivers in RISC-V and converts them to DM. This series depends on [1]. This series needs to be tested! I have only tested it on QEMU and the K210. Notably, this means that the HiFive and anything Andes is completely untested. CI for this series is located at [2]. [1] https://patchwork.ozlabs.org/project/uboot/list/?series=190862 [2] https://dev.azure.com/seanga2/u-boot/_build/results?buildId=4 Changes in v2: - Remove RISCV_RDTIME KConfig option - Split Kendryte binding changes into their own commit - Fix SiFive CLINT not getting tick-rate from rtcclk Sean Anderson (7): riscv: Rework riscv timer driver to only support S-mode riscv: Rework Andes PLMT as a UCLASS_TIMER driver riscv: Clean up initialization in Andes PLIC riscv: Rework Sifive CLINT as UCLASS_TIMER driver riscv: clk: Add CLINT clock to kendryte clock driver riscv: Update Kendryte device tree for new CLINT driver riscv: Update SiFive device tree for new CLINT driver arch/riscv/Kconfig | 16 ---- arch/riscv/dts/ae350_32.dts | 1 + arch/riscv/dts/ae350_64.dts | 1 + arch/riscv/dts/fu540-c000-u-boot.dtsi | 8 +- .../dts/hifive-unleashed-a00-u-boot.dtsi | 4 + arch/riscv/dts/k210.dtsi | 9 +- arch/riscv/include/asm/global_data.h | 3 - arch/riscv/lib/Makefile | 1 - arch/riscv/lib/andes_plic.c | 58 ++++++------- arch/riscv/lib/andes_plmt.c | 42 +++++---- arch/riscv/lib/rdtime.c | 38 -------- arch/riscv/lib/sifive_clint.c | 87 ++++++++++++------- common/spl/spl_opensbi.c | 5 ++ drivers/clk/kendryte/clk.c | 4 + drivers/ram/sifive/Kconfig | 2 + drivers/timer/Kconfig | 6 +- drivers/timer/riscv_timer.c | 39 +++++---- include/dt-bindings/clock/k210-sysctl.h | 1 + 18 files changed, 155 insertions(+), 170 deletions(-) delete mode 100644 arch/riscv/lib/rdtime.c -- 2.27.0

3 24

[PATCH] travis-ci: Add SH4 r2dplus machine with various PCI ethernet options
by Marek Vasut 02 Sep '20

02 Sep '20

Add SH4 R2Dplus machine configured to test various U-Boot PCI ethernet options -- RTL8139, EEPRO100, AMD PCnet, DEC Tulip. Signed-off-by: Marek Vasut <marek.vasut+renesas(a)gmail.com> Cc: Stephen Warren <swarren(a)nvidia.com> Cc: Tom Rini <trini(a)konsulko.com> --- bin/travis-ci/conf.r2dplus_i82557c_qemu | 27 +++++++++++++++++++ bin/travis-ci/conf.r2dplus_pcnet_qemu | 27 +++++++++++++++++++ bin/travis-ci/conf.r2dplus_rtl8139_qemu | 27 +++++++++++++++++++ bin/travis-ci/conf.r2dplus_tulip_qemu | 27 +++++++++++++++++++ .../u_boot_boardenv_r2dplus_i82557c_qemu.py | 6 +++++ .../u_boot_boardenv_r2dplus_pcnet_qemu.py | 6 +++++ .../u_boot_boardenv_r2dplus_rtl8139_qemu.py | 6 +++++ .../u_boot_boardenv_r2dplus_tulip_qemu.py | 6 +++++ 8 files changed, 132 insertions(+) create mode 100644 bin/travis-ci/conf.r2dplus_i82557c_qemu create mode 100644 bin/travis-ci/conf.r2dplus_pcnet_qemu create mode 100644 bin/travis-ci/conf.r2dplus_rtl8139_qemu create mode 100644 bin/travis-ci/conf.r2dplus_tulip_qemu create mode 100644 py/travis-ci/u_boot_boardenv_r2dplus_i82557c_qemu.py create mode 100644 py/travis-ci/u_boot_boardenv_r2dplus_pcnet_qemu.py create mode 100644 py/travis-ci/u_boot_boardenv_r2dplus_rtl8139_qemu.py create mode 100644 py/travis-ci/u_boot_boardenv_r2dplus_tulip_qemu.py diff --git a/bin/travis-ci/conf.r2dplus_i82557c_qemu b/bin/travis-ci/conf.r2dplus_i82557c_qemu new file mode 100644 index 0000000..85ad999 --- /dev/null +++ b/bin/travis-ci/conf.r2dplus_i82557c_qemu @@ -0,0 +1,27 @@ +# Copyright (c) 2020 Marek Vasut <marek.vasut+renesas(a)gmail.com> +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +# DEALINGS IN THE SOFTWARE. + +console_impl=qemu +qemu_machine="r2d" +qemu_binary="qemu-system-sh4" +qemu_extra_args="-nographic -serial null -serial mon:stdio -net user,tftp=${UBOOT_TRAVIS_BUILD_DIR} -net nic,model=i82557c" +qemu_kernel_args="-kernel ${U_BOOT_BUILD_DIR}/u-boot.bin" +reset_impl=none +flash_impl=none diff --git a/bin/travis-ci/conf.r2dplus_pcnet_qemu b/bin/travis-ci/conf.r2dplus_pcnet_qemu new file mode 100644 index 0000000..5d208bd --- /dev/null +++ b/bin/travis-ci/conf.r2dplus_pcnet_qemu @@ -0,0 +1,27 @@ +# Copyright (c) 2020 Marek Vasut <marek.vasut+renesas(a)gmail.com> +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +# DEALINGS IN THE SOFTWARE. + +console_impl=qemu +qemu_machine="r2d" +qemu_binary="qemu-system-sh4" +qemu_extra_args="-nographic -serial null -serial mon:stdio -net user,tftp=${UBOOT_TRAVIS_BUILD_DIR} -net nic,model=pcnet" +qemu_kernel_args="-kernel ${U_BOOT_BUILD_DIR}/u-boot.bin" +reset_impl=none +flash_impl=none diff --git a/bin/travis-ci/conf.r2dplus_rtl8139_qemu b/bin/travis-ci/conf.r2dplus_rtl8139_qemu new file mode 100644 index 0000000..b582eec --- /dev/null +++ b/bin/travis-ci/conf.r2dplus_rtl8139_qemu @@ -0,0 +1,27 @@ +# Copyright (c) 2020 Marek Vasut <marek.vasut+renesas(a)gmail.com> +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +# DEALINGS IN THE SOFTWARE. + +console_impl=qemu +qemu_machine="r2d" +qemu_binary="qemu-system-sh4" +qemu_extra_args="-nographic -serial null -serial mon:stdio -net user,tftp=${UBOOT_TRAVIS_BUILD_DIR} -net nic,model=rtl8139" +qemu_kernel_args="-kernel ${U_BOOT_BUILD_DIR}/u-boot.bin" +reset_impl=none +flash_impl=none diff --git a/bin/travis-ci/conf.r2dplus_tulip_qemu b/bin/travis-ci/conf.r2dplus_tulip_qemu new file mode 100644 index 0000000..b04ba06 --- /dev/null +++ b/bin/travis-ci/conf.r2dplus_tulip_qemu @@ -0,0 +1,27 @@ +# Copyright (c) 2020 Marek Vasut <marek.vasut+renesas(a)gmail.com> +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +# DEALINGS IN THE SOFTWARE. + +console_impl=qemu +qemu_machine="r2d" +qemu_binary="qemu-system-sh4" +qemu_extra_args="-nographic -serial null -serial mon:stdio -net user,tftp=${UBOOT_TRAVIS_BUILD_DIR} -net nic,model=tulip" +qemu_kernel_args="-kernel ${U_BOOT_BUILD_DIR}/u-boot.bin" +reset_impl=none +flash_impl=none diff --git a/py/travis-ci/u_boot_boardenv_r2dplus_i82557c_qemu.py b/py/travis-ci/u_boot_boardenv_r2dplus_i82557c_qemu.py new file mode 100644 index 0000000..8fdb24b --- /dev/null +++ b/py/travis-ci/u_boot_boardenv_r2dplus_i82557c_qemu.py @@ -0,0 +1,6 @@ +import os +import travis_tftp + +env__net_uses_pci = True +env__net_dhcp_server = True +env__net_tftp_readable_file = travis_tftp.file2env('u-boot') diff --git a/py/travis-ci/u_boot_boardenv_r2dplus_pcnet_qemu.py b/py/travis-ci/u_boot_boardenv_r2dplus_pcnet_qemu.py new file mode 100644 index 0000000..8fdb24b --- /dev/null +++ b/py/travis-ci/u_boot_boardenv_r2dplus_pcnet_qemu.py @@ -0,0 +1,6 @@ +import os +import travis_tftp + +env__net_uses_pci = True +env__net_dhcp_server = True +env__net_tftp_readable_file = travis_tftp.file2env('u-boot') diff --git a/py/travis-ci/u_boot_boardenv_r2dplus_rtl8139_qemu.py b/py/travis-ci/u_boot_boardenv_r2dplus_rtl8139_qemu.py new file mode 100644 index 0000000..8fdb24b --- /dev/null +++ b/py/travis-ci/u_boot_boardenv_r2dplus_rtl8139_qemu.py @@ -0,0 +1,6 @@ +import os +import travis_tftp + +env__net_uses_pci = True +env__net_dhcp_server = True +env__net_tftp_readable_file = travis_tftp.file2env('u-boot') diff --git a/py/travis-ci/u_boot_boardenv_r2dplus_tulip_qemu.py b/py/travis-ci/u_boot_boardenv_r2dplus_tulip_qemu.py new file mode 100644 index 0000000..8fdb24b --- /dev/null +++ b/py/travis-ci/u_boot_boardenv_r2dplus_tulip_qemu.py @@ -0,0 +1,6 @@ +import os +import travis_tftp + +env__net_uses_pci = True +env__net_dhcp_server = True +env__net_tftp_readable_file = travis_tftp.file2env('u-boot') -- 2.27.0

4 4

[PATCH v2 1/4] mmc: pic32: Refresh PIC32 MMC driver
by John Robertson 02 Sep '20

02 Sep '20

The existing driver is not compatible with the Driver Model. This patch makes the necessary changes while also removing obsolescent calls/properties as follows: - fdtdec_* calls replaced with dev_read_* equivalents; - 'clock-freq-min-max' property replaced by querying the frequency of the source clock 'base_clk'; - The card detect erratum workaround is applied during probe rather than overriding get_cd. The card detect workaround (Microchip ref. DS80000736E, erratum #15) is not needed if the SDCD signal is properly connected on the board and so can be disabled using a vendor specific DT property. Signed-off-by: John Robertson <john.robertson(a)simiatec.com> --- Changes in v2: - Split patch; - Fix compilation failure after 'make pic32mzdask_defconfig'. drivers/mmc/pic32_sdhci.c | 77 ++++++++++++++++++++++++--------------- 1 file changed, 48 insertions(+), 29 deletions(-) diff --git a/drivers/mmc/pic32_sdhci.c b/drivers/mmc/pic32_sdhci.c index 029e0fbc2b..93f0532ad6 100644 --- a/drivers/mmc/pic32_sdhci.c +++ b/drivers/mmc/pic32_sdhci.c @@ -9,62 +9,78 @@ #include <common.h> #include <dm.h> #include <sdhci.h> -#include <linux/errno.h> -#include <mach/pic32.h> +#include <clk.h> DECLARE_GLOBAL_DATA_PTR; -static int pic32_sdhci_get_cd(struct sdhci_host *host) -{ - /* PIC32 SDHCI CD errata: - * - set CD_TEST and clear CD_TEST_INS bit - */ - sdhci_writeb(host, SDHCI_CTRL_CD_TEST, SDHCI_HOST_CONTROL); - - return 0; -} - -static const struct sdhci_ops pic32_sdhci_ops = { - .get_cd = pic32_sdhci_get_cd, +struct pic32_sdhci_plat { + struct mmc_config cfg; + struct mmc mmc; }; static int pic32_sdhci_probe(struct udevice *dev) { + struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); + struct pic32_sdhci_plat *plat = dev_get_platdata(dev); struct sdhci_host *host = dev_get_priv(dev); - const void *fdt = gd->fdt_blob; - u32 f_min_max[2]; + fdt_addr_t addr; fdt_size_t size; + struct clk clk; + ulong clk_rate; int ret; - addr = fdtdec_get_addr_size(fdt, dev_of_offset(dev), "reg", &size); + addr = dev_read_addr_size(dev, "reg", &size); if (addr == FDT_ADDR_T_NONE) return -EINVAL; + ret = clk_get_by_name(dev, "base_clk", &clk); + if (ret) + return ret; + + clk_rate = clk_get_rate(&clk); + clk_free(&clk); + + if (IS_ERR_VALUE(clk_rate)) + return clk_rate; + host->ioaddr = ioremap(addr, size); host->name = dev->name; host->quirks = SDHCI_QUIRK_NO_HISPD_BIT; - host->bus_width = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), - "bus-width", 4); - host->ops = &pic32_sdhci_ops; - - ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev), - "clock-freq-min-max", f_min_max, 2); - if (ret) { - printf("sdhci: clock-freq-min-max not found\n"); + host->bus_width = dev_read_u32_default(dev, "bus-width", 4); + host->max_clk = clk_rate; + + host->mmc = &plat->mmc; + host->mmc->dev = dev; + + ret = sdhci_setup_cfg(&plat->cfg, host, 0, 0); + if (ret) return ret; - } - host->max_clk = f_min_max[1]; + host->mmc->priv = host; + upriv->mmc = host->mmc; - ret = add_sdhci(host, 0, f_min_max[0]); + ret = sdhci_probe(dev); if (ret) return ret; - host->mmc->dev = dev; + + if (!dev_read_bool(dev, "microchip,use-sdcd")) { + // Use workaround 1 for erratum #15 by default + u8 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); + ctrl = (ctrl & ~SDHCI_CTRL_CD_TEST_INS) | SDHCI_CTRL_CD_TEST; + sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); + } return 0; } +static int pic32_sdhci_bind(struct udevice *dev) +{ + struct pic32_sdhci_plat *plat = dev_get_platdata(dev); + + return sdhci_bind(dev, &plat->mmc, &plat->cfg); +} + static const struct udevice_id pic32_sdhci_ids[] = { { .compatible = "microchip,pic32mzda-sdhci" }, { } @@ -74,6 +90,9 @@ U_BOOT_DRIVER(pic32_sdhci_drv) = { .name = "pic32_sdhci", .id = UCLASS_MMC, .of_match = pic32_sdhci_ids, + .ops = &sdhci_ops, + .bind = pic32_sdhci_bind, .probe = pic32_sdhci_probe, .priv_auto_alloc_size = sizeof(struct sdhci_host), + .platdata_auto_alloc_size = sizeof(struct pic32_sdhci_plat) }; -- 2.28.0

2 2

[PATCH v2 4/4] mmc: pic32: Refresh PIC32 MMC driver
by John Robertson 02 Sep '20

02 Sep '20

CONFIG_BLK needs to be enabled by default to allow U-Boot to compile after a 'make pic32mzdask_defconfig'. Signed-off-by: John Robertson <john.robertson(a)simiatec.com> --- configs/pic32mzdask_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/pic32mzdask_defconfig b/configs/pic32mzdask_defconfig index 7bf61e2d8d..f5c88737b9 100644 --- a/configs/pic32mzdask_defconfig +++ b/configs/pic32mzdask_defconfig @@ -27,7 +27,7 @@ CONFIG_CMD_EXT4_WRITE=y # CONFIG_EFI_PARTITION is not set CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y -# CONFIG_BLK is not set +CONFIG_BLK is not set CONFIG_CLK=y CONFIG_MMC=y CONFIG_DM_MMC=y -- 2.28.0

2 2

[PATCH 1/2] xenon_sdhci: support for HS200 mode
by Andre Heider 02 Sep '20

02 Sep '20

From: Wojciech Macek <wma(a)semihalf.com> Add support for Marvell Xenon SDHCI HS200 mode. Changes focue mostly on correct PHY initialization. All procedure is similar to the one done by Linux driver, but simplified. Change-Id: I5e2396eeb23784f495abc18ea5a2eb7a92390730 Signed-off-by: Wojciech Macek <wma(a)semihalf.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/59230 Tested-by: iSoC Platform CI <ykjenk(a)marvell.com> Reviewed-by: Grzegorz Jaszczyk <jaz(a)semihalf.com> Reviewed-by: Kostya Porotchkin <kostap(a)marvell.com> Reviewed-by: Igal Liberman <igall(a)marvell.com> [a.heider: adapt to mainline] Signed-off-by: Andre Heider <a.heider(a)gmail.com> --- Missing downstream patch, noticed while diffing branches: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/38723250… drivers/mmc/xenon_sdhci.c | 335 ++++++++++++++++++++++++++++++++++++-- 1 file changed, 323 insertions(+), 12 deletions(-) diff --git a/drivers/mmc/xenon_sdhci.c b/drivers/mmc/xenon_sdhci.c index 7f9a579c83..ec255d30b0 100644 --- a/drivers/mmc/xenon_sdhci.c +++ b/drivers/mmc/xenon_sdhci.c @@ -16,6 +16,7 @@ #include <common.h> #include <dm.h> +#include <dm/device_compat.h> #include <fdtdec.h> #include <linux/bitops.h> #include <linux/delay.h> @@ -45,6 +46,7 @@ DECLARE_GLOBAL_DATA_PTR; #define SDHC_SLOT_EMMC_CTRL 0x0130 #define ENABLE_DATA_STROBE_SHIFT 24 +#define ENABLE_DATA_STROBE BIT(ENABLE_DATA_STROBE_SHIFT) #define SET_EMMC_RSTN_SHIFT 16 #define EMMC_VCCQ_MASK 0x3 #define EMMC_VCCQ_1_8V 0x1 @@ -64,6 +66,7 @@ DECLARE_GLOBAL_DATA_PTR; #define OUTPUT_QSN_PHASE_SELECT BIT(17) #define SAMPL_INV_QSP_PHASE_SELECT BIT(18) #define SAMPL_INV_QSP_PHASE_SELECT_SHIFT 18 +#define EMMC_PHY_SDIO_MODE BIT(28) #define EMMC_PHY_SLOW_MODE BIT(29) #define PHY_INITIALIZAION BIT(31) #define WAIT_CYCLE_BEFORE_USING_MASK 0xf @@ -90,6 +93,7 @@ DECLARE_GLOBAL_DATA_PTR; #define FC_QSN_RECEN BIT(27) #define OEN_QSN BIT(28) #define AUTO_RECEN_CTRL BIT(30) +#define FC_ALL_CMOS_RECEIVER (REC_EN_MASK << REC_EN_SHIFT) #define EMMC_PHY_PAD_CONTROL1 (EMMC_PHY_REG_BASE + 0xc) #define EMMC5_1_FC_QSP_PD BIT(9) @@ -99,10 +103,71 @@ DECLARE_GLOBAL_DATA_PTR; #define EMMC5_1_FC_DQ_PD 0xff #define EMMC5_1_FC_DQ_PU (0xff << 16) +#define EMMC_PHY_PAD_CONTROL2 (EMMC_PHY_REG_BASE + 0x10) +#define ZNR_MASK 0x1F +#define ZNR_SHIFT 8 +#define ZPR_MASK 0x1F + #define SDHCI_RETUNE_EVT_INTSIG 0x00001000 +#define SDHCI_HOST_CONTROL2 0x3E +#define SDHCI_CTRL_UHS_MASK 0x0007 +#define SDHCI_CTRL_UHS_SDR12 0x0000 +#define SDHCI_CTRL_UHS_SDR25 0x0001 +#define SDHCI_CTRL_UHS_SDR50 0x0002 +#define SDHCI_CTRL_UHS_SDR104 0x0003 +#define SDHCI_CTRL_UHS_DDR50 0x0004 +#define SDHCI_CTRL_HS400 0x0005 /* Non-standard */ +#define SDHCI_CTRL_HS200_ONLY 0x0005 /* Non-standard */ +#define SDHCI_CTRL_HS400_ONLY 0x0006 /* Non-standard */ +#define SDHCI_CTRL_VDD_180 0x0008 +#define SDHCI_CTRL_DRV_TYPE_MASK 0x0030 +#define SDHCI_CTRL_DRV_TYPE_B 0x0000 +#define SDHCI_CTRL_DRV_TYPE_A 0x0010 +#define SDHCI_CTRL_DRV_TYPE_C 0x0020 +#define SDHCI_CTRL_DRV_TYPE_D 0x0030 +#define SDHCI_CTRL_EXEC_TUNING 0x0040 +#define SDHCI_CTRL_TUNED_CLK 0x0080 +#define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000 + +/* + * Config to eMMC PHY to prepare for tuning. + * Enable HW DLL and set the TUNING_STEP + */ +#define XENON_SLOT_DLL_CUR_DLY_VAL 0x0150 + +#define XENON_SLOT_OP_STATUS_CTRL 0x0128 +#define XENON_TUN_CONSECUTIVE_TIMES_SHIFT 16 +#define XENON_TUN_CONSECUTIVE_TIMES_MASK 0x7 +#define XENON_TUN_CONSECUTIVE_TIMES 0x4 +#define XENON_TUNING_STEP_SHIFT 12 +#define XENON_TUNING_STEP_MASK 0xF +#define XENON_TUNING_STEP_DIVIDER BIT(6) + +#define XENON_EMMC_PHY_DLL_CONTROL (EMMC_PHY_REG_BASE + 0x14) +#define XENON_EMMC_5_0_PHY_DLL_CONTROL \ + (XENON_EMMC_5_0_PHY_REG_BASE + 0x10) +#define XENON_DLL_ENABLE BIT(31) +#define XENON_DLL_UPDATE_STROBE_5_0 BIT(30) +#define XENON_DLL_REFCLK_SEL BIT(30) +#define XENON_DLL_UPDATE BIT(23) +#define XENON_DLL_PHSEL1_SHIFT 24 +#define XENON_DLL_PHSEL0_SHIFT 16 +#define XENON_DLL_PHASE_MASK 0x3F +#define XENON_DLL_PHASE_90_DEGREE 0x1F +#define XENON_DLL_FAST_LOCK BIT(5) +#define XENON_DLL_GAIN2X BIT(3) +#define XENON_DLL_BYPASS_EN BIT(0) + +#define XENON_SLOT_EXT_PRESENT_STATE 0x014C +#define XENON_DLL_LOCK_STATE 0x1 + /* Hyperion only have one slot 0 */ #define XENON_MMC_SLOT_ID_HYPERION 0 +#define SLOT_MASK(slot) BIT(slot) + +#define XENON_EMMC_PHY_LOGIC_TIMING_ADJUST (EMMC_PHY_REG_BASE + 0x18) +#define XENON_LOGIC_TIMING_VALUE 0x00AA8977 #define MMC_TIMING_LEGACY 0 #define MMC_TIMING_MMC_HS 1 @@ -266,6 +331,176 @@ static int xenon_mmc_start_signal_voltage_switch(struct sdhci_host *host) return ret; } +/* + * Xenon defines different values for HS200 and HS400 + * in Host_Control_2 + */ +static void xenon_set_uhs_signaling(struct sdhci_host *host, + unsigned int timing) +{ + u16 ctrl_2; + + ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); + /* Select Bus Speed Mode for host */ + ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; + if (timing == MMC_TIMING_MMC_HS200) + ctrl_2 |= SDHCI_CTRL_HS200_ONLY; + else if (timing == MMC_TIMING_UHS_SDR104) + ctrl_2 |= SDHCI_CTRL_UHS_SDR104; + else if (timing == MMC_TIMING_UHS_SDR12) + ctrl_2 |= SDHCI_CTRL_UHS_SDR12; + else if (timing == MMC_TIMING_UHS_SDR25) + ctrl_2 |= SDHCI_CTRL_UHS_SDR25; + else if (timing == MMC_TIMING_UHS_SDR50) + ctrl_2 |= SDHCI_CTRL_UHS_SDR50; + else if ((timing == MMC_TIMING_UHS_DDR50) || + (timing == MMC_TIMING_MMC_DDR52)) + ctrl_2 |= SDHCI_CTRL_UHS_DDR50; + else if (timing == MMC_TIMING_MMC_HS400) + ctrl_2 |= SDHCI_CTRL_HS400_ONLY; + sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); +} + +/* + * If eMMC PHY Slow Mode is required in lower speed mode (SDCLK < 55MHz) + * in SDR mode, enable Slow Mode to bypass eMMC PHY. + * SDIO slower SDR mode also requires Slow Mode. + * + * If Slow Mode is enabled, return 0. + * Otherwise, return -EINVAL. + */ +static int xenon_emmc_phy_slow_mode(struct sdhci_host *host, + unsigned char timing) +{ + u32 reg; + int ret = -EINVAL; + + if (host->mmc->tran_speed > 52000000) + return -EINVAL; + + reg = sdhci_readl(host, EMMC_PHY_TIMING_ADJUST); + /* When in slower SDR mode, enable Slow Mode for SDIO */ + switch (timing) { + case MMC_TIMING_LEGACY: + /* + * If Slow Mode is required, enable Slow Mode by default + * in early init phase to avoid any potential issue. + */ + reg |= EMMC_PHY_SLOW_MODE; + ret = 0; + break; + case MMC_TIMING_UHS_SDR25: + case MMC_TIMING_UHS_SDR12: + case MMC_TIMING_SD_HS: + case MMC_TIMING_MMC_HS: + if (IS_SD(host->mmc)) { + reg |= EMMC_PHY_SLOW_MODE; + ret = 0; + break; + } + default: + reg &= ~EMMC_PHY_SLOW_MODE; + ret = -EINVAL; + } + + sdhci_writel(host, reg, EMMC_PHY_TIMING_ADJUST); + return ret; +} + +static void xenon_emmc_phy_disable_data_strobe(struct sdhci_host *host) +{ + u32 reg; + + /* Disable SDHC Data Strobe */ + reg = sdhci_readl(host, SDHC_SLOT_EMMC_CTRL); + reg &= ~ENABLE_DATA_STROBE; + sdhci_writel(host, reg, SDHC_SLOT_EMMC_CTRL); +} + +/* + * Enable eMMC PHY HW DLL + * DLL should be enabled and stable before HS200/SDR104 tuning, + * and before HS400 data strobe setting. + */ +static int xenon_emmc_phy_enable_dll(struct sdhci_host *host) +{ + u32 reg; + u32 timeout; + + if (host->mmc->tran_speed <= 52000000) + return -EINVAL; + + reg = sdhci_readl(host, XENON_EMMC_PHY_DLL_CONTROL); + if (reg & XENON_DLL_ENABLE) + return 0; + + /* Enable DLL */ + reg = sdhci_readl(host, XENON_EMMC_PHY_DLL_CONTROL); + reg |= (XENON_DLL_ENABLE | XENON_DLL_FAST_LOCK); + + /* + * Set Phase as 90 degree, which is most common value. + * Might set another value if necessary. + * The granularity is 1 degree. + */ + reg &= ~((XENON_DLL_PHASE_MASK << XENON_DLL_PHSEL0_SHIFT) | + (XENON_DLL_PHASE_MASK << XENON_DLL_PHSEL1_SHIFT)); + reg |= ((XENON_DLL_PHASE_90_DEGREE << XENON_DLL_PHSEL0_SHIFT) | + (XENON_DLL_PHASE_90_DEGREE << XENON_DLL_PHSEL1_SHIFT)); + + reg &= ~(XENON_DLL_BYPASS_EN | XENON_DLL_REFCLK_SEL); + reg |= XENON_DLL_UPDATE; + sdhci_writel(host, reg, XENON_EMMC_PHY_DLL_CONTROL); + + /* Wait max 32 ms */ + timeout = 32; + while (!(sdhci_readw(host, XENON_SLOT_EXT_PRESENT_STATE) & + XENON_DLL_LOCK_STATE)) { + if (timeout > 32) { + printf("Wait for DLL Lock time-out\n"); + return -ETIMEDOUT; + } + udelay(1000); + timeout++; + } + return 0; +} + +static int xenon_emmc_phy_config_tuning(struct sdhci_host *host) +{ + u32 reg, tuning_step; + int ret; + + if (host->mmc->tran_speed <= 52000000) + return -EINVAL; + + ret = xenon_emmc_phy_enable_dll(host); + if (ret) + return ret; + + /* Achieve TUNING_STEP with HW DLL help */ + reg = sdhci_readl(host, XENON_SLOT_DLL_CUR_DLY_VAL); + tuning_step = reg / XENON_TUNING_STEP_DIVIDER; + if (unlikely(tuning_step > XENON_TUNING_STEP_MASK)) { + dev_warn(mmc_dev(host->mmc), + "HS200 TUNING_STEP %d is larger than MAX value\n", + tuning_step); + tuning_step = XENON_TUNING_STEP_MASK; + } + + /* Set TUNING_STEP for later tuning */ + reg = sdhci_readl(host, XENON_SLOT_OP_STATUS_CTRL); + reg &= ~(XENON_TUN_CONSECUTIVE_TIMES_MASK << + XENON_TUN_CONSECUTIVE_TIMES_SHIFT); + reg |= (XENON_TUN_CONSECUTIVE_TIMES << + XENON_TUN_CONSECUTIVE_TIMES_SHIFT); + reg &= ~(XENON_TUNING_STEP_MASK << XENON_TUNING_STEP_SHIFT); + reg |= (tuning_step << XENON_TUNING_STEP_SHIFT); + sdhci_writel(host, reg, XENON_SLOT_OP_STATUS_CTRL); + + return 0; +} + static void xenon_mmc_phy_set(struct sdhci_host *host) { struct xenon_sdhci_priv *priv = host->mmc->priv; @@ -273,8 +508,8 @@ static void xenon_mmc_phy_set(struct sdhci_host *host) /* Setup pad, set bit[30], bit[28] and bits[26:24] */ var = sdhci_readl(host, EMMC_PHY_PAD_CONTROL); - var |= AUTO_RECEN_CTRL | OEN_QSN | FC_QSP_RECEN | - FC_CMD_RECEN | FC_DQ_RECEN; + var |= OEN_QSN | FC_QSP_RECEN | FC_CMD_RECEN | FC_DQ_RECEN | + FC_ALL_CMOS_RECEIVER; sdhci_writel(host, var, EMMC_PHY_PAD_CONTROL); /* Set CMD and DQ Pull Up */ @@ -284,20 +519,45 @@ static void xenon_mmc_phy_set(struct sdhci_host *host) sdhci_writel(host, var, EMMC_PHY_PAD_CONTROL1); /* - * If timing belongs to high speed, set bit[17] of + * If Timing belongs to high speed, clear bit[17] of * EMMC_PHY_TIMING_ADJUST register */ + var = sdhci_readl(host, EMMC_PHY_TIMING_ADJUST); if ((priv->timing == MMC_TIMING_MMC_HS400) || (priv->timing == MMC_TIMING_MMC_HS200) || + (priv->timing == MMC_TIMING_MMC_DDR52) || (priv->timing == MMC_TIMING_UHS_SDR50) || (priv->timing == MMC_TIMING_UHS_SDR104) || (priv->timing == MMC_TIMING_UHS_DDR50) || - (priv->timing == MMC_TIMING_UHS_SDR25) || - (priv->timing == MMC_TIMING_MMC_DDR52)) { - var = sdhci_readl(host, EMMC_PHY_TIMING_ADJUST); - var |= OUTPUT_QSN_PHASE_SELECT; + (priv->timing == MMC_TIMING_UHS_SDR25)) { + var &= ~OUTPUT_QSN_PHASE_SELECT; sdhci_writel(host, var, EMMC_PHY_TIMING_ADJUST); } + if (priv->timing == MMC_TIMING_LEGACY) { + xenon_emmc_phy_slow_mode(host, priv->timing); + goto phy_init; + } + + /* + * If SDIO card, set SDIO Mode + * Otherwise, clear SDIO Mode + */ + var = sdhci_readl(host, EMMC_PHY_TIMING_ADJUST); + if (IS_SD(host->mmc)) + var |= EMMC_PHY_SDIO_MODE; + else + var &= ~EMMC_PHY_SDIO_MODE; + sdhci_writel(host, var, EMMC_PHY_TIMING_ADJUST); + + /* + * Set preferred ZNR and ZPR value + * The ZNR and ZPR value vary between different boards. + * Define them both in sdhci-xenon-emmc-phy.h. + */ + var = sdhci_readl(host, EMMC_PHY_PAD_CONTROL2); + var &= ~((ZNR_MASK << ZNR_SHIFT) | ZPR_MASK); + var |= ((0xf << ZNR_SHIFT) | 0xf); + sdhci_writel(host, var, EMMC_PHY_PAD_CONTROL2); /* * When setting EMMC_PHY_FUNC_CONTROL register, @@ -308,11 +568,21 @@ static void xenon_mmc_phy_set(struct sdhci_host *host) sdhci_writew(host, var, SDHCI_CLOCK_CONTROL); var = sdhci_readl(host, EMMC_PHY_FUNC_CONTROL); - if (host->mmc->ddr_mode) { - var |= (DQ_DDR_MODE_MASK << DQ_DDR_MODE_SHIFT) | CMD_DDR_MODE; - } else { + switch (priv->timing) { + case MMC_TIMING_MMC_HS400: + var |= (DQ_DDR_MODE_MASK << DQ_DDR_MODE_SHIFT) | + CMD_DDR_MODE; + var &= ~DQ_ASYNC_MODE; + break; + case MMC_TIMING_UHS_DDR50: + case MMC_TIMING_MMC_DDR52: + var |= (DQ_DDR_MODE_MASK << DQ_DDR_MODE_SHIFT) | + CMD_DDR_MODE | DQ_ASYNC_MODE; + break; + default: var &= ~((DQ_DDR_MODE_MASK << DQ_DDR_MODE_SHIFT) | CMD_DDR_MODE); + var |= DQ_ASYNC_MODE; } sdhci_writel(host, var, EMMC_PHY_FUNC_CONTROL); @@ -321,7 +591,26 @@ static void xenon_mmc_phy_set(struct sdhci_host *host) var |= SDHCI_CLOCK_CARD_EN; sdhci_writew(host, var, SDHCI_CLOCK_CONTROL); + udelay(1000); + + /* Quirk, value suggested by hardware team */ + if (priv->timing == MMC_TIMING_MMC_HS400) + /* Hardware team recommend a value for HS400 */ + sdhci_writel(host, XENON_EMMC_PHY_LOGIC_TIMING_ADJUST, + XENON_LOGIC_TIMING_VALUE); + else + xenon_emmc_phy_disable_data_strobe(host); + +phy_init: + + xenon_set_uhs_signaling(host, priv->timing); xenon_mmc_phy_init(host); + + if ((priv->timing == MMC_TIMING_MMC_HS400) || + (priv->timing == MMC_TIMING_MMC_HS200)) { + if (xenon_emmc_phy_config_tuning(host) != 0) + printf("Error, failed to tune MMC PHY\n"); + } } /* Enable/Disable the Auto Clock Gating function of this slot */ @@ -338,8 +627,6 @@ static void xenon_mmc_set_acg(struct sdhci_host *host, bool enable) sdhci_writel(host, var, SDHC_SYS_OP_CTRL); } -#define SLOT_MASK(slot) BIT(slot) - /* Enable specific slot */ static void xenon_mmc_enable_slot(struct sdhci_host *host, u8 slot) { @@ -391,6 +678,7 @@ static int xenon_sdhci_set_ios_post(struct sdhci_host *host) struct xenon_sdhci_priv *priv = host->mmc->priv; uint speed = host->mmc->tran_speed; int pwr_18v = 0; + u32 reg; /* * Signal Voltage Switching is only applicable for Host Controllers @@ -423,12 +711,22 @@ static int xenon_sdhci_set_ios_post(struct sdhci_host *host) /* eMMC */ if (host->mmc->ddr_mode) priv->timing = MMC_TIMING_MMC_DDR52; + else if (speed == 200000000) + priv->timing = MMC_TIMING_MMC_HS200; else if (speed <= 26000000) priv->timing = MMC_TIMING_LEGACY; else priv->timing = MMC_TIMING_MMC_HS; } + if ((priv->timing == MMC_TIMING_MMC_HS400) || + (priv->timing == MMC_TIMING_MMC_HS200) || + (priv->timing == MMC_TIMING_MMC_HS)) { + reg = sdhci_readw(host, SDHCI_HOST_CONTROL2); + reg &= ~SDHCI_CTRL_PRESET_VAL_ENABLE; + sdhci_writew(host, reg, SDHCI_HOST_CONTROL2); + } + /* Re-init the PHY */ xenon_mmc_phy_set(host); @@ -447,6 +745,7 @@ static int xenon_sdhci_probe(struct udevice *dev) struct xenon_sdhci_priv *priv = dev_get_priv(dev); struct sdhci_host *host = dev_get_priv(dev); int ret; + int len; host->mmc = &plat->mmc; host->mmc->priv = host; @@ -500,6 +799,18 @@ static int xenon_sdhci_probe(struct udevice *dev) return -EINVAL; } + /* Support for High Speed modes */ + if (fdt_getprop(gd->fdt_blob, + dev_of_offset(dev), "mmc-hs400-1_8v", &len) != NULL) { + host->host_caps |= (MMC_MODE_HS400 | MMC_MODE_HS200); + sdhci_writeb(host, SDHCI_POWER_180 | + SDHCI_POWER_ON, SDHCI_POWER_CONTROL); + } + if (fdt_getprop(gd->fdt_blob, + dev_of_offset(dev), "mmc-hs200-1_8v", &len) != NULL) { + host->host_caps |= MMC_MODE_HS200; + } + host->ops = &xenon_sdhci_ops; host->max_clk = XENON_MMC_MAX_CLK; -- 2.28.0

3 8