June 2020 - U-Boot

[PATCH 1/4] clk: clk-imx8mm: Add flexspi clock and fix set parent
by Peng Fan 21 Aug '20

21 Aug '20

From: Ye Li <ye.li(a)nxp.com> Add flexspi relevant clocks, and fix set parent clock, so we can assign clocks through DTB Signed-off-by: Ye Li <ye.li(a)nxp.com> Signed-off-by: Peng Fan <peng.fan(a)nxp.com> --- drivers/clk/imx/clk-imx8mm.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c index fc41a028f6..95069e7395 100644 --- a/drivers/clk/imx/clk-imx8mm.c +++ b/drivers/clk/imx/clk-imx8mm.c @@ -118,6 +118,9 @@ static const char *imx8mm_wdog_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_ static const char *imx8mm_usdhc3_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m", "audio_pll2_clk", "sys_pll1_100m", }; +static const char *imx8mm_qspi_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll2_333m", "sys_pll2_500m", + "audio_pll2_out", "sys_pll1_266m", "sys_pll3_out", "sys_pll1_100m", }; + static ulong imx8mm_clk_get_rate(struct clk *clk) { struct clk *c; @@ -190,7 +193,10 @@ static int imx8mm_clk_set_parent(struct clk *clk, struct clk *parent) if (ret) return ret; - return clk_set_parent(c, cp); + ret = clk_set_parent(c, cp); + c->dev->parent = cp->dev; + + return ret; } static struct clk_ops imx8mm_clk_ops = { @@ -369,6 +375,8 @@ static int imx8mm_clk_probe(struct udevice *dev) clk_dm(IMX8MM_CLK_USDHC3, imx8m_clk_composite("usdhc3", imx8mm_usdhc3_sels, base + 0xbc80)); + clk_dm(IMX8MM_CLK_QSPI, + imx8m_clk_composite("qspi", imx8mm_qspi_sels, base + 0xab80)); clk_dm(IMX8MM_CLK_I2C1_ROOT, imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0)); @@ -392,6 +400,8 @@ static int imx8mm_clk_probe(struct udevice *dev) imx_clk_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0)); clk_dm(IMX8MM_CLK_USDHC3_ROOT, imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0)); + clk_dm(IMX8MM_CLK_QSPI_ROOT, + imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0)); /* clks not needed in SPL stage */ #ifndef CONFIG_SPL_BUILD -- 2.16.4

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[PATCH v1 0/3] add elog support for broadcom NS3 soc
by Rayagonda Kokatanur 20 Aug '20

20 Aug '20

This is fifth patch set series prepared on top of fourth patch set ("add optee support for broadcom NS3 soc"). This patch adds support for error logging and corresponding command. Sheetal Tigadoli (1): common: ns3: add error logging support Vladimir Olovyannikov (2): board: ns3: kconfig: extend board kconfig with specific commands cmd: bcm: add broadcom error log setup command board/broadcom/bcmns3/Kconfig | 5 + cmd/Kconfig | 2 + cmd/Makefile | 2 + cmd/bcm/Kconfig | 12 + cmd/bcm/Makefile | 4 + cmd/bcm/elog.h | 64 +++++ cmd/bcm/logsetup.c | 432 ++++++++++++++++++++++++++++++++++ common/Kconfig | 8 + common/Makefile | 1 + common/bcm_elog.c | 49 ++++ common/console.c | 22 ++ configs/bcm_ns3_defconfig | 1 + include/bcm_elog.h | 37 +++ 13 files changed, 639 insertions(+) create mode 100644 cmd/bcm/Kconfig create mode 100644 cmd/bcm/Makefile create mode 100644 cmd/bcm/elog.h create mode 100644 cmd/bcm/logsetup.c create mode 100644 common/bcm_elog.c create mode 100644 include/bcm_elog.h -- 2.17.1

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[PATCH] armv8: MMU: Mark code memory Executable, any other Non-Executable
by marek.bykowski＠gmail.com 19 Aug '20

19 Aug '20

From: Marek Bykowski <marek.bykowski(a)gmail.com> If the location the ARM CPU is accessing is executable (translation table descriptor Execute-Never attribute bit cleared) then the ARM CPU fetches a number of instructions from that location all at the same time. For example, Cortex-A57 can source up to 128 bits per fetch depending on alignment. If the CPU mispredicts to the Execute-Never region, it creates the memory fault but it actually never uses the instructions mispredicted. The CPU branches away elsewhere. So, as long as we program the MMU correctly these mispredictions will only affect the performance. However if we fail programming so and the instruction fetch logic goes mispredict to non-instruction memory it may eventually perturb it, eg. corrupt the FIFO, or the control registers, load the unified cache the data side memory system hits into subsequently. U-Boot adheres into attributing the device regions to Execute-Never but it actually fails doing so for data regions. Data as well as Device Regions should be Execute-Never. This patch enables attributing data memory regions to Non-Executable, and code region to Executable, additionally to Read-Only. Read-Only ensures the code region is only Readable resulting in Instruction Abort, Permission Fault exception on a write. To use the updated attributes the DDR memory of interest should be Non-Executable, it is by default Read-Write Access Permission as well with an example as follows: static struct mm_region axxia_mem_map[] = { { .virt = 0x0UL, /* DDR */ .phys = 0x0UL, .size = 0x400000000ULL, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, { .virt = AXXIA_CCN_512_BASE, .phys = AXXIA_CCN_512_BASE, .size = AXXIA_CCN_512_SIZE, .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, { .virt = AXI_MMAP_BASE, .phys = AXI_MMAP_BASE, .size = AXI_MMAP_SIZE, .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, { .virt = AXI_PERIPH_BASE, .phys = AXI_PERIPH_BASE, .size = AXI_PERIPH_SIZE, .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, { /* List terminator */ 0, } }; add_text_map() routine in cache_v8.c locates then the code region in it and modifies its attributes to Executable, Read-Only. The HW Debugger views the Memory Map set then as: EL2N:0x00000000-0x3FD35FFF NP:0x00000000-0x3FD35FFF Normal RW C S XN EL2N:0x3FD36000-0x3FD86FFF NP:0x3FD36000-0x3FD86FFF Normal RO C S EL2N:0x3FD87000-0x3FFFFFFFF NP:0x3FD87000-0x3FFFFFFFF Normal RW C S XN EL2N:0x400000000-0x3FFFFFFFFF <unmapped> EL2N:0x4000000000-0x403FFFFFFF NP:0x4000000000-0x403FFFFFFF Device-nGnRnE RW NC XN EL2N:0x4040000000-0x7FFFFFFFFF <unmapped> EL2N:0x8000000000-0x803FFFFFFF NP:0x8000000000-0x803FFFFFFF Device-nGnRnE RW NC XN EL2N:0x8040000000-0x807FFFFFFF <unmapped> EL2N:0x8080000000-0x80BFFFFFFF NP:0x8080000000-0x80BFFFFFFF Device-nGnRnE RW NC XN EL2N:0x80C0000000-0xFFFFFFFFFF <unmapped> where: C, NC is Cacheable, Non-Cacheable respectively, S, NS - Shareable and Non-Shareable, XN - Execute-Never, if XN isn't present it is Executable. May be worth to add that Shareability is of no matter to Non-Cacheable as it concerns only the Cacheable Regions. Signed-off-by: Marek Bykowski <marek.bykowski(a)gmail.com> --- arch/arm/cpu/armv8/cache_v8.c | 21 +++++++++++++++++++++ arch/arm/cpu/armv8/u-boot.lds | 6 ++++-- arch/arm/include/asm/armv8/mmu.h | 6 ++++++ arch/arm/lib/sections.c | 1 + include/asm-generic/sections.h | 1 + 5 files changed, 33 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index c1a08fb4ac..cb25fc0c8a 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -11,6 +11,7 @@ #include <cpu_func.h> #include <asm/system.h> #include <asm/armv8/mmu.h> +#include <asm/sections.h> DECLARE_GLOBAL_DATA_PTR; @@ -361,6 +362,24 @@ __weak u64 get_page_table_size(void) return size; } +__weak void add_text_map(void) +{ + if (!(gd->flags & GD_FLG_RELOC)) + return; + + /* Text is always XN=0, read-only region. */ + struct mm_region text = { + .virt = (unsigned long)__image_copy_start, + .phys = (unsigned long)__image_copy_start, + .size = (unsigned long)__text_end - (unsigned long)__image_copy_start, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE | + PTE_BLOCK_AP_RO + }; + + add_map(&text); +} + void setup_pgtables(void) { int i; @@ -378,6 +397,8 @@ void setup_pgtables(void) /* Now add all MMU table entries one after another to the table */ for (i = 0; mem_map[i].size || mem_map[i].attrs; i++) add_map(&mem_map[i]); + + add_text_map(); } static void setup_all_pgtables(void) diff --git a/arch/arm/cpu/armv8/u-boot.lds b/arch/arm/cpu/armv8/u-boot.lds index 2554980595..20f98ae74d 100644 --- a/arch/arm/cpu/armv8/u-boot.lds +++ b/arch/arm/cpu/armv8/u-boot.lds @@ -20,8 +20,8 @@ SECTIONS #endif . = 0x00000000; - . = ALIGN(8); - .text : + /* Align .text to the page size */ + .text ALIGN(0x1000): { *(.__image_copy_start) CPUDIR/start.o (.text*) @@ -39,6 +39,8 @@ SECTIONS .text_rest : { *(.text*) + . = NEXT(0x1000); + KEEP(*(.__text_end)) } #ifdef CONFIG_ARMV8_PSCI diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h index 4a573208df..4bd15c7e08 100644 --- a/arch/arm/include/asm/armv8/mmu.h +++ b/arch/arm/include/asm/armv8/mmu.h @@ -58,6 +58,12 @@ */ #define PTE_BLOCK_MEMTYPE(x) ((x) << 2) #define PTE_BLOCK_NS (1 << 5) +/* + * AP[1] bit is ignored by hardware and is + * treated as if it was One in EL2/EL3 + */ +#define PTE_BLOCK_AP_RO (1 << 7) +#define PTE_BLOCK_AP_RW (0 << 7) #define PTE_BLOCK_NON_SHARE (0 << 8) #define PTE_BLOCK_OUTER_SHARE (2 << 8) #define PTE_BLOCK_INNER_SHARE (3 << 8) diff --git a/arch/arm/lib/sections.c b/arch/arm/lib/sections.c index 3bb2d8468c..a76f2d3049 100644 --- a/arch/arm/lib/sections.c +++ b/arch/arm/lib/sections.c @@ -18,6 +18,7 @@ * aliasing warnings. */ +char __text_end[0] __attribute__((section(".__text_end"))); char __bss_start[0] __attribute__((section(".__bss_start"))); char __bss_end[0] __attribute__((section(".__bss_end"))); char __image_copy_start[0] __attribute__((section(".__image_copy_start"))); diff --git a/include/asm-generic/sections.h b/include/asm-generic/sections.h index 17a31ec788..1487e16432 100644 --- a/include/asm-generic/sections.h +++ b/include/asm-generic/sections.h @@ -70,6 +70,7 @@ extern void _start(void); */ #ifdef CONFIG_ARM +extern char __text_end[]; extern char __bss_start[]; extern char __bss_end[]; extern char __image_copy_start[]; -- 2.21.0.896.g6a6c0f1

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[PATCH] ARM: bootm: take into account gd->ram_top
by Patrick Delaunay 17 Aug '20

17 Aug '20

From: Patrice Chotard <patrice.chotard(a)st.com> If gd->ram_top has been tuned using board_get_usable_ram_top(), it must be taken into account when reserving arch lmb. Signed-off-by: Patrice Chotard <patrice.chotard(a)st.com> Reviewed-by: Patrick DELAUNAY <patrick.delaunay(a)st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay(a)st.com> --- arch/arm/lib/bootm.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c index a135bcfc7b..f4b5ca6de0 100644 --- a/arch/arm/lib/bootm.c +++ b/arch/arm/lib/bootm.c @@ -75,6 +75,9 @@ void arch_lmb_reserve(struct lmb *lmb) gd->bd->bi_dram[bank].size - 1; if (sp > bank_end) continue; + if (bank_end > gd->ram_top) + bank_end = gd->ram_top - 1; + lmb_reserve(lmb, sp, bank_end - sp + 1); break; } -- 2.17.1

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[PATCH v2 0/3] watchdog: K3: Add RTI watchdog support
by Jan Kiszka 17 Aug '20

17 Aug '20

This brings watchdog support for the TI K3 SoCs, derived from the Linux kernel, augmented with firmware loading as needed on the AM65x. Tested on the AM65x EVM and the IOT2050 (also AM65x-based, upstream support will be posted soon). Changes in v2: - keep watchdog powered when handing over to Linux - drop unneeded explicit power-on - account for RTI firmware locking the power domain Jan Jan Kiszka (3): watchdog: Add support for K3 RTI watchdog watchdog: rti_wdt: Add support for loading firmware arm: dts: k3: Add RTI watchdogs arch/arm/dts/k3-am65-mcu.dtsi | 9 ++ arch/arm/dts/k3-j721e-main.dtsi | 18 ++++ drivers/watchdog/Kconfig | 27 ++++++ drivers/watchdog/Makefile | 4 + drivers/watchdog/rti_wdt.c | 147 ++++++++++++++++++++++++++++++++ drivers/watchdog/rti_wdt_fw.S | 20 +++++ 6 files changed, 225 insertions(+) create mode 100644 drivers/watchdog/rti_wdt.c create mode 100644 drivers/watchdog/rti_wdt_fw.S -- 2.26.2

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[PATCH v2 0/2] reset: Add a managed API
by Pratyush Yadav 16 Aug '20

16 Aug '20

Hi, This is the 4th of a few series that are re-rolls of Jean-Jacques' earlier efforts. The goal is to facilitate porting drivers from the Linux kernel. This particular series is about reset controllers. It adds a managed API, close to that of Linux. The main difference is that bulk and reset_ctl are handled with different functions. Changes in v2: - Fix test build failing because of missing function prototypes and includes. - Drop NULL checks from the reset core. For now let drivers handle them. We can always add the checks back if we think they are a better idea. - Rebase on latest master. Jean-Jacques Hiblot (2): drivers: reset: Add a managed API to get reset controllers from the DT test: reset: Add tests for the managed API arch/sandbox/include/asm/reset.h | 3 + drivers/reset/reset-uclass.c | 118 ++++++++++++++++++++++++- drivers/reset/sandbox-reset-test.c | 51 +++++++++-- drivers/reset/sandbox-reset.c | 19 ++++ include/reset.h | 135 ++++++++++++++++++++++++++++- test/dm/reset.c | 60 +++++++++++++ 6 files changed, 375 insertions(+), 11 deletions(-) -- 2.27.0

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[PATCH v2 0/8] regmap: Add managed API, regmap fields, regmap config
by Pratyush Yadav 16 Aug '20

16 Aug '20

Hi, This series is a re-spin of Jean-Jacques' earlier effort [0], the goal of which was to facilitate porting drivers from the Linux kernel. It adds the managed API, using the same API as Linux. It also adds support for regmap fields. Jean-Jacques' series added support for custom regmap read/write callbacks. The design was argued against by Simon [1]. He argued that using the driver model was a better idea instead of the custom functions. That would mean slightly more memory usage and a more involved change. The main aim of adding the custom functions is to support the Cadence Sierra PHY driver from Linux [2]. The driver's custom functions aren't very complicated, so they can be replaced by some simple formatting options. So, add the struct regmap_config which contains fields to alter the behaviour of the regmap. This includes specifying the size of the read/write operations via 'width', specifying the start and size of range from code instead of device tree via 'r_start' and 'r_size', and specifying a left shift of the register offset before access via 'reg_offset_shift'. The driver can't be ported verbatim now, but this allows the changes to be very isolated and minimal. These config options allow us to avoid converting to driver model until we really need it. The patches are based on [3] which fixes a segmentation fault in sandbox which didn't allow the tests to complete. [0] https://patchwork.ozlabs.org/project/uboot/cover/20191105114700.24989-1-jjh… [1] https://patchwork.ozlabs.org/comment/2426186/ [2] https://elixir.bootlin.com/linux/latest/source/drivers/phy/cadence/phy-cade… [3] https://patchwork.ozlabs.org/project/uboot/patch/20200526120557.26240-1-p.y… Changes in v2: - Add comments explaining the need for regmap_field. - Set regmap->width to a default of REGMAP_SIZE_32 in regmap_alloc() to avoid the checks in regmap_{read,write}(). - Use calloc() instead of using malloc() and memset() to initialize a regmap to zero. - Update comments on regmap_{read,write}() and regmap_raw_{read,write}(). - Drop comments explaining two non-existent fields in struct reg_field. - Add a comment with example explaining REG_FIELD(). - Add Simon's Reviewed-by trailers. Jean-Jacques Hiblot (3): regmap: Add devm_regmap_init() regmap: Add support for regmap fields test: dm: Add tests for regmap managed API and regmap fields Pratyush Yadav (5): regmap: zero out the regmap on allocation regmap: Allow specifying read/write width regmap: Allow left shifting register offset before access regmap: Add regmap_init_mem_range() regmap: Allow devices to specify regmap range start and size in config arch/sandbox/dts/test.dts | 13 +++ drivers/core/regmap.c | 163 +++++++++++++++++++++++++++++- include/regmap.h | 205 +++++++++++++++++++++++++++++++++++--- test/dm/regmap.c | 198 ++++++++++++++++++++++++++++++++++++ 4 files changed, 562 insertions(+), 17 deletions(-) -- 2.27.0

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[PATCH v1 0/2] add brcm iproc pcie driver
by Rayagonda Kokatanur 14 Aug '20

14 Aug '20

Add support for Broadcom pcie driver and api to get dma regions. Rayagonda Kokatanur (1): drivers: pci: add api to get dma regions Srinath Mannam (1): drivers: pcie: add Broadcom IPROC PCIe RC driver drivers/pci/Kconfig | 7 + drivers/pci/Makefile | 1 + drivers/pci/pci-uclass.c | 42 ++ drivers/pci/pcie_iproc.c | 1287 ++++++++++++++++++++++++++++++++++++++ include/pci.h | 3 +- 5 files changed, 1339 insertions(+), 1 deletion(-) create mode 100644 drivers/pci/pcie_iproc.c -- 2.17.1

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[PATCH v4 00/12] riscv: Add FPIOA and GPIO support for Kendryte K210
by Sean Anderson 14 Aug '20

14 Aug '20

This patch series adds support for pinmuxing, gpios, and leds on the Kendyte K210. This patch series was previously part of https://patchwork.ozlabs.org/project/uboot/list/?series=161576 This patch series depends on https://patchwork.ozlabs.org/project/uboot/list/?series=178480 Changes in v4: - Add sandbox dt-binding headers to MAINTAINERS - Add test for led behavior - Add test/dm/pinmux.c to patch - Move sandbox_* variables into a priv structure. This resets them to the default state every time we re-probe. - Reformat documentation in dm/pinctrl.h Changes in v3: - Add dt-bindings/pinctrl/sandbox-pinmux.h to patch Changes in v2: - Add test for pinmuxing - Don't clear existing pinctrl settings on probe - Re-order GPIOs to match the defaults more closely - Rebase onto v13 of "riscv: Add Sipeed Maix support" - Rewrite FPIOA driver to use pinmux property - Support muxing the output enable signal for each function in the FPIOA - Support output and input inversion in the pinmux driver - Support pinmux property in pinctrl-generic Sean Anderson (12): pinctrl: Add pinmux property support to pinctrl-generic pinctrl: Reformat documentation in dm/pinctrl.h test: pinmux: Add test for pin muxing pinctrl: Add support for Kendryte K210 FPIOA gpio: sifive: Use generic reg read function gpio: dw: Fix warnings about casting int to pointer gpio: dw: Add a trailing underscore to generated name gpio: dw: Return output value when direction is out led: gpio: Default to using node name if label is absent test: dm: Test for default led naming riscv: Add pinmux and gpio bindings for Kendryte K210 riscv: Add FPIOA and GPIO support for Kendryte K210 MAINTAINERS | 3 + arch/riscv/dts/k210-maix-bit.dts | 104 +++ arch/riscv/dts/k210.dtsi | 12 + arch/sandbox/dts/test.dts | 47 +- board/sipeed/maix/Kconfig | 9 + doc/board/sipeed/maix.rst | 64 +- .../pinctrl/kendryte,k210-fpioa.txt | 102 +++ .../pinctrl/pinctrl-bindings.txt | 65 +- drivers/gpio/dwapb_gpio.c | 33 +- drivers/gpio/sifive-gpio.c | 2 +- drivers/led/led_gpio.c | 7 +- drivers/pinctrl/Kconfig | 1 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/kendryte/Kconfig | 7 + drivers/pinctrl/kendryte/Makefile | 1 + drivers/pinctrl/kendryte/pinctrl.c | 678 ++++++++++++++++++ drivers/pinctrl/kendryte/pinctrl.h | 70 ++ drivers/pinctrl/pinctrl-generic.c | 125 +++- drivers/pinctrl/pinctrl-sandbox.c | 186 +++-- include/dm/pinctrl.h | 360 +++++++--- include/dt-bindings/pinctrl/k210-pinctrl.h | 277 +++++++ include/dt-bindings/pinctrl/sandbox-pinmux.h | 19 + test/dm/Makefile | 3 + test/dm/led.c | 3 +- test/dm/pinmux.c | 57 ++ test/py/tests/test_pinmux.py | 36 +- 26 files changed, 2027 insertions(+), 245 deletions(-) create mode 100644 doc/device-tree-bindings/pinctrl/kendryte,k210-fpioa.txt create mode 100644 drivers/pinctrl/kendryte/Kconfig create mode 100644 drivers/pinctrl/kendryte/Makefile create mode 100644 drivers/pinctrl/kendryte/pinctrl.c create mode 100644 drivers/pinctrl/kendryte/pinctrl.h create mode 100644 include/dt-bindings/pinctrl/k210-pinctrl.h create mode 100644 include/dt-bindings/pinctrl/sandbox-pinmux.h create mode 100644 test/dm/pinmux.c -- 2.26.2

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[PATCH v3 0/6] drivers: Add a framework for MUX drivers
by Pratyush Yadav 06 Aug '20

06 Aug '20

Hi, This series is a re-roll of Jean-Jacques' earlier effort. It adds a new minimalistic subsystem that handles multiplexer controllers. It provides the same API as Linux and mux drivers should be portable with a minimum effort. This series also includes a port of the Linux's mmio-mux driver. This series relies on a series that extends the regmap [0]. [0] https://patchwork.ozlabs.org/project/uboot/list/?series=181623 Changes in v3: - Add a new command called 'mux' that allows listing, selecting, and deselecting muxes on the fly. - Move call to dm_mux_init() to initr_dm_devices(). - Enable mmio operations in sandbox on board_init() to dm_mux_init() can initialize muxes to their idle state and allow the tests to pass. - Add help for CONFIG_MULTIPLEXER. - Change dev_err() in mmio_mux_probe() to log_msg_ret() or log_err(). - Add comments on static functions in mux-class.c - Make mux_uclass_post_probe() static. - Make dm_mux_init() return an integer to signal failure. - Change ifdef of mux-internal.h to _HUX_INTERNAL_H. - Remove unused include from mux-internal.h - Remove comments for non-existent members in struct mux_chip. - Add missing comments for some members in struct mux_control. - Add missing comments for some functions in mux.h - Split up the mux_mmio test into two parts. More would lead to a lot of boilerplate. - Change ut_assertok(IS_ERR(ptr)) to ut_assertok_ptr(ptr). - Fix mis-spellings and capitalize comments. - Rebase on latest master. Changes in v2: - Fixed warning in mux_of_xlate_default() - Improved documentation - Fixed SPL build - insert the mux initialization in init_sequence_r[], just before the console is initialized as its serial port may be muxed - moved the definition of dm_mux_init() in this commit - Call sandbox_set_enable_memio(true) before running the test Jean-Jacques Hiblot (4): drivers: Add a new framework for multiplexer devices dm: board: complete the initialization of the muxes in initr_dm() drivers: mux: mmio-based syscon mux controller test: Add tests for the multiplexer framework Pratyush Yadav (2): cmd: Add a mux command sandbox: Enable memio operations in board_init arch/sandbox/dts/test.dts | 25 +++ board/sandbox/sandbox.c | 2 + cmd/Kconfig | 6 + cmd/Makefile | 1 + cmd/mux.c | 161 ++++++++++++++++ common/board_r.c | 12 ++ configs/sandbox_defconfig | 2 + drivers/Kconfig | 2 + drivers/Makefile | 1 + drivers/mux/Kconfig | 25 +++ drivers/mux/Makefile | 7 + drivers/mux/mmio.c | 143 +++++++++++++++ drivers/mux/mux-uclass.c | 334 ++++++++++++++++++++++++++++++++++ include/dm/uclass-id.h | 1 + include/dt-bindings/mux/mux.h | 17 ++ include/mux-internal.h | 109 +++++++++++ include/mux.h | 159 ++++++++++++++++ test/dm/Makefile | 1 + test/dm/mux-mmio.c | 168 +++++++++++++++++ 19 files changed, 1176 insertions(+) create mode 100644 cmd/mux.c create mode 100644 drivers/mux/Kconfig create mode 100644 drivers/mux/Makefile create mode 100644 drivers/mux/mmio.c create mode 100644 drivers/mux/mux-uclass.c create mode 100644 include/dt-bindings/mux/mux.h create mode 100644 include/mux-internal.h create mode 100644 include/mux.h create mode 100644 test/dm/mux-mmio.c -- 2.27.0

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