June 2020 - U-Boot

[PATCH v2] test/py: test_efi_fit: Update #size-cells to 1
by Bin Meng 29 Jun '20

29 Jun '20

From: Bin Meng <bin.meng(a)windriver.com> test_efi_fit tests fail on RISC-V currently. This is due to the RISC-V arch_fixup_fdt() checks the #size-cells of the root node in order to correctly fix up the reserved memory node. Per the DT binding, the /reserved-memory node requires both <#address-cells> and <#size-cells> and they should use the same values as the root node. For the root node, it's not very useful if <#size-cells> is zero. Update #size-cells to 1 so tests can pass. Signed-off-by: Bin Meng <bin.meng(a)windriver.com> --- Changes in v2: - Update the reset node's <reg> property to contain a size test/py/tests/test_efi_fit.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/test/py/tests/test_efi_fit.py b/test/py/tests/test_efi_fit.py index beaf4a3..06fb151 100644 --- a/test/py/tests/test_efi_fit.py +++ b/test/py/tests/test_efi_fit.py @@ -106,14 +106,14 @@ FDT_DATA = ''' / { #address-cells = <1>; - #size-cells = <0>; + #size-cells = <1>; model = "%(sys-arch)s %(fdt_type)s EFI FIT Boot Test"; compatible = "%(sys-arch)s"; reset@0 { compatible = "%(sys-arch)s,reset"; - reg = <0>; + reg = <0 4>; }; }; ''' -- 2.7.4

2 2

[PATCH] video: rk_vop: Fix wrong bpix for frame buffer
by Jagan Teki 28 Jun '20

28 Jun '20

Video framework would use plat size as a frame buffer pointer in rockchip video drivers. Typical frame buffer pointer would compute based on maximum resolutions supporting followed by bits per pixel value. Right now the value 4 (VIDEO_BPP16) is using on this computation even though the HDMI vop_id assigned as VIDEO_BPP32. This results below synchronous abort while clearing the frame buffer to the background color. "Synchronous Abort" handler, esr 0x96000045 elr: 0000000000236ff0 lr : 0000000000236f74 (reloc) elr: 00000000f6f6eff0 lr : 00000000f6f6ef74 x0 : 00000000f8000000 x1 : 0000000000000000 x2 : 00000000f97a4000 x3 : 00000000ff1a0000 x4 : 00000000ff1a0000 x5 : 0000000000000035 x6 : 000000000000000a x7 : 00000000f4f1fe50 x8 : 0000000000000000 x9 : 0000000000000008 x10: 00000000ffffffd8 x11: 0000000000000006 x12: 000000000001869f x13: 0000000000005dc0 x14: 0000000000000000 x15: 00000000ffffffff x16: 0000000000000001 x17: 0000000000000032 x18: 00000000f4f31dc0 x19: 00000000f4f47160 x20: 00000000f6fb5814 x21: 00000000f4f1feb0 x22: 00000000f6fea748 x23: 00000000f6fea748 x24: 00000000f4f47108 x25: 00000000f4f47110 x26: 00000000f4f46ed0 x27: 00000000f4f47118 x28: 0000000000000002 x29: 00000000f4f1fe50 Reproduced on, Board: roc-rk3399-pc Video Out: HDMI with 3480x2160 resolution. Fix this by using maximum bpix value which is VIDEO_BPP32 to satisfy all vop_id connections. Reported-by: Da Xue <da(a)lessconfused.com> Signed-off-by: Jagan Teki <jagan(a)amarulasolutions.com> --- drivers/video/rockchip/rk_vop.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/video/rockchip/rk_vop.c b/drivers/video/rockchip/rk_vop.c index ff1a80384d..3bae22a5bc 100644 --- a/drivers/video/rockchip/rk_vop.c +++ b/drivers/video/rockchip/rk_vop.c @@ -425,7 +425,7 @@ int rk_vop_bind(struct udevice *dev) { struct video_uc_platdata *plat = dev_get_uclass_platdata(dev); - plat->size = 4 * (CONFIG_VIDEO_ROCKCHIP_MAX_XRES * + plat->size = VIDEO_BPP32 * (CONFIG_VIDEO_ROCKCHIP_MAX_XRES * CONFIG_VIDEO_ROCKCHIP_MAX_YRES); return 0; -- 2.25.1

2 3

[PATCH 0/4] Convert LaCie boards to use DM drivers
by Simon Guinot 28 Jun '20

28 Jun '20

This patch converts the following LaCie boards (Marvell Kirkwood-based) to use DM drivers: - d2 Network v2 - Internet Space v2 - 2Big Network v2 - Network Space v2 - Network Space Lite v2 - Network Space Max v2 - Network Space Mini v2 Simon Guinot (4): arm: kirkwood: convert LaCie boards to DM_SPI_FLASH arm: kirkwood: switch LaCie boards to sata_mv driver arm: kirkwood: enable DM_USB for LaCie board arm: kirkwood: enable DM_ETH for LaCie board arch/arm/dts/kirkwood-netxbig.dtsi | 4 ++++ arch/arm/dts/kirkwood-ns2-common.dtsi | 4 ++++ board/LaCie/net2big_v2/net2big_v2.c | 2 +- board/LaCie/netspace_v2/netspace_v2.c | 4 ++-- configs/d2net_v2_defconfig | 13 +++++++++---- configs/inetspace_v2_defconfig | 13 +++++++++---- configs/net2big_v2_defconfig | 13 +++++++++---- configs/netspace_lite_v2_defconfig | 14 ++++++++++---- configs/netspace_max_v2_defconfig | 14 ++++++++++---- configs/netspace_mini_v2_defconfig | 12 ++++++++---- configs/netspace_v2_defconfig | 13 +++++++++---- include/configs/lacie_kw.h | 19 +++++++++---------- 12 files changed, 84 insertions(+), 41 deletions(-) -- 2.27.0

2 6

[PATCH v7 0/4] update clock handler and proper cpu features
by Sagar Shrikant Kadam 28 Jun '20

28 Jun '20

U-Boot cmd "cpu detail" shows inconsistent CPU features. The current "cpu detail" sometimes shows "Microcode" as a feature, which is not the case with FU540-C000 on HiFive Unleashed board. Patch 1: add cpu node aliases. Patch 2: Init CPU information to avoid inconsistent cpu information. Patch 3: Correctly parse and update mmu-type. Patch 4: Set L1 Cache feature if either i-cache or d-cache is present I have picked few dependent patches from Sean's series from here [1] and [2]. These have applied on mainline U-Boot commit eae62ae8de18 ("Merge tag 'efi-2020-07-rc6' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi") Patch history: ============================================= v7: -Included the nits suggestion. V6: -Rebase series with master -Split patch 2 from v5 as suggested i.e init cpu feature in cpu-class.c as one patch and handle mmu-type check into another. -Updated Reviewed-by tags V5: -Addressed review comments on v4. 1. Removed patch 1 which was for debug message. 2. Updated commit logs with proper information on number of cpu's 3. Additionally used d-cache to set the L1 feature bit. V4: 1. Rebased the series to mainline commit. 2. Updated dependency list as few patches are now merged. 3. Added U-Boot log of the flow i.e fsbl + fw_payload.bin (Opensbi+U-Boot) V3: 1. Included the cosmetic change as suggested s/L1 feature/L1 cache feature/ 2. Added Reviewed-By tags V2: 1. Incorporate review comments from Bin and Sean Anderson. and dropped 2nd patch as similar work was already done in [1] and [2] 2 Add cpu node aliases to display cpu node's in sequence. 3. Add fix to show mmu as available cpu feature. 4. Check and append L1 cache feature. V1: Base version Thanks to Vincent Chen <vincent.chen(a)sifive.com> for testing the V1 version of this series. [1] https://patchwork.ozlabs.org/patch/1316066 [2] https://patchwork.ozlabs.org/patch/1316067 All these together is available here: https://github.com/sagsifive/u-boot/commits/dev/sagark/clk-v7 U-Boot log: =========================================================== U-Boot SPL 2020.07-rc5-00063-g213d48a (Jun 28 2020 - 07:19:43 -0700) Trying to boot from MMC1 U-Boot 2020.07-rc5-00063-g213d48a (Jun 28 2020 - 07:19:43 -0700) CPU: rv64imafdc Model: SiFive HiFive Unleashed A00 DRAM: 8 GiB MMC: spi@10050000:mmc@0: 0 In: serial@10010000 Out: serial@10010000 Err: serial@10010000 Net: eth0: ethernet@10090000 Hit any key to stop autoboot: 0 => => cpu list 1: cpu@1 rv64imafdc 2: cpu@2 rv64imafdc 3: cpu@3 rv64imafdc 4: cpu@4 rv64imafdc => cpu detail 1: cpu@1 rv64imafdc ID = 1, freq = 999.100 MHz: L1 cache, MMU 2: cpu@2 rv64imafdc ID = 2, freq = 999.100 MHz: L1 cache, MMU 3: cpu@3 rv64imafdc ID = 3, freq = 999.100 MHz: L1 cache, MMU 4: cpu@4 rv64imafdc ID = 4, freq = 999.100 MHz: L1 cache, MMU => Sagar Shrikant Kadam (4): riscv: dts: hifive-unleashed-a00: add cpu aliases uclass: cpu: fix to display proper CPU features riscv: cpu: correctly handle the setting of CPU_FEAT_MMU bit riscv: cpu: check and append L1 cache to cpu features arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi | 4 ++++ drivers/cpu/cpu-uclass.c | 3 +++ drivers/cpu/riscv_cpu.c | 17 +++++++++++++---- 3 files changed, 20 insertions(+), 4 deletions(-) -- 2.7.4

1 4

rockchip: correctly set vop0 or vop1
by Patrick Wildt 28 Jun '20

28 Jun '20

The EDP_LCDC_SEL bit has to be set correctly to select vop0 or vop1, but so far we have set it in both conditions, which is not correct. Can someone verify this is the correct way round? vop1 -> set, vop0 -> clear? Signed-off-by: Patrick Wildt <patrick(a)blueri.se> diff --git a/drivers/video/rockchip/rk_edp.c b/drivers/video/rockchip/rk_edp.c index 92188be9275..000bd481408 100644 --- a/drivers/video/rockchip/rk_edp.c +++ b/drivers/video/rockchip/rk_edp.c @@ -1062,7 +1062,8 @@ static int rk_edp_probe(struct udevice *dev) rk_setreg(&priv->grf->soc_con12, 1 << 4); /* select epd signal from vop0 or vop1 */ - rk_setreg(&priv->grf->soc_con6, (vop_id == 1) ? (1 << 5) : (1 << 5)); + rk_clrsetreg(&priv->grf->soc_con6, (1 << 5), + (vop_id == 1) ? (1 << 5) : (0 << 5)); rockchip_edp_wait_hpd(priv);

4 7

[PATCH] test/py: test_efi_fit: Update #size-cells to 1
by Bin Meng 28 Jun '20

28 Jun '20

From: Bin Meng <bin.meng(a)windriver.com> test_efi_fit tests fail on RISC-V currently. This is due to the RISC-V arch_fixup_fdt() checks the #size-cells of the root node in order to correctly fix up the reserved memory node. Update #size-cells to 1 so tests can pass. Signed-off-by: Bin Meng <bin.meng(a)windriver.com> --- test/py/tests/test_efi_fit.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/test/py/tests/test_efi_fit.py b/test/py/tests/test_efi_fit.py index beaf4a3..3616e99 100644 --- a/test/py/tests/test_efi_fit.py +++ b/test/py/tests/test_efi_fit.py @@ -106,7 +106,7 @@ FDT_DATA = ''' / { #address-cells = <1>; - #size-cells = <0>; + #size-cells = <1>; model = "%(sys-arch)s %(fdt_type)s EFI FIT Boot Test"; compatible = "%(sys-arch)s"; -- 2.7.4

2 2

[PATCH v4 0/6] crypto/fsl: add RNG support
by Michael Walle 27 Jun '20

27 Jun '20

First, improve the compatibility on newer Era CAAMs. These introduced new version registers. Secondly, add RNG support for the CAAM. This way we get random number generator support for EFI for free and KASLR will work with ARM64 kernels booted with bootefi. Changes since v3: - use private data instead of platform data in RNG driver, thanks Heinrich - align end address of any invalidate/flush_dcache_range(), thanks Heinrich - because we do the alignment ourself, use memalign() again (instead of malloc_cache_aligned()) Changes since v2: - fix descriptor size of the deinstantiate descriptor - use malloc_cache_aligned() instead of memalign(ARCH_DMA_MINALIGN..) - don't check the RDSTA_PR() bit - fix memcpy() length - flush the dcache where the rng job description resides Changes since v1: - instantiate RNG with prediction resistance - add annotation for caam_get_era() - fix all prints to match u-boots status lines - remove superfluous #ifdef CONFIG_DM_RNG - changed kconfig help text Michael Walle (6): crypto/fsl: make SEC%u status line consistent crypto/fsl: export caam_get_era() crypto/fsl: support newer SEC modules crypto/fsl: don't regenerate secure keys crypto/fsl: instantiate the RNG with prediciton resistance crypto/fsl: add RNG support drivers/crypto/fsl/Kconfig | 14 +++++ drivers/crypto/fsl/Makefile | 1 + drivers/crypto/fsl/desc.h | 2 + drivers/crypto/fsl/jobdesc.c | 26 +++++++- drivers/crypto/fsl/jobdesc.h | 7 ++- drivers/crypto/fsl/jr.c | 111 +++++++++++++++++++++++++++++------ drivers/crypto/fsl/rng.c | 88 +++++++++++++++++++++++++++ drivers/crypto/fsl/sec.c | 10 +++- include/fsl_sec.h | 61 +++++++++++++++---- 9 files changed, 285 insertions(+), 35 deletions(-) create mode 100644 drivers/crypto/fsl/rng.c -- 2.20.1

2 7

[PATCH v3 0/6] crypto/fsl: add RNG support
by Michael Walle 27 Jun '20

27 Jun '20

First, improve the compatibility on newer Era CAAMs. These introduced new version registers. Secondly, add RNG support for the CAAM. This way we get random number generator support for EFI for free and KASLR will work with ARM64 kernels booted with bootefi. Changes since v2: - fix descriptor size of the deinstantiate descriptor - use malloc_cache_aligned() instead of memalign(ARCH_DMA_MINALIGN..) - don't check the RDSTA_PR() bit - fix memcpy() length - flush the dcache where the rng job description resides Changes since v1: - instantiate RNG with prediction resistance - add annotation for caam_get_era() - fix all prints to match u-boots status lines - remove superfluous #ifdef CONFIG_DM_RNG - changed kconfig help text Michael Walle (6): crypto/fsl: make SEC%u status line consistent crypto/fsl: export caam_get_era() crypto/fsl: support newer SEC modules crypto/fsl: don't regenerate secure keys crypto/fsl: instantiate the RNG with prediciton resistance crypto/fsl: add RNG support drivers/crypto/fsl/Kconfig | 14 +++++ drivers/crypto/fsl/Makefile | 1 + drivers/crypto/fsl/desc.h | 2 + drivers/crypto/fsl/jobdesc.c | 26 ++++++++- drivers/crypto/fsl/jobdesc.h | 7 ++- drivers/crypto/fsl/jr.c | 110 +++++++++++++++++++++++++++++------ drivers/crypto/fsl/rng.c | 86 +++++++++++++++++++++++++++ drivers/crypto/fsl/sec.c | 10 +++- include/fsl_sec.h | 61 +++++++++++++++---- 9 files changed, 282 insertions(+), 35 deletions(-) create mode 100644 drivers/crypto/fsl/rng.c -- 2.20.1

2 15

[PATCH 0/2] v2: rr3188: change APP to 600MHz and enable bwadj for DPLL
by Alexander Kochetkov 27 Jun '20

27 Jun '20

Hello! Here are two patches I found usefull for rk3188. Changes in v2: Add u-boot(a)lists.denx.de as addressee. Alexander Kochetkov (2): rockchip: clk: rk3188: change APLL to safe 600MHz rockchip: clk: rk3188: enable bwadj for rk3188 DPLL drivers/clk/rockchip/clk_rk3188.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) -- 2.17.1

2 5

[PATCH 0/3] rockchip: Add Radxa Rock Pi N8 support
by Jagan Teki 27 Jun '20

27 Jun '20

Rock Pi N8 is a Rockchip RK3288 based SBC, which has - VMARC RK3288 SOM (as per SMARC standard) from Vamrs. - Compatible carrier board from Radxa. VMARC RK3288 SOM need to mount on top of dalang carrier board for making Rock PI N8 SBC. All these respective dts patches are in Linux mainling list. N8 board support TPL boot flow. Any inputs? Jagan. Jagan Teki (3): ARM: dts: rockchip: radxa-dalang: Update sdmmc properties ARM: dts: rockchip: Add VMARC RK3288 SOM initial support ARM: dts: rockchip: Add Radxa Rock Pi N8 initial support arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3288-rock-pi-n8-u-boot.dtsi | 33 ++ arch/arm/dts/rk3288-rock-pi-n8.dts | 17 ++ arch/arm/dts/rk3288-vmarc-som.dtsi | 289 ++++++++++++++++++ arch/arm/dts/rk3399pro-vmarc-som.dtsi | 5 + .../dts/rockchip-radxa-dalang-carrier.dtsi | 2 - board/rockchip/evb_rk3288/MAINTAINERS | 6 + configs/rock-pi-n8-rk3288_defconfig | 66 ++++ 8 files changed, 417 insertions(+), 2 deletions(-) create mode 100644 arch/arm/dts/rk3288-rock-pi-n8-u-boot.dtsi create mode 100644 arch/arm/dts/rk3288-rock-pi-n8.dts create mode 100644 arch/arm/dts/rk3288-vmarc-som.dtsi create mode 100644 configs/rock-pi-n8-rk3288_defconfig -- 2.25.1

2 6