June 2020 - U-Boot

Bug: qemu_arm64: Cannot access the second flash bank
by Robin Randhawa 13 Sep '21

13 Sep '21

Hi folks. [CC'ing some hopefully relevant folks]. As of: commit 0ba41ce1b7816c229cc19e0621148b98f990cb68 libfdt: return correct value if #size-cells property is not present .. accesses to the second flash bank on the qemu_arm64 virtual board appear broken. To demonstrate, consider that the physical memory map for the 2 flash banks is: Bank 1: 0x0000_0000 - 0x03FC_0000 Bank 2: 0x0400_0000 - 0x7FC0_0000 Now, consider the abbreviated output of the flinfo command pre and post the above commit: Pre: === => flinfo Bank # 1: CFI conformant flash (32 x 16) Size: 64 MB in 256 Sectors Intel Extended command set, Manufacturer ID: 0x89, Device ID: 0x0018 Erase timeout: 16384 ms, write timeout: 3 ms Buffer write timeout: 3 ms, buffer size: 2048 bytes Sector Start Addresses: 00000000 RO 00040000 RO 00080000 RO 000C0000 00100000 00140000 00180000 001C0000 00200000 00240000 . . 03E80000 03EC0000 03F00000 03F40000 03F80000 03FC0000 Bank # 2: CFI conformant flash (32 x 16) Size: 64 MB in 256 Sectors Intel Extended command set, Manufacturer ID: 0x89, Device ID: 0x0018 Erase timeout: 16384 ms, write timeout: 3 ms Buffer write timeout: 3 ms, buffer size: 2048 bytes Sector Start Addresses: 04000000 RO 04040000 04080000 040C0000 04100000 04140000 04180000 041C0000 04200000 04240000 . . 07E80000 07EC0000 07F00000 07F40000 07F80000 07FC0000 Post: ==== => flinfo Bank # 1: CFI conformant flash (32 x 16) Size: 64 MB in 256 Sectors Intel Extended command set, Manufacturer ID: 0x89, Device ID: 0x0018 Erase timeout: 16384 ms, write timeout: 3 ms Buffer write timeout: 3 ms, buffer size: 2048 bytes Sector Start Addresses: 00000000 RO 00040000 RO 00080000 RO 000C0000 00100000 00140000 00180000 001C0000 00200000 00240000 . . 03E80000 03EC0000 03F00000 03F40000 03F80000 03FC0000 Bank # 2: CFI conformant flash (32 x 16) Size: 64 MB in 256 Sectors Intel Extended command set, Manufacturer ID: 0x89, Device ID: 0x0018 Erase timeout: 16384 ms, write timeout: 3 ms Buffer write timeout: 3 ms, buffer size: 2048 bytes Sector Start Addresses: 400000000000000 400000000040000 400000000080000 4000000000C0000 400000000100000 400000000140000 400000000180000 4000000001C0000 400000000200000 400000000240000 . . 400000003E80000 400000003EC0000 400000003F00000 40 0000003F40000 400000003F80000 400000003FC0000 As a result, the second bank is unusable for environment stores (CONFIG_ENV_ADDR is 0x4000000): => saveenv Saving Environment to Flash... Error: start and/or end address not on sector boundary Error: start and/or end address not on sector boundary Failed (1) Rewinding the u-boot repo to before this commit fixes the problem. Manually (uncleanly) reverting the commit and it's dependent commits fixes the problem. Here are the HEAD commits from the relevant repos that I used for the data above: qemu: commit dd5b0f95490883cd8bc7d070db8de70d5c979cbc u-boot: commit 6cb87cbb1475f668689f95911d1521ee6ba7f55c Here is the qemu invocation I used: $ dd if=/dev/zero of=./flash0-with-uboot.img bs=1M count=64 && dd if=/path/to/u-boot.bin of=./flash0-with-uboot.img conv=notrunc $ qemu-system-aarch64 -M virt -cpu cortex-a53 -m 1024M -nographic -drive if=pflash,format=raw,index=0,file=flash0-with-uboot.img -drive if=pflash,format=raw,index=1,file=flash1.img I'm happy to help test any fixes if and as needed. Cheers, Robin

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[u-boot PATCH] arm: mach-k3: am6_init: Prioritize MSMC traffic over DDR in NAVSS Northbridge
by Roger Quadros 08 Sep '21

08 Sep '21

NB0 is bridge to SRAM and NB1 is bridge to DDR. To ensure that SRAM transfers are not stalled due to delays during DDR refreshes, SRAM traffic should be higher priority (threadmap=2) than DDR traffic (threadmap=0). This patch does just that. This is required to fix ICSSG TX lock-ups due to delays in MSMC transfers due to incorrect Northbridge configuration. Signed-off-by: Roger Quadros <rogerq(a)ti.com> Acked-by: Andrew F. Davis <afd(a)ti.com> Acked-by: Tomi Valkeinen <tomi.valkeinen(a)ti.com> Acked-by: Benoit Parrot <bparrot(a)ti.com> --- arch/arm/mach-k3/am6_init.c | 14 ++++++++++++++ arch/arm/mach-k3/include/mach/am6_hardware.h | 7 +++++++ 2 files changed, 21 insertions(+) diff --git a/arch/arm/mach-k3/am6_init.c b/arch/arm/mach-k3/am6_init.c index 8d107b870b..9379b95bdb 100644 --- a/arch/arm/mach-k3/am6_init.c +++ b/arch/arm/mach-k3/am6_init.c @@ -86,6 +86,18 @@ static void store_boot_index_from_rom(void) bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX); } +static void setup_am654_navss_northbridge(void) +{ + /* + * NB0 is bridge to SRAM and NB1 is bridge to DDR. + * To ensure that SRAM transfers are not stalled due to + * delays during DDR refreshes, SRAM traffic should be higher + * priority (threadmap=2) than DDR traffic (threadmap=0). + */ + writel(0x2, NAVSS0_NBSS_NB0_CFG_BASE + NAVSS_NBSS_THREADMAP); + writel(0x0, NAVSS0_NBSS_NB1_CFG_BASE + NAVSS_NBSS_THREADMAP); +} + void board_init_f(ulong dummy) { #if defined(CONFIG_K3_LOAD_SYSFW) || defined(CONFIG_K3_AM654_DDRSS) @@ -101,6 +113,8 @@ void board_init_f(ulong dummy) /* Make all control module registers accessible */ ctrl_mmr_unlock(); + setup_am654_navss_northbridge(); + #ifdef CONFIG_CPU_V7R disable_linefill_optimization(); setup_k3_mpu_regions(); diff --git a/arch/arm/mach-k3/include/mach/am6_hardware.h b/arch/arm/mach-k3/include/mach/am6_hardware.h index 6df7631545..45a5b31c52 100644 --- a/arch/arm/mach-k3/include/mach/am6_hardware.h +++ b/arch/arm/mach-k3/include/mach/am6_hardware.h @@ -47,4 +47,11 @@ /* MCU SCRATCHPAD usage */ #define TI_SRAM_SCRATCH_BOARD_EEPROM_START CONFIG_SYS_K3_MCU_SCRATCHPAD_BASE +/* NAVSS Northbridge config */ +#define NAVSS0_NBSS_NB0_CFG_BASE 0x03802000 +#define NAVSS0_NBSS_NB1_CFG_BASE 0x03803000 + +#define NAVSS_NBSS_PID 0x0 +#define NAVSS_NBSS_THREADMAP 0x10 + #endif /* __ASM_ARCH_AM6_HARDWARE_H */ -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki

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[U-Boot] [PATCH v3 00/20] Bring NAND support to Nintendo NES Classic
by Miquel Raynal 07 Jul '21

07 Jul '21

Hello, This series first adds fixes and enhancements to sunxi NAND drivers (SPL and U-Boot). Once this is done, the SPL NAND driver is converted to use PIO instead of DMA with the goal to support all SoCs with this IP without the need for DMA-related code. Finally, NAND support is added to Nintendo NES Classic through Kconfig and DT additions. Thanks, Miquèl Changes since v2: ================= - Added Boris and Maxime Acked-by tags. - Removed extra space in nand_reset_column() - Fixed the useless wait period on failure in nand_change_column(). - Changed the title "sunxi: allow NAND support to be compiled for..." (removed the "in SPL" precision which is wrong). - Enbraced the deassertion of the reset line by #if statements about the SoCs in use. Wolfgang Denk made a comment on my proposal but I could not find a better solution, so I kept it for now. - s/alwinner,[pin,functions]/[pin,functions]/ in the DT. - Change Alwinner-specific parts in the SPL to generic sentences. Changes since v1: ================= All: ---- - Enhance all commit messages. - Rebased on top of master branch (I should have done that earlier but I forgot I was on an old revision). Fix binman_sym output check --------------------------- - SPL seems to be broken for a few weeks when using raw NAND, fix it by changing the error condition. Fix strength ------------ - Add comment explaining the added line and moved the line for clarification on why it is needed. - Add forgotten Boris' Suggested-by tag. Fix second case of modulo by zero error ---------------------------------------- - Added a reference to the first occurence of this issue. Allow SPL to be compiled for sun8i platforms -------------------------------------------- - This commit is not about compiling the SPL, but the NAND support in the SPL, as corrected by Maxime. Enhancements and cleaning ------------------------- - Patch split into several logical chunks, as requested. - Removed useless udelay(1), that was added for debugging purpose. - Introduced the nand_exec_cmd() helper to mutualize code one step further. - Add an udelay(1) after changing the column to respect the minimum tCCS delay (Change Column Setup time). - Canceled moving to global scope the ecc_strength array. Use PIO instead of DMA ---------------------- - Change commit message/title. - Cancel removing NFC related definitions: they can be useful as the this IP is quite under-documented. - Merge nand_reset_column and nand_change_column (in another patch). - Moved the copy of the data after the check of the ECC status. - ECC chunks are read manually, return if the first chunk is empty only (needed for configuration research), otherwise it should not be treated as an error. Add NAND node to sun8i ---------------------- - U-Boot master branch already has this node, remove the patch. Enable NAND on NES classic -------------------------- - Change the DT cells size from 2 to 1. Add NAND support for NES classic -------------------------------- - Split in several patches, moving SPL_NAND_SUPPORT and NAND_SUNXI out of the defconfig files (NES and CHIP pro) to be automatically selected depending on NAND_SUNXI and ARCH_SUNXI. - Moved the NAND parameters to Kconfig (only for SUNXI because the tool did not work as expected, maybe due to some definitions that are not "numbers" but multiplications and sometimes use other definitions (NAND page size, 2K_SZ, etc). Miquel Raynal (20): spl: fix binman_sym output check mtd: nand: sunxi: fix ECC strength choice spl: nand: sunxi: fix second case of modulo by zero error spl: nand: sunxi: fix typo on register name spl: nand: sunxi: introduce the nand_wait_int() helper spl: nand: sunxi: introduce the nand_wait_cmd_fifo_empty() helper spl: nand: sunxi: add missing status clear spl: nand: sunxi: create an helper to handle command execution spl: nand: sunxi: ensure enough time has passed after changing the column spl: nand: sunxi: make the reset column helper more generic sunxi: spl: deassert the NAND controller reset line spl: nand: sunxi: declare the ecc_bytes array globally spl: nand: sunxi: use PIO instead of DMA sunxi: spl: remove DMA related settings of the NAND controller sunxi: allow NAND support to be compiled for sun8i platforms sunxi: dts: enable NAND on NES classic sunxi: automatically select SPL_NAND_SUPPORT in Kconfig sunxi: make NAND_SUNXI use ARCH_SUNXI as default in Kconfig sunxi: move the NAND parameters to Kconfig configs: add NAND support for NES Classic arch/arm/dts/sun8i-a23-a33.dtsi | 17 ++ .../dts/sun8i-r16-nintendo-nes-classic-edition.dts | 14 ++ arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 6 + board/sunxi/board.c | 7 +- common/spl/spl.c | 10 +- configs/CHIP_pro_defconfig | 6 +- configs/Nintendo_NES_Classic_Edition_defconfig | 4 + drivers/mtd/nand/Kconfig | 26 ++- drivers/mtd/nand/sunxi_nand.c | 8 +- drivers/mtd/nand/sunxi_nand_spl.c | 242 ++++++++++----------- 10 files changed, 208 insertions(+), 132 deletions(-) -- 2.14.1

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imx8qxp mek: Booting mainline kernel with mainline U-Boot
by Fabio Estevam 12 Jun '21

12 Jun '21

Hi Peng, Have you managed to boot a mainline kernel with mainline U-Boot on a imx8qxp mek? Here is what I get: U-Boot SPL 2020.01-00369-ge80a8b0222-dirty (Jan 13 2020 - 12:30:21 -0300) Normal Boot WDT: Not found! Trying to boot from MMC2_2 Load image from MMC/SD 0x46800 U-Boot 2020.01-00369-ge80a8b0222-dirty (Jan 13 2020 - 12:30:21 -0300) CPU: NXP i.MX8QXP RevB A35 at 1200 MHz at 32C Model: Freescale i.MX8QXP MEK Board: iMX8QXP MEK Build: SCFW 550f3079, SECO-FW d7523fe8, ATF 70fa7bc Boot: SD1 DRAM: 3 GiB Failed to enable ipg clk MMC: FSL_SDHC: 0, FSL_SDHC: 1 Loading Environment from MMC... OK In: serial@5a060000 Out: serial@5a060000 Err: serial@5a060000 Net: Failed to enable ipg clk Warning: ethernet@5b040000 (eth0) using random MAC address - e2:9c:db:94:fc:d5 eth0: ethernet@5b040000 Hit any key to stop autoboot: 0 switch to partitions #0, OK mmc1 is current device 26221056 bytes read in 1134 ms (22.1 MiB/s) Booting from mmc ... 13953 bytes read in 14 ms (972.7 KiB/s) ## Flattened Device Tree blob at 83000000 Booting using the fdt blob at 0x83000000 Using Device Tree in place at 0000000083000000, end 0000000083006680 Starting kernel ... [It hangs here] Booting a NXP kernel also did not work. Any ideas? Regards, Fabio Estevam

8 17

[PATCH v2 0/3] Add reboot mode support
by Nandor Han 06 May '21

06 May '21

Description ----------- Add support for reboot-mode configuration using GPIOs and RTC SRAM as back-end. Testing ------- Tested on a Zynq based board where device tree was configured to contain the reboot-mode configuration: &amba { status = "okay"; reboot-mode-gpio { compatible = "reboot-mode-gpio"; gpios = <&gpio0 47 GPIO_ACTIVE_LOW>; mode-test = <0x1>; }; reboot-mode-rtc { compatible = "reboot-mode-rtc"; rtc = <&rtc_0>; reg = <0x14 4>; mode-test = <0x21969147>; }; }; In addition to this and not part of this patchset is a change to board.c where GPIO or RTC SRAM backed is selected dynamically at runtime. 1. Test that the reboot mode configured in user-space is read in U-Boot and environment configured: PASS Userspace ~ # reboot test .... [ 177.335936] reboot: Restarting system with command 'test' U-Boot SPL 2019.01 (Mar 29 2019 - 10:44:22 +0000) ... U-Boot> print reboot-mode reboot-mode=test 2. Reset the system using the reset command and stop in U-Boot. 3. Verify that reboot-mode env variable is not configured anymore: PASS U-Boot> print reboot-mode ## Error: "reboot-mode" not defined 4. Toggle the GPIO configured for test mode to active and reset the system with command reset. 5. Stop in U-Boot and check that reboot-mode env variable is configured:PASS U-Boot> print reboot-mode reboot-mode=test Changes since v1: ---------------- - rebased Nandor Han (3): reboot-mode: add support for reboot mode control reboot-mode: read the boot mode from GPIOs status reboot-mode: read the boot mode from RTC memory .../reboot-mode/reboot-mode-gpio.txt | 20 +++ .../reboot-mode/reboot-mode-rtc.txt | 22 +++ drivers/Kconfig | 2 + drivers/Makefile | 1 + drivers/reboot-mode/Kconfig | 36 +++++ drivers/reboot-mode/Makefile | 9 ++ drivers/reboot-mode/reboot-mode-gpio.c | 125 +++++++++++++++++ drivers/reboot-mode/reboot-mode-rtc.c | 132 ++++++++++++++++++ drivers/reboot-mode/reboot-mode-uclass.c | 132 ++++++++++++++++++ include/dm/uclass-id.h | 1 + include/reboot-mode/reboot-mode-gpio.h | 32 +++++ include/reboot-mode/reboot-mode-rtc.h | 16 +++ include/reboot-mode/reboot-mode.h | 56 ++++++++ 13 files changed, 584 insertions(+) create mode 100644 doc/device-tree-bindings/reboot-mode/reboot-mode-gpio.txt create mode 100644 doc/device-tree-bindings/reboot-mode/reboot-mode-rtc.txt create mode 100644 drivers/reboot-mode/Kconfig create mode 100644 drivers/reboot-mode/Makefile create mode 100644 drivers/reboot-mode/reboot-mode-gpio.c create mode 100644 drivers/reboot-mode/reboot-mode-rtc.c create mode 100644 drivers/reboot-mode/reboot-mode-uclass.c create mode 100644 include/reboot-mode/reboot-mode-gpio.h create mode 100644 include/reboot-mode/reboot-mode-rtc.h create mode 100644 include/reboot-mode/reboot-mode.h -- 2.24.1

2 9

[PATCH 0/8] net: several updates to support i.MX
by Peng Fan 05 May '21

05 May '21

The patchset is to upstream NXP downstream network patches that runs on i.MX platforms, including eqos update, sharded mdio support, mac addr accessing and etc. Fugang Duan (3): net: phy: realtek: add rx delay support for RTL8211F net: dwc_eth_qos: add dwc eqos for imx support net: eqos: implement callbaks to get interface and set txclk rate Peng Fan (1): net: eth-uclass: add return value check Ye Li (4): net: Add eth phy generic driver for shared MDIO net: Update eQos driver and FEC driver to use eth phy interfaces fec: Move imx_get_mac_from_fuse declare to imx file eQos: Implement the read_rom_hwaddr callback arch/arm/include/asm/mach-imx/sys_proto.h | 2 + drivers/net/Kconfig | 6 + drivers/net/Makefile | 1 + drivers/net/dwc_eth_qos.c | 284 +++++++++++++++++++++++++++--- drivers/net/eth-phy-uclass.c | 123 +++++++++++++ drivers/net/fec_mxc.c | 16 +- drivers/net/fec_mxc.h | 2 - drivers/net/phy/realtek.c | 11 ++ include/dm/uclass-id.h | 1 + include/eth_phy.h | 17 ++ net/eth-uclass.c | 17 +- 11 files changed, 446 insertions(+), 34 deletions(-) create mode 100644 drivers/net/eth-phy-uclass.c create mode 100644 include/eth_phy.h -- 2.16.4

2 9

sunxi_nand_spl reading zeros on NextThing C.H.I.P.
by Yevhenii Hrabliuk 02 May '21

02 May '21

Hello, I'm trying to get latest U-Boot to work on the NextThing C.H.I.P. After borrowing NFC config from the Chip Pro .dts, I can write the SPL to NAND after loading U-Boot via sunxi-fel and the bootrom will pick it up fine. So the "full" sunxi_nand.c works. SPL's sunxi_nand_spl.c appears to read all zeros however - I checked by adding prints in spl.c/jump_to_image_no_args(). Can someone please suggest possible things to try to make it work? I tried tinkering with the settings but I have no idea if that's even the issue. The NAND is a Toshiba "TC58TEG5DCLTA00"; NTC's settings for it are presumably [1] and sunxi_nand_spl.c autodetects the following settings: page_size:16384 ecc_strength:4 ecc_size:1024 addr_cycles:5 nseeds:8 randomize:0 Thanks. [1]: https://raw.githubusercontent.com/nextthingco/chip-nand-scripts/master/nand…

2 2

[RFC PATCH 1/3] net: phy: Add a generic phy file for TI generic PHYs
by Dan Murphy 27 Apr '21

27 Apr '21

Add a TI Generic init file that will initialize TI PHYs that follow that not require special handling. These PHYs can connect with the standard MII register set. This generice file will register the PHY IDs and names of the PHYs so when the command 'mdio list' is executed the PHY name will display as opposed to 'Generic PHY'. The DP8382X PHY series is a generic PHY that requires the generic registration. The DP83867 driver was updated to rename the init to a more PHY specific init call. Signed-off-by: Dan Murphy <dmurphy(a)ti.com> --- configs/am65x_evm_a53_defconfig | 2 +- configs/am65x_hs_evm_a53_defconfig | 2 +- configs/dra7xx_evm_defconfig | 2 +- configs/dra7xx_hs_evm_defconfig | 2 +- configs/dra7xx_hs_evm_usb_defconfig | 2 +- configs/j721e_evm_a72_defconfig | 2 +- configs/j721e_hs_evm_a72_defconfig | 2 +- configs/k2g_evm_defconfig | 2 +- configs/xilinx_versal_virt_defconfig | 2 +- configs/xilinx_zynqmp_virt_defconfig | 2 +- drivers/net/phy/Kconfig | 8 ++ drivers/net/phy/Makefile | 3 +- drivers/net/phy/dp83867.c | 3 +- drivers/net/phy/ti_phy_init.c | 106 +++++++++++++++++++++++++++ drivers/net/phy/ti_phy_init.h | 16 ++++ 15 files changed, 144 insertions(+), 12 deletions(-) create mode 100644 drivers/net/phy/ti_phy_init.c create mode 100644 drivers/net/phy/ti_phy_init.h diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig index 542bbd992c53..7051d6c40505 100644 --- a/configs/am65x_evm_a53_defconfig +++ b/configs/am65x_evm_a53_defconfig @@ -101,7 +101,7 @@ CONFIG_SPI_FLASH_SFDP_SUPPORT CONFIG_SPI_FLASH_STMICRO=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_SPI_FLASH_MTD=y -CONFIG_PHY_TI=y +CONFIG_PHY_DP83867=y CONFIG_PHY_FIXED=y CONFIG_DM_ETH=y CONFIG_E1000=y diff --git a/configs/am65x_hs_evm_a53_defconfig b/configs/am65x_hs_evm_a53_defconfig index 9f43cee39611..29da3826f12a 100644 --- a/configs/am65x_hs_evm_a53_defconfig +++ b/configs/am65x_hs_evm_a53_defconfig @@ -103,7 +103,7 @@ CONFIG_SPI_FLASH_SFDP_SUPPORT CONFIG_SPI_FLASH_STMICRO=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_SPI_FLASH_MTD=y -CONFIG_PHY_TI=y +CONFIG_PHY_DP83867=y CONFIG_PHY_FIXED=y CONFIG_DM_ETH=y CONFIG_E1000=y diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig index 4d765da4e052..19c024889155 100644 --- a/configs/dra7xx_evm_defconfig +++ b/configs/dra7xx_evm_defconfig @@ -86,7 +86,7 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=76800000 CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_TI=y +CONFIG_PHY_DP83867=y CONFIG_DM_ETH=y CONFIG_PHY_GIGE=y CONFIG_MII=y diff --git a/configs/dra7xx_hs_evm_defconfig b/configs/dra7xx_hs_evm_defconfig index c25d4ce5c142..e97f1a3ba338 100644 --- a/configs/dra7xx_hs_evm_defconfig +++ b/configs/dra7xx_hs_evm_defconfig @@ -89,7 +89,7 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=76800000 CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_TI=y +CONFIG_PHY_DP83867=y CONFIG_DM_ETH=y CONFIG_PHY_GIGE=y CONFIG_MII=y diff --git a/configs/dra7xx_hs_evm_usb_defconfig b/configs/dra7xx_hs_evm_usb_defconfig index 8e74496b2ccd..46970e31f02e 100644 --- a/configs/dra7xx_hs_evm_usb_defconfig +++ b/configs/dra7xx_hs_evm_usb_defconfig @@ -87,7 +87,7 @@ CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=76800000 CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_TI=y +CONFIG_PHY_DP83867=y CONFIG_DM_ETH=y CONFIG_PHY_GIGE=y CONFIG_MII=y diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig index e9e82bb4309d..784a6ff396c3 100644 --- a/configs/j721e_evm_a72_defconfig +++ b/configs/j721e_evm_a72_defconfig @@ -124,7 +124,7 @@ CONFIG_SPI_FLASH_SFDP_SUPPORT CONFIG_SPI_FLASH_STMICRO=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_SPI_FLASH_MTD=y -CONFIG_PHY_TI=y +CONFIG_PHY_DP83867=y CONFIG_PHY_FIXED=y CONFIG_DM_ETH=y CONFIG_TI_AM65_CPSW_NUSS=y diff --git a/configs/j721e_hs_evm_a72_defconfig b/configs/j721e_hs_evm_a72_defconfig index a723e2718e5e..dd93a955cefd 100644 --- a/configs/j721e_hs_evm_a72_defconfig +++ b/configs/j721e_hs_evm_a72_defconfig @@ -114,7 +114,7 @@ CONFIG_SPI_FLASH_SFDP_SUPPORT CONFIG_SPI_FLASH_STMICRO=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_SPI_FLASH_MTD=y -CONFIG_PHY_TI=y +CONFIG_PHY_DP83867=y CONFIG_PHY_FIXED=y CONFIG_DM_ETH=y CONFIG_TI_AM65_CPSW_NUSS=y diff --git a/configs/k2g_evm_defconfig b/configs/k2g_evm_defconfig index 5abf5faa450e..f47b1cabe9a8 100644 --- a/configs/k2g_evm_defconfig +++ b/configs/k2g_evm_defconfig @@ -58,7 +58,7 @@ CONFIG_PHYLIB=y CONFIG_PHY_MARVELL=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ8XXX=y -CONFIG_PHY_TI=y +CONFIG_PHY_DP83867=y CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_DRIVER_TI_KEYSTONE_NET=y diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig index e8c349261207..eb2a26bc2c7d 100644 --- a/configs/xilinx_versal_virt_defconfig +++ b/configs/xilinx_versal_virt_defconfig @@ -61,7 +61,7 @@ CONFIG_SPI_FLASH_WINBOND=y CONFIG_PHY_MARVELL=y CONFIG_PHY_NATSEMI=y CONFIG_PHY_REALTEK=y -CONFIG_PHY_TI=y +CONFIG_PHY_DP83867=y CONFIG_PHY_VITESSE=y CONFIG_PHY_FIXED=y CONFIG_PHY_GIGE=y diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig index 7b09edd78e1b..5c320f93fe5f 100644 --- a/configs/xilinx_zynqmp_virt_defconfig +++ b/configs/xilinx_zynqmp_virt_defconfig @@ -101,7 +101,7 @@ CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_PHY_NATSEMI=y CONFIG_PHY_REALTEK=y -CONFIG_PHY_TI=y +CONFIG_PHY_DP83867=y CONFIG_PHY_VITESSE=y CONFIG_PHY_XILINX_GMII2RGMII=y CONFIG_PHY_FIXED=y diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index d1f049e62ab7..e366f10afc59 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -244,6 +244,14 @@ config PHY_TERANETICS config PHY_TI bool "Texas Instruments Ethernet PHYs support" +config PHY_TI_GENERIC + select PHY_TI + bool "Texas Instruments Ethernet PHYs support" + +config PHY_DP83867 + select PHY_TI + bool "Texas Instruments Ethernet DP83867 PHY support" + config PHY_VITESSE bool "Vitesse Ethernet PHYs support" diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile index 1d81516ecd1d..9c6d31718c00 100644 --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile @@ -25,7 +25,8 @@ obj-$(CONFIG_PHY_NATSEMI) += natsemi.o obj-$(CONFIG_PHY_REALTEK) += realtek.o obj-$(CONFIG_PHY_SMSC) += smsc.o obj-$(CONFIG_PHY_TERANETICS) += teranetics.o -obj-$(CONFIG_PHY_TI) += dp83867.o +obj-$(CONFIG_PHY_TI) += ti_phy_init.o +obj-$(CONFIG_PHY_DP83867) += dp83867.o obj-$(CONFIG_PHY_XILINX) += xilinx_phy.o obj-$(CONFIG_PHY_XILINX_GMII2RGMII) += xilinx_gmii2rgmii.o obj-$(CONFIG_PHY_VITESSE) += vitesse.o diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c index 50804c130efd..c9ed4a44d4db 100644 --- a/drivers/net/phy/dp83867.c +++ b/drivers/net/phy/dp83867.c @@ -12,6 +12,7 @@ #include <dm.h> #include <dt-bindings/net/ti-dp83867.h> +#include "ti_phy_init.h" /* TI DP83867 */ #define DP83867_DEVADDR 0x1f @@ -428,7 +429,7 @@ static struct phy_driver DP83867_driver = { .shutdown = &genphy_shutdown, }; -int phy_ti_init(void) +int phy_dp83867_init(void) { phy_register(&DP83867_driver); return 0; diff --git a/drivers/net/phy/ti_phy_init.c b/drivers/net/phy/ti_phy_init.c new file mode 100644 index 000000000000..11c4c166b2f5 --- /dev/null +++ b/drivers/net/phy/ti_phy_init.c @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * TI Generic PHY Init to register all TI Ethernet PHYs + * + * Author: Dan Murphy <dmurphy(a)ti.com> + * + * Copyright (C) 2019 Texas Instruments Inc. + */ + +#include <phy.h> + +#define DP83822_PHY_ID 0x2000a240 +#define DP83825S_PHY_ID 0x2000a140 +#define DP83825I_PHY_ID 0x2000a150 +#define DP83825CM_PHY_ID 0x2000a160 +#define DP83825CS_PHY_ID 0x2000a170 +#define DP83826C_PHY_ID 0x2000a130 +#define DP83826NC_PHY_ID 0x2000a110 + +static struct phy_driver dp83822_driver = { + .name = "TI DP83822", + .uid = DP83822_PHY_ID, + .mask = 0xfffffff0, + .features = PHY_BASIC_FEATURES, + .config = &genphy_config_aneg, + .startup = &genphy_startup, + .shutdown = &genphy_shutdown, +}; + +static struct phy_driver dp83825s_driver = { + .name = "TI DP83825S", + .uid = DP83825S_PHY_ID, + .mask = 0xfffffff0, + .features = PHY_BASIC_FEATURES, + .config = &genphy_config_aneg, + .startup = &genphy_startup, + .shutdown = &genphy_shutdown, +}; + +static struct phy_driver dp83825i_driver = { + .name = "TI DP83825I", + .uid = DP83825I_PHY_ID, + .mask = 0xfffffff0, + .features = PHY_BASIC_FEATURES, + .config = &genphy_config_aneg, + .startup = &genphy_startup, + .shutdown = &genphy_shutdown, +}; + +static struct phy_driver dp83825m_driver = { + .name = "TI DP83825M", + .uid = DP83825CM_PHY_ID, + .mask = 0xfffffff0, + .features = PHY_BASIC_FEATURES, + .config = &genphy_config_aneg, + .startup = &genphy_startup, + .shutdown = &genphy_shutdown, +}; + +static struct phy_driver dp83825cs_driver = { + .name = "TI DP83825CS", + .uid = DP83825CS_PHY_ID, + .mask = 0xfffffff0, + .features = PHY_BASIC_FEATURES, + .config = &genphy_config_aneg, + .startup = &genphy_startup, + .shutdown = &genphy_shutdown, +}; + +static struct phy_driver dp83826c_driver = { + .name = "TI DP83826C", + .uid = DP83826C_PHY_ID, + .mask = 0xfffffff0, + .features = PHY_BASIC_FEATURES, + .config = &genphy_config_aneg, + .startup = &genphy_startup, + .shutdown = &genphy_shutdown, +}; +static struct phy_driver dp83826nc_driver = { + .name = "TI DP83826NC", + .uid = DP83826NC_PHY_ID, + .mask = 0xfffffff0, + .features = PHY_BASIC_FEATURES, + .config = &genphy_config_aneg, + .startup = &genphy_startup, + .shutdown = &genphy_shutdown, +}; + +int phy_ti_init(void) +{ +#ifdef CONFIG_PHY_DP83867 + phy_dp83867_init(); +#endif + +#ifdef CONFIG_PHY_TI_GENERIC + phy_register(&dp83822_driver); + phy_register(&dp83825s_driver); + phy_register(&dp83825i_driver); + phy_register(&dp83825m_driver); + phy_register(&dp83825cs_driver); + phy_register(&dp83826c_driver); + phy_register(&dp83826nc_driver); +#endif + + return 0; +} diff --git a/drivers/net/phy/ti_phy_init.h b/drivers/net/phy/ti_phy_init.h new file mode 100644 index 000000000000..309da2aacccb --- /dev/null +++ b/drivers/net/phy/ti_phy_init.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * TI Generic Ethernet PHY + * Based on code in sungem_phy.c and (long-removed) gianfar_phy.c + * + * Author: Dan Murphy <dmurphy(a)ti.com> + * + * Copyright (C) 2019 Texas Instruments Inc. + */ + +#ifndef _TI_GEN_PHY_H +#define _TI_GEN_PHY_H + +int phy_dp83867_init(void); + +#endif /* _TI_GEN_PHY_H */ -- 2.25.1

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[RFC PATCH] watchdog: base rate-limiting on get_ticks() rather than get_timer()
by Rasmus Villemoes 12 Apr '21

12 Apr '21

On powerpc, get_timer() is implemented using a volatile variable that gets incremented from the decrementer interrupt handler. Hence, when interrupts are disabled, time as measured by get_timer() ceases to pass. Interrupts are necessarily disabled during bootm (see the comment in bootm_disable_interrupts() for why). But after interrupts are disabled, there's still lots of work to do - e.g. decompressing the kernel image to the right load address. Unfortunately, the rate-limiting logic in wdt_uclass.c's watchdog_reset function means that WATCHDOG_RESET() becomes a no-op, since get_timer() never progresses past the next_reset. This, combined with an external gpio-triggered watchdog that must be petted at least every 800ms, means our board gets reset before booting into linux. Now, at least on powerpc, get_ticks() continues to return sensible results whether or not interrupts are enabled. So this fixes the above problem for our board - but I don't know if get_ticks() can be assumed to always work. Signed-off-by: Rasmus Villemoes <rasmus.villemoes(a)prevas.dk> --- This is what I had in mind. I also considered making it a config knob (possibly just auto-selected based on $ARCH) whether to use get_timer() or get_ticks(), but that becomes quite ugly. drivers/watchdog/wdt-uclass.c | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/drivers/watchdog/wdt-uclass.c b/drivers/watchdog/wdt-uclass.c index 4cdb7bd64c..7be4e9b5bc 100644 --- a/drivers/watchdog/wdt-uclass.c +++ b/drivers/watchdog/wdt-uclass.c @@ -16,14 +16,15 @@ DECLARE_GLOBAL_DATA_PTR; #define WATCHDOG_TIMEOUT_SECS (CONFIG_WATCHDOG_TIMEOUT_MSECS / 1000) -/* - * Reset every 1000ms, or however often is required as indicated by a - * hw_margin_ms property. - */ -static ulong reset_period = 1000; +static u64 ratelimit_ticks; int initr_watchdog(void) { + /* + * Reset every 1000ms, or however often is required as indicated by a + * hw_margin_ms property. + */ + u32 reset_period = 1000; u32 timeout = WATCHDOG_TIMEOUT_SECS; /* @@ -48,6 +49,7 @@ int initr_watchdog(void) 4 * reset_period) / 4; } + ratelimit_ticks = usec_to_tick(reset_period * 1000); wdt_start(gd->watchdog_dev, timeout * 1000, 0); gd->flags |= GD_FLG_WDT_READY; printf("WDT: Started with%s servicing (%ds timeout)\n", @@ -117,17 +119,17 @@ int wdt_expire_now(struct udevice *dev, ulong flags) */ void watchdog_reset(void) { - static ulong next_reset; - ulong now; + static u64 last_reset; + u64 now; /* Exit if GD is not ready or watchdog is not initialized yet */ if (!gd || !(gd->flags & GD_FLG_WDT_READY)) return; /* Do not reset the watchdog too often */ - now = get_timer(0); - if (time_after(now, next_reset)) { - next_reset = now + reset_period; + now = get_ticks(); + if (now - last_reset >= ratelimit_ticks) { + last_reset = now; wdt_reset(gd->watchdog_dev); } } -- 2.23.0

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[PATCH V4 00/13] net: smc911x: Convert to DM
by Marek Vasut 04 Mar '21

04 Mar '21

Perform DM conversion of the SMC911x driver. Note that the DT compatible is set only for 9115 , so this might need to be changed. Marek Vasut (13): net: smc911x: Remove pkt_data_{push,pull} net: smc911x: Replace malloc()+memset() with calloc() net: smc911x: Rename smc911x_rx() to smc911x_recv() net: smc911x: Invert the logic in smc911x_miiphy_{read,write}() net: smc911x: Fix potential memleak() in init fail path net: smc911x: Pull MII registration into separate function net: smc911x: Inline all functions from header file net: smc911x: Drop weak alias from 32bit accessors net: smc911x: Convert IO accessors to {read,write}{w,l}() net: smc911x: Pass around driver private data net: smc911x: Clean up the status handling in smc911x_recv() net: smc911x: Split non-DM specific bits from common code net: smc911x: Add DM support drivers/net/Kconfig | 2 + drivers/net/smc911x.c | 559 +++++++++++++++++++++------ drivers/net/smc911x.h | 157 -------- examples/standalone/Makefile | 5 +- examples/standalone/smc911x_eeprom.c | 150 +++++++ 5 files changed, 602 insertions(+), 271 deletions(-) Cc: Joe Hershberger <joe.hershberger(a)ni.com> Cc: Masahiro Yamada <yamada.masahiro(a)socionext.com> -- 2.25.1

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