April 2020 - U-Boot

[PATCH 01/16] arm: stm32mp: update dependency for STM32_ETZPC
by Patrick Delaunay 24 Apr '20

24 Apr '20

Correct the dependency for STM32 ETZPC protection, linked to SOC STM32MP identified by CONFIG_STM32MP15x and not linked to CONFIG_TARGET_STM32MP1 (no more existing). This patch fix an issue introduced by commit 846254888e2e ("stm32mp1: split board and SOC support for STM32MP15x family"). Signed-off-by: Patrick Delaunay <patrick.delaunay(a)st.com> Acked-by: Patrice Chotard <patrice.chotard(a)st.com> --- arch/arm/mach-stm32mp/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig index e4d621dee8..96153693a7 100644 --- a/arch/arm/mach-stm32mp/Kconfig +++ b/arch/arm/mach-stm32mp/Kconfig @@ -119,7 +119,7 @@ config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_MMC2 config STM32_ETZPC bool "STM32 Extended TrustZone Protection" - depends on TARGET_STM32MP1 + depends on STM32MP15x default y help Say y to enable STM32 Extended TrustZone Protection -- 2.17.1

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[PATCH v8 00/21] riscv: Add Sipeed Maix support
by Sean Anderson 24 Apr '20

24 Apr '20

This patch series adds support for Sipeed Maix boards and the Kendryte K210 CPU. Currently, only the Maix Bit V2.0 is supported, however other models are similar. Known Bugs/Limitations: - Accessing the AI ram hangs, limiting available ram to 6M - Trying to boot an image with bootm fails with ERROR: Failed to allocate 0x7d60 bytes below 0x80000000. To flash u-boot to a maix bit, run kflash -tp /dev/<your tty here> -B bit_mic u-boot-dtb.bin Boot output should look like the following: U-Boot 2020.04-rc2-00087-g2221cc09c1-dirty (Feb 28 2020 - 13:53:09 -0500) DRAM: 8 MiB In: serial@38000000 Out: serial@38000000 Err: serial@38000000 => Changes for v8: - Removed dependency on the patch "clk: Add functions to register CCF clock structs". Hopefully this will make reviewing easier. Changes for v7: - Split documentation from other board support - Split IPI clear from other IPI cleanup - Rebased onto a clean upstream. Hopefully this fixes any patching problems. Changes for v6: - Remove spi, pinmux, gpio, led, and wdt support --- to be added in separate patches - Rebase onto master - Clear IPIs before enabling them - Reorganize code so checkpatch errors less Changes for v5: - Rebase onto master - Add pinconf support - Add gpio support - Store environment in spi flash - Group patches by prefix - Add additional documentation - Add SMP support - Add WDT support Changes for v4: - Linted several patches - Updated the copyright year for several files - Added tests for syscon-reset, simple-pm-bus, and the pll calc_rate function - Added/updated documentation - Fixed SPI for the nor flash - Fixed PLLs not enabling/setting rate properly - RISCV_PRIV_1_9_1 now (un)defines all diferring CSRs, and also disables VM - More devicetree changes Changes for v3: - Remove patch to set RV64I as default - Remove patch for a separate sysctl driver - Split off cpu frequency patch into its own series - Reorder support/devicetree patches to come last - Add patch for reset driver - Add simple-pm-bus for busses with their own clocks - Add additional documentation - Reword mcounteren patch to refer to the RISC-V priv spec 1.9.1 - Many devicetree changes - Switch to "make savedefconfig" to generate the config Changes for v2: - Many bugfixes for the device tree - Modify the config to build without errors - Add support for keeping internal PLL frequencies in-range - Fix several rebase-induced artifacts Sean Anderson (21): clk: Always use the supplied struct clk clk: Check that ops of composite clock components exist before calling clk: Unconditionally recursively en-/dis-able clocks clk: Fix clk_get_by_* handling of index clk: Add K210 pll support clk: Add a bypass clock for K210 clk: Add K210 clock support dm: Add support for simple-pm-bus dm: Fix error handling for dev_read_addr_ptr reset: Add generic reset driver lib: Always set errno in hcreate_r riscv: Add headers for asm/global_data.h riscv: Clear pending interrupts before enabling IPIs riscv: Clean up IPI initialization code riscv: Add option to support RISC-V privileged spec 1.9 riscv: Allow use of reset drivers riscv: Try to get cpu frequency from a "clocks" node if it exists riscv: Enable cpu clock if it is present riscv: Add device tree for K210 and Sipeed Maix BitM doc: riscv: Add documentation for Sipeed Maix Bit riscv: Add Sipeed Maix support MAINTAINERS | 7 + arch/riscv/Kconfig | 14 + arch/riscv/cpu/cpu.c | 15 + arch/riscv/cpu/start.S | 2 + arch/riscv/dts/Makefile | 1 + arch/riscv/dts/k210-maix-bit.dts | 47 ++ arch/riscv/dts/k210.dtsi | 594 ++++++++++++++++ arch/riscv/include/asm/csr.h | 40 ++ arch/riscv/include/asm/global_data.h | 2 + arch/riscv/include/asm/smp.h | 43 ++ arch/riscv/lib/andes_plic.c | 34 +- arch/riscv/lib/reset.c | 2 + arch/riscv/lib/sbi_ipi.c | 5 + arch/riscv/lib/sifive_clint.c | 33 +- arch/riscv/lib/smp.c | 56 +- arch/sandbox/dts/test.dts | 21 + arch/sandbox/include/asm/clk.h | 1 + board/sipeed/maix/Kconfig | 47 ++ board/sipeed/maix/MAINTAINERS | 11 + board/sipeed/maix/Makefile | 5 + board/sipeed/maix/maix.c | 41 ++ configs/sandbox_defconfig | 3 + configs/sipeed_maix_bitm_defconfig | 8 + doc/board/index.rst | 1 + doc/board/sipeed/index.rst | 9 + doc/board/sipeed/maix.rst | 298 ++++++++ .../bus/simple-pm-bus.txt | 44 ++ .../mfd/kendryte,k210-sysctl.txt | 33 + .../reset/syscon-reset.txt | 36 + doc/imx/clk/ccf.txt | 63 +- drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/clk-composite.c | 64 +- drivers/clk/clk-divider.c | 6 +- drivers/clk/clk-fixed-factor.c | 3 +- drivers/clk/clk-gate.c | 6 +- drivers/clk/clk-mux.c | 12 +- drivers/clk/clk-uclass.c | 68 +- drivers/clk/imx/clk-gate2.c | 4 +- drivers/clk/imx/clk-imx8mp.c | 2 +- drivers/clk/kendryte/Kconfig | 12 + drivers/clk/kendryte/Makefile | 1 + drivers/clk/kendryte/bypass.c | 270 +++++++ drivers/clk/kendryte/clk.c | 663 ++++++++++++++++++ drivers/clk/kendryte/pll.c | 601 ++++++++++++++++ drivers/core/Kconfig | 7 + drivers/core/Makefile | 1 + drivers/core/read.c | 2 +- drivers/core/simple-pm-bus.c | 56 ++ drivers/cpu/riscv_cpu.c | 39 +- drivers/pinctrl/broadcom/pinctrl-bcm283x.c | 2 +- drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 2 +- drivers/reset/Kconfig | 5 + drivers/reset/Makefile | 1 + drivers/reset/reset-syscon.c | 80 +++ include/configs/sipeed-maix.h | 24 + include/dm/read.h | 4 +- include/dt-bindings/clock/k210-sysctl.h | 59 ++ include/dt-bindings/mfd/k210-sysctl.h | 38 + include/dt-bindings/reset/k210-sysctl.h | 38 + include/kendryte/bypass.h | 31 + include/kendryte/clk.h | 35 + include/kendryte/pll.h | 57 ++ include/test/export.h | 16 + lib/hashtable.c | 8 +- test/dm/Makefile | 3 + test/dm/k210_pll.c | 96 +++ test/dm/simple-pm-bus.c | 45 ++ test/dm/syscon-reset.c | 58 ++ 69 files changed, 3732 insertions(+), 205 deletions(-) create mode 100644 arch/riscv/dts/k210-maix-bit.dts create mode 100644 arch/riscv/dts/k210.dtsi create mode 100644 board/sipeed/maix/Kconfig create mode 100644 board/sipeed/maix/MAINTAINERS create mode 100644 board/sipeed/maix/Makefile create mode 100644 board/sipeed/maix/maix.c create mode 100644 configs/sipeed_maix_bitm_defconfig create mode 100644 doc/board/sipeed/index.rst create mode 100644 doc/board/sipeed/maix.rst create mode 100644 doc/device-tree-bindings/bus/simple-pm-bus.txt create mode 100644 doc/device-tree-bindings/mfd/kendryte,k210-sysctl.txt create mode 100644 doc/device-tree-bindings/reset/syscon-reset.txt create mode 100644 drivers/clk/kendryte/Kconfig create mode 100644 drivers/clk/kendryte/Makefile create mode 100644 drivers/clk/kendryte/bypass.c create mode 100644 drivers/clk/kendryte/clk.c create mode 100644 drivers/clk/kendryte/pll.c create mode 100644 drivers/core/simple-pm-bus.c create mode 100644 drivers/reset/reset-syscon.c create mode 100644 include/configs/sipeed-maix.h create mode 100644 include/dt-bindings/clock/k210-sysctl.h create mode 100644 include/dt-bindings/mfd/k210-sysctl.h create mode 100644 include/dt-bindings/reset/k210-sysctl.h create mode 100644 include/kendryte/bypass.h create mode 100644 include/kendryte/clk.h create mode 100644 include/kendryte/pll.h create mode 100644 include/test/export.h create mode 100644 test/dm/k210_pll.c create mode 100644 test/dm/simple-pm-bus.c create mode 100644 test/dm/syscon-reset.c -- 2.25.1

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Re: [PATCH] usb: dwc3-meson-g12a: add power-on/off of the PHYs
by Neil Armstrong 24 Apr '20

24 Apr '20

On 20/04/2020 15:46, Neil Armstrong via groups.io wrote: > Power on/off the PHYs to enable power to the USB ports, fixing USB support > on Khadas VIM3/VIM3L boards. > > Signed-off-by: Neil Armstrong <narmstrong(a)baylibre.com> > --- > drivers/usb/dwc3/dwc3-meson-g12a.c | 16 ++++++++++++++++ > 1 file changed, 16 insertions(+) > > diff --git a/drivers/usb/dwc3/dwc3-meson-g12a.c b/drivers/usb/dwc3/dwc3-meson-g12a.c > index d4453f8784..8f4a2f3f82 100644 > --- a/drivers/usb/dwc3/dwc3-meson-g12a.c > +++ b/drivers/usb/dwc3/dwc3-meson-g12a.c > @@ -408,6 +408,15 @@ static int dwc3_meson_g12a_probe(struct udevice *dev) > goto err_phy_init; > } > > + for (i = 0 ; i < PHY_COUNT ; ++i) { > + if (!priv->phys[i].dev) > + continue; > + > + ret = generic_phy_power_on(&priv->phys[i]); > + if (ret) > + goto err_phy_init; > + } > + > return 0; > > err_phy_init: > @@ -430,6 +439,13 @@ static int dwc3_meson_g12a_remove(struct udevice *dev) > > clk_release_all(&priv->clk, 1); > > + for (i = 0 ; i < PHY_COUNT ; ++i) { > + if (!priv->phys[i].dev) > + continue; > + > + generic_phy_power_off(&priv->phys[i]); > + } > + > for (i = 0 ; i < PHY_COUNT ; ++i) { > if (!priv->phys[i].dev) > continue; > Applied to u-boot-amlogic

1 0

Re: [PATCH 0/5] arm: khadas-vim: enable support for SPI NOR Flash
by Neil Armstrong 24 Apr '20

24 Apr '20

On 20/04/2020 15:44, Neil Armstrong via groups.io wrote: > This serie enables support of the on-board SPI NOR Flash found on the > Khadas VIM2, VIM3 and VIM3L board. > > Neil Armstrong (5): > arm64: dts: meson: sync dt and bindings from v5.7-rc1 > arm: dts: meson-gxm-khadas-vim2-u-boot: enable SPI NOR flash > configs: khadas-vim2: enable support for SPI NOR flash > arm: dts: meson-khadas-vim3: enable SPI NOR flash > configs: khadas-vim3: enable support for SPI NOR flash > > arch/arm/dts/meson-axg-s400.dts | 6 +- > arch/arm/dts/meson-g12-common.dtsi | 136 ++++++++++++++++-- > arch/arm/dts/meson-g12.dtsi | 1 + > arch/arm/dts/meson-g12a-sei510.dts | 4 +- > arch/arm/dts/meson-g12a-u200.dts | 2 +- > .../meson-g12b-a311d-khadas-vim3-u-boot.dtsi | 7 + > arch/arm/dts/meson-g12b-khadas-vim3.dtsi | 4 +- > arch/arm/dts/meson-g12b-odroid-n2.dts | 25 +++- > arch/arm/dts/meson-gx.dtsi | 52 +++++++ > arch/arm/dts/meson-gxbb-odroidc2.dts | 1 + > arch/arm/dts/meson-gxl-s905x-p212.dtsi | 9 +- > .../arm/dts/meson-gxm-khadas-vim2-u-boot.dtsi | 15 ++ > arch/arm/dts/meson-gxm-khadas-vim2.dts | 89 +++--------- > arch/arm/dts/meson-gxm.dtsi | 28 ++++ > arch/arm/dts/meson-khadas-vim3-u-boot.dtsi | 21 +++ > arch/arm/dts/meson-khadas-vim3.dtsi | 24 +++- > .../dts/meson-sm1-khadas-vim3l-u-boot.dtsi | 7 + > arch/arm/dts/meson-sm1-khadas-vim3l.dts | 8 +- > arch/arm/dts/meson-sm1-sei610.dts | 3 +- > arch/arm/dts/meson-sm1.dtsi | 1 + > configs/khadas-vim2_defconfig | 8 ++ > configs/khadas-vim3_defconfig | 9 ++ > configs/khadas-vim3l_defconfig | 9 ++ > include/dt-bindings/clock/g12a-clkc.h | 2 + > include/dt-bindings/clock/gxbb-clkc.h | 1 + > 25 files changed, 371 insertions(+), 101 deletions(-) > create mode 100644 arch/arm/dts/meson-g12b-a311d-khadas-vim3-u-boot.dtsi > create mode 100644 arch/arm/dts/meson-khadas-vim3-u-boot.dtsi > create mode 100644 arch/arm/dts/meson-sm1-khadas-vim3l-u-boot.dtsi > Applied to u-boot-amlogic

1 0

[PATCH] tools: k3_gen_x509_cert: Allow selecting early JTAG debug value
by Andrew F. Davis 24 Apr '20

24 Apr '20

When authenticating the initial boot binary the ROM will check a debug type value in the certificate and based on that open JTAG access to that core. The default is currently full access, on HS this is useful for early developers, but should not be the default as to prevent end system integrators from unintentionally leaving this open. On non-HS devices JTAG is left open anyway so this does not change behavior on those devices. Change the default to off and allow it to be switched back on by command line flag if needed. Signed-off-by: Andrew F. Davis <afd(a)ti.com> --- tools/k3_gen_x509_cert.sh | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/tools/k3_gen_x509_cert.sh b/tools/k3_gen_x509_cert.sh index b6d055f6f5..298cec1313 100755 --- a/tools/k3_gen_x509_cert.sh +++ b/tools/k3_gen_x509_cert.sh @@ -12,6 +12,7 @@ RAND_KEY=eckey.pem LOADADDR=0x41c00000 BOOTCORE_OPTS=0 BOOTCORE=16 +DEBUG_TYPE=0 gen_degen_template() { cat << 'EOF' > degen-template.txt @@ -79,7 +80,7 @@ cat << 'EOF' > x509-template.txt [ debug ] debugUID = FORMAT:HEX,OCT:0000000000000000000000000000000000000000000000000000000000000000 - debugType = INTEGER:4 + debugType = INTEGER:TEST_DEBUG_TYPE coreDbgEn = INTEGER:0 coreDbgSecEn = INTEGER:0 EOF @@ -151,8 +152,9 @@ options_help[k]="key_file:file with key inside it. If not provided script genera options_help[o]="output_file:Name of the final output file. default to $OUTPUT" options_help[c]="core_id:target core id on which the image would be running. Default to $BOOTCORE" options_help[l]="loadaddr: Target load address of the binary in hex. Default to $LOADADDR" +options_help[d]="debug_type: Debug type, set to 4 to enable early JTAG. Default to $DEBUG_TYPE" -while getopts "b:k:o:c:l:h" opt +while getopts "b:k:o:c:l:d:h" opt do case $opt in b) @@ -170,6 +172,9 @@ do c) BOOTCORE=$OPTARG ;; + d) + DEBUG_TYPE=$OPTARG + ;; h) usage exit 0 @@ -224,12 +229,15 @@ gen_cert() { #echo " LOADADDR = 0x$ADDR" #echo " IMAGE_SIZE = $BIN_SIZE" #echo " CERT_TYPE = $CERTTYPE" + #echo " DEBUG_TYPE = $DEBUG_TYPE" sed -e "s/TEST_IMAGE_LENGTH/$BIN_SIZE/" \ -e "s/TEST_IMAGE_SHA_VAL/$SHA_VAL/" \ -e "s/TEST_CERT_TYPE/$CERTTYPE/" \ -e "s/TEST_BOOT_CORE_OPTS/$BOOTCORE_OPTS/" \ -e "s/TEST_BOOT_CORE/$BOOTCORE/" \ - -e "s/TEST_BOOT_ADDR/$ADDR/" x509-template.txt > $TEMP_X509 + -e "s/TEST_BOOT_ADDR/$ADDR/" \ + -e "s/TEST_DEBUG_TYPE/$DEBUG_TYPE/" \ + x509-template.txt > $TEMP_X509 openssl req -new -x509 -key $KEY -nodes -outform DER -out $CERT -config $TEMP_X509 -sha512 } -- 2.17.1

2 3

[PATCH] dm: pinctrl: Use right device pointer for configuring pinctrl
by Lokesh Vutla 23 Apr '20

23 Apr '20

commit 719cab6d2e2bf ("dm: pinctrl: convert pinctrl-single to livetree") converted pinctrl driver to livetree. In this conversion, the call to read pinctrl-single,pins/bits property is provided with pinctrl device pointer instead of pinctrl config pointer. Because of this none of the pins gets configured. Fix it by passing the right udevice pointer. Fixes: 719cab6d2e2bf ("dm: pinctrl: convert pinctrl-single to livetree") Reported-by: Tom Rini <trini(a)konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla(a)ti.com> --- drivers/pinctrl/pinctrl-single.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index a5d1ff0e97..738f5bd636 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -120,7 +120,7 @@ static int single_set_state(struct udevice *dev, const struct single_fdt_bits_cfg *prop_bits; int len; - prop = dev_read_prop(dev, "pinctrl-single,pins", &len); + prop = dev_read_prop(config, "pinctrl-single,pins", &len); if (prop) { dev_dbg(dev, "configuring pins for %s\n", config->name); @@ -133,7 +133,7 @@ static int single_set_state(struct udevice *dev, } /* pinctrl-single,pins not found so check for pinctrl-single,bits */ - prop_bits = dev_read_prop(dev, "pinctrl-single,bits", &len); + prop_bits = dev_read_prop(config, "pinctrl-single,bits", &len); if (prop_bits) { dev_dbg(dev, "configuring pins for %s\n", config->name); if (len % sizeof(struct single_fdt_bits_cfg)) { -- 2.23.0

3 3

[U-Boot] Pull request: u-boot-riscv/master
by uboot＠andestech.com 23 Apr '20

23 Apr '20

Hi Tom, Please pull some riscv updates: - Adds few DT related fixes required for Linux EFI stub to work on RISC-V. - Makes SBI v0.2 the default SBI version to work with OpenSBI v0.7. - Revert "riscv: qemu: clear kernel-start/-end in device tree as workaround for BBL" - Remove unnecessary CONFIG_IS_ENABLED(). https://travis-ci.org/github/rickchen36/u-boot-riscv/builds/678432471 Thanks Rick The following changes since commit caad316b3165615f1a4848901811a4a084444c9d: Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvell (2020-04-22 13:00:21 -0400) are available in the Git repository at: git@gitlab.denx.de:u-boot/custodians/u-boot-riscv.git for you to fetch changes up to 177c53fe6c64d8656f5a647116a97047202c5455: riscv: Move all fdt fixups together (2020-04-23 10:14:16 +0800) ---------------------------------------------------------------- Atish Patra (6): riscv: Add boot hartid to device tree fdtdec: Fix boundary check riscv: Provide a mechanism to fix DT for reserved memory riscv: Setup reserved-memory node for FU540 riscv: Copy the reserved-memory nodes to final DT riscv: Move all fdt fixups together Bin Meng (6): riscv: qemu: Remove the simple-bus driver for the SoC node riscv: Merge unnecessary SMP ifdefs in start.S riscv: Introduce SPL_SMP Kconfig option for U-Boot SPL riscv: Add SMP Kconfig option dependency for U-Boot proper riscv: Add Kconfig option for SBI v0.2 riscv: Make SBI v0.2 the default SBI version Lukas Auer (1): Revert "riscv: qemu: clear kernel-start/-end in device tree as workaround for BBL" Pragnesh Patel (1): riscv: ax25: cache: Remove SPL_RISCV_MMODE config check arch/riscv/Kconfig | 34 +++++++++++++++++++++++-- arch/riscv/cpu/ax25/cache.c | 16 ++++++------ arch/riscv/cpu/generic/cpu.c | 14 ----------- arch/riscv/cpu/start.S | 19 ++++++-------- arch/riscv/include/asm/global_data.h | 3 ++- arch/riscv/include/asm/u-boot-riscv.h | 2 ++ arch/riscv/lib/Makefile | 3 ++- arch/riscv/lib/asm-offsets.c | 1 + arch/riscv/lib/bootm.c | 5 ---- arch/riscv/lib/fdt_fixup.c | 150 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ arch/riscv/lib/spl.c | 2 +- board/emulation/qemu-riscv/Kconfig | 1 - board/emulation/qemu-riscv/qemu-riscv.c | 39 ----------------------------- common/spl/spl_opensbi.c | 2 +- configs/sifive_fu540_defconfig | 1 + doc/board/emulation/qemu-riscv.rst | 2 +- lib/fdtdec.c | 3 ++- 17 files changed, 211 insertions(+), 86 deletions(-) create mode 100644 arch/riscv/lib/fdt_fixup.c

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[PATCH] ARC: AXS10x: cleanup kconfig
by Eugeniy Paltsev 23 Apr '20

23 Apr '20

As we've dropped NAND support for AXS101 and AXS103 see commit 4f5e552d95bb ("ARC: AXS10x: drop NAND support") we don't need bounce buffer anymore. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev(a)synopsys.com> --- arch/arc/Kconfig | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig index ea875711e70..6ff201fa816 100644 --- a/arch/arc/Kconfig +++ b/arch/arc/Kconfig @@ -164,11 +164,9 @@ config TARGET_NSIM config TARGET_AXS101 bool "Support Synopsys Designware SDP board AXS101" - select BOUNCE_BUFFER if CMD_NAND config TARGET_AXS103 bool "Support Synopsys Designware SDP board AXS103" - select BOUNCE_BUFFER if CMD_NAND config TARGET_EMSDP bool "Synopsys EM Software Development Platform" -- 2.21.1

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[PATCH] nand: brcmnand: return without disabling clock
by Álvaro Fernández Rojas 23 Apr '20

23 Apr '20

Linux Broadcom NAND driver only disabled clock if no childs are initialized. This section of the code seems to have been accidentally dropped when it was imported in U-Boot. Signed-off-by: Álvaro Fernández Rojas <noltari(a)gmail.com> --- drivers/mtd/nand/raw/brcmnand/brcmnand.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c b/drivers/mtd/nand/raw/brcmnand/brcmnand.c index 5232328e1e..7bdebf5869 100644 --- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c +++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c @@ -2714,6 +2714,14 @@ int brcmnand_probe(struct udevice *dev, struct brcmnand_soc *soc) } #endif /* __UBOOT__ */ + /* No chip-selects could initialize properly */ + if (list_empty(&ctrl->host_list)) { + ret = -ENODEV; + goto err; + } + + return 0; + err: #ifndef __UBOOT__ clk_disable_unprepare(ctrl->clk); @@ -2722,7 +2730,6 @@ err: clk_disable(ctrl->clk); #endif /* __UBOOT__ */ return ret; - } EXPORT_SYMBOL_GPL(brcmnand_probe); -- 2.20.1

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[PATCH] bmips: allow disabling usb support
by Álvaro Fernández Rojas 23 Apr '20

23 Apr '20

Currently, if usb is disabled the following error is produced: CC drivers/usb/host/ohci-hcd.o drivers/usb/host/ohci-hcd.c: In function ‘usb_lowlevel_init’: drivers/usb/host/ohci-hcd.c:2057:35: error: ‘CONFIG_SYS_USB_OHCI_REGS_BASE’ undeclared (first use in this function); did you mean ‘CONFIG_SYS_MONITOR_BASE’? gohci.regs = (struct ohci_regs *)CONFIG_SYS_USB_OHCI_REGS_BASE; ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ CONFIG_SYS_MONITOR_BASE drivers/usb/host/ohci-hcd.c:2057:35: note: each undeclared identifier is reported only once for each function it appears in drivers/usb/host/ohci-hcd.c:2061:20: error: ‘CONFIG_SYS_USB_OHCI_SLOT_NAME’ undeclared (first use in this function); did you mean ‘CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS’? gohci.slot_name = CONFIG_SYS_USB_OHCI_SLOT_NAME; ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS Signed-off-by: Álvaro Fernández Rojas <noltari(a)gmail.com> --- include/configs/bmips_bcm6318.h | 2 ++ include/configs/bmips_bcm63268.h | 2 ++ include/configs/bmips_bcm6328.h | 2 ++ include/configs/bmips_bcm6348.h | 2 ++ include/configs/bmips_bcm6358.h | 2 ++ include/configs/bmips_bcm6362.h | 2 ++ include/configs/bmips_bcm6368.h | 2 ++ 7 files changed, 14 insertions(+) diff --git a/include/configs/bmips_bcm6318.h b/include/configs/bmips_bcm6318.h index c7e7119aaf..45eb931c25 100644 --- a/include/configs/bmips_bcm6318.h +++ b/include/configs/bmips_bcm6318.h @@ -19,7 +19,9 @@ #define CONFIG_EHCI_MMIO_BIG_ENDIAN #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 +#if defined(CONFIG_USB_OHCI_HCD) #define CONFIG_USB_OHCI_NEW +#endif /* CONFIG_USB_OHCI_HCD */ /* U-Boot */ #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M diff --git a/include/configs/bmips_bcm63268.h b/include/configs/bmips_bcm63268.h index 45f26bb309..eed321eb6f 100644 --- a/include/configs/bmips_bcm63268.h +++ b/include/configs/bmips_bcm63268.h @@ -19,7 +19,9 @@ #define CONFIG_EHCI_MMIO_BIG_ENDIAN #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 +#if defined(CONFIG_USB_OHCI_HCD) #define CONFIG_USB_OHCI_NEW +#endif /* CONFIG_USB_OHCI_HCD */ /* U-Boot */ #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M diff --git a/include/configs/bmips_bcm6328.h b/include/configs/bmips_bcm6328.h index 8d59438785..c78099a49d 100644 --- a/include/configs/bmips_bcm6328.h +++ b/include/configs/bmips_bcm6328.h @@ -19,7 +19,9 @@ #define CONFIG_EHCI_MMIO_BIG_ENDIAN #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 +#if defined(CONFIG_USB_OHCI_HCD) #define CONFIG_USB_OHCI_NEW +#endif /* CONFIG_USB_OHCI_HCD */ /* U-Boot */ #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M diff --git a/include/configs/bmips_bcm6348.h b/include/configs/bmips_bcm6348.h index 061d6b25b7..547cf857ce 100644 --- a/include/configs/bmips_bcm6348.h +++ b/include/configs/bmips_bcm6348.h @@ -17,7 +17,9 @@ /* USB */ #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 +#if defined(CONFIG_USB_OHCI_HCD) #define CONFIG_USB_OHCI_NEW +#endif /* CONFIG_USB_OHCI_HCD */ /* U-Boot */ #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M diff --git a/include/configs/bmips_bcm6358.h b/include/configs/bmips_bcm6358.h index 583217d262..116e9705b6 100644 --- a/include/configs/bmips_bcm6358.h +++ b/include/configs/bmips_bcm6358.h @@ -19,7 +19,9 @@ #define CONFIG_EHCI_MMIO_BIG_ENDIAN #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 +#if defined(CONFIG_USB_OHCI_HCD) #define CONFIG_USB_OHCI_NEW +#endif /* CONFIG_USB_OHCI_HCD */ /* U-Boot */ #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M diff --git a/include/configs/bmips_bcm6362.h b/include/configs/bmips_bcm6362.h index 570bc3b33d..e5e8b15e18 100644 --- a/include/configs/bmips_bcm6362.h +++ b/include/configs/bmips_bcm6362.h @@ -19,7 +19,9 @@ #define CONFIG_EHCI_MMIO_BIG_ENDIAN #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 +#if defined(CONFIG_USB_OHCI_HCD) #define CONFIG_USB_OHCI_NEW +#endif /* CONFIG_USB_OHCI_HCD */ /* U-Boot */ #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M diff --git a/include/configs/bmips_bcm6368.h b/include/configs/bmips_bcm6368.h index ab5bdac726..4d4403f8d2 100644 --- a/include/configs/bmips_bcm6368.h +++ b/include/configs/bmips_bcm6368.h @@ -19,7 +19,9 @@ #define CONFIG_EHCI_MMIO_BIG_ENDIAN #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 +#if defined(CONFIG_USB_OHCI_HCD) #define CONFIG_USB_OHCI_NEW +#endif /* CONFIG_USB_OHCI_HCD */ /* U-Boot */ #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M -- 2.20.1

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