April 2020 - U-Boot

[PATCH] mtd: nand: pxa3xx: fix raw read when last_chunk_size == 0
by Baruch Siach 26 Apr '20

26 Apr '20

Commit 6293b0361d9 ("mtd: nand: pxa3xx: add raw read support") added the local data_len variable in handle_data_pio() to track read size, but forgot to update the condition of drain_fifo() call. That happens to work when the layout last_chunk_size != 0. But when last_chunk_size == 0, drain_fifo() is not called to read the last chunk, which leads to "Wait timeout!!!" error. Fix this. Fixes: 6293b0361d9 ("mtd: nand: pxa3xx: add raw read support") Cc: Miquel Raynal <miquel.raynal(a)bootlin.com> Signed-off-by: Baruch Siach <baruch(a)tkos.co.il> --- drivers/mtd/nand/raw/pxa3xx_nand.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/nand/raw/pxa3xx_nand.c b/drivers/mtd/nand/raw/pxa3xx_nand.c index 03f210bdb0b3..7e3346dfcc2d 100644 --- a/drivers/mtd/nand/raw/pxa3xx_nand.c +++ b/drivers/mtd/nand/raw/pxa3xx_nand.c @@ -639,7 +639,7 @@ static void handle_data_pio(struct pxa3xx_nand_info *info) DIV_ROUND_UP(info->step_spare_size, 4)); break; case STATE_PIO_READING: - if (info->step_chunk_size) + if (data_len) drain_fifo(info, info->data_buff + info->data_buff_pos, DIV_ROUND_UP(data_len, 4)); -- 2.25.1

2 1

[PATCH v2 0/3] common/board_f: Make reserve_mmu generic
by Ovidiu Panait 26 Apr '20

26 Apr '20

Changes in v2: - split the original patch in 3 parts - add function comments - drop #ifdefs around asm/cache.h includes - drop reserve_mmu function and leave only arch_reserve_mmu For the following suggestion: "Can you please try to use if() instead of #if as much as possible?" I tried replacing in reserve_mmu #if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) with if (!(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))) { ... } but it caused compile issues on different arm platforms such as: ... arch/arm/lib/cache.c: In function 'arm_reserve_mmu': arch/arm/lib/cache.c:134:11: error: 'volatile struct arch_global_data' has no member named 'tlb_size' gd->arch.tlb_size = PGTABLE_SIZE; ^ arch/arm/lib/cache.c:135:28: error: 'volatile struct arch_global_data' has no member named 'tlb_size' gd->relocaddr -= gd->arch.tlb_size; ^ arch/arm/lib/cache.c:140:11: error: 'volatile struct arch_global_data' has no member named 'tlb_addr' gd->arch.tlb_addr = gd->relocaddr; In file included from include/common.h:34:0, from arch/arm/lib/cache.c:9: arch/arm/lib/cache.c:141:52: error: 'volatile struct arch_global_data' has no member named 'tlb_addr' ... Ovidiu Panait (3): common/board_f: Move arm-specific reserve_mmu to arch/arm/lib/cache.c arm: asm/cache.c: Introduce arm_reserve_mmu common/board_f: Make reserve_mmu generic arch/arm/include/asm/cache.h | 11 +++++++++++ arch/arm/lib/cache.c | 33 +++++++++++++++++++++++++++++++++ arch/arm/mach-versal/cpu.c | 3 ++- arch/arm/mach-zynqmp/cpu.c | 3 ++- common/board_f.c | 29 ++--------------------------- include/init.h | 13 ++++++++++++- 6 files changed, 62 insertions(+), 30 deletions(-) -- 2.17.1

3 9

[PATCH] rockchip: rk3399: Add Nanopi M4 2GB board support
by Deepak Das 26 Apr '20

26 Apr '20

commit b2f5da9dd068 ("rockchip: rk3399: Add Nanopi M4 board support") added support for Nanopi M4 board with Dual-Channel 4GB LPDDR3-1866 RAM. This patch adds another variant of NanoPi M4 board with Dual-Channel 2GB DDR3-1866 RAM. Signed-off-by: Deepak Das <deepakdas.linux(a)gmail.com> --- arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3399-nanopi-m4-2gb-u-boot.dtsi | 8 +++ arch/arm/dts/rk3399-nanopi-m4-2gb.dts | 66 +++++++++++++++++++ board/rockchip/evb_rk3399/MAINTAINERS | 7 ++ configs/nanopi-m4-2gb-rk3399_defconfig | 63 ++++++++++++++++++ 5 files changed, 145 insertions(+) create mode 100644 arch/arm/dts/rk3399-nanopi-m4-2gb-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-nanopi-m4-2gb.dts create mode 100644 configs/nanopi-m4-2gb-rk3399_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 59a2713cb2..2bc43a37b4 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -123,6 +123,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ rk3399-leez-p710.dtb \ rk3399-nanopc-t4.dtb \ rk3399-nanopi-m4.dtb \ + rk3399-nanopi-m4-2gb.dtb \ rk3399-nanopi-neo4.dtb \ rk3399-orangepi.dtb \ rk3399-puma-ddr1333.dtb \ diff --git a/arch/arm/dts/rk3399-nanopi-m4-2gb-u-boot.dtsi b/arch/arm/dts/rk3399-nanopi-m4-2gb-u-boot.dtsi new file mode 100644 index 0000000000..a2f9786473 --- /dev/null +++ b/arch/arm/dts/rk3399-nanopi-m4-2gb-u-boot.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Jagan Teki <jagan(a)amarulasolutions.com> + * Copyright (C) 2020 Deepak Das <deepakdas.linux(a)gmail.com> + */ + +#include "rk3399-nanopi4-u-boot.dtsi" +#include "rk3399-sdram-ddr3-1866.dtsi" diff --git a/arch/arm/dts/rk3399-nanopi-m4-2gb.dts b/arch/arm/dts/rk3399-nanopi-m4-2gb.dts new file mode 100644 index 0000000000..60358ab8c7 --- /dev/null +++ b/arch/arm/dts/rk3399-nanopi-m4-2gb.dts @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * FriendlyElec NanoPi M4 board device tree source + * + * Copyright (c) 2018 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyarm.com) + * + * Copyright (c) 2018 Collabora Ltd. + * Copyright (c) 2019 Arm Ltd. + */ + +/dts-v1/; +#include "rk3399-nanopi4.dtsi" + +/ { + model = "FriendlyElec NanoPi M4"; + compatible = "friendlyarm,nanopi-m4", "rockchip,rk3399"; + + vdd_5v: vdd-5v { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v"; + regulator-always-on; + regulator-boot-on; + }; + + vcc5v0_core: vcc5v0-core { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_core"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd_5v>; + }; + + vcc5v0_usb1: vcc5v0-usb1 { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb1"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_usb2: vcc5v0-usb2 { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb2"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&vcc3v3_sys { + vin-supply = <&vcc5v0_core>; +}; + +&u2phy0_host { + phy-supply = <&vcc5v0_usb1>; +}; + +&u2phy1_host { + phy-supply = <&vcc5v0_usb2>; +}; + +&vbus_typec { + regulator-always-on; + vin-supply = <&vdd_5v>; +}; diff --git a/board/rockchip/evb_rk3399/MAINTAINERS b/board/rockchip/evb_rk3399/MAINTAINERS index 0834254f6d..792df1087f 100644 --- a/board/rockchip/evb_rk3399/MAINTAINERS +++ b/board/rockchip/evb_rk3399/MAINTAINERS @@ -42,6 +42,13 @@ S: Maintained F: configs/nanopi-m4-rk3399_defconfig F: arch/arm/dts/rk3399-nanopi-m4-u-boot.dtsi +NANOPI-M4-2GB +M: Jagan Teki <jagan(a)amarulasolutions.com> +M: Deepak Das <deepakdas.linux(a)gmail.com> +S: Maintained +F: configs/nanopi-m4-2gb-rk3399_defconfig +F: arch/arm/dts/rk3399-nanopi-m4-2gb-u-boot.dtsi + NANOPI-NEO4 M: Jagan Teki <jagan(a)amarulasolutions.com> S: Maintained diff --git a/configs/nanopi-m4-2gb-rk3399_defconfig b/configs/nanopi-m4-2gb-rk3399_defconfig new file mode 100644 index 0000000000..93c8db979c --- /dev/null +++ b/configs/nanopi-m4-2gb-rk3399_defconfig @@ -0,0 +1,63 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_ENV_OFFSET=0x3F8000 +CONFIG_ROCKCHIP_RK3399=y +CONFIG_TARGET_EVB_RK3399=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEBUG_UART_BASE=0xFF1A0000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-m4-2gb.dtb" +CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_TPL=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-m4-2gb" +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_USB_KEYBOARD=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_ERRNO_STR=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_BPP16=y +CONFIG_VIDEO_BPP32=y +CONFIG_DISPLAY=y +CONFIG_VIDEO_ROCKCHIP=y +CONFIG_DISPLAY_ROCKCHIP_HDMI=y -- 2.17.1

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[PATCH v2] cmd: mvebu: bubt: fix quoted string split across lines
by Joel Johnson 26 Apr '20

26 Apr '20

Update quoted string alignment to address checkpatch.pl warning originally introduced in commit f60a66ef5d7d ("cmd: mvebu: bubt: show image boot device"). Signed-off-by: Joel Johnson <mrjoel(a)lixil.net> --- I am sort of inferring that this is the desired fix, preferring line length infractions over split quoted strings. As such, I've combined the static part of the string for grepping and left the dynamic parts on the next line. v2 change: - syntax fix --- cmd/mvebu/bubt.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/cmd/mvebu/bubt.c b/cmd/mvebu/bubt.c index dc0ce01c35..204e1afd07 100644 --- a/cmd/mvebu/bubt.c +++ b/cmd/mvebu/bubt.c @@ -730,8 +730,8 @@ static int bubt_check_boot_mode(const struct bubt_dev *dst) for (int i = 0; i < ARRAY_SIZE(a38x_boot_modes); i++) { if (a38x_boot_modes[i].id == hdr->blockid) { - printf("Error: A38x image meant to be " - "booted from \"%s\", not \"%s\"!\n", + printf("Error: A38x image meant to be booted from ", + "\"%s\", not \"%s\"!\n", a38x_boot_modes[i].name, dst->name); return -ENOEXEC; } -- 2.26.2

1 0

[PATCH] cmd: mvebu: bubt: fix quoted string split across lines
by Joel Johnson 26 Apr '20

26 Apr '20

Update quoted string alignment to address checkpatch.pl warning originally introduced in commit f60a66ef5d7d ("cmd: mvebu: bubt: show image boot device"). Signed-off-by: Joel Johnson <mrjoel(a)lixil.net> --- I am sort of inferring that this is the desired fix, preferring line length infractions over split quoted strings. As such, I've combined the static part of the string for grepping and left the dynamic parts on the next line. --- cmd/mvebu/bubt.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/cmd/mvebu/bubt.c b/cmd/mvebu/bubt.c index dc0ce01c35..204e1afd07 100644 --- a/cmd/mvebu/bubt.c +++ b/cmd/mvebu/bubt.c @@ -730,8 +730,8 @@ static int bubt_check_boot_mode(const struct bubt_dev *dst) for (int i = 0; i < ARRAY_SIZE(a38x_boot_modes); i++) { if (a38x_boot_modes[i].id == hdr->blockid) { - printf("Error: A38x image meant to be " - "booted from \"%s\", not \"%s\"!\n", + printf("Error: A38x image meant to be booted from ", + "\"%s\", not \"%s\"!\n", a38x_boot_modes[i].name, dst->name); return -ENOEXEC; } -- 2.26.2

1 0

[PATCH] rockchip: board: roc-pc-rk3399: Remove support for push button
by sunil＠amarulasolutions.com 25 Apr '20

25 Apr '20

From: Suniel Mahesh <sunil(a)amarulasolutions.com> In case of a power interruption, human intervention is required which is not desirable if the device is installed at a remote location. Drop yellow LED as it is not much of use. Keep red LED(diy-led) as it is, to indicate board in full power mode. Signed-off-by: Suniel Mahesh <sunil(a)amarulasolutions.com> --- Note: - patch tested on rk3399-roc-pc - code related to button press is removed --- board/firefly/roc-pc-rk3399/roc-pc-rk3399.c | 16 +--------------- 1 file changed, 1 insertion(+), 15 deletions(-) diff --git a/board/firefly/roc-pc-rk3399/roc-pc-rk3399.c b/board/firefly/roc-pc-rk3399/roc-pc-rk3399.c index de9185a..0fe1914 100644 --- a/board/firefly/roc-pc-rk3399/roc-pc-rk3399.c +++ b/board/firefly/roc-pc-rk3399/roc-pc-rk3399.c @@ -10,7 +10,6 @@ #include <spl_gpio.h> #include <asm/io.h> #include <asm/arch-rockchip/gpio.h> -#include <asm/arch-rockchip/grf_rk3399.h> #ifndef CONFIG_SPL_BUILD int board_early_init_f(void) @@ -34,26 +33,13 @@ out: #if defined(CONFIG_TPL_BUILD) -#define PMUGRF_BASE 0xff320000 #define GPIO0_BASE 0xff720000 int board_early_init_f(void) { struct rockchip_gpio_regs * const gpio0 = (void *)GPIO0_BASE; - struct rk3399_pmugrf_regs * const pmugrf = (void *)PMUGRF_BASE; - /** - * 1. Glow yellow LED, termed as low power - * 2. Poll for on board power key press - * 3. Once 2 done, off yellow and glow red LED, termed as full power - * 4. Continue booting... - */ - spl_gpio_output(gpio0, GPIO(BANK_A, 2), 1); - - spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_A, 5), GPIO_PULL_NORMAL); - while (readl(&gpio0->ext_port) & 0x20); - - spl_gpio_output(gpio0, GPIO(BANK_A, 2), 0); + /* Turn on red LED, indicating full power mode */ spl_gpio_output(gpio0, GPIO(BANK_B, 5), 1); return 0; -- 2.7.4

3 4

[PATCH] ARM: imx: imx8mm: Add missing clock entries for FEC clock
by Marek Vasut 25 Apr '20

25 Apr '20

All the FEC ethernet clock entries for iMX8MM are missing, while they are already present on iMX8MQ. Fill in the nodes on iMX8MM, as the FEC ethernet gets bogus clock information otherwise which makes ethernet inoperable. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Fabio Estevam <festevam(a)gmail.com> Cc: Peng Fan <peng.fan(a)nxp.com> Cc: Stefano Babic <sbabic(a)denx.de> --- arch/arm/mach-imx/imx8m/clock_imx8mm.c | 49 ++++++++++++++++++++++++++ arch/arm/mach-imx/imx8m/clock_slice.c | 25 +++++++++++++ 2 files changed, 74 insertions(+) diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c index c423ac0058..d123ba1625 100644 --- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c +++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c @@ -578,3 +578,52 @@ u32 mxc_get_clock(enum mxc_clock clk) return 0; } + +#ifdef CONFIG_FEC_MXC +int set_clk_enet(enum enet_freq type) +{ + u32 target; + u32 enet1_ref; + + switch (type) { + case ENET_125MHZ: + enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK; + break; + case ENET_50MHZ: + enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK; + break; + case ENET_25MHZ: + enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK; + break; + default: + return -EINVAL; + } + + /* disable the clock first */ + clock_enable(CCGR_ENET1, 0); + clock_enable(CCGR_SIM_ENET, 0); + + /* set enet axi clock 266Mhz */ + target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M | + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | + CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1); + clock_set_target_val(ENET_AXI_CLK_ROOT, target); + + target = CLK_ROOT_ON | enet1_ref | + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | + CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1); + clock_set_target_val(ENET_REF_CLK_ROOT, target); + + target = CLK_ROOT_ON | + ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK | + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | + CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4); + clock_set_target_val(ENET_TIMER_CLK_ROOT, target); + + /* enable clock */ + clock_enable(CCGR_SIM_ENET, 1); + clock_enable(CCGR_ENET1, 1); + + return 0; +} +#endif diff --git a/arch/arm/mach-imx/imx8m/clock_slice.c b/arch/arm/mach-imx/imx8m/clock_slice.c index 8b7a4dad65..9e84e8d5b1 100644 --- a/arch/arm/mach-imx/imx8m/clock_slice.c +++ b/arch/arm/mach-imx/imx8m/clock_slice.c @@ -482,6 +482,16 @@ static struct clk_root_map root_array[] = { SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, SYSTEM_PLL3_CLK} }, + {MAIN_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 0, + {OSC_24M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_1000M_CLK, + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL1_100M_CLK} + }, + {ENET_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 1, + {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK, + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL3_CLK} + }, {NAND_USDHC_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 2, {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_133M_CLK, @@ -509,6 +519,21 @@ static struct clk_root_map root_array[] = { SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK} }, + {ENET_REF_CLK_ROOT, IP_CLOCK_SLICE, 19, + {OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_50M_CLK, + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK, + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, EXT_CLK_4} + }, + {ENET_TIMER_CLK_ROOT, IP_CLOCK_SLICE, 20, + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, AUDIO_PLL1_CLK, + EXT_CLK_1, EXT_CLK_2, EXT_CLK_3, EXT_CLK_4, + VIDEO_PLL_CLK} + }, + {ENET_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 21, + {OSC_24M_CLK, SYSTEM_PLL2_50M_CLK, SYSTEM_PLL2_125M_CLK, + SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_500M_CLK, + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK} + }, {UART1_CLK_ROOT, IP_CLOCK_SLICE, 30, {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK, -- 2.25.1

2 1

[PATCH] arm: dts: rockchip: rk3399-roc-pc: Enable FE1.1 USB 2.0 HUB on roc-rk3399-pc
by sunil＠amarulasolutions.com 25 Apr '20

25 Apr '20

From: Suniel Mahesh <sunil(a)amarulasolutions.com> roc-rk3399-pc has an FE1.1 USB 2.0 HUB which connects two USB ports (HOST1 and HOST2). For end devices to work we need to enable USB hub so that HOST detects there presence and enumerates them accordingly. This requires explicit pinctrl within gpio enablement. Signed-off-by: Suniel Mahesh <sunil(a)amarulasolutions.com> --- Note: 1. tested this on roc-rk3399-pc board version roc-rk3399-pc-v1.1-a 2018-9-25 2. after this changeset, HOST1 works but HOST2 still doesnt work. I have tested them with linux-next, linux-rockchip and Firefly's source (both u-boot and kernel), HOST2 doesn't work. 3. Request to test this changetest who have access to target and please advice on HOST2 --- arch/arm/dts/rk3399-roc-pc-u-boot.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi b/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi index 5746442..598e0e2 100644 --- a/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi +++ b/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi @@ -14,6 +14,16 @@ chosen { u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc; }; + + vcc_hub_en: vcc_hub_en-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 RK_PA4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hub_rst>; + regulator-name = "vcc_hub_en"; + regulator-always-on; + }; }; &vdd_log { -- 2.7.4

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[PULL] Pull request: u-boot-stm/master =u-boot-stm32-20200401
by Patrick DELAUNAY 25 Apr '20

25 Apr '20

Hi Tom, Please pull the latest STM32 master bugfix for v2020.04 = u-boot-stm32-20200401 With the following changes: - Fix device tree of Avenger96 board from Arrow Electronics and add compatibility with stm32mp15_dhcom_basic_defconfig CI status: Failed for vexpress_ca9x4 test.py https://gitlab.denx.de/u-boot/custodians/u-boot-stm/pipelines/2592 But local compilation is OK with buildman on stm32 targets. I think it is enough as the Marek's patches only update the dh board code and the AV96 device tree. Thanks, Patrick The following changes since commit af827140e5965e5bb2bcad1c53ca8419b428ff6d: vexpress_ca9x4: Enable use of correct DTB file and restore EFI loader. (2020-03-23 16:11:46 -0400) are available in the Git repository at: https://gitlab.denx.de/u-boot/custodians/u-boot-stm.git tags/u-boot-stm32-20200401 for you to fetch changes up to 2f3c4b8a0f303edbea9fc112a49e546cf03776b0: ARM: dts: stm32: Repair PMIC configuration on AV96 (2020-04-01 11:58:00 +0200) ---------------------------------------------------------------- - Fix device tree of Avenger96 board from Arrow Electronics and add compatibility with stm32mp15_dhcom_basic_defconfig ---------------------------------------------------------------- Marek Vasut (12): ARM: dts: stm32: Repair SD1 pre-reloc pinmux DT node on AV96 ARM: dts: stm32: Add alternate pinmux for SDMMC1 direction pins ARM: dts: stm32: Repair SDMMC1 operation on AV96 ARM: dts: stm32: Add alternate pinmux for SDMMC2 pins 4-7 ARM: dts: stm32: Repair SDMMC2 operation ARM: dts: stm32: Add QSPI NOR on AV96 ARM: dts: stm32: Use DT alias for the configuration EEPROM ARM: dts: stm32: Add configuration EEPROM on AV96 ARM: dts: stm32: Add alternate pinmux for ethernet RGMII ARM: dts: stm32: Repair ethernet operation on AV96 ARM: dts: stm32: Add missing ethernet PHY reset on AV96 ARM: dts: stm32: Repair PMIC configuration on AV96 arch/arm/dts/stm32mp157-pinctrl.dtsi | 96 +++++++++++++++++++++++++++++++++++++++++ arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi | 9 ++-- arch/arm/dts/stm32mp157a-avenger96.dts | 79 ++++++++++++++++++++++++++++----- arch/arm/dts/stm32mp15xx-dhcom.dtsi | 6 ++- board/dhelectronics/dh_stm32mp1/board.c | 15 +++---- 5 files changed, 182 insertions(+), 23 deletions(-)

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[PATCH v4 0/5] riscv: sifive/fu540: Enable SPI-NOR support
by Jagan Teki 25 Apr '20

25 Apr '20

This is series v4 for SPI-NOR support on SiFive FU540 platform with HiFive Unleashed board. Here is the previous version changes[1]. All patches on top of u-boot-spi/master. Changes for v4: - add spi-mem exec_op - rebase on master Changes for v3: - fixed QPP support - dropped sf commands log [1] https://patchwork.ozlabs.org/project/uboot/cover/20200420125238.9610-1-jaga… Any inputs? Jagan. Jagan Teki (5): spi: sifive: Add spi-mem exec op spi: sifive: Fix format register proto field spi: sifive: Fix QPP transfer riscv: dts: hifive-unleashed-a00: Add -u-boot.dtsi sifive: fu540: Enable spi-nor flash support .../dts/hifive-unleashed-a00-u-boot.dtsi | 11 ++ board/sifive/fu540/Kconfig | 3 + drivers/spi/spi-sifive.c | 156 +++++++++++++++--- 3 files changed, 146 insertions(+), 24 deletions(-) create mode 100644 arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi -- 2.17.1

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