February 2020 - U-Boot

[PATCH] mx7ulp: Only enable LDO if it is not already enabled
by Fabio Estevam 03 Feb '20

03 Feb '20

LDO mode may be already enabled by the ROM and enabling it again can cause U-Boot to hang. Avoid this problem by only enabling LDO mode if it is initially disabled. Reported-by: Jorge Ramirez-Ortiz <jorge(a)foundries.io> Signed-off-by: Fabio Estevam <festevam(a)gmail.com> --- arch/arm/mach-imx/mx7ulp/soc.c | 32 +++++++++++++++++--------------- 1 file changed, 17 insertions(+), 15 deletions(-) diff --git a/arch/arm/mach-imx/mx7ulp/soc.c b/arch/arm/mach-imx/mx7ulp/soc.c index 8345b01398..4d84193dec 100644 --- a/arch/arm/mach-imx/mx7ulp/soc.c +++ b/arch/arm/mach-imx/mx7ulp/soc.c @@ -117,11 +117,28 @@ void init_wdog(void) disable_wdog(WDG2_RBASE); } +#define PMC0_BASE_ADDR 0x410a1000 +#define PMC0_CTRL 0x28 +#define PMC0_CTRL_LDOEN BIT(31) + +static bool ldo_mode_is_enabled(void) +{ + unsigned int reg; + + reg = readl(PMC0_BASE_ADDR + PMC0_CTRL); + if (reg & PMC0_CTRL_LDOEN) + return true; + else + return false; +} #if defined(CONFIG_LDO_ENABLED_MODE) static void init_ldo_mode(void) { unsigned int reg; + if (ldo_mode_is_enabled()) + return; + /* Set LDOOKDIS */ setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_LDOOKDIS); @@ -190,21 +207,6 @@ const char *get_imx_type(u32 imxtype) return "7ULP"; } -#define PMC0_BASE_ADDR 0x410a1000 -#define PMC0_CTRL 0x28 -#define PMC0_CTRL_LDOEN BIT(31) - -static bool ldo_mode_is_enabled(void) -{ - unsigned int reg; - - reg = readl(PMC0_BASE_ADDR + PMC0_CTRL); - if (reg & PMC0_CTRL_LDOEN) - return true; - else - return false; -} - int print_cpuinfo(void) { u32 cpurev; -- 2.17.1

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[PATCH 0/3] Enable octal read support for mt35xu* flashes
by Kuldeep Singh 03 Feb '20

03 Feb '20

Patch series enable octal read(1-1-8) support for LX2160ARDB and LS1028ARDB which have mt35xu512aba and mt35xu02g flashes respectively. mt35xu512aba and mt35xu02g flashes support SINGLE and OCTAL I/O. Previously, 1 bit mode was used in u-boot and now use octal mode for the flashes. Also add RX and TX buswidth in qspi dts entry to use 1-1-8 mode. DTS entries can be merged once patch[1] is merged. No dependency on framework patch. [1]https://patchwork.ozlabs.org/project/uboot/list/?series=141023 Kuldeep Singh (3): mtd: spi-nor: Enable SPI_NOR_OCTAL_READ flag for mt35xu* arm: dts: ls1028a: Add RX,TX buswidth in qspi to use octal mode arm: dts: lx2160a: Add RX,TX buswidth in qspi to use octal mode arch/arm/dts/fsl-ls1028a-qds.dts | 2 ++ arch/arm/dts/fsl-ls1028a-rdb.dts | 2 ++ arch/arm/dts/fsl-lx2160a-rdb.dts | 4 ++++ drivers/mtd/spi/spi-nor-ids.c | 4 ++-- 4 files changed, 10 insertions(+), 2 deletions(-) -- 2.7.4

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[PATCH 1/2] rockchip: rk3399: split roc-rk3399-pc out of evb_rk3399
by sunil＠amarulasolutions.com 03 Feb '20

03 Feb '20

From: Suniel Mahesh <sunil(a)amarulasolutions.com> roc-rk3399-pc board has one user button & three user LED's. Currently we don't have any code support for these devices. Since button and LED's are specific to roc-rk3399-pc board, split it into its own board file and add any code support here. Signed-off-by: Suniel Mahesh <sunil(a)amarulasolutions.com> --- arch/arm/mach-rockchip/rk3399/Kconfig | 20 +++++++++++++++++++ board/firefly/roc-rk3399-pc/Kconfig | 16 +++++++++++++++ board/firefly/roc-rk3399-pc/MAINTAINERS | 6 ++++++ board/firefly/roc-rk3399-pc/Makefile | 7 +++++++ board/firefly/roc-rk3399-pc/roc-rk3399-pc.c | 30 +++++++++++++++++++++++++++++ board/rockchip/evb_rk3399/MAINTAINERS | 6 ------ configs/roc-pc-rk3399_defconfig | 1 + include/configs/roc-rk3399-pc.h | 22 +++++++++++++++++++++ 8 files changed, 102 insertions(+), 6 deletions(-) create mode 100644 board/firefly/roc-rk3399-pc/Kconfig create mode 100644 board/firefly/roc-rk3399-pc/MAINTAINERS create mode 100644 board/firefly/roc-rk3399-pc/Makefile create mode 100644 board/firefly/roc-rk3399-pc/roc-rk3399-pc.c create mode 100644 include/configs/roc-rk3399-pc.h diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig index f994152..23214ca 100644 --- a/arch/arm/mach-rockchip/rk3399/Kconfig +++ b/arch/arm/mach-rockchip/rk3399/Kconfig @@ -81,6 +81,25 @@ config TARGET_ROCKPRO64_RK3399 * GPIO expansion ports * DC 12V/2A +config TARGET_ROC_RK3399_PC + bool "Firefly ROC-RK3399-PC board" + help + ROC-RK3399-PC is SBC produced by Firefly. Key features: + + * Rockchip RK3399 + * 4GB Dual-Channel LPDDR4 64-bit + * SD card slot + * eMMC socket + * 16MB SPI Flash + * Gigabit ethernet + * PCIe + * HDMI In/Out, DP, MIPI DSI/CSI, eDP + * USB 3.0, 2.0 + * USB Type C power and data + * GPIO expansion ports + * wide voltage input(5V-15V), dual cell battery + * Wifi/BT accessible via expansion board M.2 + endchoice config ROCKCHIP_BOOT_MODE_REG @@ -128,5 +147,6 @@ source "board/theobroma-systems/puma_rk3399/Kconfig" source "board/vamrs/rock960_rk3399/Kconfig" source "board/google/gru/Kconfig" source "board/pine64/rockpro64_rk3399/Kconfig" +source "board/firefly/roc-rk3399-pc/Kconfig" endif diff --git a/board/firefly/roc-rk3399-pc/Kconfig b/board/firefly/roc-rk3399-pc/Kconfig new file mode 100644 index 0000000..26dce89 --- /dev/null +++ b/board/firefly/roc-rk3399-pc/Kconfig @@ -0,0 +1,16 @@ +if TARGET_ROC_RK3399_PC + +config SYS_BOARD + default "roc-rk3399-pc" + +config SYS_VENDOR + default "firefly" + +config SYS_CONFIG_NAME + default "roc-rk3399-pc" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif + diff --git a/board/firefly/roc-rk3399-pc/MAINTAINERS b/board/firefly/roc-rk3399-pc/MAINTAINERS new file mode 100644 index 0000000..0dbd953 --- /dev/null +++ b/board/firefly/roc-rk3399-pc/MAINTAINERS @@ -0,0 +1,6 @@ +ROC-RK3399-PC +M: Levin Du <djw(a)t-chip.com.cn> +S: Maintained +F: board/firefly/roc-rk3399-pc +F: include/configs/roc-rk3399-pc.h +F: configs/roc-pc-rk3399_defconfig diff --git a/board/firefly/roc-rk3399-pc/Makefile b/board/firefly/roc-rk3399-pc/Makefile new file mode 100644 index 0000000..200dab0 --- /dev/null +++ b/board/firefly/roc-rk3399-pc/Makefile @@ -0,0 +1,7 @@ +# +# (C) Copyright 2016 Rockchip Electronics Co., Ltd +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += roc-rk3399-pc.o diff --git a/board/firefly/roc-rk3399-pc/roc-rk3399-pc.c b/board/firefly/roc-rk3399-pc/roc-rk3399-pc.c new file mode 100644 index 0000000..b9049ab --- /dev/null +++ b/board/firefly/roc-rk3399-pc/roc-rk3399-pc.c @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + */ + +#include <common.h> +#include <dm.h> +#include <asm/arch-rockchip/periph.h> +#include <power/regulator.h> + +#ifndef CONFIG_SPL_BUILD +int board_early_init_f(void) +{ + struct udevice *regulator; + int ret; + + ret = regulator_get_by_platname("vcc5v0_host", &regulator); + if (ret) { + debug("%s vcc5v0_host init fail! ret %d\n", __func__, ret); + goto out; + } + + ret = regulator_set_enable(regulator, true); + if (ret) + debug("%s vcc5v0-host-en set fail! ret %d\n", __func__, ret); + +out: + return 0; +} +#endif diff --git a/board/rockchip/evb_rk3399/MAINTAINERS b/board/rockchip/evb_rk3399/MAINTAINERS index eab4c4c..0834254 100644 --- a/board/rockchip/evb_rk3399/MAINTAINERS +++ b/board/rockchip/evb_rk3399/MAINTAINERS @@ -55,12 +55,6 @@ F: configs/orangepi-rk3399_defconfig F: arch/arm/dts/rk3399-u-boot.dtsi F: arch/arm/dts/rk3399-orangepi-u-boot.dtsi -ROC-RK3399-PC -M: Levin Du <djw(a)t-chip.com.cn> -S: Maintained -F: configs/roc-pc-rk3399_defconfig -F: arch/arm/dts/rk3399-roc-pc-u-boot.dtsi - ROCK-PI-4 M: Akash Gajjar <akash(a)openedev.com> M: Jagan Teki <jagan(a)amarulasolutions.com> diff --git a/configs/roc-pc-rk3399_defconfig b/configs/roc-pc-rk3399_defconfig index 8204e00..c7187dc 100644 --- a/configs/roc-pc-rk3399_defconfig +++ b/configs/roc-pc-rk3399_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_ROCKCHIP_RK3399=y +CONFIG_TARGET_ROC_RK3399_PC=y CONFIG_NR_DRAM_BANKS=1 CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 diff --git a/include/configs/roc-rk3399-pc.h b/include/configs/roc-rk3399-pc.h new file mode 100644 index 0000000..3fd1062 --- /dev/null +++ b/include/configs/roc-rk3399-pc.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + */ + +#ifndef __ROC_PC_RK3399_H +#define __ROC_PC_RK3399_H + +#define ROCKCHIP_DEVICE_SETTINGS \ + "stdin=serial,cros-ec-keyb\0" \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +#include <configs/rk3399_common.h> + +#if defined(CONFIG_ENV_IS_IN_MMC) +# define CONFIG_SYS_MMC_ENV_DEV 0 +#endif + +#define SDRAM_BANK_SIZE (2UL << 30) + +#endif -- 2.7.4

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[PATCH v3 1/4] serial: ns16550: Support run-time configuration
by Simon Glass 03 Feb '20

03 Feb '20

At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg(a)chromium.org> --- Changes in v3: - Rewrite the conditional logic to a fix a bug and match serial_xx_shift() - Add a separate flag for whether to use endian-aware out() functions Changes in v2: - runtime -> run-time - Enable run-time config for slimbootloader too - Improve Kconfig help based on Bin's comments - Use ns16550 in patch subject drivers/serial/Kconfig | 21 ++++++++++++++ drivers/serial/ns16550.c | 59 ++++++++++++++++++++++++++++++++++------ include/ns16550.h | 16 ++++++++++- 3 files changed, 87 insertions(+), 9 deletions(-) diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index ece7d87d4c..472a9f0929 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -598,6 +598,27 @@ config SYS_NS16550 be used. It can be a constant or a function to get clock, eg, get_serial_clock(). +config NS16550_DYNAMIC + bool "Allow NS16550 to be configured at runtime" + default y if SYS_COREBOOT || SYS_SLIMBOOTLOADER + help + Enable this option to allow device-tree control of the driver. + + Normally this driver is controlled by the following options: + + CONFIG_SYS_NS16550_PORT_MAPPED - indicates that port I/O is used for + access. If not enabled, then the UART is memory-mapped. + CONFIG_SYS_NS16550_MEM32 - if memory-mapped, indicates that 32-bit + access should be used (instead of 8-bit) + CONFIG_SYS_NS16550_REG_SIZE - indicates register width and also + endianness. If positive, big-endian access is used. If negative, + little-endian is used. + + It is not a good practice for a driver to be statically configured, + since it prevents the same driver being used for different types of + UARTs in a system. This option avoids this problem at the cost of a + slightly increased code size. + config INTEL_MID_SERIAL bool "Intel MID platform UART support" depends on DM_SERIAL && OF_CONTROL diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index 754b6e9921..eacca5b703 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -92,19 +92,59 @@ static inline int serial_in_shift(void *addr, int shift) #define CONFIG_SYS_NS16550_CLK 0 #endif +static void serial_out_dynamic(struct ns16550_platdata *plat, u8 *addr, + int value) +{ + if (plat->flags & NS16550_FLAG_IO) { + outb(value, addr); + } else if (plat->reg_width == 4) { + if (plat->flags & NS16550_FLAG_ENDIAN) { + if (plat->flags & NS16550_FLAG_BE) + out_be32(addr, value); + else + out_le32(addr, value); + } else { + writel(value, addr); + } + } else if (plat->flags & NS16550_FLAG_BE) { + writeb(value, addr + (1 << plat->reg_shift) - 1); + } else { + writeb(value, addr); + } +} + +static int serial_in_dynamic(struct ns16550_platdata *plat, u8 *addr) +{ + if (plat->flags & NS16550_FLAG_IO) { + return inb(addr); + } else if (plat->reg_width == 4) { + if (plat->flags & NS16550_FLAG_ENDIAN) { + if (plat->flags & NS16550_FLAG_BE) + return in_be32(addr); + else + return in_le32(addr); + } else { + return readl(addr); + } + } else if (plat->flags & NS16550_FLAG_BE) { + return readb(addr + (1 << plat->reg_shift) - 1); + } else { + return readb(addr); + } +} + static void ns16550_writeb(NS16550_t port, int offset, int value) { struct ns16550_platdata *plat = port->plat; unsigned char *addr; offset *= 1 << plat->reg_shift; - addr = (unsigned char *)plat->base + offset; + addr = (unsigned char *)plat->base + offset + plat->reg_offset; - /* - * As far as we know it doesn't make sense to support selection of - * these options at run-time, so use the existing CONFIG options. - */ - serial_out_shift(addr + plat->reg_offset, plat->reg_shift, value); + if (IS_ENABLED(CONFIG_NS16550_DYNAMIC)) + serial_out_dynamic(plat, addr, value); + else + serial_out_shift(addr, plat->reg_shift, value); } static int ns16550_readb(NS16550_t port, int offset) @@ -113,9 +153,12 @@ static int ns16550_readb(NS16550_t port, int offset) unsigned char *addr; offset *= 1 << plat->reg_shift; - addr = (unsigned char *)plat->base + offset; + addr = (unsigned char *)plat->base + offset + plat->reg_offset; - return serial_in_shift(addr + plat->reg_offset, plat->reg_shift); + if (IS_ENABLED(CONFIG_NS16550_DYNAMIC)) + return serial_in_dynamic(plat, addr); + else + return serial_in_shift(addr, plat->reg_shift); } static u32 ns16550_getfcr(NS16550_t port) diff --git a/include/ns16550.h b/include/ns16550.h index 701efeea85..18c9077755 100644 --- a/include/ns16550.h +++ b/include/ns16550.h @@ -31,6 +31,9 @@ #define CONFIG_SYS_NS16550_REG_SIZE (-1) #endif +#ifdef CONFIG_NS16550_DYNAMIC +#define UART_REG(x) unsigned char x +#else #if !defined(CONFIG_SYS_NS16550_REG_SIZE) || (CONFIG_SYS_NS16550_REG_SIZE == 0) #error "Please define NS16550 registers size." #elif defined(CONFIG_SYS_NS16550_MEM32) && !defined(CONFIG_DM_SERIAL) @@ -44,14 +47,24 @@ unsigned char x; \ unsigned char postpad_##x[-CONFIG_SYS_NS16550_REG_SIZE - 1]; #endif +#endif /* CONFIG_NS16550_DYNAMIC */ + +enum ns16550_flags { + NS16550_FLAG_IO = 1 << 0, /* Use I/O access (else mem-mapped) */ + NS16550_FLAG_ENDIAN = 1 << 1, /* Use out_le/be_32() */ + NS16550_FLAG_BE = 1 << 2, /* Big-endian access (else little) */ +}; /** * struct ns16550_platdata - information about a NS16550 port * * @base: Base register address - * @reg_width: IO accesses size of registers (in bytes) + * @reg_width: IO accesses size of registers (in bytes, 1 or 4) * @reg_shift: Shift size of registers (0=byte, 1=16bit, 2=32bit...) + * @reg_offset: Offset to start of registers (normally 0) * @clock: UART base clock speed in Hz + * @fcr: Offset of FCR register (normally UART_FCR_DEFVAL) + * @flags: A few flags (enum ns16550_flags) * @bdf: PCI slot/function (pci_dev_t) */ struct ns16550_platdata { @@ -61,6 +74,7 @@ struct ns16550_platdata { int reg_offset; int clock; u32 fcr; + int flags; #if defined(CONFIG_PCI) && defined(CONFIG_SPL) int bdf; #endif -- 2.24.1.735.g03f4e72817-goog

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[RFC PATCH 0/4] x86: Move ITSS from Apollo Lake to a more generic location
by Wolfgang Wallner 03 Feb '20

03 Feb '20

The Interrupt Timer Subsystem (ITSS) is not specific to Apollo Lake, so move it to a more generic location. Additionally, the series adds the term "Interrupt Timer Subsystem" for ITSS in the file descriptions. Moving the ITSS implementation out of the Apllo Lake-specific folders not only allows to use this driver on other platforms, it is also useful for Apollo Lake when U-Boot is chain-loaded via coreboot (in which case the files within arch/x86/cpu/apollolake would not be compiled and the include/asm/arch-symlink points to arch-coreboot instead of arch-apollolake). Wolfgang Wallner (4): x86: apl: Add the term "Interrupt Timer Subsystem" to ITSS files x86: Move itss.h from Apollo Lake to the generic x86 include directory x86: Move itss.c from Apollo Lake to a more generic location x86: itss: Remove apl-prefix arch/x86/cpu/apollolake/Makefile | 1 - arch/x86/cpu/intel_common/Makefile | 1 + .../cpu/{apollolake => intel_common}/itss.c | 60 +++++++++---------- arch/x86/dts/chromebook_coral.dts | 2 +- .../include/asm/{arch-apollolake => }/itss.h | 2 + drivers/pinctrl/intel/pinctrl.c | 2 +- 6 files changed, 35 insertions(+), 33 deletions(-) rename arch/x86/cpu/{apollolake => intel_common}/itss.c (73%) rename arch/x86/include/asm/{arch-apollolake => }/itss.h (97%) -- 2.25.0

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[PATCH 0/3] gpio: intel_gpio: Fix Intel gpio driver
by Wolfgang Wallner 03 Feb '20

03 Feb '20

This series fixes some issues in the Intel gpio driver. I have tested it on an Apollo Lake device, where U-Boot is booted as a coreboot payload. Wolfgang Wallner (3): gpio: intel_gpio: Pass pinctrl device to pcr_clrsetbits32() gpio: intel_gpio: Clear tx state bit when setting output gpio: intel_gpio: Fix register/bit offsets intel_gpio_get_value() drivers/gpio/intel_gpio.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) -- 2.24.1

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[RFC] azure: Move to vs2017-win2016 platform build host
by Tom Rini 03 Feb '20

03 Feb '20

Azure is moving to remove the vs2015-win2012r2 platform build host. The two suggested new platforms to use are vs2017-win2016 and windows-2019. For now, move up to vs2017-win2016. Cc: Bin Meng <bmeng.cn(a)gmail.com> Signed-off-by: Tom Rini <trini(a)konsulko.com> --- I'm sending this as RFC as it fails to build for i686 but builds for x86_64 and I'm out of my depth on fixing that. Can you please take a look Bin? Thanks! --- .azure-pipelines.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml index 916ab84ea0c4..a0713dd66c0a 100644 --- a/.azure-pipelines.yml +++ b/.azure-pipelines.yml @@ -1,5 +1,5 @@ variables: - windows_vm: vs2015-win2012r2 + windows_vm: vs2017-win2016 ubuntu_vm: ubuntu-18.04 ci_runner_image: trini/u-boot-gitlab-ci-runner:bionic-20200112-17Jan2020 # Add '-u 0' options for Azure pipelines, otherwise we get "permission -- 2.17.1

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[RFC PATCH] spi: ich: Drop while loop in hardware sequencing erase case
by Wolfgang Wallner 03 Feb '20

03 Feb '20

When ich_spi_exec_op_hwseq() is called to erase a 4k block (opcode = SPINOR_OP_BE_4K), it expects to find a length value in op->data.nbytes, but that value is always 0. As a result, the while loop is never executed and no erase is carried out. Fix this by dropping the loop code entirely, only keeping the relevant parts of the loop body. Signed-off-by: Wolfgang Wallner <wolfgang.wallner(a)br-automation.com> --- I tried using an SPI NOR flash on an Apollo Lake based board, but calling 'sf erase' fails to erase the flash memory, it looks like it does nothing. Debugging the issue I find that the function ich_spi_exec_op_hwseq() in drivers/spi/ich.c tries to loop over the provided number of bytes, but that value is always 0. The spi operation that is handled by ich_spi_exec_op_hwseq() is initially created in the function spi_nor_erase_sector(), and handed down via the following call stack: spi_nor_erase_sector() in drivers/mtd/spi/spi-nor-core.c spi_mem_exec_op() in drivers/spi/spi-mem.c spi_mem_exec_op() calls ops->mem_ops->exec_op() which points to ich_spi_exec_op() ich_spi_exec_op() in drivers/spi/ich.c ich_spi_exec_op_hwseq() in drivers/spi/ich.c The number of bytes (op.data.nbytes) is always set to 0 in spi_nor_erase_sector(), thus the loop in ich_spi_exec_op_hwseq can never be executed. I tried to fix this by dropping the loop code entirely, and with this change 'sf erase' works for me as expected. The code in spi_nor_erase_sector() that sets data.nbytes always to 0 was introduced in commit f909ddb3e177 ("mtd: spi: Replace ad-hoc default implementation with spi_mem_op"), but that commit is older then the code in ich_spi_exec_op_hwseq() which was introduced in commit 1facebd18fd7 ("spi: ich: Support hardware sequencing"). I would like to ask for feedback on the provided patch. drivers/spi/ich.c | 12 ++---------- 1 file changed, 2 insertions(+), 10 deletions(-) diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c index 133b25b72e..a9d7715a55 100644 --- a/drivers/spi/ich.c +++ b/drivers/spi/ich.c @@ -562,16 +562,8 @@ static int ich_spi_exec_op_hwseq(struct spi_slave *slave, return 0; /* ignore */ case SPINOR_OP_BE_4K: cycle = HSFSTS_CYCLE_4K_ERASE; - while (len) { - uint xfer_len = 0x1000; - - ret = exec_sync_hwseq_xfer(regs, cycle, offset, 0); - if (ret) - return ret; - offset += xfer_len; - len -= xfer_len; - } - return 0; + ret = exec_sync_hwseq_xfer(regs, cycle, offset, 0); + return ret; default: debug("Unknown cycle %x\n", op->cmd.opcode); return -EINVAL; -- 2.24.1

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[PATCH v1 1/2] x86: edison: Enable command line editing
by Andy Shevchenko 03 Feb '20

03 Feb '20

From: Marek Vasut <marex(a)denx.de> Enable command line editing, because it is extremely convenient. Signed-off-by: Marek Vasut <marex(a)denx.de> Signed-off-by: Andy Shevchenko <andriy.shevchenko(a)linux.intel.com> --- configs/edison_defconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/configs/edison_defconfig b/configs/edison_defconfig index 14b2eec3ba..124f0f628f 100644 --- a/configs/edison_defconfig +++ b/configs/edison_defconfig @@ -9,7 +9,6 @@ CONFIG_SMP=y CONFIG_BOARD_EARLY_INIT_R=y CONFIG_LAST_STAGE_INIT=y CONFIG_HUSH_PARSER=y -# CONFIG_CMDLINE_EDITING is not set CONFIG_CMD_CPU=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y -- 2.24.1

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[PATCH 1/2] configs: ls2080ardb: Make QSPI_MC_INIT access flash memory as per spi-mem
by Kuldeep Singh 03 Feb '20

03 Feb '20

MC_INIT command currently access spi-nor flash memory directly. As per spi-mem framework, flash memory access via absolute addresses is no more possible. Use flash APIs to access memory instead of directly using it. Signed-off-by: Kuldeep Singh <kuldeep.singh(a)nxp.com> --- include/configs/ls2080ardb.h | 22 +++++++++++++++------- 1 file changed, 15 insertions(+), 7 deletions(-) diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index de14fb4..6a74f62 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -322,10 +322,14 @@ unsigned long get_board_sys_clk(void); #ifdef CONFIG_TFABOOT #define QSPI_MC_INIT_CMD \ + "sf probe 0:0; sf read 0x80A00000 0xA00000 0x100000; " \ + "sf read 0x80E00000 0xE00000 0x100000; " \ "env exists secureboot && " \ - "esbc_validate 0x20700000 && " \ - "esbc_validate 0x20740000;" \ - "fsl_mc start mc 0x20a00000 0x20e00000 \0" + "sf read 0x80700000 0x700000 0x40000 && " \ + "sf read 0x80740000 0x740000 0x40000 && " \ + "esbc_validate 0x80700000 && " \ + "esbc_validate 0x80740000; " \ + "fsl_mc start mc 0x80A00000 0x80E00000 \0" #define SD_MC_INIT_CMD \ "mmcinfo;mmc read 0x80a00000 0x5000 0x1200;" \ "mmc read 0x80e00000 0x7000 0x800;" \ @@ -343,10 +347,14 @@ unsigned long get_board_sys_clk(void); #else #ifdef CONFIG_QSPI_BOOT #define MC_INIT_CMD \ - "mcinitcmd=env exists secureboot && " \ - "esbc_validate 0x20700000 && " \ - "esbc_validate 0x20740000;" \ - "fsl_mc start mc 0x20a00000 0x20e00000 \0" + "mcinitcmd=sf probe 0:0;sf read 0x80A00000 0xA00000 0x100000; " \ + " sf read 0x80E00000 0xE00000 0x100000; " \ + "env exists secureboot && " \ + "sf read 0x80700000 0x700000 0x40000 && " \ + "sf read 0x80740000 0x740000 0x40000 && " \ + "esbc_validate 0x80700000 && " \ + "esbc_validate 0x80740000; " \ + "fsl_mc start mc 0x80A00000 0x80E00000 \0" #elif defined(CONFIG_SD_BOOT) #define MC_INIT_CMD \ "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;" \ -- 2.7.4

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