February 2020 - U-Boot

[PATCH v3 0/2] gpio: add possibility to search for gpio label name
by Heiko Schocher 15 May '20

15 May '20

search for gpio label if gpio name from bankname is not found. This makes sense on boards with different hardware verions. You can now search for the gpio label name, and can give the gpio a unique name. The real gpio pin number is not needed in board code anymore. while at it add basic gpio hog test functions in seperate patch. Travis build: https://travis-ci.org/hsdenx/u-boot-test/builds/645826819 Changes in v3: - add comment from Simon Glass make this new function configurable through Kconfig option DM_GPIO_LOOKUP_LABEL Changes in v2: - add basic gpio hog test functions - add comment from Simon Glass move code into seperate function dm_gpio_lookup_label() add test if dm_gpio_lookup_label() works Heiko Schocher (2): sandbox, test: add test for GPIO_HOG function gpio: search for gpio label if gpio is not found through bank name arch/sandbox/dts/test.dts | 24 +++++++++++++++ configs/sandbox64_defconfig | 1 + configs/sandbox_defconfig | 1 + configs/sandbox_flattree_defconfig | 1 + configs/sandbox_spl_defconfig | 1 + drivers/gpio/Kconfig | 22 ++++++++++++++ drivers/gpio/gpio-uclass.c | 47 ++++++++++++++++++++++++++++++ test/dm/gpio.c | 30 +++++++++++++++++++ 8 files changed, 127 insertions(+) -- 2.24.1

4 12

[PATCH 2/2] rpi: use the newly-added RPI_EFI_NR_SPIN_PAGES
by kevans＠FreeBSD.org 13 May '20

13 May '20

From: Kyle Evans <kevans(a)FreeBSD.org> Some systems may use a slightly larger stub to do PSCI for booting the RPi family. The number of pages has been made configurable so that operating systems building U-Boot for use in these kinds of environments can reserve more memory in the EFI memory map. Signed-off-by: Kyle Evans <kevans(a)FreeBSD.org> --- board/raspberrypi/rpi/rpi.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c index e367ba3092..0206a093d4 100644 --- a/board/raspberrypi/rpi/rpi.c +++ b/board/raspberrypi/rpi/rpi.c @@ -489,7 +489,8 @@ int ft_board_setup(void *blob, bd_t *bd) #ifdef CONFIG_EFI_LOADER /* Reserve the spin table */ - efi_add_memory_map(0, 1, EFI_RESERVED_MEMORY_TYPE, 0); + efi_add_memory_map(0, CONFIG_RPI_EFI_NR_SPIN_PAGES, + EFI_RESERVED_MEMORY_TYPE, 0); #endif return 0; -- 2.25.1

3 2

[PATCH 1/2] rpi: add an RPi Kconfig to configure size of initial page reservation
by kevans＠FreeBSD.org 13 May '20

13 May '20

From: Kyle Evans <kevans(a)FreeBSD.org> While the nearly-universal default for the Raspberry Pi family is to use spin tables and the spin table implementation provided by the Raspberry Pi Foundation, FreeBSD and others may use a PSCI implementation instead. Accommodate these setups by allowing them to configure for more than one page to be reserved in the initial reservation. The default reservation remains as one page. Signed-off-by: Kyle Evans <kevans(a)FreeBSD.org> --- arch/arm/mach-bcm283x/Kconfig | 2 ++ board/raspberrypi/rpi/Kconfig | 10 ++++++++++ 2 files changed, 12 insertions(+) create mode 100644 board/raspberrypi/rpi/Kconfig diff --git a/arch/arm/mach-bcm283x/Kconfig b/arch/arm/mach-bcm283x/Kconfig index 00419bf254..e6eb904e7f 100644 --- a/arch/arm/mach-bcm283x/Kconfig +++ b/arch/arm/mach-bcm283x/Kconfig @@ -209,4 +209,6 @@ config SYS_SOC config SYS_CONFIG_NAME default "rpi" +source "board/raspberrypi/rpi/Kconfig" + endmenu diff --git a/board/raspberrypi/rpi/Kconfig b/board/raspberrypi/rpi/Kconfig new file mode 100644 index 0000000000..e40088fde1 --- /dev/null +++ b/board/raspberrypi/rpi/Kconfig @@ -0,0 +1,10 @@ +if SYS_BOARD = "rpi" + +config RPI_EFI_NR_SPIN_PAGES + int "Spin table page count" + default 1 + help + Number of pages to reserve starting at page 0 for spin tables in the EFI + memory map + +endif -- 2.25.1

3 3

[U-Boot] [PPC] Internet connection on qemu-ppce500
by vnktux 12 May '20

12 May '20

Hello guys, I am running an image of U-boot 2018.09 in qemu 3.0, the goal would be to load an OS-9 rom file from tftp. The problem is that I can't manage to have an Internet connection in U-boot. No matter how I run the image I always have Net: "No Ethernet found". I run qemu 3.0 with the following command: > qemu-system-ppc -cpu e500v2 -M ppce500 -nographic -kernel ~/u-boot -net nic -net tap,ifname=tap0,script=no I tried to use different -net options in qemu but the problem is always the same. And from the u-boot source code I have edited the board file qemu-ppce500.c in order to have a few ENV variables (since I can't save any env variables from the running U-boot in qemu). > ethact=eTSEC1 > ethprime=eTSEC1 > ethaddr=192.168.10.40 > netmask=255.255.254.0 > serverip=192.168.10.2 > gatewayip=192.168.10.254 The image is compiled using of course: qemu-ppce500_defconfig. What am I doing wrong? Is it even possible to initialize the Ethernet port? Thanks in advance, Vincenzo Sent with [ProtonMail](https://protonmail.com) Secure Email.

3 2

[U-Boot] [PATCH v6 1/4] dm: spi: Convert Freescale ESPI driver to driver model
by Xiaowei Bao 12 May '20

12 May '20

From: Chuanhua Han <chuanhua.han(a)nxp.com> Modify the Freescale ESPI driver to support the driver model. Also resolved the following problems: ===================== WARNING ====================== This board does not use CONFIG_DM_SPI. Please update the board before v2019.04 for no dm conversion and v2019.07 for partially dm converted drivers. Failure to update can lead to driver/board removal See doc/driver-model/MIGRATION.txt for more info. ==================================================== ===================== WARNING ====================== This board does not use CONFIG_DM_SPI_FLASH. Please update the board to use CONFIG_SPI_FLASH before the v2019.07 release. Failure to update by the deadline may result in board removal. See doc/driver-model/MIGRATION.txt for more info. ==================================================== Signed-off-by: Chuanhua Han <chuanhua.han(a)nxp.com> Signed-off-by: Xiaowei Bao <xiaowei.bao(a)nxp.com> --- depends on: https://patchwork.ozlabs.org/cover/1146494/ Changes in v6: - Change #ifndef CONFIG_DM_SPI to #if !CONFIG_IS_ENABLED(DM_SPI). Changes in v5: - Modify the function spi_cs_activate to fsl_spi_cs_activate. - Move cs to the parameter of the fsl_spi_cs_activate function. Changes in v4: - Update copyright information. - Move the fsl_espi_platdata data structure to the include/dm/platform_data/. - Merge the contents of the fsl_espi_priv structure into the fsl_spi_slave structure. - Implement the fsl_espi_set_speed function. - Implement the fsl_espi_set_mode function. - Implement the espi_release_bus function. - Remove unwanted fsl_espi_bind functions. - Implement the fsl_espi_child_pre_probe function as needed. - Use #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA). Changes in v3: - Add a cover-letter for this patch set. Changes in v2: - The fsl_espi driver support both OF_CONTROL and PLATDATA. drivers/spi/fsl_espi.c | 445 ++++++++++++++++++++++++++---------- drivers/spi/fsl_espi.c | 445 ++++++++++++++++++++++++++---------- include/dm/platform_data/fsl_espi.h | 16 ++ 2 files changed, 337 insertions(+), 124 deletions(-) create mode 100644 include/dm/platform_data/fsl_espi.h diff --git a/drivers/spi/fsl_espi.c b/drivers/spi/fsl_espi.c index 7444ae1..fd5ac97 100644 --- a/drivers/spi/fsl_espi.c +++ b/drivers/spi/fsl_espi.c @@ -3,18 +3,25 @@ * eSPI controller driver. * * Copyright 2010-2011 Freescale Semiconductor, Inc. + * Copyright 2019 NXP * Author: Mingkai Hu (Mingkai.hu(a)freescale.com) + * Chuanhua Han (chuanhua.han(a)nxp.com) */ #include <common.h> - #include <malloc.h> #include <spi.h> #include <asm/immap_85xx.h> +#include <dm.h> +#include <errno.h> +#include <fdtdec.h> +#include <dm/platform_data/fsl_espi.h> struct fsl_spi_slave { struct spi_slave slave; ccsr_espi_t *espi; + u32 speed_hz; + unsigned int cs; unsigned int div16; unsigned int pm; int tx_timeout; @@ -28,6 +35,9 @@ struct fsl_spi_slave { #define to_fsl_spi_slave(s) container_of(s, struct fsl_spi_slave, slave) #define US_PER_SECOND 1000000UL +/* default SCK frequency, unit: HZ */ +#define FSL_ESPI_DEFAULT_SCK_FREQ 10000000 + #define ESPI_MAX_CS_NUM 4 #define ESPI_FIFO_WIDTH_BIT 32 @@ -62,116 +72,27 @@ struct fsl_spi_slave { #define ESPI_MAX_DATA_TRANSFER_LEN 0xFFF0 -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, - unsigned int max_hz, unsigned int mode) -{ - struct fsl_spi_slave *fsl; - sys_info_t sysinfo; - unsigned long spibrg = 0; - unsigned long spi_freq = 0; - unsigned char pm = 0; - - if (!spi_cs_is_valid(bus, cs)) - return NULL; - - fsl = spi_alloc_slave(struct fsl_spi_slave, bus, cs); - if (!fsl) - return NULL; - - fsl->espi = (void *)(CONFIG_SYS_MPC85xx_ESPI_ADDR); - fsl->mode = mode; - fsl->max_transfer_length = ESPI_MAX_DATA_TRANSFER_LEN; - - /* Set eSPI BRG clock source */ - get_sys_info(&sysinfo); - spibrg = sysinfo.freq_systembus / 2; - fsl->div16 = 0; - if ((spibrg / max_hz) > 32) { - fsl->div16 = ESPI_CSMODE_DIV16; - pm = spibrg / (max_hz * 16 * 2); - if (pm > 16) { - pm = 16; - debug("Requested speed is too low: %d Hz, %ld Hz " - "is used.\n", max_hz, spibrg / (32 * 16)); - } - } else - pm = spibrg / (max_hz * 2); - if (pm) - pm--; - fsl->pm = pm; - - if (fsl->div16) - spi_freq = spibrg / ((pm + 1) * 2 * 16); - else - spi_freq = spibrg / ((pm + 1) * 2); - - /* set tx_timeout to 10 times of one espi FIFO entry go out */ - fsl->tx_timeout = DIV_ROUND_UP((US_PER_SECOND * ESPI_FIFO_WIDTH_BIT - * 10), spi_freq); - - return &fsl->slave; -} - -void spi_free_slave(struct spi_slave *slave) -{ - struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave); - free(fsl); -} - -int spi_claim_bus(struct spi_slave *slave) +void fsl_spi_cs_activate(struct spi_slave *slave, uint cs) { struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave); ccsr_espi_t *espi = fsl->espi; - unsigned char pm = fsl->pm; - unsigned int cs = slave->cs; - unsigned int mode = fsl->mode; - unsigned int div16 = fsl->div16; - int i; - - debug("%s: bus:%i cs:%i\n", __func__, slave->bus, cs); - - /* Enable eSPI interface */ - out_be32(&espi->mode, ESPI_MODE_RXTHR(3) - | ESPI_MODE_TXTHR(4) | ESPI_MODE_EN); - - out_be32(&espi->event, 0xffffffff); /* Clear all eSPI events */ - out_be32(&espi->mask, 0x00000000); /* Mask all eSPI interrupts */ - - /* Init CS mode interface */ - for (i = 0; i < ESPI_MAX_CS_NUM; i++) - out_be32(&espi->csmode[i], ESPI_CSMODE_INIT_VAL); - - out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) & - ~(ESPI_CSMODE_PM(0xF) | ESPI_CSMODE_DIV16 - | ESPI_CSMODE_CI_INACTIVEHIGH | ESPI_CSMODE_CP_BEGIN_EDGCLK - | ESPI_CSMODE_REV_MSB_FIRST | ESPI_CSMODE_LEN(0xF))); - - /* Set eSPI BRG clock source */ - out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) - | ESPI_CSMODE_PM(pm) | div16); - - /* Set eSPI mode */ - if (mode & SPI_CPHA) - out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) - | ESPI_CSMODE_CP_BEGIN_EDGCLK); - if (mode & SPI_CPOL) - out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) - | ESPI_CSMODE_CI_INACTIVEHIGH); - - /* Character bit order: msb first */ - out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) - | ESPI_CSMODE_REV_MSB_FIRST); - - /* Character length in bits, between 0x3~0xf, i.e. 4bits~16bits */ - out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) - | ESPI_CSMODE_LEN(7)); + unsigned int com = 0; + size_t data_len = fsl->data_len; - return 0; + com &= ~(ESPI_COM_CS(0x3) | ESPI_COM_TRANLEN(0xFFFF)); + com |= ESPI_COM_CS(cs); + com |= ESPI_COM_TRANLEN(data_len - 1); + out_be32(&espi->com, com); } -void spi_release_bus(struct spi_slave *slave) +void fsl_spi_cs_deactivate(struct spi_slave *slave) { + struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave); + ccsr_espi_t *espi = fsl->espi; + /* clear the RXCNT and TXCNT */ + out_be32(&espi->mode, in_be32(&espi->mode) & (~ESPI_MODE_EN)); + out_be32(&espi->mode, in_be32(&espi->mode) | ESPI_MODE_EN); } static void fsl_espi_tx(struct fsl_spi_slave *fsl, const void *dout) @@ -204,7 +125,8 @@ static void fsl_espi_tx(struct fsl_spi_slave *fsl, const void *dout) debug("***spi_xfer:...Tx timeout! event = %08x\n", event); } -static int fsl_espi_rx(struct fsl_spi_slave *fsl, void *din, unsigned int bytes) +static int fsl_espi_rx(struct fsl_spi_slave *fsl, void *din, + unsigned int bytes) { ccsr_espi_t *espi = fsl->espi; unsigned int tmpdin, rx_times; @@ -236,10 +158,17 @@ static int fsl_espi_rx(struct fsl_spi_slave *fsl, void *din, unsigned int bytes) return bytes; } -int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *data_out, - void *data_in, unsigned long flags) +void espi_release_bus(struct fsl_spi_slave *fsl) { - struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave); + /* Disable the SPI hardware */ + out_be32(&fsl->espi->mode, + in_be32(&fsl->espi->mode) & (~ESPI_MODE_EN)); +} + +int espi_xfer(struct fsl_spi_slave *fsl, uint cs, unsigned int bitlen, + const void *data_out, void *data_in, unsigned long flags) +{ + struct spi_slave *slave = &fsl->slave; ccsr_espi_t *espi = fsl->espi; unsigned int event, rx_bytes; const void *dout = NULL; @@ -258,13 +187,14 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *data_out, max_tran_len = fsl->max_transfer_length; switch (flags) { case SPI_XFER_BEGIN: - cmd_len = fsl->cmd_len = data_len; + cmd_len = data_len; + fsl->cmd_len = cmd_len; memcpy(cmd_buf, data_out, cmd_len); return 0; case 0: case SPI_XFER_END: if (bitlen == 0) { - spi_cs_deactivate(slave); + fsl_spi_cs_deactivate(slave); return 0; } buf_len = 2 * cmd_len + min(data_len, (size_t)max_tran_len); @@ -304,7 +234,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *data_out, num_blks = DIV_ROUND_UP(tran_len + cmd_len, 4); num_bytes = (tran_len + cmd_len) % 4; fsl->data_len = tran_len + cmd_len; - spi_cs_activate(slave); + fsl_spi_cs_activate(slave, cs); /* Clear all eSPI events */ out_be32(&espi->event , 0xffffffff); @@ -347,37 +277,304 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *data_out, *(int *)buffer += tran_len; } } - spi_cs_deactivate(slave); + fsl_spi_cs_deactivate(slave); } free(buffer); return 0; } +void espi_claim_bus(struct fsl_spi_slave *fsl, unsigned int cs) +{ + ccsr_espi_t *espi = fsl->espi; + unsigned char pm = fsl->pm; + unsigned int mode = fsl->mode; + unsigned int div16 = fsl->div16; + int i; + + /* Enable eSPI interface */ + out_be32(&espi->mode, ESPI_MODE_RXTHR(3) + | ESPI_MODE_TXTHR(4) | ESPI_MODE_EN); + + out_be32(&espi->event, 0xffffffff); /* Clear all eSPI events */ + out_be32(&espi->mask, 0x00000000); /* Mask all eSPI interrupts */ + + /* Init CS mode interface */ + for (i = 0; i < ESPI_MAX_CS_NUM; i++) + out_be32(&espi->csmode[i], ESPI_CSMODE_INIT_VAL); + + out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) & + ~(ESPI_CSMODE_PM(0xF) | ESPI_CSMODE_DIV16 + | ESPI_CSMODE_CI_INACTIVEHIGH | ESPI_CSMODE_CP_BEGIN_EDGCLK + | ESPI_CSMODE_REV_MSB_FIRST | ESPI_CSMODE_LEN(0xF))); + + /* Set eSPI BRG clock source */ + out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) + | ESPI_CSMODE_PM(pm) | div16); + + /* Set eSPI mode */ + if (mode & SPI_CPHA) + out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) + | ESPI_CSMODE_CP_BEGIN_EDGCLK); + if (mode & SPI_CPOL) + out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) + | ESPI_CSMODE_CI_INACTIVEHIGH); + + /* Character bit order: msb first */ + out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) + | ESPI_CSMODE_REV_MSB_FIRST); + + /* Character length in bits, between 0x3~0xf, i.e. 4bits~16bits */ + out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) + | ESPI_CSMODE_LEN(7)); +} + +void espi_setup_slave(struct fsl_spi_slave *fsl) +{ + unsigned int max_hz; + sys_info_t sysinfo; + unsigned long spibrg = 0; + unsigned long spi_freq = 0; + unsigned char pm = 0; + + max_hz = fsl->speed_hz; + + get_sys_info(&sysinfo); + spibrg = sysinfo.freq_systembus / 2; + fsl->div16 = 0; + if ((spibrg / max_hz) > 32) { + fsl->div16 = ESPI_CSMODE_DIV16; + pm = spibrg / (max_hz * 16 * 2); + if (pm > 16) { + pm = 16; + debug("max_hz is too low: %d Hz, %ld Hz is used.\n", + max_hz, spibrg / (32 * 16)); + } + } else { + pm = spibrg / (max_hz * 2); + } + if (pm) + pm--; + fsl->pm = pm; + + if (fsl->div16) + spi_freq = spibrg / ((pm + 1) * 2 * 16); + else + spi_freq = spibrg / ((pm + 1) * 2); + + /* set tx_timeout to 10 times of one espi FIFO entry go out */ + fsl->tx_timeout = DIV_ROUND_UP((US_PER_SECOND * ESPI_FIFO_WIDTH_BIT + * 10), spi_freq);/* Set eSPI BRG clock source */ +} + +#if !CONFIG_IS_ENABLED(DM_SPI) int spi_cs_is_valid(unsigned int bus, unsigned int cs) { return bus == 0 && cs < ESPI_MAX_CS_NUM; } -void spi_cs_activate(struct spi_slave *slave) +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + struct fsl_spi_slave *fsl; + + if (!spi_cs_is_valid(bus, cs)) + return NULL; + + fsl = spi_alloc_slave(struct fsl_spi_slave, bus, cs); + if (!fsl) + return NULL; + + fsl->espi = (void *)(CONFIG_SYS_MPC85xx_ESPI_ADDR); + fsl->mode = mode; + fsl->max_transfer_length = ESPI_MAX_DATA_TRANSFER_LEN; + fsl->speed_hz = max_hz; + + espi_setup_slave(fsl); + + return &fsl->slave; +} + +void spi_free_slave(struct spi_slave *slave) { struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave); - ccsr_espi_t *espi = fsl->espi; - unsigned int com = 0; - size_t data_len = fsl->data_len; - com &= ~(ESPI_COM_CS(0x3) | ESPI_COM_TRANLEN(0xFFFF)); - com |= ESPI_COM_CS(slave->cs); - com |= ESPI_COM_TRANLEN(data_len - 1); - out_be32(&espi->com, com); + free(fsl); } -void spi_cs_deactivate(struct spi_slave *slave) +int spi_claim_bus(struct spi_slave *slave) { struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave); - ccsr_espi_t *espi = fsl->espi; - /* clear the RXCNT and TXCNT */ - out_be32(&espi->mode, in_be32(&espi->mode) & (~ESPI_MODE_EN)); - out_be32(&espi->mode, in_be32(&espi->mode) | ESPI_MODE_EN); + espi_claim_bus(fsl, slave->cs); + + return 0; +} + +void spi_release_bus(struct spi_slave *slave) +{ + struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave); + + espi_release_bus(fsl); +} + +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, + void *din, unsigned long flags) +{ + struct fsl_spi_slave *fsl = (struct fsl_spi_slave *)slave; + + return espi_xfer(fsl, slave->cs, bitlen, dout, din, flags); +} +#else +static void __espi_set_speed(struct fsl_spi_slave *fsl) +{ + espi_setup_slave(fsl); + + /* Set eSPI BRG clock source */ + out_be32(&fsl->espi->csmode[fsl->cs], + in_be32(&fsl->espi->csmode[fsl->cs]) + | ESPI_CSMODE_PM(fsl->pm) | fsl->div16); +} + +static void __espi_set_mode(struct fsl_spi_slave *fsl) +{ + /* Set eSPI mode */ + if (fsl->mode & SPI_CPHA) + out_be32(&fsl->espi->csmode[fsl->cs], + in_be32(&fsl->espi->csmode[fsl->cs]) + | ESPI_CSMODE_CP_BEGIN_EDGCLK); + if (fsl->mode & SPI_CPOL) + out_be32(&fsl->espi->csmode[fsl->cs], + in_be32(&fsl->espi->csmode[fsl->cs]) + | ESPI_CSMODE_CI_INACTIVEHIGH); +} + +static int fsl_espi_claim_bus(struct udevice *dev) +{ + struct udevice *bus = dev->parent; + struct fsl_spi_slave *fsl = dev_get_priv(bus); + + espi_claim_bus(fsl, fsl->cs); + + return 0; +} + +static int fsl_espi_release_bus(struct udevice *dev) +{ + struct udevice *bus = dev->parent; + struct fsl_spi_slave *fsl = dev_get_priv(bus); + + espi_release_bus(fsl); + + return 0; +} + +static int fsl_espi_xfer(struct udevice *dev, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct udevice *bus = dev->parent; + struct fsl_spi_slave *fsl = dev_get_priv(bus); + + return espi_xfer(fsl, fsl->cs, bitlen, dout, din, flags); +} + +static int fsl_espi_set_speed(struct udevice *bus, uint speed) +{ + struct fsl_spi_slave *fsl = dev_get_priv(bus); + + debug("%s speed %u\n", __func__, speed); + fsl->speed_hz = speed; + + __espi_set_speed(fsl); + + return 0; +} + +static int fsl_espi_set_mode(struct udevice *bus, uint mode) +{ + struct fsl_spi_slave *fsl = dev_get_priv(bus); + + debug("%s mode %u\n", __func__, mode); + fsl->mode = mode; + + __espi_set_mode(fsl); + + return 0; } + +static int fsl_espi_child_pre_probe(struct udevice *dev) +{ + struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); + struct udevice *bus = dev->parent; + struct fsl_spi_slave *fsl = dev_get_priv(bus); + + debug("%s cs %u\n", __func__, slave_plat->cs); + fsl->cs = slave_plat->cs; + + return 0; +} + +static int fsl_espi_probe(struct udevice *bus) +{ + struct fsl_espi_platdata *plat = dev_get_platdata(bus); + struct fsl_spi_slave *fsl = dev_get_priv(bus); + + fsl->espi = (ccsr_espi_t *)((u32)plat->regs_addr); + fsl->max_transfer_length = ESPI_MAX_DATA_TRANSFER_LEN; + fsl->speed_hz = plat->speed_hz; + + debug("%s probe done, bus-num %d.\n", bus->name, bus->seq); + + return 0; +} + +static const struct dm_spi_ops fsl_espi_ops = { + .claim_bus = fsl_espi_claim_bus, + .release_bus = fsl_espi_release_bus, + .xfer = fsl_espi_xfer, + .set_speed = fsl_espi_set_speed, + .set_mode = fsl_espi_set_mode, +}; + +#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +static int fsl_espi_ofdata_to_platdata(struct udevice *bus) +{ + fdt_addr_t addr; + struct fsl_espi_platdata *plat = bus->platdata; + const void *blob = gd->fdt_blob; + int node = dev_of_offset(bus); + + addr = dev_read_addr(bus); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + plat->regs_addr = lower_32_bits(addr); + plat->speed_hz = fdtdec_get_int(blob, node, "spi-max-frequency", + FSL_ESPI_DEFAULT_SCK_FREQ); + + debug("ESPI: regs=%p, max-frequency=%d\n", + &plat->regs_addr, plat->speed_hz); + + return 0; +} + +static const struct udevice_id fsl_espi_ids[] = { + { .compatible = "fsl,mpc8536-espi" }, + { } +}; +#endif + +U_BOOT_DRIVER(fsl_espi) = { + .name = "fsl_espi", + .id = UCLASS_SPI, +#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) + .of_match = fsl_espi_ids, + .ofdata_to_platdata = fsl_espi_ofdata_to_platdata, +#endif + .ops = &fsl_espi_ops, + .platdata_auto_alloc_size = sizeof(struct fsl_espi_platdata), + .priv_auto_alloc_size = sizeof(struct fsl_spi_slave), + .probe = fsl_espi_probe, + .child_pre_probe = fsl_espi_child_pre_probe, +}; +#endif diff --git a/include/dm/platform_data/fsl_espi.h b/include/dm/platform_data/fsl_espi.h new file mode 100644 index 0000000..812933f --- /dev/null +++ b/include/dm/platform_data/fsl_espi.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 NXP + */ + +#ifndef __fsl_espi_h +#define __fsl_espi_h + +struct fsl_espi_platdata { + uint flags; + uint speed_hz; + uint num_chipselect; + fdt_addr_t regs_addr; +}; + +#endif /* __fsl_espi_h */ -- 2.9.5

4 12

[U-Boot] [PATCH 00/29] Add the SPI DM support for PPC
by Xiaowei Bao 12 May '20

12 May '20

Add the SPI DM support for PPC. depends on: http://patchwork.ozlabs.org/project/uboot/list/?series=127282 Xiaowei Bao (29): dts: P1020: Add ESPI DT nodes dts: P1020RDB: Add ESPI slave device node configs: P1020RDB: Enable ESPI driver dts: P2020: Add ESPI DT nodes dts: P2020RDB: Add ESPI slave device node configs: P2020RDB: Enable ESPI driver dts: P2041: Add ESPI DT nodes dts: P2041RDB: Add ESPI slave device node configs: P2041RDB: Enable ESPI driver dts: P3041: Add ESPI DT nodes dts: P3041DS: Add ESPI slave device node configs: P3041DS: Enable ESPI driver dts: P4080: Add ESPI DT nodes dts: P4080DS: Add ESPI slave device node configs: P4080DS: Enable ESPI driver dts: P5040: Add ESPI DT nodes dts: P5040DS: Add ESPI slave device node configs: P5040DS: Enable ESPI driver dts: T102x: Add ESPI DT nodes dts: T1024RDB: Add ESPI slave device node configs: T1024RDB: Enable ESPI driver dts: T104x: Add ESPI DT nodes dts: T1042D4RDB: Add ESPI slave device node configs: T1042D4RDB: Enable ESPI driver dts: T2080RDB: Add ESPI slave device node configs: T2080RDB: Enable ESPI driver dts: T4240: Add ESPI DT nodes dts: T4240RDB: Add ESPI slave device node configs: T4240RDB: Enable ESPI driver arch/powerpc/dts/p1020-post.dtsi | 9 +++++++++ arch/powerpc/dts/p1020rdb-pc.dts | 15 +++++++++++++++ arch/powerpc/dts/p1020rdb-pc_36b.dts | 15 +++++++++++++++ arch/powerpc/dts/p1020rdb-pd.dts | 15 +++++++++++++++ arch/powerpc/dts/p2020-post.dtsi | 9 +++++++++ arch/powerpc/dts/p2020rdb-pc.dts | 15 +++++++++++++++ arch/powerpc/dts/p2020rdb-pc_36b.dts | 15 +++++++++++++++ arch/powerpc/dts/p2041.dtsi | 9 +++++++++ arch/powerpc/dts/p2041rdb.dts | 14 ++++++++++++++ arch/powerpc/dts/p3041.dtsi | 9 +++++++++ arch/powerpc/dts/p3041ds.dts | 14 ++++++++++++++ arch/powerpc/dts/p4080.dtsi | 9 +++++++++ arch/powerpc/dts/p4080ds.dts | 14 ++++++++++++++ arch/powerpc/dts/p5040.dtsi | 9 +++++++++ arch/powerpc/dts/p5040ds.dts | 14 ++++++++++++++ arch/powerpc/dts/t1024rdb.dts | 15 +++++++++++++++ arch/powerpc/dts/t102x.dtsi | 9 +++++++++ arch/powerpc/dts/t1042d4rdb.dts | 15 +++++++++++++++ arch/powerpc/dts/t104x.dtsi | 9 +++++++++ arch/powerpc/dts/t2080rdb.dts | 15 +++++++++++++++ arch/powerpc/dts/t4240.dtsi | 9 +++++++++ arch/powerpc/dts/t4240rdb.dts | 15 +++++++++++++++ configs/P1020RDB-PC_36BIT_NAND_defconfig | 2 ++ configs/P1020RDB-PC_36BIT_SDCARD_defconfig | 2 ++ configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig | 2 ++ configs/P1020RDB-PC_36BIT_defconfig | 2 ++ configs/P1020RDB-PC_NAND_defconfig | 2 ++ configs/P1020RDB-PC_SDCARD_defconfig | 2 ++ configs/P1020RDB-PC_SPIFLASH_defconfig | 2 ++ configs/P1020RDB-PC_defconfig | 2 ++ configs/P1020RDB-PD_NAND_defconfig | 2 ++ configs/P1020RDB-PD_SDCARD_defconfig | 2 ++ configs/P1020RDB-PD_SPIFLASH_defconfig | 2 ++ configs/P1020RDB-PD_defconfig | 2 ++ configs/P2020RDB-PC_36BIT_NAND_defconfig | 2 ++ configs/P2020RDB-PC_36BIT_SDCARD_defconfig | 2 ++ configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig | 2 ++ configs/P2020RDB-PC_36BIT_defconfig | 2 ++ configs/P2020RDB-PC_NAND_defconfig | 2 ++ configs/P2020RDB-PC_SDCARD_defconfig | 2 ++ configs/P2020RDB-PC_SPIFLASH_defconfig | 2 ++ configs/P2020RDB-PC_defconfig | 2 ++ configs/P2041RDB_NAND_defconfig | 2 ++ configs/P2041RDB_SDCARD_defconfig | 2 ++ configs/P2041RDB_SPIFLASH_defconfig | 2 ++ configs/P2041RDB_defconfig | 2 ++ configs/P3041DS_NAND_defconfig | 2 ++ configs/P3041DS_SDCARD_defconfig | 2 ++ configs/P3041DS_SPIFLASH_defconfig | 2 ++ configs/P3041DS_defconfig | 2 ++ configs/P4080DS_SDCARD_defconfig | 2 ++ configs/P4080DS_SPIFLASH_defconfig | 2 ++ configs/P4080DS_defconfig | 2 ++ configs/P5040DS_NAND_defconfig | 2 ++ configs/P5040DS_SDCARD_defconfig | 2 ++ configs/P5040DS_SPIFLASH_defconfig | 2 ++ configs/P5040DS_defconfig | 2 ++ configs/T1024RDB_NAND_defconfig | 2 ++ configs/T1024RDB_SDCARD_defconfig | 2 ++ configs/T1024RDB_SPIFLASH_defconfig | 2 ++ configs/T1024RDB_defconfig | 2 ++ configs/T1042D4RDB_NAND_defconfig | 2 ++ configs/T1042D4RDB_SDCARD_defconfig | 2 ++ configs/T1042D4RDB_SPIFLASH_defconfig | 2 ++ configs/T1042D4RDB_defconfig | 2 ++ configs/T2080RDB_NAND_defconfig | 2 ++ configs/T2080RDB_SDCARD_defconfig | 2 ++ configs/T2080RDB_SPIFLASH_defconfig | 2 ++ configs/T2080RDB_defconfig | 2 ++ configs/T4240RDB_SDCARD_defconfig | 2 ++ configs/T4240RDB_defconfig | 2 ++ 71 files changed, 370 insertions(+) -- 2.9.5

2 30

[PATCH] configs: ls1046a: Define ENV_ADDR value
by Kuldeep Singh 12 May '20

12 May '20

CONFIG_ENV_ADDR helps in picking environment from flash before DDR init. Define value 0x40300000 in QSPI defconfig for LS1046ARDB as value is already defined in TFA. Correct ENV_ADDR and ENV_SECT_SIZE value for LS1046AQDS as per defconfig. Signed-off-by: Kuldeep Singh <kuldeep.singh(a)nxp.com> --- configs/ls1046aqds_qspi_defconfig | 3 ++- configs/ls1046aqds_tfa_defconfig | 4 ++-- configs/ls1046ardb_qspi_defconfig | 1 + 3 files changed, 5 insertions(+), 3 deletions(-) diff --git a/configs/ls1046aqds_qspi_defconfig b/configs/ls1046aqds_qspi_defconfig index 22904a0..1f28ad5 100644 --- a/configs/ls1046aqds_qspi_defconfig +++ b/configs/ls1046aqds_qspi_defconfig @@ -2,7 +2,7 @@ CONFIG_ARM=y CONFIG_TARGET_LS1046AQDS=y CONFIG_SYS_TEXT_BASE=0x40100000 CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_ENV_SECT_SIZE=0x40000 CONFIG_ENV_OFFSET=0x300000 CONFIG_FSL_LS_PPA=y CONFIG_NR_DRAM_BANKS=2 @@ -31,6 +31,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.spi-0:2m(uboot),14m(free)" CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart" CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_ADDR=0x40300000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y diff --git a/configs/ls1046aqds_tfa_defconfig b/configs/ls1046aqds_tfa_defconfig index df85533..18e3993 100644 --- a/configs/ls1046aqds_tfa_defconfig +++ b/configs/ls1046aqds_tfa_defconfig @@ -3,7 +3,7 @@ CONFIG_TARGET_LS1046AQDS=y CONFIG_TFABOOT=y CONFIG_SYS_TEXT_BASE=0x82000000 CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_ENV_SECT_SIZE=0x40000 CONFIG_ENV_OFFSET=0x500000 CONFIG_NR_DRAM_BANKS=2 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y @@ -39,7 +39,7 @@ CONFIG_ENV_IS_IN_NAND=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_USE_ENV_SPI_BUS=y CONFIG_ENV_SPI_BUS=0 -CONFIG_ENV_ADDR=0x60500000 +CONFIG_ENV_ADDR=0x40500000 CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y diff --git a/configs/ls1046ardb_qspi_defconfig b/configs/ls1046ardb_qspi_defconfig index d5e0f02..d836421 100644 --- a/configs/ls1046ardb_qspi_defconfig +++ b/configs/ls1046ardb_qspi_defconfig @@ -28,6 +28,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.i CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb" CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_ADDR=0x40300000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y -- 2.7.4

2 4

[U-Boot] [PATCH v2 0/4] regmap: Add a managed API, custom read/write callbacks and support for regmap fields
by Jean-Jacques Hiblot 11 May '20

11 May '20

This is the first of a few series, the goal of which is to facilitate porting drivers from the linux kernel. Most of the series will be about adding managed API to existing infrastructure (GPIO, reset, phy,...) This particular series is about regmaps. It adds the managed API, using the same API as linux. It also adds support for regmap fields and for custom read/write callbacks. Changes in v2: - Fix comment for devm_regmap_init() - Fix spelling in commit log - Only use custom accessors if {,SPL,TPL}_REGMAP_ACCESSORS is enabled Jean-Jacques Hiblot (4): regmap: Add devm_regmap_init() regmap: Allow providing read/write callbacks through struct regmap_config regmap: Add support for regmap fields test: dm: Add tests for regmap managed API and regmap fields arch/sandbox/dts/test.dts | 13 +++ drivers/core/Kconfig | 25 +++++ drivers/core/regmap.c | 123 ++++++++++++++++++++++++- include/regmap.h | 148 +++++++++++++++++++++++++++++ test/dm/regmap.c | 189 ++++++++++++++++++++++++++++++++++++++ 5 files changed, 497 insertions(+), 1 deletion(-) -- 2.17.1

5 15

[PATCH 0/5] CMD_SAVEENV ifdef cleanup
by Rasmus Villemoes 11 May '20

11 May '20

The various env storage drivers almost all have their own logic [1] for deciding whether to compile and provide the .save method, many of which fail to honour CONFIG_SPL_SAVEENV. For example, fat.c and sf.c define a CMD_SAVEENV macro only for !CONFIG_SPL_BUILD, while ext4.c "only" depends on CONFIG_CMD_SAVEENV - but CONFIG_SPL_SAVEENV=y, CONFIG_CMD_SAVEENV=n is a valid combination. A lot of that ifdeffery can be removed while at the same time providing the .save method if either CONFIG_SPL_SAVEENV (for an SPL build) or CONFIG_CMD_SAVEENV (for U-Boot proper) is set. The first two patches introduce infrastructure for that, while the last three are example conversions for the above-mentioned three storage drivers. The sf.c is the one I need to use in the SPL and have actually tested, ext4.c and fat.c are included mostly as low-hanging fruit. [1] Here's the current conditions for which these three drivers provide .save: SPL U-Boot ext4.c CONFIG_CMD_SAVEENV=y CONFIG_CMD_SAVEENV=y fat.c never CONFIG_CMD_SAVEENV=y sf.c never CONFIG_CMD_SAVEENV=y [2] [2] It always compiles env_sf_save for U-Boot proper, but then the use of env_save_ptr() ends up with a build warning in case CONFIG_CMD_SAVEENV=n - fat.c doesn't have that proplem. Rasmus Villemoes (5): env: add SAVEENV as an alias of the CMD_SAVEENV symbol env_internal.h: add alternative ENV_SAVE_PTR macro env/fat.c: remove private CMD_SAVEENV logic env/ext4.c: remove CONFIG_CMD_SAVEENV ifdef env/sf.c: drop private CMD_SAVEENV logic env/Kconfig | 3 +++ env/ext4.c | 4 +--- env/fat.c | 9 +-------- env/sf.c | 12 +----------- include/env_internal.h | 2 ++ 5 files changed, 8 insertions(+), 22 deletions(-) -- 2.23.0

3 34

[U-Boot] Enable USB host controller on Odroid-C2
by Beniamino Galvani 11 May '20

11 May '20

Hi, these two patches enable the USB host controller on Odroid-C2. The first patch adds a PHY driver; the second one enables the necessary configuration options and updates the device tree. Note that the DWC2 driver currently does not support enabling PHYs from the device tree and so the following series (still on review) is needed as runtime requirement for the second patch: [PATCH 0/5] usb: host: dwc2: use driver model for PHY and CLOCK Thanks, Beniamino Beniamino Galvani (2): phy: meson: add GXBB PHY driver odroid-c2: enable USB host controller arch/arm/dts/meson-gxbb-odroidc2-u-boot.dtsi | 8 + configs/odroid-c2_defconfig | 7 + drivers/phy/Kconfig | 8 + drivers/phy/Makefile | 1 + drivers/phy/meson-gxbb-usb2.c | 235 +++++++++++++++++++ include/configs/meson64.h | 5 + 6 files changed, 264 insertions(+) create mode 100644 drivers/phy/meson-gxbb-usb2.c -- 2.21.0

2 10