February 2020 - U-Boot

[PATCH v5 00/20] Refactor the architecture parts of mt7628
by Weijie Gao 13 Feb '20

13 Feb '20

This patch series are divided into two parts: The main part is to rewrite the whole architecture code of mt7628: * Lock parts of the d-cache for initial stack so the rest of the code can be reimplemented in C. * Memory controller & DDR initialization have been fully written to support detecting DDR size automatically. * DDR calibration has also been reimplemented with a clear logic. * Implemented a new sysreset driver to take advantage of the reset controller so we can drop the use of syscon-based sysreset to reduce size. The second part is to add SPL support for mt7628: * With SPL enabled we can build the ROM-bootable and RAM-bootable binary simultaneously, and we can drop RAM boot related configs and defconfig files. * Generate compressed u-boot.bin image for SPL to reduce size of final combined binary. * Enable DM support for SPL for a more flexible device probing. * Add a demo board (mt7628_rfb) aims at router application. Changes since v2: * Dropped a patch which removes unused parts of mt7628a.dtsi * Move lzma decompression support to common spl_nor.c * Move u-boot,dm-pre-reloc to u-boot-mt7628.dtsi Changes since v3: * Rebased on newest master branch * Add a test for binman etype u-boot-lzma-img to make sure binman passes 100% code coverage * Use u-boot-with-spl.bin for SPL-enabled output file * Remove unused code from spl_nor loader. Weijie Gao (20): mips: add support to restore exception vector base before booting linux mips: mtmips: add predefined i-cache/d-cache size and linesize mips: add an option to support initialize SRAM for initial stack mips: start.S: avoid overwriting outside gd when clearing global data in stack sysreset: add reset controller based reboot driver mips: mtmips: make use of sysreset-resetctrl for mt7628 soc configs: enable CONFIG_RESTORE_EXCEPTION_VECTOR_BASE for all mtmips boards mips: add a mtmips-specific field to architecture-specific global data mips: add a option to support not reserving malloc space on initial stack mips: mtmips: rewrite lowlevel codes of mt7628 dts: mtmips: add alternative pinmux node for uart2 mips: enable support for appending dtb to spl binary mips: add an option to enable u_boot_list section for SPL loaders in u-boot-spl.lds lib: enable lzma decompression support for SPL build Makefile: add support to generate LZMA compressed u-boot image tools: binman: add etype file for u-boot-lzma-img spl: nor: add lzma decompression support for legacy image mips: mtmips: add SPL support mips: mtmips: enable SPL for all boards mips: mtmips: add support for mt7628-rfb Makefile | 19 + arch/mips/Kconfig | 66 ++++ arch/mips/cpu/start.S | 16 +- arch/mips/cpu/u-boot-spl.lds | 4 +- arch/mips/dts/Makefile | 1 + arch/mips/dts/mediatek,mt7628-rfb.dts | 67 ++++ arch/mips/dts/mt7628-u-boot.dtsi | 56 +++ arch/mips/dts/mt7628a.dtsi | 17 +- arch/mips/include/asm/global_data.h | 3 + arch/mips/include/asm/u-boot-mips.h | 2 + arch/mips/lib/bootm.c | 3 + arch/mips/lib/traps.c | 19 + arch/mips/mach-mtmips/Kconfig | 135 +++---- arch/mips/mach-mtmips/Makefile | 8 +- arch/mips/mach-mtmips/cpu.c | 58 +--- arch/mips/mach-mtmips/ddr_cal.c | 211 +++++++++++ arch/mips/mach-mtmips/ddr_calibrate.c | 309 ----------------- arch/mips/mach-mtmips/ddr_init.c | 194 +++++++++++ arch/mips/mach-mtmips/include/mach/ddr.h | 52 +++ arch/mips/mach-mtmips/include/mach/mc.h | 180 ++++++++++ arch/mips/mach-mtmips/include/mach/serial.h | 13 + arch/mips/mach-mtmips/lowlevel_init.S | 328 ------------------ arch/mips/mach-mtmips/mt7628/Makefile | 6 + arch/mips/mach-mtmips/mt7628/ddr.c | 173 +++++++++ arch/mips/mach-mtmips/mt7628/init.c | 109 ++++++ arch/mips/mach-mtmips/mt7628/lowlevel_init.S | 161 +++++++++ arch/mips/mach-mtmips/mt7628/mt7628.h | 104 ++++++ arch/mips/mach-mtmips/mt7628/serial.c | 34 ++ arch/mips/mach-mtmips/mt76xx.h | 32 -- arch/mips/mach-mtmips/spl.c | 44 +++ board/gardena/smart-gateway-mt7688/board.c | 2 + board/mediatek/mt7628/Kconfig | 12 + board/mediatek/mt7628/MAINTAINERS | 7 + board/mediatek/mt7628/Makefile | 3 + board/mediatek/mt7628/board.c | 8 + common/spl/spl_nor.c | 51 ++- ...gardena-smart-gateway-mt7688-ram_defconfig | 74 ---- .../gardena-smart-gateway-mt7688_defconfig | 14 +- configs/linkit-smart-7688-ram_defconfig | 65 ---- configs/linkit-smart-7688_defconfig | 14 +- configs/mt7628_rfb_defconfig | 46 +++ drivers/sysreset/Kconfig | 6 + drivers/sysreset/Makefile | 1 + drivers/sysreset/sysreset_resetctl.c | 48 +++ .../configs/gardena-smart-gateway-mt7688.h | 21 +- include/configs/linkit-smart-7688.h | 22 +- include/configs/mt7628.h | 56 +++ lib/Kconfig | 5 + lib/Makefile | 1 + tools/binman/README.entries | 15 + tools/binman/etype/u_boot_lzma_img.py | 28 ++ tools/binman/ftest.py | 7 + tools/binman/test/156_u_boot_lzma_img.dts | 11 + 53 files changed, 1962 insertions(+), 979 deletions(-) create mode 100644 arch/mips/dts/mediatek,mt7628-rfb.dts create mode 100644 arch/mips/dts/mt7628-u-boot.dtsi create mode 100644 arch/mips/mach-mtmips/ddr_cal.c delete mode 100644 arch/mips/mach-mtmips/ddr_calibrate.c create mode 100644 arch/mips/mach-mtmips/ddr_init.c create mode 100644 arch/mips/mach-mtmips/include/mach/ddr.h create mode 100644 arch/mips/mach-mtmips/include/mach/mc.h create mode 100644 arch/mips/mach-mtmips/include/mach/serial.h delete mode 100644 arch/mips/mach-mtmips/lowlevel_init.S create mode 100644 arch/mips/mach-mtmips/mt7628/Makefile create mode 100644 arch/mips/mach-mtmips/mt7628/ddr.c create mode 100644 arch/mips/mach-mtmips/mt7628/init.c create mode 100644 arch/mips/mach-mtmips/mt7628/lowlevel_init.S create mode 100644 arch/mips/mach-mtmips/mt7628/mt7628.h create mode 100644 arch/mips/mach-mtmips/mt7628/serial.c delete mode 100644 arch/mips/mach-mtmips/mt76xx.h create mode 100644 arch/mips/mach-mtmips/spl.c create mode 100644 board/mediatek/mt7628/Kconfig create mode 100644 board/mediatek/mt7628/MAINTAINERS create mode 100644 board/mediatek/mt7628/Makefile create mode 100644 board/mediatek/mt7628/board.c delete mode 100644 configs/gardena-smart-gateway-mt7688-ram_defconfig delete mode 100644 configs/linkit-smart-7688-ram_defconfig create mode 100644 configs/mt7628_rfb_defconfig create mode 100644 drivers/sysreset/sysreset_resetctl.c create mode 100644 include/configs/mt7628.h create mode 100644 tools/binman/etype/u_boot_lzma_img.py create mode 100644 tools/binman/test/156_u_boot_lzma_img.dts -- 2.17.1

2 3

[PATCH] gadget: f_thor: add missing line breaks for pr_err()
by Seung-Woo Kim 13 Feb '20

13 Feb '20

After the commit 9b643e312d52 ("treewide: replace with error() with pr_err()"), there are pr_err() usages without line break. Add missing line breaks for pr_err() used in f_thor. Signed-off-by: Seung-Woo Kim <sw0312.kim(a)samsung.com> --- drivers/usb/gadget/f_thor.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/usb/gadget/f_thor.c b/drivers/usb/gadget/f_thor.c index 5a023a2b34..ee646fdd5c 100644 --- a/drivers/usb/gadget/f_thor.c +++ b/drivers/usb/gadget/f_thor.c @@ -174,7 +174,7 @@ static long long int download_head(unsigned long long total, transfer_buffer, THOR_STORE_UNIT_SIZE, (*cnt)++); if (ret) { - pr_err("DFU write failed [%d] cnt: %d", + pr_err("DFU write failed [%d] cnt: %d\n", ret, *cnt); return ret; } @@ -224,14 +224,14 @@ static int download_tail(long long int left, int cnt) transfer_buffer = dfu_get_buf(dfu_entity); if (!transfer_buffer) { - pr_err("Transfer buffer not allocated!"); + pr_err("Transfer buffer not allocated!\n"); return -ENXIO; } if (left) { ret = dfu_write(dfu_entity, transfer_buffer, left, cnt++); if (ret) { - pr_err("DFU write failed [%d]: left: %llu", ret, left); + pr_err("DFU write failed[%d]: left: %llu\n", ret, left); return ret; } } @@ -245,7 +245,7 @@ static int download_tail(long long int left, int cnt) */ ret = dfu_flush(dfu_entity, transfer_buffer, 0, cnt); if (ret) - pr_err("DFU flush failed!"); + pr_err("DFU flush failed!\n"); return ret; } @@ -290,7 +290,7 @@ static long long int process_rqt_download(const struct rqt_box *rqt) alt_setting_num = dfu_get_alt(f_name); if (alt_setting_num < 0) { - pr_err("Alt setting [%d] to write not found!", + pr_err("Alt setting [%d] to write not found!\n", alt_setting_num); rsp->ack = -ENODEV; ret = rsp->ack; @@ -316,7 +316,7 @@ static long long int process_rqt_download(const struct rqt_box *rqt) debug("DL EXIT\n"); break; default: - pr_err("Operation not supported: %d", rqt->rqt_data); + pr_err("Operation not supported: %d\n", rqt->rqt_data); ret = -ENOTSUPP; } @@ -347,7 +347,7 @@ static int process_data(void) puts("RQT: UPLOAD not supported!\n"); break; default: - pr_err("unknown request (%d)", rqt->rqt); + pr_err("unknown request (%d)\n", rqt->rqt); } return ret; @@ -546,7 +546,7 @@ static int thor_rx_data(void) status = usb_ep_queue(dev->out_ep, dev->out_req, 0); if (status) { - pr_err("kill %s: resubmit %d bytes --> %d", + pr_err("kill %s: resubmit %d bytes --> %d\n", dev->out_ep->name, dev->out_req->length, status); usb_ep_set_halt(dev->out_ep); return -EAGAIN; @@ -580,7 +580,7 @@ static void thor_tx_data(unsigned char *data, int len) status = usb_ep_queue(dev->in_ep, dev->in_req, 0); if (status) { - pr_err("kill %s: resubmit %d bytes --> %d", + pr_err("kill %s: resubmit %d bytes --> %d\n", dev->in_ep->name, dev->in_req->length, status); usb_ep_set_halt(dev->in_ep); } @@ -613,7 +613,7 @@ static void thor_rx_tx_complete(struct usb_ep *ep, struct usb_request *req) case -ESHUTDOWN: /* disconnect from host */ case -EREMOTEIO: /* short read */ case -EOVERFLOW: - pr_err("ERROR:%d", status); + pr_err("ERROR:%d\n", status); break; } @@ -653,7 +653,7 @@ thor_func_setup(struct usb_function *f, const struct usb_ctrlrequest *ctrl) break; default: - pr_err("thor_setup: unknown request: %d", ctrl->bRequest); + pr_err("thor_setup: unknown request: %d\n", ctrl->bRequest); } if (value >= 0) { @@ -984,7 +984,7 @@ static int thor_func_set_alt(struct usb_function *f, debug("Communication Data interface\n"); result = thor_eps_setup(f); if (result) - pr_err("%s: EPs setup failed!", __func__); + pr_err("%s: EPs setup failed!\n", __func__); dev->configuration_done = 1; break; } -- 2.19.2

1 0

[PATCH v4 17/20] spl: nor: add lzma decompression support for legacy image
by Weijie Gao 13 Feb '20

13 Feb '20

This patch adds support for decompressing LZMA compressed u-boot payload in legacy uImage format. Using this patch together with u-boot-lzma.img is useful for NOR flashes as they can reduce the size and load time of u-boot payload. Reviewed-by: Stefan Roese <sr(a)denx.de> Signed-off-by: Weijie Gao <weijie.gao(a)mediatek.com> --- Changes since v3: none --- common/spl/spl_nor.c | 59 ++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 54 insertions(+), 5 deletions(-) diff --git a/common/spl/spl_nor.c b/common/spl/spl_nor.c index b1e79b9ded..7c81fb28f6 100644 --- a/common/spl/spl_nor.c +++ b/common/spl/spl_nor.c @@ -4,8 +4,19 @@ */ #include <common.h> +#include <cpu_func.h> #include <spl.h> +#if IS_ENABLED(CONFIG_SPL_LZMA) +#include <lzma/LzmaTypes.h> +#include <lzma/LzmaDec.h> +#include <lzma/LzmaTools.h> +#endif + +#ifndef CONFIG_SYS_BOOTM_LEN +#define CONFIG_SYS_BOOTM_LEN (8 << 20) +#endif + static ulong spl_nor_load_read(struct spl_load_info *load, ulong sector, ulong count, void *buf) { @@ -27,6 +38,9 @@ static int spl_nor_load_image(struct spl_image_info *spl_image, int ret; __maybe_unused const struct image_header *header; __maybe_unused struct spl_load_info load; + __maybe_unused SizeT lzma_len; + struct image_header hdr; + uintptr_t dataptr; /* * Loading of the payload to SDRAM is done with skipping of @@ -107,14 +121,49 @@ static int spl_nor_load_image(struct spl_image_info *spl_image, spl_nor_get_uboot_base()); } - ret = spl_parse_image_header(spl_image, - (const struct image_header *)spl_nor_get_uboot_base()); + /* Payload image may not be aligned, so copy it for safety. */ + memcpy(&hdr, (void *)spl_nor_get_uboot_base(), sizeof(hdr)); + ret = spl_parse_image_header(spl_image, &hdr); if (ret) return ret; - memcpy((void *)(unsigned long)spl_image->load_addr, - (void *)(spl_nor_get_uboot_base() + sizeof(struct image_header)), - spl_image->size); + dataptr = spl_nor_get_uboot_base() + sizeof(struct image_header); + + switch (image_get_comp(&hdr)) { + case IH_COMP_NONE: + memmove((void *)(unsigned long)spl_image->load_addr, + (void *)dataptr, spl_image->size); + break; +#if IS_ENABLED(CONFIG_SPL_LZMA) + case IH_COMP_LZMA: + lzma_len = CONFIG_SYS_BOOTM_LEN; + + ret = lzmaBuffToBuffDecompress((void *)spl_image->load_addr, + &lzma_len, (void *)dataptr, + spl_image->size); + + if (ret) { + printf("LZMA decompression error: %d\n", ret); + return ret; + } + + spl_image->size = lzma_len; + break; +#endif + default: + debug("Compression method %s is not supported\n", + genimg_get_comp_short_name(image_get_comp(&hdr))); + return -EINVAL; + } + + flush_cache((unsigned long)spl_image->load_addr, spl_image->size); + + /* + * If the image did not provide an entry point, assume the entry point + * is the same as its load address. + */ + if (!spl_image->entry_point) + spl_image->entry_point = spl_image->load_addr; return 0; } -- 2.17.1

4 9

[PATCH 00/21] dm: Various enhancements to prepare for ACPI
by Simon Glass 12 Feb '20

12 Feb '20

This series contains various minor enhancements needed to implement the programmatic generation of ACPI tables on x86 devices. These are mostly generic routines and are likely to be useful elsewhere. It also includes a few test improvements to support checking console output more easily. Simon Glass (21): dm: core: Use const where possible in device.h dm: pci: Update the PCI read_config() method to const dev * dm: pci: Update a few more interfaces for const udevice * dm: core: Use const device for the devfdt...() interface dm: core: Use const device for the dev_read_...() interface test: Add underscore prefix to macro parameters dm: core: Update comment for ofnode_get_chosen_node() dm: core: Rename ofnode_get_chosen_prop() dm: core: Add ofnode_read_prop() dm: core: Reimplement ofnode_read_size() dm: core: Add ofnode_get_chosen_prop() dm: core: Add a way to read platdata for all child devices dm: core: Add a way to iterate through children, probing each dm: core: Drop uclass_find_next_free_req_seq() conditions bloblist: Add a new function to add or check size bloblist: Tidy up a few comments and code-style nits bloblist: Zero records when adding sandbox: pmic: Correct i2c pmic emulator platdata method console: Add a function to read a line of the output / eof test: Enable console recording in tests test: Add a way to check each line of console output arch/sandbox/dts/test.dts | 3 + .../puma_rk3399/puma-rk3399.c | 2 +- board/xilinx/common/board.c | 2 +- common/bloblist.c | 23 +- common/console.c | 11 + doc/README.bloblist | 4 +- drivers/core/device.c | 85 +++++-- drivers/core/fdtaddr.c | 26 +-- drivers/core/ofnode.c | 71 +++--- drivers/core/read.c | 97 ++++---- drivers/core/uclass.c | 4 - drivers/misc/p2sb_emul.c | 5 +- drivers/misc/swap_case.c | 9 +- drivers/pci/pci-aardvark.c | 2 +- drivers/pci/pci-emul-uclass.c | 2 +- drivers/pci/pci-rcar-gen2.c | 4 +- drivers/pci/pci-rcar-gen3.c | 2 +- drivers/pci/pci-uclass.c | 32 +-- drivers/pci/pci_mpc85xx.c | 2 +- drivers/pci/pci_mvebu.c | 2 +- drivers/pci/pci_sandbox.c | 2 +- drivers/pci/pci_sh7751.c | 2 +- drivers/pci/pci_tegra.c | 2 +- drivers/pci/pci_x86.c | 5 +- drivers/pci/pcie_dw_mvebu.c | 2 +- drivers/pci/pcie_dw_ti.c | 2 +- drivers/pci/pcie_ecam_generic.c | 11 +- drivers/pci/pcie_fsl.c | 2 +- drivers/pci/pcie_imx.c | 2 +- drivers/pci/pcie_intel_fpga.c | 4 +- drivers/pci/pcie_layerscape.c | 4 +- drivers/pci/pcie_layerscape_gen4.c | 2 +- drivers/pci/pcie_mediatek.c | 4 +- drivers/pci/pcie_phytium.c | 7 +- drivers/pci/pcie_xilinx.c | 4 +- drivers/power/acpi_pmc/pmc_emul.c | 2 +- drivers/power/pmic/i2c_pmic_emul.c | 16 +- include/bloblist.h | 16 +- include/console.h | 19 ++ include/dm/device.h | 111 +++++++-- include/dm/fdtaddr.h | 26 +-- include/dm/ofnode.h | 39 +++- include/dm/read.h | 212 +++++++++--------- include/fdtdec.h | 2 +- include/pci.h | 38 ++-- include/test/test.h | 4 + include/test/ut.h | 109 +++++++-- lib/fdtdec.c | 2 +- test/bloblist.c | 61 ++++- test/dm/ofnode.c | 55 +++++ test/dm/test-fdt.c | 38 ++++ test/dm/test-main.c | 4 +- test/ut.c | 46 ++++ 53 files changed, 892 insertions(+), 351 deletions(-) -- 2.25.0.341.g760bfbb309-goog

5 46

[PATCH v2] mx6slevk: Convert to DM_ETH
by Pedro Jardim 12 Feb '20

12 Feb '20

This fixes the following warning: ===================== WARNING ====================== This board does not use CONFIG_DM_ETH (Driver Model for Ethernet drivers). Please update the board to use CONFIG_DM_ETH before the v2020.07 release. Failure to update by the deadline may result in board removal. See doc/driver-model/migration.rst for more info. ==================================================== Signed-off-by: Pedro Jardim <jardim.c.pedro(a)gmail.com> Changes since v1" - Remove CONFIG_ETHPRIME --- board/freescale/mx6slevk/mx6slevk.c | 31 ----------------------------- configs/mx6slevk_defconfig | 3 +++ include/configs/mx6slevk.h | 6 ------ 3 files changed, 3 insertions(+), 37 deletions(-) diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c index 453f281418..43029e4245 100644 --- a/board/freescale/mx6slevk/mx6slevk.c +++ b/board/freescale/mx6slevk/mx6slevk.c @@ -21,7 +21,6 @@ #include <fsl_esdhc_imx.h> #include <i2c.h> #include <mmc.h> -#include <netdev.h> #include <power/pmic.h> #include <power/pfuze100_pmic.h> #include "../common/pfuze.h" @@ -102,35 +101,11 @@ static iomux_v3_cfg_t const usdhc3_pads[] = { }; #endif -static iomux_v3_cfg_t const fec_pads[] = { - MX6_PAD_FEC_MDC__FEC_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_FEC_MDIO__FEC_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_FEC_CRS_DV__FEC_RX_DV | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_FEC_RXD0__FEC_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_FEC_RXD1__FEC_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_FEC_TX_EN__FEC_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_FEC_TXD0__FEC_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_FEC_TXD1__FEC_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_FEC_REF_CLK__FEC_REF_OUT | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_FEC_RX_ER__GPIO_4_19 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_FEC_TX_CLK__GPIO_4_21 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - static void setup_iomux_uart(void) { imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); } -static void setup_iomux_fec(void) -{ - imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); - - /* Power up LAN8720 PHY */ - gpio_request(ETH_PHY_POWER, "eth_pwr"); - gpio_direction_output(ETH_PHY_POWER , 1); - udelay(15000); -} - int board_mmc_get_env_dev(int devno) { return devno; @@ -179,12 +154,6 @@ int power_init_board(void) #endif #ifdef CONFIG_FEC_MXC -int board_eth_init(bd_t *bis) -{ - setup_iomux_fec(); - - return cpu_eth_init(bis); -} static int setup_fec(void) { diff --git a/configs/mx6slevk_defconfig b/configs/mx6slevk_defconfig index dc22e830a3..163cb1a7ae 100644 --- a/configs/mx6slevk_defconfig +++ b/configs/mx6slevk_defconfig @@ -61,3 +61,6 @@ CONFIG_DM_USB=y CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y +CONFIG_DM_ETH=y +CONFIG_FEC_MXC=y +CONFIG_PHY_SMSC=y diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h index 6b2a174e7a..71d72d8c74 100644 --- a/include/configs/mx6slevk.h +++ b/include/configs/mx6slevk.h @@ -32,12 +32,7 @@ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE RMII -#define CONFIG_FEC_MXC_PHYADDR 0 - -#define CONFIG_PHY_SMSC #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ -- 2.17.1

2 1

[PATCH V3] ARM: dts: stm32: Add DH Electronics DHCOM SoM and PDK2 board
by Marek Vasut 12 Feb '20

12 Feb '20

Add support for DH Electronics DHCOM SoM and PDK2 rev. 400 carrier board. This is an SoM with STM32MP15xx and an evaluation kit. The baseboard provides Ethernet, UART, USB, CAN and optional display. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Patrick Delaunay <patrick.delaunay(a)st.com> Cc: Patrice Chotard <patrice.chotard(a)st.com> --- V2: Rebase on u-boot/master and multi-board changes. V3: - Fold in changes from Patrick to scrub more ST-board bits - Rename DTs to stm32mp15xx-dhcom* as the devkit can host any of the STM32MP1 SoCs --- arch/arm/dts/Makefile | 3 +- .../dts/stm32mp15xx-dhcom-pdk2-u-boot.dtsi | 6 + arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts | 88 +++ arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi | 238 ++++++ arch/arm/dts/stm32mp15xx-dhcom.dtsi | 379 ++++++++++ arch/arm/mach-stm32mp/Kconfig | 9 + board/dhelectronics/dh_stm32mp1/Kconfig | 21 + board/dhelectronics/dh_stm32mp1/MAINTAINERS | 7 + board/dhelectronics/dh_stm32mp1/Makefile | 10 + board/dhelectronics/dh_stm32mp1/board.c | 689 ++++++++++++++++++ configs/stm32mp15_dhcom_basic_defconfig | 138 ++++ 11 files changed, 1587 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/stm32mp15xx-dhcom-pdk2-u-boot.dtsi create mode 100644 arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts create mode 100644 arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi create mode 100644 arch/arm/dts/stm32mp15xx-dhcom.dtsi create mode 100644 board/dhelectronics/dh_stm32mp1/Kconfig create mode 100644 board/dhelectronics/dh_stm32mp1/MAINTAINERS create mode 100644 board/dhelectronics/dh_stm32mp1/Makefile create mode 100644 board/dhelectronics/dh_stm32mp1/board.c create mode 100644 configs/stm32mp15_dhcom_basic_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index b48b05fd24..7c868ba8d7 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -874,7 +874,8 @@ dtb-$(CONFIG_STM32MP15x) += \ stm32mp157a-avenger96.dtb \ stm32mp157c-dk2.dtb \ stm32mp157c-ed1.dtb \ - stm32mp157c-ev1.dtb + stm32mp157c-ev1.dtb \ + stm32mp15xx-dhcom-pdk2.dtb dtb-$(CONFIG_SOC_K3_AM6) += k3-am654-base-board.dtb k3-am654-r5-base-board.dtb dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-common-proc-board.dtb \ diff --git a/arch/arm/dts/stm32mp15xx-dhcom-pdk2-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-pdk2-u-boot.dtsi new file mode 100644 index 0000000000..12f89b3398 --- /dev/null +++ b/arch/arm/dts/stm32mp15xx-dhcom-pdk2-u-boot.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2019 Marek Vasut <marex(a)denx.de> + */ + +#include "stm32mp15xx-dhcom-u-boot.dtsi" diff --git a/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts b/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts new file mode 100644 index 0000000000..dd98c7abee --- /dev/null +++ b/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2019 Marek Vasut <marex(a)denx.de> + */ + +#include "stm32mp15xx-dhcom.dtsi" + +/ { + model = "STMicroelectronics STM32MP15xx DHCOM Premium Developer Kit (2)"; + compatible = "dh,stm32mp15xx-dhcom-pdk2", "st,stm32mp15x"; + + aliases { + serial0 = &uart4; + ethernet0 = &ethernet0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + ethernet_vio: vioregulator { + compatible = "regulator-fixed"; + regulator-name = "vio"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpiog 3 GPIO_ACTIVE_LOW>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&ethernet0 { + status = "okay"; + pinctrl-0 = <&ethernet0_rmii_pins_a>; + pinctrl-1 = <&ethernet0_rmii_pins_sleep_a>; + pinctrl-names = "default", "sleep"; + phy-mode = "rmii"; + max-speed = <100>; + phy-handle = <&phy0>; + st,eth_ref_clk_sel; + phy-reset-gpios = <&gpioh 15 GPIO_ACTIVE_LOW>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + phy0: ethernet-phy@1 { + reg = <1>; + }; + }; +}; + +&pinctrl { + ethernet0_rmii_pins_a: rmii-0 { + pins1 { + pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */ + <STM32_PINMUX('G', 14, AF11)>, /* ETH1_RMII_TXD1 */ + <STM32_PINMUX('B', 11, AF11)>, /* ETH1_RMII_TX_EN */ + <STM32_PINMUX('A', 1, AF0)>, /* ETH1_RMII_REF_CLK */ + <STM32_PINMUX('A', 2, AF11)>, /* ETH1_MDIO */ + <STM32_PINMUX('C', 1, AF11)>; /* ETH1_MDC */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + pins2 { + pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH1_RMII_RXD0 */ + <STM32_PINMUX('C', 5, AF11)>, /* ETH1_RMII_RXD1 */ + <STM32_PINMUX('A', 7, AF11)>; /* ETH1_RMII_CRS_DV */ + bias-disable; + }; + }; + + ethernet0_rmii_pins_sleep_a: rmii-sleep-0 { + pins1 { + pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_RMII_TXD0 */ + <STM32_PINMUX('G', 14, ANALOG)>, /* ETH1_RMII_TXD1 */ + <STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_RMII_TX_EN */ + <STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */ + <STM32_PINMUX('C', 1, ANALOG)>, /* ETH1_MDC */ + <STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RMII_RXD0 */ + <STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RMII_RXD1 */ + <STM32_PINMUX('A', 1, ANALOG)>, /* ETH1_RMII_REF_CLK */ + <STM32_PINMUX('A', 7, ANALOG)>; /* ETH1_RMII_CRS_DV */ + }; + }; +}; diff --git a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi new file mode 100644 index 0000000000..320912edd8 --- /dev/null +++ b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi @@ -0,0 +1,238 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2019 Marek Vasut <marex(a)denx.de> + */ + +#include <dt-bindings/clock/stm32mp1-clksrc.h> +#include "stm32mp157-u-boot.dtsi" +#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi" + +/ { + aliases { + i2c1 = &i2c2; + i2c3 = &i2c4; + i2c4 = &i2c5; + mmc0 = &sdmmc1; + mmc1 = &sdmmc2; + spi0 = &qspi; + usb0 = &usbotg_hs; + }; + + config { + u-boot,boot-led = "heartbeat"; + u-boot,error-led = "error"; + st,fastboot-gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; + st,stm32prog-gpios = <&gpioa 14 GPIO_ACTIVE_LOW>; + }; + + led { + red { + label = "error"; + gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; + default-state = "off"; + status = "okay"; + }; + + blue { + default-state = "on"; + }; + }; +}; + +&i2c4 { + u-boot,dm-pre-reloc; +}; + +&i2c4_pins_a { + u-boot,dm-pre-reloc; + pins { + u-boot,dm-pre-reloc; + }; +}; + +&pmic { + u-boot,dm-pre-reloc; +}; + +&flash0 { + u-boot,dm-spl; +}; + +&qspi { + u-boot,dm-spl; +}; + +&qspi_clk_pins_a { + u-boot,dm-spl; + pins { + u-boot,dm-spl; + }; +}; + +&qspi_bk1_pins_a { + u-boot,dm-spl; + pins1 { + u-boot,dm-spl; + }; + pins2 { + u-boot,dm-spl; + }; +}; + +&qspi_bk2_pins_a { + u-boot,dm-spl; + pins1 { + u-boot,dm-spl; + }; + pins2 { + u-boot,dm-spl; + }; +}; + +&rcc { + st,clksrc = < + CLK_MPU_PLL1P + CLK_AXI_PLL2P + CLK_MCU_PLL3P + CLK_PLL12_HSE + CLK_PLL3_HSE + CLK_PLL4_HSE + CLK_RTC_LSE + CLK_MCO1_DISABLED + CLK_MCO2_DISABLED + >; + + st,clkdiv = < + 1 /*MPU*/ + 0 /*AXI*/ + 0 /*MCU*/ + 1 /*APB1*/ + 1 /*APB2*/ + 1 /*APB3*/ + 1 /*APB4*/ + 2 /*APB5*/ + 23 /*RTC*/ + 0 /*MCO1*/ + 0 /*MCO2*/ + >; + + st,pkcs = < + CLK_CKPER_HSE + CLK_FMC_ACLK + CLK_QSPI_ACLK + CLK_ETH_PLL4P + CLK_SDMMC12_PLL4P + CLK_DSI_DSIPLL + CLK_STGEN_HSE + CLK_USBPHY_HSE + CLK_SPI2S1_PLL3Q + CLK_SPI2S23_PLL3Q + CLK_SPI45_HSI + CLK_SPI6_HSI + CLK_I2C46_HSI + CLK_SDMMC3_PLL4P + CLK_USBO_USBPHY + CLK_ADC_CKPER + CLK_CEC_LSE + CLK_I2C12_HSI + CLK_I2C35_HSI + CLK_UART1_HSI + CLK_UART24_HSI + CLK_UART35_HSI + CLK_UART6_HSI + CLK_UART78_HSI + CLK_SPDIF_PLL4P + CLK_FDCAN_PLL4Q + CLK_SAI1_PLL3Q + CLK_SAI2_PLL3Q + CLK_SAI3_PLL3Q + CLK_SAI4_PLL3Q + CLK_RNG1_LSI + CLK_RNG2_LSI + CLK_LPTIM1_PCLK1 + CLK_LPTIM23_PCLK3 + CLK_LPTIM45_LSE + >; + + /* VCO = 1300.0 MHz => P = 650 (CPU) */ + pll1: st,pll@0 { + cfg = < 2 80 0 0 0 PQR(1,0,0) >; + frac = < 0x800 >; + u-boot,dm-pre-reloc; + }; + + /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */ + pll2: st,pll@1 { + cfg = < 2 65 1 0 0 PQR(1,1,1) >; + frac = < 0x1400 >; + u-boot,dm-pre-reloc; + }; + + /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */ + pll3: st,pll@2 { + cfg = < 1 33 1 16 36 PQR(1,1,1) >; + frac = < 0x1a04 >; + u-boot,dm-pre-reloc; + }; + + /* VCO = 600.0 MHz => P = 50, Q = 50, R = 50 */ + pll4: st,pll@3 { + cfg = < 1 49 11 11 11 PQR(1,1,1) >; + u-boot,dm-pre-reloc; + }; +}; + +&sdmmc1 { + u-boot,dm-spl; +}; + +&sdmmc1_b4_pins_a { + u-boot,dm-spl; + pins { + u-boot,dm-spl; + }; +}; + +&sdmmc1_dir_pins_a { + u-boot,dm-spl; + pins1 { + u-boot,dm-spl; + }; + pins2 { + u-boot,dm-spl; + }; +}; + +&sdmmc2 { + u-boot,dm-spl; +}; + +&sdmmc2_b4_pins_a { + u-boot,dm-spl; + pins { + u-boot,dm-spl; + }; +}; + +&sdmmc2_d47_pins_a { + u-boot,dm-spl; + pins { + u-boot,dm-spl; + }; +}; + +&uart4 { + u-boot,dm-pre-reloc; +}; + +&uart4_pins_a { + u-boot,dm-pre-reloc; + pins1 { + u-boot,dm-pre-reloc; + }; + pins2 { + u-boot,dm-pre-reloc; + /* pull-up on rx to avoid floating level */ + bias-pull-up; + }; +}; diff --git a/arch/arm/dts/stm32mp15xx-dhcom.dtsi b/arch/arm/dts/stm32mp15xx-dhcom.dtsi new file mode 100644 index 0000000000..96661ae783 --- /dev/null +++ b/arch/arm/dts/stm32mp15xx-dhcom.dtsi @@ -0,0 +1,379 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2019 Marek Vasut <marex(a)denx.de> + */ +/dts-v1/; + +#include "stm32mp157c.dtsi" +#include "stm32mp157xaa-pinctrl.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/mfd/st,stpmic1.h> + +/ { + memory@c0000000 { + device_type = "memory"; + reg = <0xC0000000 0x40000000>; + }; +}; + +&cec { + pinctrl-names = "default"; + pinctrl-0 = <&cec_pins_a>; + status = "okay"; +}; + +&dcmi { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&dcmi_pins_a>; + pinctrl-1 = <&dcmi_sleep_pins_a>; +}; + +&dts { + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + + pmic: stpmic@33 { + compatible = "st,stpmic1"; + reg = <0x33>; + interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + status = "okay"; + + regulators { + compatible = "st,stpmic1-regulators"; + ldo1-supply = <&v3v3>; + ldo2-supply = <&v3v3>; + ldo3-supply = <&vdd_ddr>; + ldo5-supply = <&v3v3>; + ldo6-supply = <&v3v3>; + pwr_sw1-supply = <&bst_out>; + pwr_sw2-supply = <&bst_out>; + + vddcore: buck1 { + regulator-name = "vddcore"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd_ddr: buck2 { + regulator-name = "vdd_ddr"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd: buck3 { + regulator-name = "vdd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + st,mask-reset; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + v3v3: buck4 { + regulator-name = "v3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-over-current-protection; + regulator-initial-mode = <0>; + }; + + vdda: ldo1 { + regulator-name = "vdda"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + interrupts = <IT_CURLIM_LDO1 0>; + }; + + v2v8: ldo2 { + regulator-name = "v2v8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + interrupts = <IT_CURLIM_LDO2 0>; + }; + + vtt_ddr: ldo3 { + regulator-name = "vtt_ddr"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <750000>; + regulator-always-on; + regulator-over-current-protection; + }; + + vdd_usb: ldo4 { + regulator-name = "vdd_usb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + interrupts = <IT_CURLIM_LDO4 0>; + }; + + vdd_sd: ldo5 { + regulator-name = "vdd_sd"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + interrupts = <IT_CURLIM_LDO5 0>; + regulator-boot-on; + }; + + v1v8: ldo6 { + regulator-name = "v1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + interrupts = <IT_CURLIM_LDO6 0>; + }; + + vref_ddr: vref_ddr { + regulator-name = "vref_ddr"; + regulator-always-on; + regulator-over-current-protection; + }; + + bst_out: boost { + regulator-name = "bst_out"; + interrupts = <IT_OCP_BOOST 0>; + }; + + vbus_otg: pwr_sw1 { + regulator-name = "vbus_otg"; + interrupts = <IT_OCP_OTG 0>; + }; + + vbus_sw: pwr_sw2 { + regulator-name = "vbus_sw"; + interrupts = <IT_OCP_SWOUT 0>; + regulator-active-discharge; + }; + }; + + onkey { + compatible = "st,stpmic1-onkey"; + interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 0>; + interrupt-names = "onkey-falling", "onkey-rising"; + power-off-time-sec = <10>; + status = "okay"; + }; + + watchdog { + compatible = "st,stpmic1-wdt"; + status = "disabled"; + }; + }; + + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +&i2c5 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; +}; + +&ipcc { + status = "okay"; +}; + +&iwdg2 { + timeout-sec = <32>; + status = "okay"; +}; + +&m4_rproc { + mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>; + mbox-names = "vq0", "vq1", "shutdown"; + status = "okay"; +}; + +&pwr { + pwr-regulators { + vdd-supply = <&vdd>; + vdd_3v3_usbfs-supply = <&vdd_usb>; + }; +}; + +&qspi { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a &qspi_bk2_pins_a>; + pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a &qspi_bk2_sleep_pins_a>; + reg = <0x58003000 0x1000>, <0x70000000 0x4000000>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + flash0: mx66l51235l@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-rx-bus-width = <4>; + spi-max-frequency = <108000000>; + #address-cells = <1>; + #size-cells = <1>; + }; + + flash1: mx66l51235l@1 { + compatible = "jedec,spi-nor"; + reg = <1>; + spi-rx-bus-width = <4>; + spi-max-frequency = <108000000>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +&rng1 { + status = "okay"; +}; + +&rtc { + status = "okay"; +}; + +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_a>; + broken-cd; + st,sig-dir; + st,neg-edge; + st,use-ckin; + bus-width = <4>; + vmmc-supply = <&vdd_sd>; + status = "okay"; +}; + +&sdmmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>; + non-removable; + no-sd; + no-sdio; + st,sig-dir; + st,neg-edge; + bus-width = <8>; + vmmc-supply = <&v3v3>; + status = "okay"; +}; + +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins_a>; + status = "disabled"; +}; + +&timers2 { + /* spare dmas for other usage (un-delete to enable pwm capture) */ + /delete-property/dmas; + /delete-property/dma-names; + status = "disabled"; + pwm { + pinctrl-0 = <&pwm2_pins_a>; + pinctrl-names = "default"; + status = "okay"; + }; + timer@1 { + status = "okay"; + }; +}; + +&timers6 { + status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + timer@5 { + status = "okay"; + }; +}; + +&timers8 { + /delete-property/dmas; + /delete-property/dma-names; + status = "disabled"; + pwm { + pinctrl-0 = <&pwm8_pins_a>; + pinctrl-names = "default"; + status = "okay"; + }; + timer@7 { + status = "okay"; + }; +}; + +&timers12 { + /delete-property/dmas; + /delete-property/dma-names; + status = "disabled"; + pwm { + pinctrl-0 = <&pwm12_pins_a>; + pinctrl-names = "default"; + status = "okay"; + }; + timer@11 { + status = "okay"; + }; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins_a>; + status = "okay"; +}; + +&usbh_ehci { + phys = <&usbphyc_port0>; + phy-names = "usb"; + status = "okay"; +}; + +&usbotg_hs { + dr_mode = "peripheral"; + phys = <&usbphyc_port1 0>; + phy-names = "usb2-phy"; + vbus-supply = <&vbus_otg>; + status = "okay"; +}; + +&usbphyc { + status = "okay"; +}; + +&usbphyc_port0 { + phy-supply = <&vdd_usb>; +}; + +&usbphyc_port1 { + phy-supply = <&vdd_usb>; +}; diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig index 137178aa45..e4d621dee8 100644 --- a/arch/arm/mach-stm32mp/Kconfig +++ b/arch/arm/mach-stm32mp/Kconfig @@ -73,6 +73,14 @@ config TARGET_ST_STM32MP15x Evalulation board (EV1) or Discovery board (DK1 and DK2). The difference between board are managed with devicetree +config TARGET_DH_STM32MP1_PDK2 + bool "DH STM32MP1 PDK2" + select STM32MP15x + imply BOOTCOUNT_LIMIT + imply CMD_BOOTCOUNT + help + Target the DH PDK2 development kit with STM32MP15x SoM. + endchoice config STM32MP1_TRUSTED @@ -158,5 +166,6 @@ config DEBUG_UART_CLOCK endif source "board/st/stm32mp1/Kconfig" +source "board/dhelectronics/dh_stm32mp1/Kconfig" endif diff --git a/board/dhelectronics/dh_stm32mp1/Kconfig b/board/dhelectronics/dh_stm32mp1/Kconfig new file mode 100644 index 0000000000..8eab986640 --- /dev/null +++ b/board/dhelectronics/dh_stm32mp1/Kconfig @@ -0,0 +1,21 @@ +if TARGET_DH_STM32MP1_PDK2 + +config SYS_BOARD + default "dh_stm32mp1" + +config SYS_VENDOR + default "dhelectronics" + +config SYS_CONFIG_NAME + default "stm32mp1" + +config ENV_SECT_SIZE + default 0x10000 if ENV_IS_IN_SPI_FLASH + +config ENV_OFFSET + default 0x1E0000 if ENV_IS_IN_SPI_FLASH + +config ENV_OFFSET_REDUND + default 0x1F0000 if ENV_IS_IN_SPI_FLASH + +endif diff --git a/board/dhelectronics/dh_stm32mp1/MAINTAINERS b/board/dhelectronics/dh_stm32mp1/MAINTAINERS new file mode 100644 index 0000000000..1511ecb65d --- /dev/null +++ b/board/dhelectronics/dh_stm32mp1/MAINTAINERS @@ -0,0 +1,7 @@ +DH_STM32MP1_PDK2 BOARD +M: Marek Vasut <marex(a)denx.de> +S: Maintained +F: arch/arm/dts/stm32mp15xx-dhcom* +F: board/dhelectronics/dh_stm32mp1/ +F: configs/stm32mp15_dhcom_basic_defconfig +F: include/configs/stm32mp1.h diff --git a/board/dhelectronics/dh_stm32mp1/Makefile b/board/dhelectronics/dh_stm32mp1/Makefile new file mode 100644 index 0000000000..b42c4e4c04 --- /dev/null +++ b/board/dhelectronics/dh_stm32mp1/Makefile @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +# +# Copyright (C) 2018, STMicroelectronics - All Rights Reserved +# + +ifdef CONFIG_SPL_BUILD +obj-y += ../../st/stm32mp1/spl.o +endif + +obj-y += ../../st/stm32mp1/board.o board.o diff --git a/board/dhelectronics/dh_stm32mp1/board.c b/board/dhelectronics/dh_stm32mp1/board.c new file mode 100644 index 0000000000..b663696983 --- /dev/null +++ b/board/dhelectronics/dh_stm32mp1/board.c @@ -0,0 +1,689 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2018, STMicroelectronics - All Rights Reserved + */ + +#include <common.h> +#include <adc.h> +#include <asm/arch/stm32.h> +#include <asm/arch/sys_proto.h> +#include <asm/gpio.h> +#include <asm/io.h> +#include <bootm.h> +#include <clk.h> +#include <config.h> +#include <dm.h> +#include <dm/device.h> +#include <dm/uclass.h> +#include <env.h> +#include <env_internal.h> +#include <g_dnl.h> +#include <generic-phy.h> +#include <hang.h> +#include <i2c.h> +#include <i2c_eeprom.h> +#include <init.h> +#include <led.h> +#include <memalign.h> +#include <misc.h> +#include <mtd.h> +#include <mtd_node.h> +#include <netdev.h> +#include <phy.h> +#include <power/regulator.h> +#include <remoteproc.h> +#include <reset.h> +#include <syscon.h> +#include <usb.h> +#include <usb/dwc2_udc.h> +#include <watchdog.h> + +/* SYSCFG registers */ +#define SYSCFG_BOOTR 0x00 +#define SYSCFG_PMCSETR 0x04 +#define SYSCFG_IOCTRLSETR 0x18 +#define SYSCFG_ICNR 0x1C +#define SYSCFG_CMPCR 0x20 +#define SYSCFG_CMPENSETR 0x24 +#define SYSCFG_PMCCLRR 0x44 + +#define SYSCFG_BOOTR_BOOT_MASK GENMASK(2, 0) +#define SYSCFG_BOOTR_BOOTPD_SHIFT 4 + +#define SYSCFG_IOCTRLSETR_HSLVEN_TRACE BIT(0) +#define SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI BIT(1) +#define SYSCFG_IOCTRLSETR_HSLVEN_ETH BIT(2) +#define SYSCFG_IOCTRLSETR_HSLVEN_SDMMC BIT(3) +#define SYSCFG_IOCTRLSETR_HSLVEN_SPI BIT(4) + +#define SYSCFG_CMPCR_SW_CTRL BIT(1) +#define SYSCFG_CMPCR_READY BIT(8) + +#define SYSCFG_CMPENSETR_MPU_EN BIT(0) + +#define SYSCFG_PMCSETR_ETH_CLK_SEL BIT(16) +#define SYSCFG_PMCSETR_ETH_REF_CLK_SEL BIT(17) + +#define SYSCFG_PMCSETR_ETH_SELMII BIT(20) + +#define SYSCFG_PMCSETR_ETH_SEL_MASK GENMASK(23, 21) +#define SYSCFG_PMCSETR_ETH_SEL_GMII_MII 0 +#define SYSCFG_PMCSETR_ETH_SEL_RGMII BIT(21) +#define SYSCFG_PMCSETR_ETH_SEL_RMII BIT(23) + +/* + * Get a global data pointer + */ +DECLARE_GLOBAL_DATA_PTR; + +int setup_mac_address(void) +{ + struct udevice *dev; + ofnode eeprom; + unsigned char enetaddr[6]; + int ret; + + ret = eth_env_get_enetaddr("ethaddr", enetaddr); + if (ret) /* ethaddr is already set */ + return 0; + + eeprom = ofnode_path("/soc/i2c@5c002000/eeprom@50"); + if (!ofnode_valid(eeprom)) { + printf("Invalid hardware path to EEPROM!\n"); + return -ENODEV; + } + + ret = uclass_get_device_by_ofnode(UCLASS_I2C_EEPROM, eeprom, &dev); + if (ret) { + printf("Cannot find EEPROM!\n"); + return ret; + } + + ret = i2c_eeprom_read(dev, 0xfa, enetaddr, 0x6); + if (ret) { + printf("Error reading configuration EEPROM!\n"); + return ret; + } + + if (is_valid_ethaddr(enetaddr)) + eth_env_set_enetaddr("ethaddr", enetaddr); + + return 0; +} + +int checkboard(void) +{ + char *mode; + const char *fdt_compat; + int fdt_compat_len; + + if (IS_ENABLED(CONFIG_STM32MP1_OPTEE)) + mode = "trusted with OP-TEE"; + else if (IS_ENABLED(CONFIG_STM32MP1_TRUSTED)) + mode = "trusted"; + else + mode = "basic"; + + printf("Board: stm32mp1 in %s mode", mode); + fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible", + &fdt_compat_len); + if (fdt_compat && fdt_compat_len) + printf(" (%s)", fdt_compat); + puts("\n"); + + return 0; +} + +static void board_key_check(void) +{ +#if defined(CONFIG_FASTBOOT) || defined(CONFIG_CMD_STM32PROG) + ofnode node; + struct gpio_desc gpio; + enum forced_boot_mode boot_mode = BOOT_NORMAL; + + node = ofnode_path("/config"); + if (!ofnode_valid(node)) { + debug("%s: no /config node?\n", __func__); + return; + } +#ifdef CONFIG_FASTBOOT + if (gpio_request_by_name_nodev(node, "st,fastboot-gpios", 0, + &gpio, GPIOD_IS_IN)) { + debug("%s: could not find a /config/st,fastboot-gpios\n", + __func__); + } else { + if (dm_gpio_get_value(&gpio)) { + puts("Fastboot key pressed, "); + boot_mode = BOOT_FASTBOOT; + } + + dm_gpio_free(NULL, &gpio); + } +#endif +#ifdef CONFIG_CMD_STM32PROG + if (gpio_request_by_name_nodev(node, "st,stm32prog-gpios", 0, + &gpio, GPIOD_IS_IN)) { + debug("%s: could not find a /config/st,stm32prog-gpios\n", + __func__); + } else { + if (dm_gpio_get_value(&gpio)) { + puts("STM32Programmer key pressed, "); + boot_mode = BOOT_STM32PROG; + } + dm_gpio_free(NULL, &gpio); + } +#endif + + if (boot_mode != BOOT_NORMAL) { + puts("entering download mode...\n"); + clrsetbits_le32(TAMP_BOOT_CONTEXT, + TAMP_BOOT_FORCED_MASK, + boot_mode); + } +#endif +} + +#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG) + +#include <usb/dwc2_udc.h> +int g_dnl_board_usb_cable_connected(void) +{ + struct udevice *dwc2_udc_otg; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_USB_GADGET_GENERIC, + DM_GET_DRIVER(dwc2_udc_otg), + &dwc2_udc_otg); + if (!ret) + debug("dwc2_udc_otg init failed\n"); + + return dwc2_udc_B_session_valid(dwc2_udc_otg); +} + +#define STM32MP1_G_DNL_DFU_PRODUCT_NUM 0xdf11 +#define STM32MP1_G_DNL_FASTBOOT_PRODUCT_NUM 0x0afb + +int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name) +{ + if (!strcmp(name, "usb_dnl_dfu")) + put_unaligned(STM32MP1_G_DNL_DFU_PRODUCT_NUM, &dev->idProduct); + else if (!strcmp(name, "usb_dnl_fastboot")) + put_unaligned(STM32MP1_G_DNL_FASTBOOT_PRODUCT_NUM, + &dev->idProduct); + else + put_unaligned(CONFIG_USB_GADGET_PRODUCT_NUM, &dev->idProduct); + + return 0; +} + +#endif /* CONFIG_USB_GADGET */ + +#ifdef CONFIG_LED +static int get_led(struct udevice **dev, char *led_string) +{ + char *led_name; + int ret; + + led_name = fdtdec_get_config_string(gd->fdt_blob, led_string); + if (!led_name) { + pr_debug("%s: could not find %s config string\n", + __func__, led_string); + return -ENOENT; + } + ret = led_get_by_label(led_name, dev); + if (ret) { + debug("%s: get=%d\n", __func__, ret); + return ret; + } + + return 0; +} + +static int setup_led(enum led_state_t cmd) +{ + struct udevice *dev; + int ret; + + ret = get_led(&dev, "u-boot,boot-led"); + if (ret) + return ret; + + ret = led_set_state(dev, cmd); + return ret; +} +#endif + +static void __maybe_unused led_error_blink(u32 nb_blink) +{ +#ifdef CONFIG_LED + int ret; + struct udevice *led; + u32 i; +#endif + + if (!nb_blink) + return; + +#ifdef CONFIG_LED + ret = get_led(&led, "u-boot,error-led"); + if (!ret) { + /* make u-boot,error-led blinking */ + /* if U32_MAX and 125ms interval, for 17.02 years */ + for (i = 0; i < 2 * nb_blink; i++) { + led_set_state(led, LEDST_TOGGLE); + mdelay(125); + WATCHDOG_RESET(); + } + } +#endif + + /* infinite: the boot process must be stopped */ + if (nb_blink == U32_MAX) + hang(); +} + +static void sysconf_init(void) +{ +#ifndef CONFIG_STM32MP1_TRUSTED + u8 *syscfg; +#ifdef CONFIG_DM_REGULATOR + struct udevice *pwr_dev; + struct udevice *pwr_reg; + struct udevice *dev; + int ret; + u32 otp = 0; +#endif + u32 bootr; + + syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG); + + /* interconnect update : select master using the port 1 */ + /* LTDC = AXI_M9 */ + /* GPU = AXI_M8 */ + /* today information is hardcoded in U-Boot */ + writel(BIT(9), syscfg + SYSCFG_ICNR); + + /* disable Pull-Down for boot pin connected to VDD */ + bootr = readl(syscfg + SYSCFG_BOOTR); + bootr &= ~(SYSCFG_BOOTR_BOOT_MASK << SYSCFG_BOOTR_BOOTPD_SHIFT); + bootr |= (bootr & SYSCFG_BOOTR_BOOT_MASK) << SYSCFG_BOOTR_BOOTPD_SHIFT; + writel(bootr, syscfg + SYSCFG_BOOTR); + +#ifdef CONFIG_DM_REGULATOR + /* High Speed Low Voltage Pad mode Enable for SPI, SDMMC, ETH, QSPI + * and TRACE. Needed above ~50MHz and conditioned by AFMUX selection. + * The customer will have to disable this for low frequencies + * or if AFMUX is selected but the function not used, typically for + * TRACE. Otherwise, impact on power consumption. + * + * WARNING: + * enabling High Speed mode while VDD>2.7V + * with the OTP product_below_2v5 (OTP 18, BIT 13) + * erroneously set to 1 can damage the IC! + * => U-Boot set the register only if VDD < 2.7V (in DT) + * but this value need to be consistent with board design + */ + ret = uclass_get_device_by_driver(UCLASS_PMIC, + DM_GET_DRIVER(stm32mp_pwr_pmic), + &pwr_dev); + if (!ret) { + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_GET_DRIVER(stm32mp_bsec), + &dev); + if (ret) { + pr_err("Can't find stm32mp_bsec driver\n"); + return; + } + + ret = misc_read(dev, STM32_BSEC_SHADOW(18), &otp, 4); + if (ret > 0) + otp = otp & BIT(13); + + /* get VDD = vdd-supply */ + ret = device_get_supply_regulator(pwr_dev, "vdd-supply", + &pwr_reg); + + /* check if VDD is Low Voltage */ + if (!ret) { + if (regulator_get_value(pwr_reg) < 2700000) { + writel(SYSCFG_IOCTRLSETR_HSLVEN_TRACE | + SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI | + SYSCFG_IOCTRLSETR_HSLVEN_ETH | + SYSCFG_IOCTRLSETR_HSLVEN_SDMMC | + SYSCFG_IOCTRLSETR_HSLVEN_SPI, + syscfg + SYSCFG_IOCTRLSETR); + + if (!otp) + pr_err("product_below_2v5=0: HSLVEN protected by HW\n"); + } else { + if (otp) + pr_err("product_below_2v5=1: HSLVEN update is destructive, no update as VDD>2.7V\n"); + } + } else { + debug("VDD unknown"); + } + } +#endif + + /* activate automatic I/O compensation + * warning: need to ensure CSI enabled and ready in clock driver + */ + writel(SYSCFG_CMPENSETR_MPU_EN, syscfg + SYSCFG_CMPENSETR); + + while (!(readl(syscfg + SYSCFG_CMPCR) & SYSCFG_CMPCR_READY)) + ; + clrbits_le32(syscfg + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL); +#endif +} + +/* board dependent setup after realloc */ +int board_init(void) +{ + struct udevice *dev; + + /* address of boot parameters */ + gd->bd->bi_boot_params = STM32_DDR_BASE + 0x100; + + /* probe all PINCTRL for hog */ + for (uclass_first_device(UCLASS_PINCTRL, &dev); + dev; + uclass_next_device(&dev)) { + pr_debug("probe pincontrol = %s\n", dev->name); + } + + board_key_check(); + +#ifdef CONFIG_DM_REGULATOR + regulators_enable_boot_on(_DEBUG); +#endif + + sysconf_init(); + + if (CONFIG_IS_ENABLED(CONFIG_LED)) + led_default_state(); + + return 0; +} + +int board_late_init(void) +{ + char *boot_device; +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + const void *fdt_compat; + int fdt_compat_len; + + fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible", + &fdt_compat_len); + if (fdt_compat && fdt_compat_len) { + if (strncmp(fdt_compat, "st,", 3) != 0) + env_set("board_name", fdt_compat); + else + env_set("board_name", fdt_compat + 3); + } +#endif + + /* Check the boot-source to disable bootdelay */ + boot_device = env_get("boot_device"); + if (!strcmp(boot_device, "serial") || !strcmp(boot_device, "usb")) + env_set("bootdelay", "0"); + + return 0; +} + +void board_quiesce_devices(void) +{ +#ifdef CONFIG_LED + setup_led(LEDST_OFF); +#endif +} + +/* eth init function : weak called in eqos driver */ +int board_interface_eth_init(struct udevice *dev, + phy_interface_t interface_type) +{ + u8 *syscfg; + u32 value; + bool eth_clk_sel_reg = false; + bool eth_ref_clk_sel_reg = false; + + /* Gigabit Ethernet 125MHz clock selection. */ + eth_clk_sel_reg = dev_read_bool(dev, "st,eth_clk_sel"); + + /* Ethernet 50Mhz RMII clock selection */ + eth_ref_clk_sel_reg = + dev_read_bool(dev, "st,eth_ref_clk_sel"); + + syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG); + + if (!syscfg) + return -ENODEV; + + switch (interface_type) { + case PHY_INTERFACE_MODE_MII: + value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII | + SYSCFG_PMCSETR_ETH_REF_CLK_SEL; + debug("%s: PHY_INTERFACE_MODE_MII\n", __func__); + break; + case PHY_INTERFACE_MODE_GMII: + if (eth_clk_sel_reg) + value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII | + SYSCFG_PMCSETR_ETH_CLK_SEL; + else + value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII; + debug("%s: PHY_INTERFACE_MODE_GMII\n", __func__); + break; + case PHY_INTERFACE_MODE_RMII: + if (eth_ref_clk_sel_reg) + value = SYSCFG_PMCSETR_ETH_SEL_RMII | + SYSCFG_PMCSETR_ETH_REF_CLK_SEL; + else + value = SYSCFG_PMCSETR_ETH_SEL_RMII; + debug("%s: PHY_INTERFACE_MODE_RMII\n", __func__); + break; + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: + if (eth_clk_sel_reg) + value = SYSCFG_PMCSETR_ETH_SEL_RGMII | + SYSCFG_PMCSETR_ETH_CLK_SEL; + else + value = SYSCFG_PMCSETR_ETH_SEL_RGMII; + debug("%s: PHY_INTERFACE_MODE_RGMII\n", __func__); + break; + default: + debug("%s: Do not manage %d interface\n", + __func__, interface_type); + /* Do not manage others interfaces */ + return -EINVAL; + } + + /* clear and set ETH configuration bits */ + writel(SYSCFG_PMCSETR_ETH_SEL_MASK | SYSCFG_PMCSETR_ETH_SELMII | + SYSCFG_PMCSETR_ETH_REF_CLK_SEL | SYSCFG_PMCSETR_ETH_CLK_SEL, + syscfg + SYSCFG_PMCCLRR); + writel(value, syscfg + SYSCFG_PMCSETR); + + return 0; +} + +enum env_location env_get_location(enum env_operation op, int prio) +{ + if (prio) + return ENVL_UNKNOWN; + +#ifdef CONFIG_ENV_IS_IN_SPI_FLASH + return ENVL_SPI_FLASH; +#else + return ENVL_NOWHERE; +#endif +} + +#ifdef CONFIG_SYS_MTDPARTS_RUNTIME + +#define MTDPARTS_LEN 256 +#define MTDIDS_LEN 128 + +/** + * The mtdparts_nand0 and mtdparts_nor0 variable tends to be long. + * If we need to access it before the env is relocated, then we need + * to use our own stack buffer. gd->env_buf will be too small. + * + * @param buf temporary buffer pointer MTDPARTS_LEN long + * @return mtdparts variable string, NULL if not found + */ +static const char *env_get_mtdparts(const char *str, char *buf) +{ + if (gd->flags & GD_FLG_ENV_READY) + return env_get(str); + if (env_get_f(str, buf, MTDPARTS_LEN) != -1) + return buf; + + return NULL; +} + +/** + * update the variables "mtdids" and "mtdparts" with content of mtdparts_<dev> + */ +static void board_get_mtdparts(const char *dev, + char *mtdids, + char *mtdparts) +{ + char env_name[32] = "mtdparts_"; + char tmp_mtdparts[MTDPARTS_LEN]; + const char *tmp; + + /* name of env variable to read = mtdparts_<dev> */ + strcat(env_name, dev); + tmp = env_get_mtdparts(env_name, tmp_mtdparts); + if (tmp) { + /* mtdids: "<dev>=<dev>, ...." */ + if (mtdids[0] != '\0') + strcat(mtdids, ","); + strcat(mtdids, dev); + strcat(mtdids, "="); + strcat(mtdids, dev); + + /* mtdparts: "mtdparts=<dev>:<mtdparts_<dev>>;..." */ + if (mtdparts[0] != '\0') + strncat(mtdparts, ";", MTDPARTS_LEN); + else + strcat(mtdparts, "mtdparts="); + strncat(mtdparts, dev, MTDPARTS_LEN); + strncat(mtdparts, ":", MTDPARTS_LEN); + strncat(mtdparts, tmp, MTDPARTS_LEN); + } +} + +void board_mtdparts_default(const char **mtdids, const char **mtdparts) +{ + struct udevice *dev; + static char parts[3 * MTDPARTS_LEN + 1]; + static char ids[MTDIDS_LEN + 1]; + static bool mtd_initialized; + + if (mtd_initialized) { + *mtdids = ids; + *mtdparts = parts; + return; + } + + memset(parts, 0, sizeof(parts)); + memset(ids, 0, sizeof(ids)); + + /* probe all MTD devices */ + for (uclass_first_device(UCLASS_MTD, &dev); + dev; + uclass_next_device(&dev)) { + pr_debug("mtd device = %s\n", dev->name); + } + + if (!uclass_get_device(UCLASS_SPI_FLASH, 0, &dev)) + board_get_mtdparts("nor0", ids, parts); + + mtd_initialized = true; + *mtdids = ids; + *mtdparts = parts; + debug("%s:mtdids=%s & mtdparts=%s\n", __func__, ids, parts); +} +#endif + +#if defined(CONFIG_OF_BOARD_SETUP) +int ft_board_setup(void *blob, bd_t *bd) +{ + return 0; +} +#endif + +#ifdef CONFIG_SET_DFU_ALT_INFO +#define DFU_ALT_BUF_LEN SZ_1K + +static void board_get_alt_info(const char *dev, char *buff) +{ + char var_name[32] = "dfu_alt_info_"; + int ret; + + ALLOC_CACHE_ALIGN_BUFFER(char, tmp_alt, DFU_ALT_BUF_LEN); + + /* name of env variable to read = dfu_alt_info_<dev> */ + strcat(var_name, dev); + ret = env_get_f(var_name, tmp_alt, DFU_ALT_BUF_LEN); + if (ret) { + if (buff[0] != '\0') + strcat(buff, "&"); + strncat(buff, tmp_alt, DFU_ALT_BUF_LEN); + } +} + +void set_dfu_alt_info(char *interface, char *devstr) +{ + struct udevice *dev; + + ALLOC_CACHE_ALIGN_BUFFER(char, buf, DFU_ALT_BUF_LEN); + + if (env_get("dfu_alt_info")) + return; + + memset(buf, 0, sizeof(buf)); + + /* probe all MTD devices */ + mtd_probe_devices(); + + board_get_alt_info("ram", buf); + + if (!uclass_get_device(UCLASS_MMC, 0, &dev)) + board_get_alt_info("mmc0", buf); + + if (!uclass_get_device(UCLASS_MMC, 1, &dev)) + board_get_alt_info("mmc1", buf); + + if (!uclass_get_device(UCLASS_SPI_FLASH, 0, &dev)) + board_get_alt_info("nor0", buf); + + env_set("dfu_alt_info", buf); + puts("DFU alt info setting: done\n"); +} +#endif + +static void board_copro_image_process(ulong fw_image, size_t fw_size) +{ + int ret, id = 0; /* Copro id fixed to 0 as only one coproc on mp1 */ + + if (!rproc_is_initialized()) + if (rproc_init()) { + printf("Remote Processor %d initialization failed\n", + id); + return; + } + + ret = rproc_load(id, fw_image, fw_size); + printf("Load Remote Processor %d with data@addr=0x%08lx %u bytes:%s\n", + id, fw_image, fw_size, ret ? " Failed!" : " Success!"); + + if (!ret) { + rproc_start(id); + env_set("copro_state", "booted"); + } +} + +U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_COPRO, board_copro_image_process); diff --git a/configs/stm32mp15_dhcom_basic_defconfig b/configs/stm32mp15_dhcom_basic_defconfig new file mode 100644 index 0000000000..921dea242a --- /dev/null +++ b/configs/stm32mp15_dhcom_basic_defconfig @@ -0,0 +1,138 @@ +CONFIG_ARM=y +CONFIG_ARCH_STM32MP=y +CONFIG_SYS_MALLOC_F_LEN=0x3000 +CONFIG_ENV_SIZE=0x4000 +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL=y +CONFIG_TARGET_DH_STM32MP1_PDK2=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +# CONFIG_ARMV7_VIRT is not set +CONFIG_SPL_TEXT_BASE=0x2FFC2500 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_BOOTCOMMAND="run bootcmd_stm32mp" +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=3 +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000 +CONFIG_SYS_PROMPT="STM32MP> " +# CONFIG_CMD_BOOTD is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +CONFIG_CMD_EEPROM=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_ADC=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_CMD_REMOTEPROC=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_MTDPARTS=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_DEFAULT_DEVICE_TREE="stm32mp15xx-dhcom-pdk2" +CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-names interrupts-extended interrupt-controller \\\#interrupt-cells interrupt-parent dmas dma-names assigned-clocks assigned-clock-rates assigned-clock-parents hwlocks" +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_USE_ENV_SPI_BUS=y +CONFIG_ENV_SPI_BUS=0 +CONFIG_USE_ENV_SPI_CS=y +CONFIG_ENV_SPI_CS=0 +CONFIG_USE_ENV_SPI_MAX_HZ=y +CONFIG_ENV_SPI_MAX_HZ=10000000 +CONFIG_USE_ENV_SPI_MODE=y +CONFIG_ENV_SPI_MODE=0x0 +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_IP_DEFRAG=y +CONFIG_TFTP_BLOCKSIZE=1536 +CONFIG_STM32_ADC=y +CONFIG_SPL_BLOCK_CACHE=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_DFU_VIRT=y +CONFIG_DM_HWSPINLOCK=y +CONFIG_HWSPINLOCK_STM32=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_STM32F7=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_DM_MAILBOX=y +CONFIG_STM32_IPCC=y +CONFIG_I2C_EEPROM=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_STM32_SDMMC2=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_SPI_FLASH_MTD=y +CONFIG_SPL_SPI_FLASH_MTD=y +CONFIG_DM_ETH=y +CONFIG_DWC_ETH_QOS=y +CONFIG_PHY=y +CONFIG_PHY_STM32_USBPHYC=y +CONFIG_PINCONF=y +# CONFIG_SPL_PINCTRL_FULL is not set +CONFIG_PINCTRL_STMFX=y +CONFIG_DM_PMIC=y +# CONFIG_SPL_PMIC_CHILDREN is not set +CONFIG_PMIC_STPMIC1=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_REGULATOR_STM32_VREFBUF=y +CONFIG_DM_REGULATOR_STPMIC1=y +CONFIG_REMOTEPROC_STM32_COPRO=y +CONFIG_DM_RTC=y +CONFIG_RTC_STM32=y +CONFIG_SERIAL_RX_BUFFER=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_STM32_QSPI=y +CONFIG_STM32_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="dh" +CONFIG_USB_GADGET_VENDOR_NUM=0x0483 +CONFIG_USB_GADGET_PRODUCT_NUM=0x5720 +CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_DM_VIDEO=y +CONFIG_BACKLIGHT_GPIO=y +CONFIG_VIDEO_LCD_ORISETECH_OTM8009A=y +CONFIG_VIDEO_LCD_RAYDIUM_RM68200=y +CONFIG_VIDEO_STM32=y +CONFIG_VIDEO_STM32_DSI=y +CONFIG_VIDEO_STM32_MAX_XRES=1280 +CONFIG_VIDEO_STM32_MAX_YRES=800 +CONFIG_LZO=y +CONFIG_FDT_FIXUP_PARTITIONS=y -- 2.24.1

2 2

[PATCH 00/10]
by Patrick Delaunay 12 Feb '20

12 Feb '20

env: ext4: add test for env in ext4 Hi, In this serie, I add sandbox test with CONFIG_ENV_IS_NOWHERE activated with other location: at least one CONFIG_ENV_IS_IN_... is defined and ENV_IS_IN_DEVICE is automatically defined. To test this feature, I activate and test ENV_IS_IN_EXT4 in sandbox; I add a new command "env_loc" to change this ENV location. This serie depends on previous env test introduced in: "cmd: env: add option for quiet output on env info" http://patchwork.ozlabs.org/project/uboot/list/?series=158105 To be able to test invalid file (bad CRC), I also add the support of the command "env erase" for EXT4 env location. Regards Patrick Patrick Delaunay (10): env: add absolute path at CONFIG_ENV_EXT4_FILE env: ext4: set gd->env_valid env: correctly handle result in env_init sandbox: activate env in ext4 support sandbox: support the change of env location test: environment in ext4 env: ext4: fix possible compilation issue env: ext4: introduce new function env_ext4_save_buffer env: ext4: add support of command env erase test: sandbox: add test for erase command board/sandbox/sandbox.c | 50 ++++++++++++++ configs/sandbox64_defconfig | 5 ++ configs/sandbox_defconfig | 5 ++ configs/sandbox_flattree_defconfig | 5 ++ configs/sandbox_spl_defconfig | 5 ++ env/Kconfig | 2 +- env/env.c | 5 +- env/ext4.c | 63 +++++++++++++++--- test/py/tests/test_env.py | 103 +++++++++++++++++++++++++++++ 9 files changed, 232 insertions(+), 11 deletions(-) -- 2.17.1

1 10

[PATCH v2 1/1] test: log functions with CONFIG_LOG=n
by Heinrich Schuchardt 12 Feb '20

12 Feb '20

If CONFIG_LOG=n, we still expect output for log_err(), log_warning(), log_notice(), log_info() and in case of DEBUG=1 also for log_debug(). Provide unit tests verifying this. The tests depend on: CONFIG_CONSOLE_RECORD=y CONFIG_LOG=n CONFIG_UT_LOG=y It may be necessary to increase the value of CONFIG_SYS_MALLOC_F_LEN to accommodate CONFIG_CONSOLE_RECORD=y. Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- v2: use ut_check_console_line() move do_ut_log() to test/log/test-main.c to accomodate further tests provide CONFIG_UT_LOG configuration option --- MAINTAINERS | 2 +- include/test/log.h | 16 +++++ include/test/suites.h | 1 + test/Kconfig | 9 +++ test/Makefile | 2 +- test/cmd_ut.c | 6 ++ test/log/Makefile | 10 ++++ test/log/nolog_test.c | 135 ++++++++++++++++++++++++++++++++++++++++++ test/log/test-main.c | 20 +++++++ 9 files changed, 199 insertions(+), 2 deletions(-) create mode 100644 include/test/log.h create mode 100644 test/log/nolog_test.c create mode 100644 test/log/test-main.c diff --git a/MAINTAINERS b/MAINTAINERS index d630176e33..ee80460fd7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -632,7 +632,7 @@ S: Maintained T: git https://gitlab.denx.de/u-boot/u-boot.git F: common/log* F: cmd/log.c -F: test/log/log_test.c +F: test/log/ F: test/py/tests/test_log.py MALI DISPLAY PROCESSORS diff --git a/include/test/log.h b/include/test/log.h new file mode 100644 index 0000000000..0b3a3ce51a --- /dev/null +++ b/include/test/log.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2019, Heinrich Schuchardt <xypron.glpk(a)gmx.de> + * + * Tests for logging functions + */ + +#ifndef __TEST_ENV_H__ +#define __TEST_ENV_H__ + +#include <test/test.h> + +/* Declare a new logging test */ +#define LOG_TEST(_name) UNIT_TEST(_name, 0, log_test) + +#endif /* __TEST_ENV_H__ */ diff --git a/include/test/suites.h b/include/test/suites.h index 0748185eaf..39ad81a90f 100644 --- a/include/test/suites.h +++ b/include/test/suites.h @@ -30,6 +30,7 @@ int do_ut_compression(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]); int do_ut_dm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); int do_ut_env(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); int do_ut_lib(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); +int do_ut_log(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); int do_ut_optee(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); int do_ut_overlay(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); int do_ut_time(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); diff --git a/test/Kconfig b/test/Kconfig index cb51b46721..32e6197dca 100644 --- a/test/Kconfig +++ b/test/Kconfig @@ -30,6 +30,15 @@ config UT_LIB_ASN1 endif +config UT_LOG + bool "Unit tests for logging functions" + depends on UNIT_TEST + default y + help + Enables the 'ut log' command which tests logging functions like + log_err(). + See also CONFIG_LOG_TEST which provides the 'log test' command. + config UT_TIME bool "Unit tests for time functions" depends on UNIT_TEST diff --git a/test/Makefile b/test/Makefile index 2fe41f489c..2971d0d87f 100644 --- a/test/Makefile +++ b/test/Makefile @@ -10,5 +10,5 @@ obj-$(CONFIG_SANDBOX) += compression.o obj-$(CONFIG_SANDBOX) += print_ut.o obj-$(CONFIG_UT_TIME) += time_ut.o obj-$(CONFIG_UT_UNICODE) += unicode_ut.o -obj-$(CONFIG_$(SPL_)LOG) += log/ +obj-y += log/ obj-$(CONFIG_UNIT_TEST) += lib/ diff --git a/test/cmd_ut.c b/test/cmd_ut.c index a3a9d49f7e..9b0d5e3e03 100644 --- a/test/cmd_ut.c +++ b/test/cmd_ut.c @@ -60,6 +60,9 @@ static cmd_tbl_t cmd_ut_sub[] = { #ifdef CONFIG_UT_LIB U_BOOT_CMD_MKENT(lib, CONFIG_SYS_MAXARGS, 1, do_ut_lib, "", ""), #endif +#if !defined(CONFIG_LOG) && defined(CONFIG_CONSOLE_RECORD) + U_BOOT_CMD_MKENT(log, CONFIG_SYS_MAXARGS, 1, do_ut_log, "", ""), +#endif #ifdef CONFIG_UT_TIME U_BOOT_CMD_MKENT(time, CONFIG_SYS_MAXARGS, 1, do_ut_time, "", ""), #endif @@ -122,6 +125,9 @@ static char ut_help_text[] = #ifdef CONFIG_UT_ENV "ut env [test-name]\n" #endif +#if !defined(CONFIG_LOG) && defined(CONFIG_CONSOLE_RECORD) + "ut log [test-name] - test logging functions\n" +#endif #ifdef CONFIG_UT_LIB "ut lib [test-name] - test library functions\n" #endif diff --git a/test/log/Makefile b/test/log/Makefile index e0d0a4745f..98178f5e2b 100644 --- a/test/log/Makefile +++ b/test/log/Makefile @@ -3,3 +3,13 @@ # Copyright (c) 2017 Google, Inc obj-$(CONFIG_LOG_TEST) += log_test.o + +ifdef CONFIG_UT_LOG + +obj-y += test-main.o + +ifndef CONFIG_LOG +obj-$(CONFIG_CONSOLE_RECORD) += nolog_test.o +endif + +endif # CONFIG_UT_LOG diff --git a/test/log/nolog_test.c b/test/log/nolog_test.c new file mode 100644 index 0000000000..050aec15a6 --- /dev/null +++ b/test/log/nolog_test.c @@ -0,0 +1,135 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2019, Heinrich Schuchardt <xypron.glpk(a)gmx.de> + * + * Logging function tests for CONFIG_LOG=n. + */ + +/* Needed for testing log_debug() */ +#define DEBUG 1 + +#include <common.h> +#include <console.h> +#include <test/log.h> +#include <test/test.h> +#include <test/suites.h> +#include <test/ut.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define BUFFSIZE 32 + +static int nolog_test_log_err(struct unit_test_state *uts) +{ + char buf[BUFFSIZE]; + + memset(buf, 0, BUFFSIZE); + console_record_reset_enable(); + log_err("testing %s\n", "log_err"); + gd->flags &= ~GD_FLG_RECORD; + ut_assertok(ut_check_console_line(uts, "testing log_err")); + ut_assertok(ut_check_console_end(uts)); + return 0; +} +LOG_TEST(nolog_test_log_err); + +static int nolog_test_log_warning(struct unit_test_state *uts) +{ + char buf[BUFFSIZE]; + + memset(buf, 0, BUFFSIZE); + console_record_reset_enable(); + log_warning("testing %s\n", "log_warning"); + gd->flags &= ~GD_FLG_RECORD; + ut_assertok(ut_check_console_line(uts, "testing log_warning")); + ut_assertok(ut_check_console_end(uts)); + return 0; +} +LOG_TEST(nolog_test_log_warning); + +static int nolog_test_log_notice(struct unit_test_state *uts) +{ + char buf[BUFFSIZE]; + + memset(buf, 0, BUFFSIZE); + console_record_reset_enable(); + log_notice("testing %s\n", "log_notice"); + gd->flags &= ~GD_FLG_RECORD; + ut_assertok(ut_check_console_line(uts, "testing log_notice")); + ut_assertok(ut_check_console_end(uts)); + return 0; +} +LOG_TEST(nolog_test_log_notice); + +static int nolog_test_log_info(struct unit_test_state *uts) +{ + char buf[BUFFSIZE]; + + memset(buf, 0, BUFFSIZE); + console_record_reset_enable(); + log_err("testing %s\n", "log_info"); + gd->flags &= ~GD_FLG_RECORD; + ut_assertok(ut_check_console_line(uts, "testing log_info")); + ut_assertok(ut_check_console_end(uts)); + return 0; +} +LOG_TEST(nolog_test_log_info); + +#undef _DEBUG +#define _DEBUG 0 +static int nolog_test_nodebug(struct unit_test_state *uts) +{ + char buf[BUFFSIZE]; + + memset(buf, 0, BUFFSIZE); + console_record_reset_enable(); + debug("testing %s\n", "debug"); + gd->flags &= ~GD_FLG_RECORD; + ut_assertok(ut_check_console_end(uts)); + return 0; +} +LOG_TEST(nolog_test_nodebug); + +static int nolog_test_log_nodebug(struct unit_test_state *uts) +{ + char buf[BUFFSIZE]; + + memset(buf, 0, BUFFSIZE); + console_record_reset_enable(); + log_debug("testing %s\n", "log_debug"); + gd->flags &= ~GD_FLG_RECORD; + ut_assert(!strcmp(buf, "")); + ut_assertok(ut_check_console_end(uts)); + return 0; +} +LOG_TEST(nolog_test_log_nodebug); + +#undef _DEBUG +#define _DEBUG 1 +static int nolog_test_debug(struct unit_test_state *uts) +{ + char buf[BUFFSIZE]; + + memset(buf, 0, BUFFSIZE); + console_record_reset_enable(); + debug("testing %s\n", "debug"); + gd->flags &= ~GD_FLG_RECORD; + ut_assertok(ut_check_console_line(uts, "testing debug")); + ut_assertok(ut_check_console_end(uts)); + return 0; +} +LOG_TEST(nolog_test_debug); + +static int nolog_test_log_debug(struct unit_test_state *uts) +{ + char buf[BUFFSIZE]; + + memset(buf, 0, BUFFSIZE); + console_record_reset_enable(); + log_debug("testing %s\n", "log_debug"); + gd->flags &= ~GD_FLG_RECORD; + ut_assertok(ut_check_console_line(uts, "testing log_debug")); + ut_assertok(ut_check_console_end(uts)); + return 0; +} +LOG_TEST(nolog_test_log_debug); diff --git a/test/log/test-main.c b/test/log/test-main.c new file mode 100644 index 0000000000..6d57f78e2a --- /dev/null +++ b/test/log/test-main.c @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2019, Heinrich Schuchardt <xypron.glpk(a)gmx.de> + * + * Logging function tests for CONFIG_LOG=n. + */ + +#include <common.h> +#include <console.h> +#include <test/log.h> +#include <test/suites.h> + +int do_ut_log(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + struct unit_test *tests = ll_entry_start(struct unit_test, log_test); + const int n_ents = ll_entry_count(struct unit_test, log_test); + + return cmd_ut_category("log", "log_test_", + tests, n_ents, argc, argv); +} -- 2.25.0

1 0

FYI: Please pull u-boot-dm
by Simon Glass 12 Feb '20

12 Feb '20

4 18

[PATCH] mx6slevk: Convert to DM_ETH
by Pedro Jardim 12 Feb '20

12 Feb '20

This fixes the following warning: ===================== WARNING ====================== This board does not use CONFIG_DM_ETH (Driver Model for Ethernet drivers). Please update the board to use CONFIG_DM_ETH before the v2020.07 release. Failure to update by the deadline may result in board removal. See doc/driver-model/migration.rst for more info. ==================================================== Signed-off-by: Pedro Jardim <jardim.c.pedro(a)gmail.com> --- board/freescale/mx6slevk/mx6slevk.c | 31 ----------------------------- configs/mx6slevk_defconfig | 3 +++ include/configs/mx6slevk.h | 7 +------ 3 files changed, 4 insertions(+), 37 deletions(-) diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c index 453f281418..43029e4245 100644 --- a/board/freescale/mx6slevk/mx6slevk.c +++ b/board/freescale/mx6slevk/mx6slevk.c @@ -21,7 +21,6 @@ #include <fsl_esdhc_imx.h> #include <i2c.h> #include <mmc.h> -#include <netdev.h> #include <power/pmic.h> #include <power/pfuze100_pmic.h> #include "../common/pfuze.h" @@ -102,35 +101,11 @@ static iomux_v3_cfg_t const usdhc3_pads[] = { }; #endif -static iomux_v3_cfg_t const fec_pads[] = { - MX6_PAD_FEC_MDC__FEC_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_FEC_MDIO__FEC_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_FEC_CRS_DV__FEC_RX_DV | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_FEC_RXD0__FEC_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_FEC_RXD1__FEC_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_FEC_TX_EN__FEC_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_FEC_TXD0__FEC_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_FEC_TXD1__FEC_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_FEC_REF_CLK__FEC_REF_OUT | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_FEC_RX_ER__GPIO_4_19 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_FEC_TX_CLK__GPIO_4_21 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - static void setup_iomux_uart(void) { imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); } -static void setup_iomux_fec(void) -{ - imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); - - /* Power up LAN8720 PHY */ - gpio_request(ETH_PHY_POWER, "eth_pwr"); - gpio_direction_output(ETH_PHY_POWER , 1); - udelay(15000); -} - int board_mmc_get_env_dev(int devno) { return devno; @@ -179,12 +154,6 @@ int power_init_board(void) #endif #ifdef CONFIG_FEC_MXC -int board_eth_init(bd_t *bis) -{ - setup_iomux_fec(); - - return cpu_eth_init(bis); -} static int setup_fec(void) { diff --git a/configs/mx6slevk_defconfig b/configs/mx6slevk_defconfig index dc22e830a3..163cb1a7ae 100644 --- a/configs/mx6slevk_defconfig +++ b/configs/mx6slevk_defconfig @@ -61,3 +61,6 @@ CONFIG_DM_USB=y CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y +CONFIG_DM_ETH=y +CONFIG_FEC_MXC=y +CONFIG_PHY_SMSC=y diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h index 6b2a174e7a..71d72d8c74 100644 --- a/include/configs/mx6slevk.h +++ b/include/configs/mx6slevk.h @@ -32,12 +32,7 @@ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE RMII -#define CONFIG_FEC_MXC_PHYADDR 0 - -#define CONFIG_PHY_SMSC +#define CONFIG_ETHPRIME "eth0" #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ -- 2.17.1

1 0