February 2020 - U-Boot

[PATCH v3 00/11] Add Support for eMMC boot in AM65x and J721e
by Faiz Abbas 05 Mar '20

05 Mar '20

The following patches add support for eMMC boot in TI's Am65x and J721e devices. v3: 1. Added a patch to fix a clash between two dummy clocks of the same name in k3-j721e-r5-common-proc-board.dtb 2. Converted the init() API patch to two patches adding deferred_probe() APIs to the mmc core and sdhci layers respectively. 3. Fixed up config_pm_pre_callback() call order in patch 9. v2: 1. Reordered the patches according to Lokesh's preference 2. Fixed patch 2 breaking platforms where DM_MMC is not enabled. Faiz Abbas (11): mmc: Add a saved_clock member mmc: Add a deferred_probe() API sdhci: Add sdhci_deferred_probe() API mmc: Merge SD_LEGACY and MMC_LEGACY bus modes mmc: am654_sdhci: Update output tap delay writes mmc: am654_sdhci: Implement workaround for card detect spl: mmc: Fix spl_mmc_get_uboot_raw_sector() implementation arm: K3: sysfw-loader: Add a config_pm_pre_callback() arm: dts: k3-j721e-r5-common-proc-board: Use unique names for dummy clocks configs: am65x_evm: Add CONFIG_SUPPORT_EMMC_BOOT configs: j721e_evm: Add Support for eMMC boot arch/arm/dts/k3-am65-main.dtsi | 12 +- arch/arm/dts/k3-am654-base-board-u-boot.dtsi | 11 +- arch/arm/dts/k3-j721e-main.dtsi | 15 +- .../arm/dts/k3-j721e-r5-common-proc-board.dts | 4 +- arch/arm/mach-imx/imx8/image.c | 3 +- arch/arm/mach-k3/am6_init.c | 33 +++- arch/arm/mach-k3/include/mach/sysfw-loader.h | 2 +- arch/arm/mach-k3/j721e_init.c | 33 +++- arch/arm/mach-k3/sysfw-loader.c | 6 +- common/spl/spl_mmc.c | 11 +- configs/am65x_evm_a53_defconfig | 1 + configs/am65x_evm_r5_defconfig | 1 + configs/j721e_evm_a72_defconfig | 3 + configs/j721e_evm_r5_defconfig | 3 + drivers/mmc/am654_sdhci.c | 173 +++++++++++++----- drivers/mmc/fsl_esdhc_imx.c | 1 - drivers/mmc/mmc-uclass.c | 15 ++ drivers/mmc/mmc.c | 20 +- drivers/mmc/omap_hsmmc.c | 1 - drivers/mmc/sdhci.c | 15 ++ drivers/mmc/zynq_sdhci.c | 1 - include/configs/am65x_evm.h | 2 - include/mmc.h | 12 +- include/sdhci.h | 1 + 24 files changed, 298 insertions(+), 81 deletions(-) -- 2.19.2

3 15

[PATCH] arch: arm: rockchip: order the rk3399 entries alphabetically
by Peter Robinson 05 Mar '20

05 Mar '20

Put the target entries for rk3399 devices in alphabetical order. Signed-off-by: Peter Robinson <pbrobinson(a)gmail.com> --- arch/arm/mach-rockchip/rk3399/Kconfig | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig index 868e85fc2a..176707e816 100644 --- a/arch/arm/mach-rockchip/rk3399/Kconfig +++ b/arch/arm/mach-rockchip/rk3399/Kconfig @@ -3,6 +3,15 @@ if ROCKCHIP_RK3399 choice prompt "RK3399 board select" +config TARGET_CHROMEBOOK_BOB + bool "Asus Flip C101PA Chromebook (RK3399)" + help + Bob is a small RK3299-based device similar in apperance to Minnie. + It has two USB 3.0 type-C ports, 4GB of SDRAM, WiFi and a 10.1", + 1280x800 display. It uses its USB ports for both power and external + display. It includes a Chrome OS EC (Cortex-M3) to provide access to + the keyboard and battery functions. + config TARGET_EVB_RK3399 bool "RK3399 evaluation board" help @@ -53,15 +62,6 @@ config TARGET_ROCK960_RK3399 * 2x USB 3.0 type A, 2x USB 2.0 type A (host mode only), 1x USB 3.0 type C OTG -config TARGET_CHROMEBOOK_BOB - bool "Asus Flip C101PA Chromebook (RK3399)" - help - Bob is a small RK3299-based device similar in apperance to Minnie. - It has two USB 3.0 type-C ports, 4GB of SDRAM, WiFi and a 10.1", - 1280x800 display. It uses its USB ports for both power and external - display. It includes a Chrome OS EC (Cortex-M3) to provide access to - the keyboard and battery functions. - config TARGET_ROCKPRO64_RK3399 bool "Pine64 Rockpro64 board" help @@ -113,10 +113,10 @@ config TPL_TEXT_BASE config SPL_STACK_R_ADDR default 0x04000000 +source "board/google/gru/Kconfig" +source "board/pine64/rockpro64_rk3399/Kconfig" source "board/rockchip/evb_rk3399/Kconfig" source "board/theobroma-systems/puma_rk3399/Kconfig" source "board/vamrs/rock960_rk3399/Kconfig" -source "board/google/gru/Kconfig" -source "board/pine64/rockpro64_rk3399/Kconfig" endif -- 2.24.1

4 6

[PATCH v5 00/33] riscv: Add Sipeed Maix support
by Sean Anderson 05 Mar '20

05 Mar '20

This patch series adds support for Sipeed Maix boards and the Kendryte K210 CPU. Currently, only the Maix Bit V2.0 is supported, however other models are similar. This series depends on <https://patchwork.ozlabs.org/patch/1215327/> (clk: Include missing headers for linux/clk-provider.h). This will (hopefully) be the last version of this series adding any new functionality, other than that needed to fix the bugs below. Known Bugs/Limitations: - Accessing the AI ram hangs, limiting available ram to 6M - The MMC cannot be accessed with the dw_spi driver - Trying to boot an image with bootm fails with ERROR: Failed to allocate 0x7d60 bytes below 0x80000000. To flash u-boot to a maix bit, run kflash -tp /dev/<your tty here> -B bit_mic u-boot-dtb.bin Boot output should look like the following: U-Boot 2020.04-rc2-00087-g2221cc09c1-dirty (Feb 28 2020 - 13:53:09 -0500) DRAM: 8 MiB WDT: Started with servicing (60s timeout) MMC: spi@53000000:slot@0: 0 In: serial@38000000 Out: serial@38000000 Err: serial@38000000 Hit any key to stop autoboot: 0 SF: Detected w25q128fw with page size 256 Bytes, erase size 4 KiB, total 16 MiB Reading 5242880 byte(s) at offset 0x00000000 ## Starting application at 0x80000000 ... Changes for v5: - Rebase onto master - Add pinconf support - Add gpio support - Store environment in spi flash - Group patches by prefix - Add additional documentation - Add SMP support - Add WDT support Changes for v4: - Linted several patches - Updated the copyright year for several files - Added tests for syscon-reset, simple-pm-bus, and the pll calc_rate function - Added/updated documentation - Fixed SPI for the nor flash - Fixed PLLs not enabling/setting rate properly - RISCV_PRIV_1_9_1 now (un)defines all diferring CSRs, and also disables VM - More devicetree changes Changes for v3: - Remove patch to set RV64I as default - Remove patch for a separate sysctl driver - Split off cpu frequency patch into its own series - Reorder support/devicetree patches to come last - Add patch for reset driver - Add simple-pm-bus for busses with their own clocks - Add additional documentation - Reword mcounteren patch to refer to the RISC-V priv spec 1.9.1 - Many devicetree changes - Switch to "make savedefconfig" to generate the config Changes for v2: - Many bugfixes for the device tree - Modify the config to build without errors - Add support for keeping internal PLL frequencies in-range - Fix several rebase-induced artifacts Sean Anderson (33): clk: Always use the supplied struct clk clk: Check that ops of composite clock components exist before calling clk: Unconditionally recursively en-/dis-able clocks clk: Add functions to register CCF clock structs clk: Add K210 pll support clk: Add a bypass clock for K210 clk: Add K210 clock support doc: Fix typo in FIT documentation dm: Add support for simple-pm-bus dm: Fix error handling for dev_read_addr_ptr reset: Add generic reset driver lib: Always set errno in hcreate_r pinctrl: Add support for Kendryte K210 FPIOA gpio: sifive: Use generic reg read function gpio: dw: Fix warnings about casting int to pointer gpio: dw: Add a trailing underscore to generated name gpio: dw: Return output value when direction is out led: gpio: Default to using node name if label is absent spi: dw: Add device tree properties for fields in CTRL1 spi: dw: Rename "cs-gpio" to "cs-gpios" spi: dw: Use generic function to read reg address spi: dw: Speed up transfer loops spi: dw: Properly set rx_end when not recieving spi: dw: Add mem_ops wdt: Move asm/utils.h to log2.h riscv: Add headers for asm/global_data.h riscv: Fix race conditions when initializing IPI riscv: Add option to support RISC-V privileged spec 1.9 riscv: Allow use of reset drivers riscv: Try to get cpu frequency from a "clocks" node if it exists riscv: Enable cpu clock if it is present riscv: Add device tree for K210 and Sipeed Maix BitM riscv: Add Sipeed Maix support MAINTAINERS | 9 + arch/arc/dts/axs10x_mb.dtsi | 3 +- arch/arc/dts/hsdk.dts | 3 +- arch/arm/cpu/armv7/cache_v7.c | 2 +- arch/arm/mach-davinci/spl.c | 2 +- arch/arm/mach-omap2/clocks-common.c | 2 +- arch/arm/mach-omap2/emif-common.c | 2 +- arch/arm/mach-omap2/omap4/emif.c | 2 +- arch/arm/mach-omap2/omap5/dra7xx_iodelay.c | 2 +- arch/arm/mach-omap2/omap5/emif.c | 2 +- arch/arm/mach-omap2/omap5/hwinit.c | 2 +- arch/arm/mach-socfpga/spl_a10.c | 2 +- arch/arm/mach-socfpga/spl_agilex.c | 2 +- arch/arm/mach-socfpga/spl_gen5.c | 2 +- arch/arm/mach-socfpga/spl_s10.c | 2 +- arch/riscv/Kconfig | 14 + arch/riscv/cpu/cpu.c | 18 + arch/riscv/dts/Makefile | 1 + arch/riscv/dts/k210-maix-bit.dts | 333 +++++++++ arch/riscv/dts/k210.dtsi | 649 +++++++++++++++++ arch/riscv/include/asm/csr.h | 40 ++ arch/riscv/include/asm/global_data.h | 3 + arch/riscv/include/asm/smp.h | 43 ++ arch/riscv/lib/andes_plic.c | 34 +- arch/riscv/lib/reset.c | 2 + arch/riscv/lib/sbi_ipi.c | 5 + arch/riscv/lib/sifive_clint.c | 33 +- arch/riscv/lib/smp.c | 68 +- arch/sandbox/dts/test.dts | 21 + arch/sandbox/include/asm/clk.h | 1 + board/sipeed/maix/Kconfig | 72 ++ board/sipeed/maix/MAINTAINERS | 11 + board/sipeed/maix/Makefile | 5 + board/sipeed/maix/maix.c | 54 ++ configs/sandbox_defconfig | 2 + configs/sipeed_maix_bitm_defconfig | 16 + doc/board/index.rst | 1 + doc/board/sipeed/index.rst | 9 + doc/board/sipeed/maix.rst | 223 ++++++ .../bus/simple-pm-bus.txt | 44 ++ .../mfd/kendryte,k210-sysctl.txt | 33 + .../pinctrl/kendryte,k210-fpioa.txt | 116 +++ .../reset/syscon-reset.txt | 36 + .../spi/snps,dw-apb-ssi.txt | 43 ++ doc/imx/clk/ccf.txt | 63 +- doc/uImage.FIT/source_file_format.txt | 2 +- drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/clk-composite.c | 145 ++-- drivers/clk/clk-divider.c | 62 +- drivers/clk/clk-fixed-factor.c | 3 +- drivers/clk/clk-gate.c | 44 +- drivers/clk/clk-mux.c | 12 +- drivers/clk/clk-uclass.c | 60 +- drivers/clk/imx/clk-gate2.c | 4 +- drivers/clk/imx/clk-imx8mp.c | 2 +- drivers/clk/kendryte/Kconfig | 12 + drivers/clk/kendryte/Makefile | 1 + drivers/clk/kendryte/bypass.c | 270 +++++++ drivers/clk/kendryte/clk.c | 478 +++++++++++++ drivers/clk/kendryte/pll.c | 600 ++++++++++++++++ drivers/core/Kconfig | 7 + drivers/core/Makefile | 1 + drivers/core/read.c | 2 +- drivers/core/simple-pm-bus.c | 56 ++ drivers/cpu/riscv_cpu.c | 39 +- drivers/gpio/dwapb_gpio.c | 33 +- drivers/gpio/sifive-gpio.c | 2 +- drivers/led/led_gpio.c | 7 +- drivers/pinctrl/Kconfig | 1 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/broadcom/pinctrl-bcm283x.c | 2 +- drivers/pinctrl/kendryte/Kconfig | 7 + drivers/pinctrl/kendryte/Makefile | 1 + drivers/pinctrl/kendryte/pinctrl.c | 663 ++++++++++++++++++ drivers/pinctrl/kendryte/pinctrl.h | 325 +++++++++ drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 2 +- drivers/reset/Kconfig | 5 + drivers/reset/Makefile | 1 + drivers/reset/reset-syscon.c | 80 +++ drivers/spi/designware_spi.c | 212 ++++-- drivers/watchdog/designware_wdt.c | 3 +- include/configs/sipeed-maix.h | 24 + include/dm/read.h | 4 +- include/dt-bindings/clock/k210-sysctl.h | 56 ++ include/dt-bindings/mfd/k210-sysctl.h | 38 + include/dt-bindings/pinctrl/k210-pinctrl.h | 12 + include/dt-bindings/reset/k210-sysctl.h | 38 + include/kendryte/bypass.h | 31 + include/kendryte/clk.h | 35 + include/kendryte/pll.h | 57 ++ include/linux/clk-provider.h | 9 + .../arm/include/asm/utils.h => include/log2.h | 4 +- include/test/export.h | 16 + lib/hashtable.c | 8 +- test/dm/Makefile | 3 + test/dm/k210_pll.c | 95 +++ test/dm/simple-pm-bus.c | 45 ++ test/dm/syscon-reset.c | 58 ++ 99 files changed, 5344 insertions(+), 368 deletions(-) create mode 100644 arch/riscv/dts/k210-maix-bit.dts create mode 100644 arch/riscv/dts/k210.dtsi create mode 100644 board/sipeed/maix/Kconfig create mode 100644 board/sipeed/maix/MAINTAINERS create mode 100644 board/sipeed/maix/Makefile create mode 100644 board/sipeed/maix/maix.c create mode 100644 configs/sipeed_maix_bitm_defconfig create mode 100644 doc/board/sipeed/index.rst create mode 100644 doc/board/sipeed/maix.rst create mode 100644 doc/device-tree-bindings/bus/simple-pm-bus.txt create mode 100644 doc/device-tree-bindings/mfd/kendryte,k210-sysctl.txt create mode 100644 doc/device-tree-bindings/pinctrl/kendryte,k210-fpioa.txt create mode 100644 doc/device-tree-bindings/reset/syscon-reset.txt create mode 100644 doc/device-tree-bindings/spi/snps,dw-apb-ssi.txt create mode 100644 drivers/clk/kendryte/Kconfig create mode 100644 drivers/clk/kendryte/Makefile create mode 100644 drivers/clk/kendryte/bypass.c create mode 100644 drivers/clk/kendryte/clk.c create mode 100644 drivers/clk/kendryte/pll.c create mode 100644 drivers/core/simple-pm-bus.c create mode 100644 drivers/pinctrl/kendryte/Kconfig create mode 100644 drivers/pinctrl/kendryte/Makefile create mode 100644 drivers/pinctrl/kendryte/pinctrl.c create mode 100644 drivers/pinctrl/kendryte/pinctrl.h create mode 100644 drivers/reset/reset-syscon.c create mode 100644 include/configs/sipeed-maix.h create mode 100644 include/dt-bindings/clock/k210-sysctl.h create mode 100644 include/dt-bindings/mfd/k210-sysctl.h create mode 100644 include/dt-bindings/pinctrl/k210-pinctrl.h create mode 100644 include/dt-bindings/reset/k210-sysctl.h create mode 100644 include/kendryte/bypass.h create mode 100644 include/kendryte/clk.h create mode 100644 include/kendryte/pll.h rename arch/arm/include/asm/utils.h => include/log2.h (93%) create mode 100644 include/test/export.h create mode 100644 test/dm/k210_pll.c create mode 100644 test/dm/simple-pm-bus.c create mode 100644 test/dm/syscon-reset.c -- 2.25.0

6 68

[PATCH] common/board_f.c: use #ifdefs a little more consistently
by Rasmus Villemoes 05 Mar '20

05 Mar '20

Some init functions, e.g. print_resetinfo(), are conditionally defined depending on some config options, and are correspondingly conditionally included in the init_sequence_f[] array. Others are unconditionally defined and included in init_sequence_f[], but have their entire body, sans a mandatory "return 0", conditionally compiled. For the simple cases, switch to the former model, making it a bit more consistent. This also makes the U-Boot image very slightly smaller and avoids a few useless calls to no-op functions during board_init_f. Signed-off-by: Rasmus Villemoes <rasmus.villemoes(a)prevas.dk> --- common/board_f.c | 54 ++++++++++++++++++++++++++++++++---------------- 1 file changed, 36 insertions(+), 18 deletions(-) diff --git a/common/board_f.c b/common/board_f.c index 82a164752a..ed63fbcea2 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -285,16 +285,16 @@ static int setup_mon_len(void) return 0; } +#if CONFIG_IS_ENABLED(HANDOFF) static int setup_spl_handoff(void) { -#if CONFIG_IS_ENABLED(HANDOFF) gd->spl_handoff = bloblist_find(BLOBLISTT_SPL_HANDOFF, sizeof(struct spl_handoff)); debug("Found SPL hand-off info %p\n", gd->spl_handoff); -#endif return 0; } +#endif __weak int arch_cpu_init(void) { @@ -437,17 +437,17 @@ static int reserve_video(void) return 0; } +#ifdef CONFIG_TRACE static int reserve_trace(void) { -#ifdef CONFIG_TRACE gd->relocaddr -= CONFIG_TRACE_BUFFER_SIZE; gd->trace_buff = map_sysmem(gd->relocaddr, CONFIG_TRACE_BUFFER_SIZE); debug("Reserving %luk for trace data at: %08lx\n", (unsigned long)CONFIG_TRACE_BUFFER_SIZE >> 10, gd->relocaddr); -#endif return 0; } +#endif static int reserve_uboot(void) { @@ -520,13 +520,13 @@ static int reserve_board(void) return 0; } +#ifdef CONFIG_MACH_TYPE static int setup_machine(void) { -#ifdef CONFIG_MACH_TYPE gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */ -#endif return 0; } +#endif static int reserve_global_data(void) { @@ -537,9 +537,9 @@ static int reserve_global_data(void) return 0; } +#ifndef CONFIG_OF_EMBED static int reserve_fdt(void) { -#ifndef CONFIG_OF_EMBED /* * If the device tree is sitting immediately above our image then we * must relocate it. If it is embedded in the data section, then it @@ -553,24 +553,24 @@ static int reserve_fdt(void) debug("Reserving %lu Bytes for FDT at: %08lx\n", gd->fdt_size, gd->start_addr_sp); } -#endif return 0; } +#endif +#ifdef CONFIG_BOOTSTAGE static int reserve_bootstage(void) { -#ifdef CONFIG_BOOTSTAGE int size = bootstage_get_size(); gd->start_addr_sp -= size; gd->new_bootstage = map_sysmem(gd->start_addr_sp, size); debug("Reserving %#x Bytes for bootstage at: %08lx\n", size, gd->start_addr_sp); -#endif return 0; } +#endif __weak int arch_reserve_stacks(void) { @@ -590,16 +590,16 @@ static int reserve_stacks(void) return arch_reserve_stacks(); } +#ifdef CONFIG_BLOBLIST static int reserve_bloblist(void) { -#ifdef CONFIG_BLOBLIST gd->start_addr_sp &= ~0xf; gd->start_addr_sp -= CONFIG_BLOBLIST_SIZE; gd->new_bloblist = map_sysmem(gd->start_addr_sp, CONFIG_BLOBLIST_SIZE); -#endif return 0; } +#endif static int display_new_sp(void) { @@ -675,23 +675,23 @@ static int init_post(void) } #endif +#ifndef CONFIG_OF_EMBED static int reloc_fdt(void) { -#ifndef CONFIG_OF_EMBED if (gd->flags & GD_FLG_SKIP_RELOC) return 0; if (gd->new_fdt) { memcpy(gd->new_fdt, gd->fdt_blob, gd->fdt_size); gd->fdt_blob = gd->new_fdt; } -#endif return 0; } +#endif +#ifdef CONFIG_BOOTSTAGE static int reloc_bootstage(void) { -#ifdef CONFIG_BOOTSTAGE if (gd->flags & GD_FLG_SKIP_RELOC) return 0; if (gd->new_bootstage) { @@ -703,14 +703,14 @@ static int reloc_bootstage(void) gd->bootstage = gd->new_bootstage; bootstage_relocate(); } -#endif return 0; } +#endif +#ifdef CONFIG_BLOBLIST static int reloc_bloblist(void) { -#ifdef CONFIG_BLOBLIST if (gd->flags & GD_FLG_SKIP_RELOC) return 0; if (gd->new_bloblist) { @@ -721,10 +721,10 @@ static int reloc_bloblist(void) memcpy(gd->new_bloblist, gd->bloblist, size); gd->bloblist = gd->new_bloblist; } -#endif return 0; } +#endif static int setup_reloc(void) { @@ -886,7 +886,9 @@ static const init_fnc_t init_sequence_f[] = { #ifdef CONFIG_BLOBLIST bloblist_init, #endif +#if CONFIG_IS_ENABLED(HANDOFF) setup_spl_handoff, +#endif initf_console_record, #if defined(CONFIG_HAVE_FSP) arch_fsp_init, @@ -974,15 +976,25 @@ static const init_fnc_t init_sequence_f[] = { reserve_mmu, #endif reserve_video, +#ifdef CONFIG_TRACE reserve_trace, +#endif reserve_uboot, reserve_malloc, reserve_board, +#ifdef CONFIG_MACH_TYPE setup_machine, +#endif reserve_global_data, +#ifndef CONFIG_OF_EMBED reserve_fdt, +#endif +#ifdef CONFIG_BOOTSTAGE reserve_bootstage, +#endif +#ifdef CONFIG_BLOBLIST reserve_bloblist, +#endif reserve_arch, reserve_stacks, dram_init_banksize, @@ -1000,9 +1012,15 @@ static const init_fnc_t init_sequence_f[] = { fix_fdt, #endif INIT_FUNC_WATCHDOG_RESET +#ifndef CONFIG_OF_EMBED reloc_fdt, +#endif +#ifdef CONFIG_BOOTSTAGE reloc_bootstage, +#endif +#ifdef CONFIG_BLOBLIST reloc_bloblist, +#endif setup_reloc, #if defined(CONFIG_X86) || defined(CONFIG_ARC) copy_uboot_to_ram, -- 2.23.0

3 9

[PATCH 0/8] malloc: implement USE_DL_PREFIX using inline functions
by Simon Goldschmidt 04 Mar '20

04 Mar '20

Commit cfda60f99ae2 ("sandbox: Use a prefix for all allocation functions") introduced preprocessor macros for malloc/free etc. This is bad practice as it essentially makes 'free' a reserved keyword and resulted in quite a bit of renaming to avoid that reserved keyword. A better solution is to define the allocation functions as 'static inline'. This should go in before the release, as it's a regression not seen before the last release. A side-effect is that exports.h may not declare malloc/free. I'm not really sure if this is correct, but for sandbox, it should probably be ok? Simon Goldschmidt (8): malloc: implement USE_DL_PREFIX via inline functions Revert "mtd: Rename free() to rfree()" Revert "dma: Rename free() to rfree()" Revert "clk: Rename free() to rfree()" Revert "gpio: Rename free() to rfree()" Revert "reset: Rename free() to rfree()" Revert "power-domain: Rename free() to rfree()" Revert "mailbox: Rename free() to rfree()" drivers/clk/clk-ti-sci.c | 2 +- drivers/clk/clk-uclass.c | 4 +- drivers/clk/clk_sandbox.c | 2 +- drivers/clk/tegra/tegra-car-clk.c | 2 +- drivers/dma/dma-uclass.c | 4 +- drivers/dma/sandbox-dma-test.c | 4 +- drivers/dma/ti/k3-udma.c | 4 +- drivers/gpio/gpio-rcar.c | 2 +- drivers/gpio/gpio-uclass.c | 8 ++-- drivers/mailbox/k3-sec-proxy.c | 2 +- drivers/mailbox/mailbox-uclass.c | 4 +- drivers/mailbox/sandbox-mbox.c | 2 +- drivers/mailbox/stm32-ipcc.c | 2 +- drivers/mailbox/tegra-hsp.c | 2 +- drivers/mtd/mtdcore.c | 4 +- drivers/mtd/nand/raw/denali.c | 2 +- drivers/mtd/nand/spi/core.c | 2 +- drivers/mtd/nand/spi/gigadevice.c | 2 +- drivers/mtd/nand/spi/macronix.c | 2 +- drivers/mtd/nand/spi/micron.c | 2 +- drivers/mtd/nand/spi/winbond.c | 2 +- drivers/power/domain/bcm6328-power-domain.c | 2 +- .../power/domain/imx8-power-domain-legacy.c | 2 +- drivers/power/domain/imx8-power-domain.c | 2 +- drivers/power/domain/imx8m-power-domain.c | 2 +- drivers/power/domain/meson-ee-pwrc.c | 2 +- drivers/power/domain/meson-gx-pwrc-vpu.c | 2 +- drivers/power/domain/mtk-power-domain.c | 2 +- drivers/power/domain/power-domain-uclass.c | 2 +- drivers/power/domain/sandbox-power-domain.c | 2 +- drivers/power/domain/tegra186-power-domain.c | 2 +- drivers/power/domain/ti-sci-power-domain.c | 2 +- drivers/reset/reset-bcm6345.c | 2 +- drivers/reset/reset-hisilicon.c | 2 +- drivers/reset/reset-hsdk.c | 2 +- drivers/reset/reset-imx7.c | 2 +- drivers/reset/reset-mediatek.c | 2 +- drivers/reset/reset-meson.c | 2 +- drivers/reset/reset-mtmips.c | 2 +- drivers/reset/reset-rockchip.c | 2 +- drivers/reset/reset-socfpga.c | 2 +- drivers/reset/reset-sunxi.c | 2 +- drivers/reset/reset-ti-sci.c | 2 +- drivers/reset/reset-uclass.c | 2 +- drivers/reset/reset-uniphier.c | 2 +- drivers/reset/sandbox-reset.c | 2 +- drivers/reset/sti-reset.c | 2 +- drivers/reset/stm32-reset.c | 2 +- drivers/reset/tegra-car-reset.c | 2 +- drivers/reset/tegra186-reset.c | 2 +- include/_exports.h | 2 + include/asm-generic/gpio.h | 2 +- include/clk-uclass.h | 4 +- include/dma-uclass.h | 4 +- include/exports.h | 2 + include/linux/mtd/mtd.h | 4 +- include/mailbox-uclass.h | 4 +- include/malloc.h | 44 ++++++++++++------- include/power-domain-uclass.h | 4 +- include/reset-uclass.h | 4 +- 60 files changed, 105 insertions(+), 87 deletions(-) -- 2.20.1

4 22

[PATCH 0/2] ARM: zynq: Start to use unified configurations
by Michal Simek 04 Mar '20

04 Mar '20

Hi, over the time there are a lot of zynq configurations which are almost the same. It just increasing amount of time for building/testing/maintaining that's why this patch starts to use xilinx_zynq_virt_defconfig which is all in one configurations which can be used on all zynq board. The series contains two patches. The first which setup device tree name for SPL FIT image selection. The second which removes all xilinx/avnet/myirtech configurations with extending defconfig and OF_LIST which ensures that u-boot.img contains DTS files for all these boards. Thanks, Michal Michal Simek (2): Makefile: Add environment variable DEVICE_TREE to header ARM: zynq: Switch to single zynq configurations Makefile | 14 ++++- arch/arm/mach-zynq/spl.c | 8 ++- configs/xilinx_zynq_virt_defconfig | 19 +++++- configs/zynq_cc108_defconfig | 61 ------------------ configs/zynq_dlc20_rev1_0_defconfig | 76 ---------------------- configs/zynq_microzed_defconfig | 66 ------------------- configs/zynq_minized_defconfig | 67 -------------------- configs/zynq_picozed_defconfig | 54 ---------------- configs/zynq_z_turn_defconfig | 67 -------------------- configs/zynq_zc702_defconfig | 83 ------------------------ configs/zynq_zc706_defconfig | 87 -------------------------- configs/zynq_zc770_xm010_defconfig | 61 ------------------ configs/zynq_zc770_xm011_defconfig | 48 -------------- configs/zynq_zc770_xm011_x16_defconfig | 48 -------------- configs/zynq_zc770_xm012_defconfig | 50 --------------- configs/zynq_zc770_xm013_defconfig | 53 ---------------- configs/zynq_zed_defconfig | 70 --------------------- configs/zynq_zybo_defconfig | 69 -------------------- configs/zynq_zybo_z7_defconfig | 66 ------------------- 19 files changed, 37 insertions(+), 1030 deletions(-) delete mode 100644 configs/zynq_cc108_defconfig delete mode 100644 configs/zynq_dlc20_rev1_0_defconfig delete mode 100644 configs/zynq_microzed_defconfig delete mode 100644 configs/zynq_minized_defconfig delete mode 100644 configs/zynq_picozed_defconfig delete mode 100644 configs/zynq_z_turn_defconfig delete mode 100644 configs/zynq_zc702_defconfig delete mode 100644 configs/zynq_zc706_defconfig delete mode 100644 configs/zynq_zc770_xm010_defconfig delete mode 100644 configs/zynq_zc770_xm011_defconfig delete mode 100644 configs/zynq_zc770_xm011_x16_defconfig delete mode 100644 configs/zynq_zc770_xm012_defconfig delete mode 100644 configs/zynq_zc770_xm013_defconfig delete mode 100644 configs/zynq_zed_defconfig delete mode 100644 configs/zynq_zybo_defconfig delete mode 100644 configs/zynq_zybo_z7_defconfig -- 2.25.0

3 10

[PATCH 1/2] configs: socfpga: Add QSPI support for Cyclone 5
by Ley Foon Tan 04 Mar '20

04 Mar '20

Add QSPI boot support to boot target devices list. Platform can provide their own boot settings through SOCFPGA_BOOT_SETTINGS macro if needed. Add SOCFPGA_BOOT_SETTINGS for Cyclone 5. Signed-off-by: Ley Foon Tan <ley.foon.tan(a)intel.com> --- include/configs/socfpga_common.h | 18 ++++++++++++++++++ include/configs/socfpga_cyclone5_socdk.h | 18 ++++++++++++++++++ 2 files changed, 36 insertions(+) diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 8d10469e7c..f3ddfca289 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -228,11 +228,28 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #define BOOT_TARGET_DEVICES_MMC(func) #endif +#ifdef CONFIG_CMD_SF +#define BOOT_TARGET_DEVICES_QSPI(func) func(QSPI, qspi, na) +#else +#define BOOT_TARGET_DEVICES_QSPI(func) +#endif + +#define BOOTENV_DEV_QSPI(devtypeu, devtypel, instance) \ + "bootcmd_qspi=run qspiload; run qspiboot\0" + +#define BOOTENV_DEV_NAME_QSPI(devtypeu, devtypel, instance) \ + "qspi " + #define BOOT_TARGET_DEVICES(func) \ BOOT_TARGET_DEVICES_MMC(func) \ + BOOT_TARGET_DEVICES_QSPI(func) \ BOOT_TARGET_DEVICES_PXE(func) \ BOOT_TARGET_DEVICES_DHCP(func) +#ifndef SOCFPGA_BOOT_SETTINGS +#define SOCFPGA_BOOT_SETTINGS +#endif + #include <config_distro_bootcmd.h> #ifndef CONFIG_EXTRA_ENV_SETTINGS @@ -245,6 +262,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void); "pxefile_addr_r=0x02200000\0" \ "ramdisk_addr_r=0x02300000\0" \ "socfpga_legacy_reset_compat=1\0" \ + SOCFPGA_BOOT_SETTINGS \ BOOTENV #endif diff --git a/include/configs/socfpga_cyclone5_socdk.h b/include/configs/socfpga_cyclone5_socdk.h index 028db2a09e..62ad001c4b 100644 --- a/include/configs/socfpga_cyclone5_socdk.h +++ b/include/configs/socfpga_cyclone5_socdk.h @@ -14,6 +14,24 @@ #define CONFIG_LOADADDR 0x01000000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +/* QSPI boot */ +#define FDT_SIZE __stringify(0x00010000) +#define KERNEL_SIZE __stringify(0x005d0000) +#define QSPI_FDT_ADDR __stringify(0x00220000) +#define QSPI_KERNEL_ADDR __stringify(0x00230000) + +#define SOCFPGA_BOOT_SETTINGS \ + "fdt_size=" FDT_SIZE "\0" \ + "kernel_size=" KERNEL_SIZE "\0" \ + "qspi_fdt_addr=" QSPI_FDT_ADDR "\0" \ + "qspi_kernel_addr=" QSPI_KERNEL_ADDR "\0" \ + "qspiboot=setenv bootargs earlycon " \ + "root=/dev/mtdblock1 rw rootfstype=jffs2; " \ + "bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \ + "qspiload=sf probe; " \ + "sf read ${kernel_addr_r} ${qspi_kernel_addr} ${kernel_size}; " \ + "sf read ${fdt_addr_r} ${qspi_fdt_addr} ${fdt_size}\0" + /* The rest of the configuration is shared */ #include <configs/socfpga_common.h> -- 2.19.0

3 9

[PATCH V2] ARM: socfpga: Add initial support for the ABB SECU board
by Marek Vasut 04 Mar '20

04 Mar '20

From: Holger Brunck <holger.brunck(a)ch.abb.com> Add initial support for the ABB SECU board, which is an ArriaV-based SoCFPGA system with ethernet and booting from Denali NAND. Signed-off-by: Holger Brunck <holger.brunck(a)ch.abb.com> Cc: Ley Foon Tan <ley.foon.tan(a)intel.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt(a)gmail.com> --- V2: Use CONFIG_SYS_I2C_EEPROM_ADDR in printf() in ivm.c Enable CONFIG_SYS_NAND_USE_FLASH_BBT --- arch/arm/dts/Makefile | 1 + arch/arm/dts/socfpga_arria5_secu1.dts | 130 +++++ arch/arm/mach-socfpga/Kconfig | 10 + board/keymile/Kconfig | 11 +- board/keymile/common/ivm.c | 19 +- board/keymile/secu1/Makefile | 7 + board/keymile/secu1/qts/iocsr_config.h | 694 ++++++++++++++++++++++++ board/keymile/secu1/qts/pinmux_config.h | 218 ++++++++ board/keymile/secu1/qts/pll_config.h | 83 +++ board/keymile/secu1/qts/sdram_config.h | 327 +++++++++++ board/keymile/secu1/socfpga.c | 67 +++ configs/socfpga_secu1_defconfig | 84 +++ include/configs/socfpga_arria5_secu1.h | 131 +++++ 13 files changed, 1778 insertions(+), 4 deletions(-) create mode 100644 arch/arm/dts/socfpga_arria5_secu1.dts create mode 100644 board/keymile/secu1/Makefile create mode 100644 board/keymile/secu1/qts/iocsr_config.h create mode 100644 board/keymile/secu1/qts/pinmux_config.h create mode 100644 board/keymile/secu1/qts/pll_config.h create mode 100644 board/keymile/secu1/qts/sdram_config.h create mode 100644 board/keymile/secu1/socfpga.c create mode 100644 configs/socfpga_secu1_defconfig create mode 100644 include/configs/socfpga_arria5_secu1.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index be4cf029d0..9c593b2c98 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -333,6 +333,7 @@ dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb dtb-$(CONFIG_ARCH_SOCFPGA) += \ socfpga_agilex_socdk.dtb \ + socfpga_arria5_secu1.dtb \ socfpga_arria5_socdk.dtb \ socfpga_arria10_socdk_sdmmc.dtb \ socfpga_cyclone5_mcvevk.dtb \ diff --git a/arch/arm/dts/socfpga_arria5_secu1.dts b/arch/arm/dts/socfpga_arria5_secu1.dts new file mode 100644 index 0000000000..dadf766682 --- /dev/null +++ b/arch/arm/dts/socfpga_arria5_secu1.dts @@ -0,0 +1,130 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2016-2020 ABB + */ + +#include "socfpga_arria5.dtsi" +#include "socfpga-common-u-boot.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "ABB SoC SECU1 Board"; + compatible = "altr,socfpga-secu1", "altr,socfpga"; + + chosen { + stdout-path = "serial0:115200n8"; + bootargs = "console=ttyS0,115200"; + }; + + memory { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x20000000>; /* 512MB */ + }; + + aliases { + /* + * this allow the ethaddr uboot environment variable contents + * to be added to the gmac0 device tree blob. + */ + ethernet0 = &gmac0; + spi0 = &spi1; + }; + + i2c_gpio: i2c@0 { + compatible = "i2c-gpio"; + #address-cells = <1>; + #size-cells = <0>; + gpios = <&portc 5 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN) /* SDA */ + &portc 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; /* SCL */ + i2c-gpio,delay-us = <5>; /* ~100 kHz */ + i2c-gpio,deblock; + + temp_sensor@48 { + compatible = "national,lm75"; + reg = <0x48>; + }; + + eeprom@50 { + compatible = "at,24c08"; + reg = <0x50>; + }; + + rtc: rtc@68 { + compatible = "st,m41st87"; + reg = <0x68>; + interrupt-parent = <&intc>; + interrupts = <0 42 0x4>; + }; + }; + + regulator_3_3v: 3-3-v-regulator { + compatible = "regulator-fixed"; + regulator-name = "3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&gmac0 { + status = "okay"; + phy-mode = "rgmii"; + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&mmc0 { + vmmc-supply = <&regulator_3_3v>; + vqmmc-supply = <&regulator_3_3v>; + bus-width = <4>; + u-boot,dm-pre-reloc; +}; + +&nand0 { + status = "okay"; +}; + +&porta { + bank-name = "porta"; +}; + +&portb { + bank-name = "portb"; +}; + +&portc { + bank-name = "portc"; +}; + +&spi1 { + status = "okay"; +}; + +&uart0 { + clock-frequency = <100000000>; + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&uart1 { + clock-frequency = <100000000>; +}; + +&watchdog0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 969698c83f..38d6c1b2ba 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -96,6 +96,11 @@ config TARGET_SOCFPGA_ARRIA10_SOCDK bool "Altera SOCFPGA SoCDK (Arria 10)" select TARGET_SOCFPGA_ARRIA10 +config TARGET_SOCFPGA_ARRIA5_SECU1 + bool "ABB SECU1 (Arria V)" + select TARGET_SOCFPGA_ARRIA5 + select VENDOR_KM + config TARGET_SOCFPGA_ARRIA5_SOCDK bool "Altera SOCFPGA SoCDK (Arria V)" select TARGET_SOCFPGA_ARRIA5 @@ -158,6 +163,7 @@ config SYS_BOARD default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO default "is1" if TARGET_SOCFPGA_IS1 default "mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK + default "secu1" if TARGET_SOCFPGA_ARRIA5_SECU1 default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES default "sr1500" if TARGET_SOCFPGA_SR1500 @@ -173,6 +179,7 @@ config SYS_VENDOR default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1 default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES + default "keymile" if TARGET_SOCFPGA_ARRIA5_SECU1 default "softing" if TARGET_SOCFPGA_SOFTING_VINING_FPGA default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO default "terasic" if TARGET_SOCFPGA_TERASIC_DE1_SOC @@ -184,6 +191,7 @@ config SYS_SOC config SYS_CONFIG_NAME default "socfpga_agilex_socdk" if TARGET_SOCFPGA_AGILEX_SOCDK + default "socfpga_arria5_secu1" if TARGET_SOCFPGA_ARRIA5_SECU1 default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK @@ -199,4 +207,6 @@ config SYS_CONFIG_NAME default "socfpga_stratix10_socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK default "socfpga_vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA +source "board/keymile/Kconfig" + endif diff --git a/board/keymile/Kconfig b/board/keymile/Kconfig index 634dbbe097..7f4cad86aa 100644 --- a/board/keymile/Kconfig +++ b/board/keymile/Kconfig @@ -14,6 +14,7 @@ menu "KM Board Setup" config KM_PNVRAM hex "Pseudo RAM" default 0x80000 + depends on !ARCH_SOCFPGA help Start address of the pseudo non-volatile RAM for application. @@ -21,6 +22,7 @@ config KM_PHRAM hex "Physical RAM" default 0x17F000 if ARM default 0x100000 if PPC + depends on !ARCH_SOCFPGA help Start address of the physical RAM, which is the mounted /var folder. @@ -29,6 +31,7 @@ config KM_RESERVED_PRAM default 0x801000 if KIRKWOOD default 0x0 if MPC83xx default 0x1000 if MPC85xx + depends on !ARCH_SOCFPGA help Reserved physical RAM area at the end of memory for special purposes. @@ -37,6 +40,7 @@ config KM_CRAMFS_ADDR default 0x2400000 if KIRKWOOD default 0xC00000 if MPC83xx default 0x2000000 if MPC85xx + depends on !ARCH_SOCFPGA help Start address of the CRAMFS containing the Linux kernel. @@ -44,13 +48,13 @@ config KM_KERNEL_ADDR hex "Kernel Load Address" default 0x2000000 if KIRKWOOD default 0x400000 if MPC83xx - default 0x1000000 if MPC85xx + default 0x1000000 if MPC85xx || ARCH_SOCFPGA help Address where to load Linux kernel in RAM. config KM_FDT_ADDR hex "FDT Load Address" - default 0x23E0000 if KIRKWOOD + default 0x23E0000 if KIRKWOOD || ARCH_SOCFPGA default 0xB80000 if MPC83xx default 0x1F80000 if MPC85xx help @@ -71,7 +75,7 @@ config KM_DEF_NETDEV config KM_COMMON_ETH_INIT bool "Common Ethernet Initialization" default y if KIRKWOOD || MPC83xx - default n if MPC85xx + default n if MPC85xx || ARCH_SOCFPGA help Use the Ethernet initialization implemented in common code, which detects if a Piggy board is present. @@ -91,6 +95,7 @@ config KM_MVEXTSW_ADDR config KM_IVM_BUS int "IVM I2C Bus" + default 0 if ARCH_SOCFPGA default 1 if KIRKWOOD || MPC85xx default 2 if MPC83xx help diff --git a/board/keymile/common/ivm.c b/board/keymile/common/ivm.c index fee7f03c8c..60b89fe348 100644 --- a/board/keymile/common/ivm.c +++ b/board/keymile/common/ivm.c @@ -328,7 +328,24 @@ static int ivm_populate_env(unsigned char *buf, int len, int mac_address_offset) int ivm_read_eeprom(unsigned char *buf, int len, int mac_address_offset) { int ret; +#ifdef CONFIG_DM_I2C + struct udevice *eedev = NULL; + + ret = i2c_get_chip_for_busnum(CONFIG_KM_IVM_BUS, + CONFIG_SYS_I2C_EEPROM_ADDR, 1, &eedev); + if (ret) { + printf("failed to get device for EEPROM at address 0x%02x\n", + CONFIG_SYS_I2C_EEPROM_ADDR); + return 1; + } + ret = dm_i2c_read(eedev, 0, buf, len); + if (ret != 0) { + printf("Error: Unable to read from I2C EEPROM at address %02X:%02X\n", + CONFIG_SYS_I2C_EEPROM_ADDR, 0); + return 1; + } +#else i2c_set_bus_num(CONFIG_KM_IVM_BUS); /* add deblocking here */ i2c_make_abort(); @@ -338,6 +355,6 @@ int ivm_read_eeprom(unsigned char *buf, int len, int mac_address_offset) printf("Error reading EEprom\n"); return -2; } - +#endif return ivm_populate_env(buf, len, mac_address_offset); } diff --git a/board/keymile/secu1/Makefile b/board/keymile/secu1/Makefile new file mode 100644 index 0000000000..4704d59e48 --- /dev/null +++ b/board/keymile/secu1/Makefile @@ -0,0 +1,7 @@ +# +# (C) Copyright 2020 ABB +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := socfpga.o ../common/ivm.o diff --git a/board/keymile/secu1/qts/iocsr_config.h b/board/keymile/secu1/qts/iocsr_config.h new file mode 100644 index 0000000000..7640c56db1 --- /dev/null +++ b/board/keymile/secu1/qts/iocsr_config.h @@ -0,0 +1,694 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Altera SoCFPGA IOCSR configuration + */ + +#ifndef __SOCFPGA_IOCSR_CONFIG_H__ +#define __SOCFPGA_IOCSR_CONFIG_H__ + +#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 1337 +#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719 +#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 1528 +#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766 + +const unsigned long iocsr_scan_chain0_table[] = { + 0x00100000, + 0x40000000, + 0x00000000, + 0x00000100, + 0x00040000, + 0x00008000, + 0x00080000, + 0x20000000, + 0x00000000, + 0x00000080, + 0x00020000, + 0x00004000, + 0x00040000, + 0x10000000, + 0x00000000, + 0x00000040, + 0x00010000, + 0x00002000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000020, + 0x00008000, + 0x00001000, + 0x00000000, + 0x0300C000, + 0x0000000C, + 0x00000000, + 0x00000000, + 0x00000800, + 0x01806018, + 0x00000000, + 0x01800000, + 0x00001806, + 0x00001806, + 0x00000400, + 0x00C0300C, + 0x00C03000, + 0x00C00003, + 0x00000C03, + 0x00300C03, + 0x00000200, +}; + +const unsigned long iocsr_scan_chain1_table[] = { + 0x00100000, + 0x40000000, + 0x00000000, + 0x00000100, + 0x00040000, + 0x00008000, + 0x00060180, + 0x18060000, + 0x00000000, + 0x00000080, + 0x00020000, + 0x00004000, + 0x00040000, + 0x10000000, + 0x00000000, + 0x00000040, + 0x00010000, + 0x00002000, + 0x00020000, + 0x08000000, + 0x01FE0000, + 0xF8000000, + 0x00000007, + 0x00001000, + 0x00010000, + 0x04000000, + 0x00000000, + 0x00000010, + 0x00004000, + 0x00000800, + 0x00006018, + 0x01806000, + 0x00000006, + 0x00000008, + 0x00601806, + 0x00000400, + 0x0000300C, + 0x00C03000, + 0x00C00000, + 0x00000003, + 0x00000C03, + 0x00000200, + 0x00000000, + 0x00601800, + 0x80600000, + 0x80000001, + 0x00000601, + 0x00000100, + 0x00300C03, + 0xC0300C00, + 0xC0300000, + 0xC0000300, + 0x000C0300, + 0x00000080, +}; + +const unsigned long iocsr_scan_chain2_table[] = { + 0x00100000, + 0x40000000, + 0x00000000, + 0x00000100, + 0x00040000, + 0x00008000, + 0x00080000, + 0x20000000, + 0x00000000, + 0x00000080, + 0x00020000, + 0x00004000, + 0x00040000, + 0x10000000, + 0x00000000, + 0x00000040, + 0x00010000, + 0x00002000, + 0x00018060, + 0x08000000, + 0x00000000, + 0x00000020, + 0x00008000, + 0x00001000, + 0x0300C030, + 0x00000000, + 0x03000000, + 0x0000000C, + 0x00C0300C, + 0x00000800, + 0x01806018, + 0x01806000, + 0x00000006, + 0x00000000, + 0x00601806, + 0x00000400, + 0x00C0300C, + 0x00C03000, + 0x00C00003, + 0x00000C03, + 0x00300C03, + 0x00000200, + 0x00601806, + 0x80601800, + 0x80600001, + 0x80000601, + 0x00180601, + 0x00000100, +}; + +const unsigned long iocsr_scan_chain3_table[] = { + 0x2CC20D80, + 0x082000FF, + 0x08028001, + 0x00100000, + 0x08020000, + 0x00100000, + 0x0A800000, + 0x07900000, + 0x08020000, + 0x00100000, + 0x00000000, + 0xC0000010, + 0x00C00512, + 0x00000000, + 0x00000021, + 0x82000004, + 0x05400000, + 0x03C80000, + 0x04010000, + 0x00080000, + 0x05400000, + 0x03C80000, + 0x05400000, + 0x03C80000, + 0xA2580000, + 0x60001800, + 0x00600289, + 0x800A2580, + 0x00000001, + 0x40000002, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x512C0000, + 0xB0000C00, + 0x00300144, + 0xC00512C0, + 0x144B0000, + 0x20000300, + 0x00040000, + 0x50670000, + 0x00000050, + 0x24590000, + 0x00001000, + 0xA0000034, + 0x0D000001, + 0xA0680514, + 0xC3034028, + 0x06181A00, + 0x805140D0, + 0x34069A06, + 0x01A034D0, + 0x240D0000, + 0x28A06809, + 0x00000340, + 0xD000001A, + 0x06809240, + 0x10040000, + 0x00200000, + 0x10040000, + 0x00200000, + 0x15000000, + 0x0F200000, + 0x15000000, + 0x0F200000, + 0x01FE0000, + 0x80000000, + 0x01800A25, + 0x00289600, + 0x007F8006, + 0x00000000, + 0x0A800001, + 0x07900000, + 0x0A800000, + 0x07900000, + 0x0A800000, + 0x07900000, + 0x08020000, + 0x00100000, + 0x44B00000, + 0xC0003001, + 0x00C00512, + 0x00000FF0, + 0x512C0000, + 0x80000C00, + 0x05400000, + 0x02480000, + 0x04000000, + 0x00080000, + 0x05400000, + 0x03C80000, + 0x05400000, + 0x03C80000, + 0x581D8000, + 0x60001800, + 0x00600289, + 0x800A2580, + 0x16076001, + 0x40000600, + 0x02A00040, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x512C0000, + 0xB0000C00, + 0x00300144, + 0xC00512C0, + 0x144B0000, + 0x20000300, + 0x00040000, + 0x50670000, + 0x00000050, + 0x24590000, + 0x00001000, + 0xA0000034, + 0x0D000001, + 0xA0680514, + 0x4D034028, + 0x1A681A03, + 0x805140D0, + 0x34069A06, + 0x01A00020, + 0x240D0001, + 0x49206809, + 0x034D0340, + 0xD01A681A, + 0x06805140, + 0x10040000, + 0x00200000, + 0x10040000, + 0x00200000, + 0x15000000, + 0x0F200000, + 0x15000000, + 0x0F200000, + 0x01FE0000, + 0x80000000, + 0x01800A25, + 0x00289600, + 0x007F8006, + 0x00000000, + 0x99300001, + 0x34343400, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x01000000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x0002A000, + 0x0001E400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0x44B0090C, + 0x00003001, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00002000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0xFFFFFFFF, + 0x14F3690D, + 0x1A041414, + 0x00D00000, + 0x1C864000, + 0x45147A07, + 0xA228A3DA, + 0xF491451E, + 0x0358D348, + 0x821A0000, + 0x0000D000, + 0x028A0680, + 0xDA79E47A, + 0x1EA228A3, + 0xC8F49965, + 0x000344B2, + 0x00080000, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x00000000, + 0x00000020, + 0x0080C000, + 0x41000000, + 0x00003FC2, + 0x00820000, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040000, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x01000000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x00020080, + 0x00000400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0x0000090C, + 0x00000010, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00015000, + 0x0000F200, + 0x00000000, + 0x00000482, + 0x60120800, + 0x00600289, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0xFFFFFFFF, + 0x14F3690D, + 0x1A041414, + 0x00D00000, + 0x14864000, + 0x59647A05, + 0xC228A3DC, + 0xF491451E, + 0x0344B2C8, + 0x821A034D, + 0x0000D000, + 0x00000680, + 0xD469A47A, + 0x1E83CF23, + 0xC8F71E79, + 0x000344B2, + 0x00080000, + 0x00001000, + 0x00080000, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x00000000, + 0x00000020, + 0x0080C000, + 0x41000000, + 0x00000002, + 0x00820008, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040000, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x01000000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x00020080, + 0x00000400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0x0000090C, + 0x00000010, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00010000, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00400000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0xFFFFFFFF, + 0x14F1690D, + 0x1A041414, + 0x00D00000, + 0x0C864000, + 0x79E47A03, + 0x92AAA3D2, + 0xF595551E, + 0x034CF3C8, + 0x821A0000, + 0x0000D000, + 0x00000680, + 0xDA79E47A, + 0x1EA32CA3, + 0xC8F69965, + 0x000354F3, + 0x00080000, + 0x00001000, + 0x00080000, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x00000000, + 0x00000020, + 0x0080C000, + 0x41000000, + 0x00000002, + 0x00820008, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040000, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x01000000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x00020000, + 0x00000400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0x0000090C, + 0x00002000, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00400000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0xFFFFFFFF, + 0x14F1690D, + 0x1A041414, + 0x00D00000, + 0x0C864000, + 0x59647A03, + 0xC3CF23DC, + 0xF711451E, + 0x0358D348, + 0x821A0000, + 0x0000D000, + 0x00000680, + 0xD459647A, + 0x1E83CF23, + 0x48F51E79, + 0x000348D3, + 0x00080000, + 0x00001000, + 0x00080000, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x00000000, + 0x00000020, + 0x0080C000, + 0x41000000, + 0x00000002, + 0x00820008, + 0x00489800, + 0x801A1A1A, + 0x00000200, + 0x80000004, + 0x00000200, + 0x80000004, + 0x00000200, + 0x00000004, + 0x00000200, + 0x00000004, + 0x00040000, + 0x10000000, + 0x00000000, + 0x00008000, + 0x00010000, + 0x40002000, + 0x00000100, + 0x40000002, + 0x00000100, + 0x00000002, + 0x00000100, + 0x40000002, + 0x00000100, + 0x00000002, + 0x00020000, + 0x00000000, + 0x00000010, + 0x00000020, + 0x00008000, + 0x20001000, + 0x00000080, + 0x20000001, + 0x00000080, + 0x20000001, + 0x00000080, + 0x20000001, + 0x00000080, + 0x00000001, + 0x00010000, + 0x04000000, + 0x00FF0000, + 0x00000000, + 0x00004000, + 0x00000800, + 0xC0000001, + 0x00141419, + 0x40000000, + 0x04000816, + 0x000D0000, + 0x00006800, + 0x00000340, + 0xD000001A, + 0x06800000, + 0x00340000, + 0x0001A000, + 0x00000D00, + 0x40000068, + 0x1A000003, + 0x00D00000, + 0x00068000, + 0x00003400, + 0x000001A0, + 0x00000401, + 0x00000008, + 0x00000401, + 0x00000008, + 0x00000401, + 0x00000008, + 0x00000401, + 0x80000008, + 0x0000007F, + 0x20000000, + 0x00000000, + 0xE0000080, + 0x0000001F, + 0x00004000, +}; + +#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */ diff --git a/board/keymile/secu1/qts/pinmux_config.h b/board/keymile/secu1/qts/pinmux_config.h new file mode 100644 index 0000000000..a9406060ed --- /dev/null +++ b/board/keymile/secu1/qts/pinmux_config.h @@ -0,0 +1,218 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Altera SoCFPGA PinMux configuration + */ + +#ifndef __SOCFPGA_PINMUX_CONFIG_H__ +#define __SOCFPGA_PINMUX_CONFIG_H__ + +const u8 sys_mgr_init_table[] = { + 3, /* EMACIO0 */ + 3, /* EMACIO1 */ + 3, /* EMACIO2 */ + 3, /* EMACIO3 */ + 3, /* EMACIO4 */ + 3, /* EMACIO5 */ + 3, /* EMACIO6 */ + 3, /* EMACIO7 */ + 3, /* EMACIO8 */ + 3, /* EMACIO9 */ + 3, /* EMACIO10 */ + 3, /* EMACIO11 */ + 3, /* EMACIO12 */ + 3, /* EMACIO13 */ + 0, /* EMACIO14 */ + 0, /* EMACIO15 */ + 0, /* EMACIO16 */ + 0, /* EMACIO17 */ + 0, /* EMACIO18 */ + 0, /* EMACIO19 */ + 0, /* FLASHIO0 */ + 0, /* FLASHIO1 */ + 0, /* FLASHIO2 */ + 0, /* FLASHIO3 */ + 0, /* FLASHIO4 */ + 0, /* FLASHIO5 */ + 0, /* FLASHIO6 */ + 0, /* FLASHIO7 */ + 0, /* FLASHIO8 */ + 0, /* FLASHIO9 */ + 0, /* FLASHIO10 */ + 0, /* FLASHIO11 */ + 3, /* GENERALIO0 */ + 3, /* GENERALIO1 */ + 3, /* GENERALIO2 */ + 3, /* GENERALIO3 */ + 3, /* GENERALIO4 */ + 3, /* GENERALIO5 */ + 3, /* GENERALIO6 */ + 3, /* GENERALIO7 */ + 3, /* GENERALIO8 */ + 3, /* GENERALIO9 */ + 3, /* GENERALIO10 */ + 3, /* GENERALIO11 */ + 3, /* GENERALIO12 */ + 3, /* GENERALIO13 */ + 3, /* GENERALIO14 */ + 0, /* GENERALIO15 */ + 0, /* GENERALIO16 */ + 0, /* GENERALIO17 */ + 0, /* GENERALIO18 */ + 0, /* GENERALIO19 */ + 0, /* GENERALIO20 */ + 0, /* GENERALIO21 */ + 0, /* GENERALIO22 */ + 0, /* GENERALIO23 */ + 0, /* GENERALIO24 */ + 0, /* GENERALIO25 */ + 0, /* GENERALIO26 */ + 0, /* GENERALIO27 */ + 0, /* GENERALIO28 */ + 0, /* GENERALIO29 */ + 0, /* GENERALIO30 */ + 0, /* GENERALIO31 */ + 3, /* MIXED1IO0 */ + 3, /* MIXED1IO1 */ + 3, /* MIXED1IO2 */ + 3, /* MIXED1IO3 */ + 3, /* MIXED1IO4 */ + 3, /* MIXED1IO5 */ + 3, /* MIXED1IO6 */ + 3, /* MIXED1IO7 */ + 3, /* MIXED1IO8 */ + 3, /* MIXED1IO9 */ + 3, /* MIXED1IO10 */ + 3, /* MIXED1IO11 */ + 3, /* MIXED1IO12 */ + 3, /* MIXED1IO13 */ + 3, /* MIXED1IO14 */ + 0, /* MIXED1IO15 */ + 0, /* MIXED1IO16 */ + 0, /* MIXED1IO17 */ + 0, /* MIXED1IO18 */ + 0, /* MIXED1IO19 */ + 0, /* MIXED1IO20 */ + 0, /* MIXED1IO21 */ + 0, /* MIXED2IO0 */ + 0, /* MIXED2IO1 */ + 0, /* MIXED2IO2 */ + 0, /* MIXED2IO3 */ + 0, /* MIXED2IO4 */ + 0, /* MIXED2IO5 */ + 0, /* MIXED2IO6 */ + 0, /* MIXED2IO7 */ + 0, /* GPLINMUX48 */ + 0, /* GPLINMUX49 */ + 0, /* GPLINMUX50 */ + 0, /* GPLINMUX51 */ + 0, /* GPLINMUX52 */ + 0, /* GPLINMUX53 */ + 0, /* GPLINMUX54 */ + 0, /* GPLINMUX55 */ + 0, /* GPLINMUX56 */ + 0, /* GPLINMUX57 */ + 0, /* GPLINMUX58 */ + 0, /* GPLINMUX59 */ + 0, /* GPLINMUX60 */ + 0, /* GPLINMUX61 */ + 0, /* GPLINMUX62 */ + 0, /* GPLINMUX63 */ + 0, /* GPLINMUX64 */ + 0, /* GPLINMUX65 */ + 0, /* GPLINMUX66 */ + 0, /* GPLINMUX67 */ + 0, /* GPLINMUX68 */ + 0, /* GPLINMUX69 */ + 0, /* GPLINMUX70 */ + 1, /* GPLMUX0 */ + 1, /* GPLMUX1 */ + 1, /* GPLMUX2 */ + 1, /* GPLMUX3 */ + 1, /* GPLMUX4 */ + 1, /* GPLMUX5 */ + 1, /* GPLMUX6 */ + 1, /* GPLMUX7 */ + 1, /* GPLMUX8 */ + 1, /* GPLMUX9 */ + 1, /* GPLMUX10 */ + 1, /* GPLMUX11 */ + 1, /* GPLMUX12 */ + 1, /* GPLMUX13 */ + 1, /* GPLMUX14 */ + 1, /* GPLMUX15 */ + 1, /* GPLMUX16 */ + 1, /* GPLMUX17 */ + 1, /* GPLMUX18 */ + 1, /* GPLMUX19 */ + 1, /* GPLMUX20 */ + 1, /* GPLMUX21 */ + 1, /* GPLMUX22 */ + 1, /* GPLMUX23 */ + 1, /* GPLMUX24 */ + 1, /* GPLMUX25 */ + 1, /* GPLMUX26 */ + 1, /* GPLMUX27 */ + 1, /* GPLMUX28 */ + 1, /* GPLMUX29 */ + 1, /* GPLMUX30 */ + 1, /* GPLMUX31 */ + 1, /* GPLMUX32 */ + 1, /* GPLMUX33 */ + 1, /* GPLMUX34 */ + 1, /* GPLMUX35 */ + 1, /* GPLMUX36 */ + 1, /* GPLMUX37 */ + 1, /* GPLMUX38 */ + 1, /* GPLMUX39 */ + 1, /* GPLMUX40 */ + 1, /* GPLMUX41 */ + 1, /* GPLMUX42 */ + 1, /* GPLMUX43 */ + 1, /* GPLMUX44 */ + 1, /* GPLMUX45 */ + 1, /* GPLMUX46 */ + 1, /* GPLMUX47 */ + 1, /* GPLMUX48 */ + 1, /* GPLMUX49 */ + 1, /* GPLMUX50 */ + 1, /* GPLMUX51 */ + 1, /* GPLMUX52 */ + 1, /* GPLMUX53 */ + 1, /* GPLMUX54 */ + 1, /* GPLMUX55 */ + 1, /* GPLMUX56 */ + 1, /* GPLMUX57 */ + 1, /* GPLMUX58 */ + 1, /* GPLMUX59 */ + 1, /* GPLMUX60 */ + 1, /* GPLMUX61 */ + 1, /* GPLMUX62 */ + 1, /* GPLMUX63 */ + 1, /* GPLMUX64 */ + 1, /* GPLMUX65 */ + 1, /* GPLMUX66 */ + 1, /* GPLMUX67 */ + 1, /* GPLMUX68 */ + 1, /* GPLMUX69 */ + 1, /* GPLMUX70 */ + 0, /* NANDUSEFPGA */ + 0, /* UART0USEFPGA */ + 0, /* RGMII1USEFPGA */ + 0, /* SPIS0USEFPGA */ + 0, /* CAN0USEFPGA */ + 0, /* I2C0USEFPGA */ + 0, /* SDMMCUSEFPGA */ + 0, /* QSPIUSEFPGA */ + 0, /* SPIS1USEFPGA */ + 0, /* RGMII0USEFPGA */ + 0, /* UART1USEFPGA */ + 0, /* CAN1USEFPGA */ + 0, /* USB1USEFPGA */ + 0, /* I2C3USEFPGA */ + 0, /* I2C2USEFPGA */ + 0, /* I2C1USEFPGA */ + 1, /* SPIM1USEFPGA */ + 0, /* USB0USEFPGA */ + 0 /* SPIM0USEFPGA */ +}; +#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */ diff --git a/board/keymile/secu1/qts/pll_config.h b/board/keymile/secu1/qts/pll_config.h new file mode 100644 index 0000000000..f0c31860ca --- /dev/null +++ b/board/keymile/secu1/qts/pll_config.h @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Altera SoCFPGA Clock and PLL configuration + */ + +#ifndef __SOCFPGA_PLL_CONFIG_H__ +#define __SOCFPGA_PLL_CONFIG_H__ + +#define CONFIG_HPS_DBCTRL_STAYOSC1 1 + +#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0 +#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 39 +#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0 +#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0 +#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 +#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511 +#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 +#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15 +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 +#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 +#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 +#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 +#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1 +#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1 + +#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0 +#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 24 +#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0 +#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3 +#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 511 +#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 +#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 7 +#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4 +#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511 +#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 4 +#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0 +#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4 +#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4 +#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 +#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 1 +#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2 +#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1 + +#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0 +#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 14 +#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0 +#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 +#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 +#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 +#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 +#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 +#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 +#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 1 +#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0 + +#define CONFIG_HPS_CLK_OSC1_HZ 40000000 +#define CONFIG_HPS_CLK_OSC2_HZ 40000000 +#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 +#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0 +#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000 +#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000 +#define CONFIG_HPS_CLK_SDRVCO_HZ 600000000 +#define CONFIG_HPS_CLK_EMAC0_HZ 250000000 +#define CONFIG_HPS_CLK_EMAC1_HZ 1953125 +#define CONFIG_HPS_CLK_USBCLK_HZ 12500000 +#define CONFIG_HPS_CLK_NAND_HZ 31250000 +#define CONFIG_HPS_CLK_SDMMC_HZ 3125000 +#define CONFIG_HPS_CLK_QSPI_HZ 3125000 +#define CONFIG_HPS_CLK_SPIM_HZ 200000000 +#define CONFIG_HPS_CLK_CAN0_HZ 12500000 +#define CONFIG_HPS_CLK_CAN1_HZ 12500000 +#define CONFIG_HPS_CLK_GPIODB_HZ 32000 +#define CONFIG_HPS_CLK_L4_MP_HZ 100000000 +#define CONFIG_HPS_CLK_L4_SP_HZ 100000000 + +#define CONFIG_HPS_ALTERAGRP_MPUCLK 1 +#define CONFIG_HPS_ALTERAGRP_MAINCLK 3 +#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3 + +#endif /* __SOCFPGA_PLL_CONFIG_H__ */ diff --git a/board/keymile/secu1/qts/sdram_config.h b/board/keymile/secu1/qts/sdram_config.h new file mode 100644 index 0000000000..b0ff86ef38 --- /dev/null +++ b/board/keymile/secu1/qts/sdram_config.h @@ -0,0 +1,327 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Altera SoCFPGA SDRAM configuration + * + */ + +#ifndef __SOCFPGA_SDRAM_CONFIG_H__ +#define __SOCFPGA_SDRAM_CONFIG_H__ + +/* SDRAM configuration */ +#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A +#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 +#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 +#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 1 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 14 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 5 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 4 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 16 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 60 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 4 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 5 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 2341 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 5 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 5 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 2 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 2 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 13 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 17 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 200 +#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 3 +#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 3 +#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 3 +#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 +#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 +#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0 +#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 +#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 +#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 +#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x0 +#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 +#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 +#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x10441 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x78 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0x0 +#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 +#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 +#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 +#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 +#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 +#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543 + +/* Sequencer auto configuration */ +#define RW_MGR_ACTIVATE_0_AND_1 0x11 +#define RW_MGR_ACTIVATE_0_AND_1_WAIT1 0x12 +#define RW_MGR_ACTIVATE_0_AND_1_WAIT2 0x14 +#define RW_MGR_CLEAR_DQS_ENABLE 0x4B +#define RW_MGR_EMR 0x09 +#define RW_MGR_EMR2 0x0D +#define RW_MGR_EMR3 0x0F +#define RW_MGR_EMR_OCD_ENABLE 0x0B +#define RW_MGR_GUARANTEED_READ 0x4E +#define RW_MGR_GUARANTEED_READ_CONT 0x56 +#define RW_MGR_GUARANTEED_WRITE 0x1A +#define RW_MGR_GUARANTEED_WRITE_WAIT0 0x1D +#define RW_MGR_GUARANTEED_WRITE_WAIT1 0x21 +#define RW_MGR_GUARANTEED_WRITE_WAIT2 0x1B +#define RW_MGR_GUARANTEED_WRITE_WAIT3 0x1F +#define RW_MGR_IDLE 0x00 +#define RW_MGR_IDLE_LOOP1 0x77 +#define RW_MGR_IDLE_LOOP2 0x76 +#define RW_MGR_INIT_CKE_0 0x71 +#define RW_MGR_LFSR_WR_RD_BANK_0 0x24 +#define RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x27 +#define RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x26 +#define RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x25 +#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x34 +#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x23 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0 0x38 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x3B +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x3A +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x39 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x48 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x37 +#define RW_MGR_MR_CALIB 0x05 +#define RW_MGR_MR_DLL_RESET 0x07 +#define RW_MGR_MR_USER 0x03 +#define RW_MGR_NOP 0x01 +#define RW_MGR_PRECHARGE_ALL 0x16 +#define RW_MGR_READ_B2B 0x5B +#define RW_MGR_READ_B2B_WAIT1 0x63 +#define RW_MGR_READ_B2B_WAIT2 0x6D +#define RW_MGR_REFRESH 0x18 + +/* Sequencer defines configuration */ +#define AFI_CLK_FREQ 301 +#define AFI_RATE_RATIO 1 +#define CALIB_LFIFO_OFFSET 6 +#define CALIB_VFIFO_OFFSET 4 +#define ENABLE_SUPER_QUICK_CALIBRATION 0 +#define IO_DELAY_PER_DCHAIN_TAP 25 +#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25 +#define IO_DELAY_PER_OPA_TAP 416 +#define IO_DLL_CHAIN_LENGTH 8 +#define IO_DQDQS_OUT_PHASE_MAX 0 +#define IO_DQS_EN_DELAY_MAX 31 +#define IO_DQS_EN_DELAY_OFFSET 0 +#define IO_DQS_EN_PHASE_MAX 7 +#define IO_DQS_IN_DELAY_MAX 31 +#define IO_DQS_IN_RESERVE 4 +#define IO_DQS_OUT_RESERVE 4 +#define IO_IO_IN_DELAY_MAX 31 +#define IO_IO_OUT1_DELAY_MAX 31 +#define IO_IO_OUT2_DELAY_MAX 0 +#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0 +#define MAX_LATENCY_COUNT_WIDTH 5 +#define READ_VALID_FIFO_SIZE 16 +#define REG_FILE_INIT_SEQ_SIGNATURE 0x555504bf +#define RW_MGR_MEM_ADDRESS_MIRRORING 0 +#define RW_MGR_MEM_DATA_MASK_WIDTH 4 +#define RW_MGR_MEM_DATA_WIDTH 32 +#define RW_MGR_MEM_DQ_PER_READ_DQS 8 +#define RW_MGR_MEM_DQ_PER_WRITE_DQS 8 +#define RW_MGR_MEM_IF_READ_DQS_WIDTH 4 +#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 4 +#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1 +#define RW_MGR_MEM_NUMBER_OF_RANKS 1 +#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1 +#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1 +#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 4 +#define TINIT_CNTR0_VAL 74 +#define TINIT_CNTR1_VAL 20 +#define TINIT_CNTR2_VAL 20 +#define TRESET_CNTR0_VAL 74 +#define TRESET_CNTR1_VAL 99 +#define TRESET_CNTR2_VAL 10 + +/* Sequencer ac_rom_init configuration */ +const u32 ac_rom_init[] = { + 0x30700000, + 0x38700000, + 0x30700000, + 0x20700000, + 0x10000853, + 0x10000853, + 0x10000953, + 0x10010000, + 0x10010380, + 0x10020000, + 0x10030000, + 0x10300400, + 0x10600000, + 0x10620000, + 0x10200400, + 0x10400000, + 0x1c900000, + 0x1c920000, + 0x1c900008, + 0x1c920008, + 0x38f00000, + 0x3cf00000, + 0x38700000, + 0x10100000, + 0x18900000, + 0x13500000, + 0x13520000, + 0x13500008, + 0x13520008, + 0x33700000, + 0x10500008 +}; + +/* Sequencer inst_rom_init configuration */ +const u32 inst_rom_init[] = { + 0x80180, + 0x100, + 0x80000, + 0x200, + 0x80000, + 0x280, + 0x80000, + 0x300, + 0x80000, + 0x380, + 0x80000, + 0x400, + 0x80000, + 0x480, + 0x80000, + 0x500, + 0x80000, + 0x600, + 0x8000, + 0x680, + 0xa000, + 0x80000, + 0x700, + 0x80000, + 0x780, + 0x80000, + 0x968, + 0xcae8, + 0x8e8, + 0x8ae8, + 0x988, + 0xea88, + 0x808, + 0xaa88, + 0x80000, + 0xcc00, + 0xcb80, + 0xe080, + 0xa00, + 0x20ae0, + 0x20ae0, + 0x20ae0, + 0x20ae0, + 0xb00, + 0x0, + 0x0, + 0x0, + 0x0, + 0x60c80, + 0x60e80, + 0x60e80, + 0x60e80, + 0xa000, + 0x8000, + 0x80000, + 0xcc00, + 0xcb80, + 0xe080, + 0xa00, + 0x30ae0, + 0x30ae0, + 0x30ae0, + 0x30ae0, + 0xb00, + 0x0, + 0x0, + 0x0, + 0x0, + 0x70c80, + 0x70e80, + 0x70e80, + 0x70e80, + 0xa000, + 0x8000, + 0x80000, + 0xf58, + 0x58, + 0x80000, + 0xf68, + 0x168, + 0x168, + 0x8168, + 0x40de8, + 0x40ee8, + 0x40ee8, + 0x40ee8, + 0xf68, + 0x168, + 0x168, + 0xa168, + 0x80000, + 0x40c88, + 0x40e88, + 0x40e88, + 0x40e88, + 0x40d68, + 0x40ee8, + 0x40ee8, + 0x40ee8, + 0xa000, + 0x40de8, + 0x40ee8, + 0x40ee8, + 0x40ee8, + 0x40e08, + 0x40e88, + 0x40e88, + 0x40e88, + 0xf00, + 0xc000, + 0x8000, + 0xe000, + 0x80000, + 0x180, + 0x8180, + 0xa180, + 0xc180, + 0x80180, + 0x8000, + 0xa000, + 0x80000 +}; + +#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */ diff --git a/board/keymile/secu1/socfpga.c b/board/keymile/secu1/socfpga.c new file mode 100644 index 0000000000..dc04a21abe --- /dev/null +++ b/board/keymile/secu1/socfpga.c @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017-2020 ABB + */ +#include <common.h> +#include <i2c.h> +#include <asm/gpio.h> + +#include "../common/common.h" + +/* + * For FU1, the MAC address associated with the mgmt port should + * be the base address (as read from the IVM) + 4, and for FU2 it + * is + 10 + */ +#define MAC_ADDRESS_OFFSET_FU1 4 +#define MAC_ADDRESS_OFFSET_FU2 10 + +/* + * This function reads the state of GPIO40 and returns true (non-zero) + * if it is '1' and false(0) otherwise. + * + * This pin is routed to a pull-up on FU2 and a pull-down on + */ +#define GPIO_FU_DETECTION 40 + +int secu1_is_fu2(void) +{ + int value; + int ret = gpio_request(GPIO_FU_DETECTION, "secu"); + + if (ret) { + printf("gpio: failed to request pin for FU detection\n"); + return 1; + } + gpio_direction_input(GPIO_FU_DETECTION); + value = gpio_get_value(GPIO_FU_DETECTION); + + if (value == 1) + printf("FU2 detected\n"); + else + printf("FU1 detected\n"); + + return value; +} + +static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN]; + +#if defined(CONFIG_HUSH_INIT_VAR) +int hush_init_var(void) +{ + ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN); + return 0; +} +#endif + +int misc_init_r(void) +{ + if (secu1_is_fu2()) + ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN, + MAC_ADDRESS_OFFSET_FU2); + else + ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN, + MAC_ADDRESS_OFFSET_FU1); + + return 0; +} diff --git a/configs/socfpga_secu1_defconfig b/configs/socfpga_secu1_defconfig new file mode 100644 index 0000000000..230959ec86 --- /dev/null +++ b/configs/socfpga_secu1_defconfig @@ -0,0 +1,84 @@ +CONFIG_ARM=y +CONFIG_ARCH_SOCFPGA=y +CONFIG_SYS_MALLOC_F_LEN=0x800 +CONFIG_ENV_SIZE=0x1000 +CONFIG_ENV_OFFSET=0x100000 +CONFIG_DM_GPIO=y +# CONFIG_SPL_MMC_SUPPORT is not set +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_TARGET_SOCFPGA_ARRIA5_SECU1=y +CONFIG_ENV_OFFSET_REDUND=0x120000 +# CONFIG_SPL_LIBDISK_SUPPORT is not set +# CONFIG_SPL_SPI_SUPPORT is not set +CONFIG_SPL_TEXT_BASE=0xFFFF0000 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_BUILD_TARGET="u-boot-with-nand-spl.sfp" +CONFIG_FIT=y +# CONFIG_USE_BOOTCOMMAND is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y +CONFIG_DEFAULT_FDT_FILE="socfpga_arria5_secu1.dtb" +CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_LEGACY_IMAGE_CRC_CHECK=y +# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set +# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION is not set +CONFIG_SPL_MTD_SUPPORT=y +CONFIG_CMD_ASKENV=y +CONFIG_CMD_GREPENV=y +CONFIG_CMD_EEPROM=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_NAND_TRIMFFS=y +CONFIG_CMD_SPI=y +CONFIG_CMD_WDT=y +CONFIG_CMD_CACHE=y +CONFIG_MTDIDS_DEFAULT="nand0=denali-nand" +CONFIG_MTDPARTS_DEFAULT="mtdparts=denali-nand:512k(nand.4spl),512k(nand.uboot),128k(nand.env1),128k(nand.env2),0x1000000(nand.rec),0x3ee40000(nand.ubi),0x80000@0x3ff80000(nand.bbt)" +CONFIG_CMD_UBI=y +# CONFIG_CMD_UBIFS is not set +# CONFIG_ISO_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria5_secu1" +CONFIG_ENV_IS_IN_NAND=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_SPL_DM_SEQ_ALIAS=y +# CONFIG_SPL_BLK is not set +CONFIG_DWAPB_GPIO=y +CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_DM_I2C_GPIO=y +CONFIG_MISC=y +CONFIG_I2C_EEPROM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x50 +CONFIG_SYS_EEPROM_SIZE=1024 +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 +CONFIG_DM_MMC=y +CONFIG_MMC_DW=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_RAW_NAND=y +CONFIG_SYS_NAND_USE_FLASH_BBT=y +CONFIG_NAND_DENALI_DT=y +CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=2 +CONFIG_SPL_NAND_DENALI=y +# CONFIG_DM_SPI_FLASH is not set +CONFIG_MTD_UBI_FASTMAP=y +CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1 +CONFIG_MV88E6352_SWITCH=y +CONFIG_PHY_FIXED=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_MII=y +CONFIG_DM_RESET=y +CONFIG_SPI=y +CONFIG_SPI_MEM=y +CONFIG_DESIGNWARE_SPI=y +CONFIG_DESIGNWARE_WATCHDOG=y +CONFIG_WDT=y +# CONFIG_GZIP is not set diff --git a/include/configs/socfpga_arria5_secu1.h b/include/configs/socfpga_arria5_secu1.h new file mode 100644 index 0000000000..b059100ccd --- /dev/null +++ b/include/configs/socfpga_arria5_secu1.h @@ -0,0 +1,131 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017-2020 ABB + * + */ +#ifndef __CONFIG_SOCFPGA_SECU1_H__ +#define __CONFIG_SOCFPGA_SECU1_H__ + +#include <asm/arch/base_addr_ac5.h> + +/* Call misc_init_r */ +#define CONFIG_MISC_INIT_R + +#define CONFIG_HUSH_INIT_VAR +/* Eternal oscillator */ +#define CONFIG_SYS_TIMER_RATE 40000000 + +/* Memory configurations */ +#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512MiB on SECU1 */ + +/* + * We use bootcounter in i2c nvram of the RTC (0x68) + * The offset fopr the bootcounter is 0x9e, which are + * the last two bytes of the 128 bytes large NVRAM in the + * RTC which begin at address 0x20 + */ +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 + +/* Booting Linux */ +#define CONFIG_BOOTDELAY 2 +#define CONFIG_BOOTFILE "zImage" +#define CONFIG_BOOTARGS \ + "console=ttyS0," __stringify(CONFIG_BAUDRATE) \ + " ubi.fm_autoconvert=1" \ + " uio_pdrv_genirq.of_id=\"idq,regbank\"" + +#define CONFIG_BOOTCOMMAND \ + "setenv bootcmd '" \ + "bridge enable; " \ + "if test ${bootnum} = \"b\"; " \ + "then run _fpga_loadsafe; " \ + "else if test ${bootcount} -eq 4; then echo \"Switching copy...\"; setexpr x $bootnum % 2 && setexpr bootnum $x + 1; saveenv; fi; " \ + "run _fpga_loaduser; " \ + "fi;" \ + "echo \"Booting bank $bootnum\" && run userload && run userboot;" \ + "' && " \ + "setenv altbootcmd 'setenv bootnum b && saveenv && boot;' && " \ + "saveenv && saveenv && boot;" + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SYS_BOOTM_LEN (64 << 20) + +/* Environment settings */ +#define CONFIG_ENV_OVERWRITE + +/* + * Autoboot + * + * After 45s of inactivity in the prompt, the board will reset. + * Set 'bootretry' in the environment to -1 to disable this behavior + */ +#define CONFIG_BOOT_RETRY_TIME 45 +#define CONFIG_RESET_TO_RETRY + +#define CONFIG_LOADADDR 0x01000000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_KM_KERNEL_ADDR + +/* + * FPGA Remote Update related environment + * + * Note that since those commands access the FPGA, the HPS-to-FPGA + * bridges MUST have been previously enabled (for example + * with 'bridge enable'). + */ +#define FPGA_RMTU_ENV \ + "rmtu_page=0xFF29000C\0" \ + "rmtu_reconfig=0xFF290018\0" \ + "fpga_safebase=0x0\0" \ + "fpga_userbase=0x2000000\0" \ + "_fpga_loaduser=echo Loading FPGA USER image..." \ + " && mw ${rmtu_page} ${fpga_userbase} && mw ${rmtu_reconfig} 1\0" \ + "_fpga_loadsafe=echo Loading FPGA SAFE image..." \ + " && mw ${rmtu_page} ${fpga_safebase} && mw ${rmtu_reconfig} 1\0" \ + +#define CONFIG_KM_NEW_ENV \ + "newenv=" \ + "nand erase 0x100000 0x40000\0" + +#define CONFIG_KM_DEF_ENV_BOOTTARGETS \ + "release=" \ + "run newenv; reset\0" \ + "develop=" \ + "tftp 0x200000 scripts/develop-secu.txt && env import -t 0x200000 ${filesize} && saveenv && reset\0" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + FPGA_RMTU_ENV \ + CONFIG_KM_DEF_ENV_BOOTTARGETS \ + CONFIG_KM_NEW_ENV \ + "socfpga_legacy_reset_compat=1\0" \ + "altbootcmd=run bootcmd;\0" \ + "bootlimit=6\0" \ + "bootnum=1\0" \ + "bootretry=" __stringify(CONFIG_BOOT_RETRY_TIME) "\0" \ + "fdt_addr=" __stringify(CONFIG_KM_FDT_ADDR) "\0" \ + "load=tftpboot ${loadaddr} u-boot-with-nand-spl.sfp\0" \ + "loadaddr=" __stringify(CONFIG_KM_KERNEL_ADDR) "\0" \ + "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ + "update=nand erase 0x0 0x00100000 && nand write ${loadaddr} 0x0 ${filesize}\0" \ + "userload=ubi part nand.ubi &&" \ + "ubi check rootfs$bootnum &&" \ + "ubi read $fdt_addr dtb$bootnum &&" \ + "ubi read $loadaddr kernel$bootnum\0" \ + "userboot=setenv bootargs " CONFIG_BOOTARGS \ + " ubi.mtd=1 ubi.block=0,rootfs$bootnum root=/dev/ubiblock0_$ubivolid" \ + " ro rootfstype=squashfs init=sbin/preinit;" \ + "bootz ${loadaddr} - ${fdt_addr}\0" \ + "verify=y\0" + +/* The rest of the configuration is shared */ +#include <configs/socfpga_common.h> + +#ifdef CONFIG_SPL_NAND_SUPPORT +#undef CONFIG_SYS_NAND_U_BOOT_OFFS +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 +#endif + +#undef CONFIG_WATCHDOG_TIMEOUT_MSECS +#define CONFIG_WATCHDOG_TIMEOUT_MSECS 60000 + +#endif /* __CONFIG_SOCFPGA_SECU1_H__ */ -- 2.24.1

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[PATCH v2 1/2] sunxi: fix support board-specific CONFIG_PREBOOT
by Jonas Smedegaard 03 Mar '20

03 Mar '20

commit 37304aaf60bf ("Convert CONFIG_USE_PREBOOT and CONFIG_PREBOOT to Kconfig") intended to support CONFIG_PREBOOT, but include/configs/sunxi-common.h hardcodes preboot as part of internally defined CONSOLE_STDIN_SETTINGS, silently ignoring any board-specific CONFIG_PREBOOT. Simply moving CONFIG_PREBOOT to Kconfig does not work here, as that would loose the logic of implicitly setting a conditional default. This commit implements support for explicit CONFIG_PREBOOT for sunxi boards, while keeping as fallback the implicity default preboot value. Tested-by: Jonas Smedegaard <dr(a)jones.dk> Signed-off-by: Jonas Smedegaard <dr(a)jones.dk> Series-Cc: Jagan Teki <jagan(a)amarulasolutions.com> --- Changes in v2: - Rephrase commit message to clarify relationship with KConfig entries --- include/configs/sunxi-common.h | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 0ef289fd64..5edde29d1c 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -428,8 +428,13 @@ extern int soft_i2c_gpio_scl; #include <config_distro_bootcmd.h> #ifdef CONFIG_USB_KEYBOARD +#ifdef CONFIG_USE_PREBOOT +#ifndef CONFIG_PREBOOT +#define CONFIG_PREBOOT \ + "usb start" +#endif +#endif #define CONSOLE_STDIN_SETTINGS \ - "preboot=usb start\0" \ "stdin=serial,usbkbd\0" #else #define CONSOLE_STDIN_SETTINGS \ -- 2.25.1

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[PATCH v3 00/21] Actions S700 SoC support
by Amit Singh Tomar 03 Mar '20

03 Mar '20

Hi, This is continuation of work[1], submitted(v2) almost a year back. It adds Cubieboard7[1] support based on Action Semi's S700 SoC[2], It's Quad-core ARMv8 SoC with Cortex-A53 cores. Peripheral like UART seems to be compatible with S900 SoC(basic support for it is alreay present in u-boot). First few patches(from 1/21 to 3/21) consolidates Actions Semiconductor SoCs support in u-boot(mostly insprired by SUXNI as suggested by Andre). Idea is to move every bit out from board/ucRobotics into arch/arm/mach-owl. It allows different SoCs to be driven by single "soc and Kconfig" file. It also includes common clock driver for S700 and S900. Patches(from 4/21 to 6/21 and 10/21 to 12/21) enables S700 SoC support alongwith Cubieboard7 board. While at it, took the opportunity to sync S900 DT sources and bindings(patches from 7/21 to 8/21) with Linux(tag v5.5-rc6) and it is compiled-tested. Patch(9/21) uses same name for ethernet clock binding and if it's ok, would like to send it to LKML as well. Patches(from 13/21 to 14/21) adds support for RTL 8201F PHY module and introduce configuration option "RTL8201F_PHY_S700_RMII_TIMINGS" to fulfill specific timing requirements for S700. Patches(from 15/21 to 17/21) adds support for generic reset controller, originally used for NEXELL[3] series but never gets merged and it can be used for S700. Patches(from 18/21 to 21/21) are there to enable Ethenet support in S700, MAC is based on Designware IP These patches re-uses the existing driver(drivers/net/designware.c) and programs SoC specific bits to enable ethernet. SoC specific glue code is kept in dwmac_s700.c file, did it this way as found it more cleaner(but having said that I am not really sure, if it's bit of a overkill to have it) or we can keep this glue code somewhere in machine file? S700 support is tested[4] on Cubieboard7 board and S900 support is just compiled tested. Also, patches are rebased upon following commit: 2c871f9e084b2c03d1961884228a6901387ab8d6 Merge branch '2020-01-22-master-imports' Thanks -Amit [1]: https://patchwork.ozlabs.org/cover/1020286/ [2]: http://www.actions-semi.com/en/productview.aspx?id=225 [3]: https://lists.denx.de/pipermail/u-boot/2017-November/313135.html [4]: https://paste.ubuntu.com/p/GkFPn2xJfn/ Amit Singh Tomar (21): arm: actions: Add common framework for Actions Semi SoCs arm: actions: rename sysmap-s900 to sysmap-owl clk: actions: Add common clock driver arm: add support Actions Semi S700 arm: actions: add S700 SoC device tree actions:s700: add u-boot specific dts file arm: dts: sync dts for Action Semi S900 actions: s900: add u-boot specific dts file arm: dts: Use consistent name "CLK_ETHERNET" for the Ethernet clock binding serial: actions: add uart support for s700 arm: add Cubieboard7 board support actions: add Cubieboard7 README net: phy: realtek: Add support for RTL8201F PHY module. net: phy: realtek: Introduce PHY_RTL8201F_S700_RMII_TIMINGS to adjust rx/tx timings reset: add driver for generic reset controllers arm: dts: s700: add node for reset controller owl: Kconfig: Enable dm reset and generic reset net: designware: s700: Add glue code for S700 mac arm: dts: s700: add node for ethernet controller owl: Kconfig: Enable dm eth for OWL platform configs: Enable mac and phy configs MAINTAINERS | 2 + arch/arm/Kconfig | 8 +- arch/arm/dts/Makefile | 6 +- arch/arm/dts/s700-cubieboard7.dts | 39 +++ arch/arm/dts/s700-u-boot.dtsi | 39 +++ arch/arm/dts/s700.dtsi | 248 +++++++++++++++++++ arch/arm/dts/s900-u-boot.dtsi | 17 ++ arch/arm/dts/s900.dtsi | 322 +++++++++++++++++++++++-- arch/arm/include/asm/arch-owl/clk_s900.h | 57 ----- arch/arm/include/asm/arch-owl/regs_s700.h | 62 +++++ arch/arm/mach-owl/Kconfig | 35 +-- arch/arm/mach-owl/Makefile | 3 +- arch/arm/mach-owl/README.cubieboard7 | 88 +++++++ arch/arm/mach-owl/soc.c | 57 +++++ arch/arm/mach-owl/sysmap-owl.c | 32 +++ arch/arm/mach-owl/sysmap-s900.c | 32 --- board/ucRobotics/bubblegum_96/Kconfig | 15 -- board/ucRobotics/bubblegum_96/MAINTAINERS | 6 - board/ucRobotics/bubblegum_96/Makefile | 3 - board/ucRobotics/bubblegum_96/bubblegum_96.c | 57 ----- configs/bubblegum_96_defconfig | 7 +- configs/cubieboard7_defconfig | 20 ++ drivers/clk/owl/Kconfig | 8 +- drivers/clk/owl/Makefile | 2 +- drivers/clk/owl/clk_owl.c | 159 ++++++++++++ drivers/clk/owl/clk_owl.h | 65 +++++ drivers/clk/owl/clk_s900.c | 137 ----------- drivers/net/Kconfig | 7 + drivers/net/Makefile | 1 + drivers/net/dwmac_s700.c | 66 +++++ drivers/net/phy/Kconfig | 9 + drivers/net/phy/realtek.c | 55 +++++ drivers/reset/Kconfig | 6 + drivers/reset/Makefile | 1 + drivers/reset/reset-generic.c | 111 +++++++++ drivers/serial/serial_owl.c | 1 + include/configs/bubblegum_96.h | 40 --- include/configs/owl-common.h | 40 +++ include/configs/s700.h | 13 + include/configs/s900.h | 16 ++ include/dt-bindings/clock/actions,s700-cmu.h | 118 +++++++++ include/dt-bindings/clock/actions,s900-cmu.h | 129 ++++++++++ include/dt-bindings/clock/s900_cmu.h | 77 ------ include/dt-bindings/reset/actions,s700-reset.h | 34 +++ include/dt-bindings/reset/actions,s900-reset.h | 65 +++++ 45 files changed, 1835 insertions(+), 480 deletions(-) create mode 100644 arch/arm/dts/s700-cubieboard7.dts create mode 100644 arch/arm/dts/s700-u-boot.dtsi create mode 100644 arch/arm/dts/s700.dtsi create mode 100644 arch/arm/dts/s900-u-boot.dtsi delete mode 100644 arch/arm/include/asm/arch-owl/clk_s900.h create mode 100644 arch/arm/include/asm/arch-owl/regs_s700.h create mode 100644 arch/arm/mach-owl/README.cubieboard7 create mode 100644 arch/arm/mach-owl/soc.c create mode 100644 arch/arm/mach-owl/sysmap-owl.c delete mode 100644 arch/arm/mach-owl/sysmap-s900.c delete mode 100644 board/ucRobotics/bubblegum_96/Kconfig delete mode 100644 board/ucRobotics/bubblegum_96/MAINTAINERS delete mode 100644 board/ucRobotics/bubblegum_96/Makefile delete mode 100644 board/ucRobotics/bubblegum_96/bubblegum_96.c create mode 100644 configs/cubieboard7_defconfig create mode 100644 drivers/clk/owl/clk_owl.c create mode 100644 drivers/clk/owl/clk_owl.h delete mode 100644 drivers/clk/owl/clk_s900.c create mode 100644 drivers/net/dwmac_s700.c create mode 100644 drivers/reset/reset-generic.c delete mode 100644 include/configs/bubblegum_96.h create mode 100644 include/configs/owl-common.h create mode 100644 include/configs/s700.h create mode 100644 include/configs/s900.h create mode 100644 include/dt-bindings/clock/actions,s700-cmu.h create mode 100644 include/dt-bindings/clock/actions,s900-cmu.h delete mode 100644 include/dt-bindings/clock/s900_cmu.h create mode 100644 include/dt-bindings/reset/actions,s700-reset.h create mode 100644 include/dt-bindings/reset/actions,s900-reset.h -- 2.7.4

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