December 2020 - U-Boot

[PATCHv2 0/2] add support for Compulab iot-gate-imx8
by Ying-Chun Liu 02 Dec '20

02 Dec '20

From: "Ying-Chun Liu (PaulLiu)" <paul.liu(a)linaro.org> Add initial support for Compulab iot-gate-imx8 board (imx8mm-cl-iot-gate). The initial support includes: - MMC - eMMC - I2C - FEC - Serial console Ying-Chun Liu (PaulLiu) (2): arm: dts: add imx8mm-cl-iot-gate dts file arm: imx8m: add support for Compulab iot-gate-imx8 (imx8mm-cl-iot-gate) arch/arm/dts/Makefile | 2 + arch/arm/dts/imx8mm-cl-iot-gate-u-boot.dtsi | 131 ++ arch/arm/dts/imx8mm-cl-iot-gate.dts | 550 +++++ arch/arm/mach-imx/imx8m/Kconfig | 8 + board/compulab/imx8mm-cl-iot-gate/Kconfig | 12 + board/compulab/imx8mm-cl-iot-gate/MAINTAINERS | 6 + board/compulab/imx8mm-cl-iot-gate/Makefile | 13 + .../compulab/imx8mm-cl-iot-gate/ddr/Makefile | 8 + board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c | 211 ++ board/compulab/imx8mm-cl-iot-gate/ddr/ddr.h | 26 + .../ddr/lpddr4_timing_01061010.1_2.c | 1848 +++++++++++++++++ .../ddr/lpddr4_timing_01061010.c | 1847 ++++++++++++++++ .../ddr/lpddr4_timing_ff000110.c | 1847 ++++++++++++++++ .../ddr/lpddr4_timing_ff020008.c | 1847 ++++++++++++++++ .../imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c | 69 + board/compulab/imx8mm-cl-iot-gate/spl.c | 187 ++ configs/imx8mm-cl-iot-gate_defconfig | 130 ++ include/configs/imx8mm-cl-iot-gate.h | 153 ++ 18 files changed, 8895 insertions(+) create mode 100644 arch/arm/dts/imx8mm-cl-iot-gate-u-boot.dtsi create mode 100644 arch/arm/dts/imx8mm-cl-iot-gate.dts create mode 100644 board/compulab/imx8mm-cl-iot-gate/Kconfig create mode 100644 board/compulab/imx8mm-cl-iot-gate/MAINTAINERS create mode 100644 board/compulab/imx8mm-cl-iot-gate/Makefile create mode 100644 board/compulab/imx8mm-cl-iot-gate/ddr/Makefile create mode 100644 board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c create mode 100644 board/compulab/imx8mm-cl-iot-gate/ddr/ddr.h create mode 100644 board/compulab/imx8mm-cl-iot-gate/ddr/lpddr4_timing_01061010.1_2.c create mode 100644 board/compulab/imx8mm-cl-iot-gate/ddr/lpddr4_timing_01061010.c create mode 100644 board/compulab/imx8mm-cl-iot-gate/ddr/lpddr4_timing_ff000110.c create mode 100644 board/compulab/imx8mm-cl-iot-gate/ddr/lpddr4_timing_ff020008.c create mode 100644 board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c create mode 100644 board/compulab/imx8mm-cl-iot-gate/spl.c create mode 100644 configs/imx8mm-cl-iot-gate_defconfig create mode 100644 include/configs/imx8mm-cl-iot-gate.h -- 2.29.2

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[v1 0/5] Add Vendor Authorized Boot (VAB) support
by Siew Chin Lim 02 Dec '20

02 Dec '20

This patchset add Vendor Authorized Boot (VAB) support for Intel Agilex and Diamond Mesa SoC devices. Vendor Authorized Boot is a security feature for authenticating the images such as U-Boot, ARM trusted Firmware, Linux kernel, device tree blob and etc loaded from FIT. After those images are loaded from FIT, the VAB certificate and signature block appended at the end of each image are sent to Secure Device Manager (SDM) for authentication. U-Boot will validate the SHA384 of the image against the SHA384 hash stored in the VAB certificate before sending the image to SDM for authentication. These patchsets have dependency on: -------- Enable ARM Trusted Firmware for U-Boot https://patchwork.ozlabs.org/project/uboot/cover/20201015122955.10259-1-ell… Add Intel Diamond Mesa SoC support https://patchwork.ozlabs.org/project/uboot/cover/20201110064439.9683-1-elly… Siew Chin Lim (5): arm: socfpga: soc64: Support Vendor Authorized Boot (VAB) arm: socfpga: cmd: Support 'vab' command arm: socfpga: dts: soc64: Update filename in binman node of FIT image with VAB support configs: socfpga: soc64: Remove 'run linux_qspi_enable' from bootcommand configs: socfpga: Add defconfig for Agilex and Diamond Mesa with VAB support arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi | 22 +++ arch/arm/mach-socfpga/Kconfig | 15 ++ arch/arm/mach-socfpga/Makefile | 4 + arch/arm/mach-socfpga/include/mach/mailbox_s10.h | 1 + arch/arm/mach-socfpga/include/mach/secure_vab.h | 63 +++++++ arch/arm/mach-socfpga/secure_vab.c | 188 +++++++++++++++++++++ arch/arm/mach-socfpga/vab.c | 37 ++++ common/Kconfig.boot | 2 +- ..._atf_defconfig => socfpga_agilex_vab_defconfig} | 3 +- ...a_dm_atf_defconfig => socfpga_dm_vab_defconfig} | 3 +- include/configs/socfpga_soc64_common.h | 3 +- 11 files changed, 336 insertions(+), 5 deletions(-) create mode 100644 arch/arm/mach-socfpga/include/mach/secure_vab.h create mode 100644 arch/arm/mach-socfpga/secure_vab.c create mode 100644 arch/arm/mach-socfpga/vab.c copy configs/{socfpga_agilex_atf_defconfig => socfpga_agilex_vab_defconfig} (96%) copy configs/{socfpga_dm_atf_defconfig => socfpga_dm_vab_defconfig} (96%) -- 2.13.0

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mt7628-eth: phy link up detection takes too long
by Andrii Voloshyn 01 Dec '20

01 Dec '20

Hi there, I enabled (Automatic software update from a TFTP server [CONFIG_UPDATE_TFTP]), and noticed that it takes around 7 seconds to detect link up on the PHY. Is there a way to make this detection faster? I tried to advertise only 10MBit full duplex mode with auto negotiation disabled, but somehow host connected on the other end does not seem to recognize this. Could not find any documents on mt7628 Ethernet PHY, registers, timings, etc. Any ideas on how to speed up this link detection would be helpful. Cheers, Andrew

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[PATCH 1/4] arm: cache-cp15: add error when region is not aligned on MMU_SECTION
by Patrick Delaunay 01 Dec '20

01 Dec '20

Since commit d877f8fd0f09 ("arm: provide a function for boards init code to modify MMU virtual-physical map"), the mmu_set_region_dcache_behaviour_phys parameter need to be aligned on MMU_SECTION_SIZE to avoid unpredictable behavior (alignment was done previously done in the function mmu_set_region_dcache_behaviour_phys). This patch raised a error when this alignment is not respected. Even if this function is called so early, this message can be printed when CONFIG_DEBUG_UART is activated or can be treated later with CONFIG_PRE_CONSOLE_BUFFER. CC: Marek Szyprowski <m.szyprowski(a)samsung.com> Signed-off-by: Patrick Delaunay <patrick.delaunay(a)st.com> --- See complete analysis in comment #3 of patch [1] For example of workaround patch already sent see [2] [1] http://patchwork.ozlabs.org/project/uboot/patch/20200603124345.18595-4-m.sz… [2] stm32mp1: mmu_set_region_dcache_behaviour http://patchwork.ozlabs.org/project/uboot/patch/20200724092151.21335-1-patr… arch/arm/lib/cache-cp15.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index abd81d21c7..e2efe6f244 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -68,6 +68,11 @@ void mmu_set_region_dcache_behaviour_phys(phys_addr_t start, phys_addr_t phys, unsigned long startpt, stoppt; unsigned long upto, end; + if (!IS_ALIGNED(start, MMU_SECTION_SIZE) || + !IS_ALIGNED(size, MMU_SECTION_SIZE)) + log_err("%s: start=%p or size =%zx is not aligned with MMU_SECTION_SIZE (%x)\n", + __func__, (void *)start, size, MMU_SECTION_SIZE); + /* div by 2 before start + size to avoid phys_addr_t overflow */ end = ALIGN((start / 2) + (size / 2), MMU_SECTION_SIZE / 2) >> (MMU_SECTION_SHIFT - 1); -- 2.17.1

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[PATCH 1/3] mtd: spi nor: add support for dual and quad bit transfers
by Jean Pihet 01 Dec '20

01 Dec '20

Use the flags field of the SPI slave struct to pass the dual and quad read properties, from the SPI NOR layer to the low level driver. Tested with TI QSPI in 1, 2 and 4 bits modes. Signed-off-by: Jean Pihet <jean.pihet(a)newoldbits.com> --- drivers/mtd/spi/spi-nor-core.c | 34 +++++++++++++++++++++++++++++++--- drivers/spi/spi-mem.c | 8 +++++++- include/spi.h | 2 ++ 3 files changed, 40 insertions(+), 4 deletions(-) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index e16b0e1462..54569b3cba 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -94,22 +94,50 @@ static ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len, /* convert the dummy cycles to the number of bytes */ op.dummy.nbytes = (nor->read_dummy * op.dummy.buswidth) / 8; + /* Check for dual and quad I/O read */ + switch (op.cmd.opcode) { + case SPINOR_OP_READ_1_1_2: + case SPINOR_OP_READ_1_2_2: + case SPINOR_OP_READ_1_1_2_4B: + case SPINOR_OP_READ_1_2_2_4B: + case SPINOR_OP_READ_1_2_2_DTR: + case SPINOR_OP_READ_1_2_2_DTR_4B: + nor->spi->flags |= SPI_XFER_DUAL_READ; + break; + case SPINOR_OP_READ_1_1_4: + case SPINOR_OP_READ_1_4_4: + case SPINOR_OP_READ_1_1_4_4B: + case SPINOR_OP_READ_1_4_4_4B: + case SPINOR_OP_READ_1_4_4_DTR: + case SPINOR_OP_READ_1_4_4_DTR_4B: + nor->spi->flags |= SPI_XFER_QUAD_READ; + break; + default: + break; + } + while (remaining) { op.data.nbytes = remaining < UINT_MAX ? remaining : UINT_MAX; ret = spi_mem_adjust_op_size(nor->spi, &op); if (ret) - return ret; + goto out; ret = spi_mem_exec_op(nor->spi, &op); if (ret) - return ret; + goto out; op.addr.val += op.data.nbytes; remaining -= op.data.nbytes; op.data.buf.in += op.data.nbytes; } - return len; + ret = len; + +out: + /* Reset dual and quad I/O read flags for upcoming transactions */ + nor->spi->flags &= ~(SPI_XFER_DUAL_READ | SPI_XFER_QUAD_READ); + + return ret; } static ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t to, size_t len, diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c index c095ae9505..24e38ea95e 100644 --- a/drivers/spi/spi-mem.c +++ b/drivers/spi/spi-mem.c @@ -387,9 +387,15 @@ int spi_mem_exec_op(struct spi_slave *slave, const struct spi_mem_op *op) return ret; /* 2nd transfer: rx or tx data path */ + flag = SPI_XFER_END; + /* Check for dual and quad I/O reads */ + if (slave->flags & SPI_XFER_DUAL_READ) + flag |= SPI_XFER_DUAL_READ; + if (slave->flags & SPI_XFER_QUAD_READ) + flag |= SPI_XFER_QUAD_READ; if (tx_buf || rx_buf) { ret = spi_xfer(slave, op->data.nbytes * 8, tx_buf, - rx_buf, SPI_XFER_END); + rx_buf, flag); if (ret) return ret; } diff --git a/include/spi.h b/include/spi.h index ef8c1f6692..cf5f05e526 100644 --- a/include/spi.h +++ b/include/spi.h @@ -146,6 +146,8 @@ struct spi_slave { #define SPI_XFER_BEGIN BIT(0) /* Assert CS before transfer */ #define SPI_XFER_END BIT(1) /* Deassert CS after transfer */ #define SPI_XFER_ONCE (SPI_XFER_BEGIN | SPI_XFER_END) +#define SPI_XFER_DUAL_READ BIT(2) /* Dual I/O read */ +#define SPI_XFER_QUAD_READ BIT(3) /* Quad I/O read */ }; /** -- 2.26.2

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[PATCH 0/2] add support for Compulab iot-gate-imx8
by Ying-Chun Liu 01 Dec '20

01 Dec '20

From: "Ying-Chun Liu (PaulLiu)" <paul.liu(a)linaro.org> Add initial support for Compulab iot-gate-imx8 board. The initial support includes: - MMC - eMMC - I2C - FEC - Serial console Ying-Chun Liu (PaulLiu) (2): dts: add iot-gate-imx8 dts file arm: imx8m: add support for Compulab iot-gate-imx8 arch/arm/dts/Makefile | 2 + arch/arm/dts/iot-gate-imx8-u-boot.dtsi | 131 ++ arch/arm/dts/iot-gate-imx8.dts | 550 +++++ arch/arm/mach-imx/imx8m/Kconfig | 8 + board/compulab/iot-gate-imx8/Kconfig | 12 + board/compulab/iot-gate-imx8/MAINTAINERS | 6 + board/compulab/iot-gate-imx8/Makefile | 13 + board/compulab/iot-gate-imx8/ddr/Makefile | 8 + board/compulab/iot-gate-imx8/ddr/ddr.c | 211 ++ board/compulab/iot-gate-imx8/ddr/ddr.h | 26 + .../ddr/lpddr4_timing_01061010.1_2.c | 1848 +++++++++++++++++ .../ddr/lpddr4_timing_01061010.c | 1847 ++++++++++++++++ .../ddr/lpddr4_timing_ff000110.c | 1847 ++++++++++++++++ .../ddr/lpddr4_timing_ff020008.c | 1847 ++++++++++++++++ board/compulab/iot-gate-imx8/iot-gate-imx8.c | 69 + board/compulab/iot-gate-imx8/spl.c | 187 ++ configs/iot-gate-imx8_defconfig | 130 ++ include/configs/iot-gate-imx8.h | 153 ++ 18 files changed, 8895 insertions(+) create mode 100644 arch/arm/dts/iot-gate-imx8-u-boot.dtsi create mode 100644 arch/arm/dts/iot-gate-imx8.dts create mode 100644 board/compulab/iot-gate-imx8/Kconfig create mode 100644 board/compulab/iot-gate-imx8/MAINTAINERS create mode 100644 board/compulab/iot-gate-imx8/Makefile create mode 100644 board/compulab/iot-gate-imx8/ddr/Makefile create mode 100644 board/compulab/iot-gate-imx8/ddr/ddr.c create mode 100644 board/compulab/iot-gate-imx8/ddr/ddr.h create mode 100644 board/compulab/iot-gate-imx8/ddr/lpddr4_timing_01061010.1_2.c create mode 100644 board/compulab/iot-gate-imx8/ddr/lpddr4_timing_01061010.c create mode 100644 board/compulab/iot-gate-imx8/ddr/lpddr4_timing_ff000110.c create mode 100644 board/compulab/iot-gate-imx8/ddr/lpddr4_timing_ff020008.c create mode 100644 board/compulab/iot-gate-imx8/iot-gate-imx8.c create mode 100644 board/compulab/iot-gate-imx8/spl.c create mode 100644 configs/iot-gate-imx8_defconfig create mode 100644 include/configs/iot-gate-imx8.h -- 2.29.2

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[PATCH v2 1/2] cmd: load: Fix code indentation
by Michal Simek 01 Dec '20

01 Dec '20

Reported by smatch like: cmd/load.c:228 read_record() warn: inconsistent indenting Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- Changes in v2: - One } was missing. Get it back. arch/arm/dts/zynqmp.dtsi | 48 ++++++++-------------------------------- cmd/load.c | 9 ++++---- 2 files changed, 13 insertions(+), 44 deletions(-) diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 1634af0bd896..d5840ab8737e 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -672,6 +672,15 @@ power-domains = <&zynqmp_firmware PD_QSPI>; }; + psgtr: phy@fd400000 { + compatible = "xlnx,zynqmp-psgtr-v1.1"; + status = "disabled"; + reg = <0x0 0xfd400000 0x0 0x40000>, + <0x0 0xfd3d0000 0x0 0x1000>; + reg-names = "serdes", "siou"; + #phy-cells = <4>; + }; + rtc: rtc@ffa60000 { compatible = "xlnx,zynqmp-rtc"; status = "disabled"; @@ -682,45 +691,6 @@ calibration = <0x8000>; }; - serdes: zynqmp_phy@fd400000 { - compatible = "xlnx,zynqmp-psgtr"; - status = "disabled"; - reg = <0x0 0xfd400000 0x0 0x40000>, - <0x0 0xfd3d0000 0x0 0x1000>, - <0x0 0xff5e0000 0x0 0x1000>; - reg-names = "serdes", "siou", "lpd"; - nvmem-cells = <&soc_revision>; - nvmem-cell-names = "soc_revision"; - resets = <&zynqmp_reset ZYNQMP_RESET_SATA>, - <&zynqmp_reset ZYNQMP_RESET_USB0_CORERESET>, - <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>, - <&zynqmp_reset ZYNQMP_RESET_USB0_HIBERRESET>, - <&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>, - <&zynqmp_reset ZYNQMP_RESET_USB0_APB>, - <&zynqmp_reset ZYNQMP_RESET_USB1_APB>, - <&zynqmp_reset ZYNQMP_RESET_DP>, - <&zynqmp_reset ZYNQMP_RESET_GEM0>, - <&zynqmp_reset ZYNQMP_RESET_GEM1>, - <&zynqmp_reset ZYNQMP_RESET_GEM2>, - <&zynqmp_reset ZYNQMP_RESET_GEM3>; - reset-names = "sata_rst", "usb0_crst", "usb1_crst", - "usb0_hibrst", "usb1_hibrst", "usb0_apbrst", - "usb1_apbrst", "dp_rst", "gem0_rst", - "gem1_rst", "gem2_rst", "gem3_rst"; - lane0: lane0 { - #phy-cells = <4>; - }; - lane1: lane1 { - #phy-cells = <4>; - }; - lane2: lane2 { - #phy-cells = <4>; - }; - lane3: lane3 { - #phy-cells = <4>; - }; - }; - sata: ahci@fd0c0000 { compatible = "ceva,ahci-1v84"; status = "disabled"; diff --git a/cmd/load.c b/cmd/load.c index 9a3a16979c71..c6a7cc465153 100644 --- a/cmd/load.c +++ b/cmd/load.c @@ -228,12 +228,11 @@ static int read_record(char *buf, ulong len) *p = c; } - /* Check for the console hangup (if any different from serial) */ - if (gd->jt->getc != getchar) { - if (ctrlc()) { - return (-1); + /* Check for the console hangup (if any different from serial) */ + if (gd->jt->getc != getchar) { + if (ctrlc()) + return (-1); } - } } /* line too long - truncate */ -- 2.29.2

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[PULL] u-boot-mips fixes for v2021.01
by Daniel Schwierzeck 01 Dec '20

01 Dec '20

Hi Tom, please pull some bugfixes and some minor updates for compatibility with the Marvell Octeon MIPS64 boot header. Although this adds a new tool, everything is small and isolated to MIPS/Octeon. Gitlab CI: https://gitlab.denx.de/u-boot/custodians/u-boot-mips/-/pipelines/5455 Azure: https://dev.azure.com/danielschwierzeck/u-boot/_build/results?buildId=10&vi… The following changes since commit a7ab4b71d563b6e0b65f911a8bf7d6950625982e: Merge tag 'mmc-2020-11-29' of https://gitlab.denx.de/u-boot/custodians/u-boot-mmc (2020-11-29 11:12:59 -0500) are available in the Git repository at: https://gitlab.denx.de/u-boot/custodians/u-boot-mips.git tags/mips-fixes-for-v2021.01 for you to fetch changes up to 540a2bcec1389a3a31c23b5275e73186be6102b2: mips: octeon: tools: Add update_octeon_header tool (2020-11-30 18:32:09 +0100) ---------------------------------------------------------------- - MIPS: octeon: fix allocation bug in DDR driver - MIPS: octeon: fix init of gd->ram_size - MIPS: octeon: add support for Octeon boot header ---------------------------------------------------------------- Stefan Roese (5): mips: start.S: Add Octeon boot header compatibility mips: octeon: Fix Octeon DDR driver to use the correct struct mips: octeon: Report full DDR size in dram_init() to gd->ram_size mips: octeon: bootoctlinux: Use gd->ram_size instead of ram_get_info() mips: octeon: tools: Add update_octeon_header tool arch/mips/cpu/start.S | 10 +- arch/mips/mach-octeon/bootoctlinux.c | 21 +- arch/mips/mach-octeon/dram.c | 7 +- arch/mips/mach-octeon/include/mach/cvmx-bootinfo.h | 222 ---------- .../mach-octeon/include/mach/cvmx-bootloader.h | 172 ++++++++ drivers/ram/octeon/octeon_ddr.c | 2 +- tools/.gitignore | 1 + tools/Makefile | 3 + tools/update_octeon_header.c | 456 +++++++++++++++++++++ 9 files changed, 650 insertions(+), 244 deletions(-) create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-bootloader.h create mode 100644 tools/update_octeon_header.c

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[PATCH 1/2] cmd: load: Fix code indentation
by Michal Simek 01 Dec '20

01 Dec '20

Reported by smatch like: cmd/load.c:228 read_record() warn: inconsistent indenting Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- cmd/load.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/cmd/load.c b/cmd/load.c index 9a3a16979c71..9af0414c9c48 100644 --- a/cmd/load.c +++ b/cmd/load.c @@ -228,13 +228,11 @@ static int read_record(char *buf, ulong len) *p = c; } - /* Check for the console hangup (if any different from serial) */ - if (gd->jt->getc != getchar) { - if (ctrlc()) { - return (-1); + /* Check for the console hangup (if any different from serial) */ + if (gd->jt->getc != getchar) { + if (ctrlc()) + return (-1); } - } - } /* line too long - truncate */ *p = '\0'; -- 2.29.2

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[PATCH v4 0/2] dm: core: drivers: add function uclass_probe_all()
by Vabhav Sharma 01 Dec '20

01 Dec '20

From: Vabhav Sharma <vabhav.sharma(a)nxp.com> - Add common method to probe devices belonging to same uclass - Add config in serial uclass to support optional inclusion of uclass_probe_all - Enable support for available serial devices probe Changes for v4: Incorporated review comments from Simon - Removed if (dev).. conditional check in function uclass_probe_all() Changes for v3: Incorporated Simon and Stephan review comment - Define generic function uclass_probe_all(enum uclass_id) in drivers/core/uclass.c - Added the function in caller of serial_find_console_or_panic() - Removed repeated sequence with generic function call uclass_probe_all() Changes for v2: Incorporated Stefan review comment,Update #ifdef with macro if (IS_ENABLED). Vabhav Sharma (2): dm: core: add function uclass_probe_all() to probe all devices drivers: serial: probe all uart devices drivers/core/uclass.c | 16 ++++++++++++++++ drivers/serial/Kconfig | 17 +++++++++++++++++ drivers/serial/serial-uclass.c | 4 ++++ include/dm/uclass.h | 12 ++++++++++++ 4 files changed, 49 insertions(+) -- 2.7.4

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