December 2020 - U-Boot

[PATCH] cmd: mmc: modify partconf to be used in script
by grygorii tertychnyi 14 Dec '20

14 Dec '20

To implement dual-boot strategy we need to know what is the current boot partition for U-Boot. It can be easily identified by looking at the PARTITION_CONFIG value shown by "mmc partconf dev", but I didn't find any way to use it in the boot script. Hence, modify it, so that "mmc partboot dev part_num" command returns true if "part_num" is the current boot partition, otherwise it returns false. Signed-off-by: Grygorii Tertychnyi <grygorii.tertychnyi(a)leica-geosystems.com> --- cmd/mmc.c | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/cmd/mmc.c b/cmd/mmc.c index 1529a3e05ddd..c8db008bc90d 100644 --- a/cmd/mmc.c +++ b/cmd/mmc.c @@ -792,6 +792,23 @@ static int mmc_partconf_print(struct mmc *mmc) return CMD_RET_SUCCESS; } +static int mmc_partnum_cmp(struct mmc *mmc, u8 part_num) +{ + u8 part; + + if (mmc->part_config == MMCPART_NOAVAILABLE) { + printf("No part_config info for ver. 0x%x\n", mmc->version); + return CMD_RET_FAILURE; + } + + part = EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config); + + if (part == part_num) + return CMD_RET_SUCCESS; + else + return CMD_RET_FAILURE; +} + static int do_mmc_partconf(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { @@ -799,7 +816,7 @@ static int do_mmc_partconf(struct cmd_tbl *cmdtp, int flag, struct mmc *mmc; u8 ack, part_num, access; - if (argc != 2 && argc != 5) + if (argc != 2 && argc != 3 && argc != 5) return CMD_RET_USAGE; dev = simple_strtoul(argv[1], NULL, 10); @@ -815,6 +832,10 @@ static int do_mmc_partconf(struct cmd_tbl *cmdtp, int flag, if (argc == 2) return mmc_partconf_print(mmc); + if (argc == 3) { + part_num = simple_strtoul(argv[2], NULL, 10); + return mmc_partnum_cmp(mmc, part_num); + } ack = simple_strtoul(argv[2], NULL, 10); part_num = simple_strtoul(argv[3], NULL, 10); -- 2.25.1

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[PATCH v5 0/7] Microchip PolarFire SoC support
by Padmarao Begari 14 Dec '20

14 Dec '20

This patch set adds Microchip PolarFire SoC Icicle Kit support to RISC-V U-Boot. The patches are based upon latest U-Boot tree (https://gitlab.denx.de/u-boot/u-boot.git) at commit id 80cbd731df50b9ab646940ea862b70bcaff37225 All drivers namely: NS16550 Serial, Microchip clock, Cadence eMMC and Cadence MACB Ethernet work fine on actual Microchip PolarFire SoC Icicle Kit. Changes in v5: - Replace compatible string "microchip,polarfire-soc" with "microchip,mpfs-icicle-kit" in the device tree - Use "mpfs" as identifier in place of "polarfire-soc", "pfsoc" - Fix some typos in doc - Rename the clock driver files clk_pfsoc_* to mpfs_clk_* - Rename pfsoc-clock.h to mpfs-clock.h Changes in v4: - Add dual-license GPL or MIT in the device tree - Replace microsemi compatible strings with microchip - Add MACB compatible string for Microchip PolarFire SoC ethernet - Update MACB driver for 32-bit/64-bit DMA based on compatible string Changes in v3: - Add 'default y if 64BIT' for config DMA_ADDR_T_64BIT - Update MACB driver for 32-bit/64-bit DMA based on design config register - Add phy-handle in MACB driver to read the phy address from device tree - Fix checkpatch warnings in the clock driver - Remove fu540 related compatible strings from soc device tree node - Move refclk device tree node under /soc device tree node - Use local-mac-address instead of mac-address in the device tree - Rename device tree to microchip-mpfs-icicle-kit.dts - Add U-Boot specific dts microchip-mpfs-icicle-kit-u-boot.dtsi file - Drop the imply DMA_ADDR_T_64BIT from board config - Fix some typos - Update doc with Microchip and Custom boot-flow Changes in v2: - Add clock frequency for the clint device tree node - Move peripheral device tree nodes under /soc device tree node - Device tree nodes are in order based on the address - Enable UART0 for U-Boot logs - Update doc for the U-Boot logs are on UART0 - Move clock and reset index source into patch4 - Remove "dma_addr_r" type in the macb driver - Add lower_32_bits() for 32-bit address in the macb driver - Add set_rate() returns the new clock rate in the clock driver Padmarao Begari (7): riscv: Add DMA 64-bit address support net: macb: Add DMA 64-bit address support for macb net: macb: Add phy address to read it from device tree clk: Add Microchip PolarFire SoC clock driver riscv: dts: Add device tree for Microchip Icicle Kit riscv: Add Microchip MPFS Icicle Kit support doc: board: Add Microchip MPFS Icicle Kit doc arch/riscv/Kconfig | 4 + arch/riscv/dts/Makefile | 1 + .../dts/microchip-mpfs-icicle-kit-u-boot.dtsi | 14 + arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 421 +++++++++ arch/riscv/include/asm/types.h | 4 + board/microchip/mpfs_icicle/Kconfig | 24 + board/microchip/mpfs_icicle/mpfs_icicle.c | 97 +- configs/microchip_mpfs_icicle_defconfig | 9 +- doc/board/index.rst | 1 + doc/board/microchip/index.rst | 9 + doc/board/microchip/mpfs_icicle.rst | 830 ++++++++++++++++++ drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/microchip/Kconfig | 5 + drivers/clk/microchip/Makefile | 1 + drivers/clk/microchip/mpfs_clk.c | 127 +++ drivers/clk/microchip/mpfs_clk.h | 19 + drivers/clk/microchip/mpfs_clk_cfg.c | 134 +++ drivers/clk/microchip/mpfs_clk_periph.c | 173 ++++ drivers/net/macb.c | 144 ++- drivers/net/macb.h | 6 + include/configs/microchip_mpfs_icicle.h | 60 +- .../dt-bindings/clock/microchip,mpfs-clock.h | 45 + 23 files changed, 2068 insertions(+), 62 deletions(-) create mode 100644 arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi create mode 100644 arch/riscv/dts/microchip-mpfs-icicle-kit.dts create mode 100644 doc/board/microchip/index.rst create mode 100644 doc/board/microchip/mpfs_icicle.rst create mode 100644 drivers/clk/microchip/Kconfig create mode 100644 drivers/clk/microchip/Makefile create mode 100644 drivers/clk/microchip/mpfs_clk.c create mode 100644 drivers/clk/microchip/mpfs_clk.h create mode 100644 drivers/clk/microchip/mpfs_clk_cfg.c create mode 100644 drivers/clk/microchip/mpfs_clk_periph.c create mode 100644 include/dt-bindings/clock/microchip,mpfs-clock.h -- 2.17.1

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[PATCH] usb: dwc3-meson-g12a: always configure dr-mode
by Marek Szyprowski 14 Dec '20

14 Dec '20

dwc3_meson_g12a_force_mode() sets the dr-mode of the USB PHY. However it skips setting the mode if it matches the one done during driver probe (stored in private structure). This fails if the mode has been changed to other value and then back to initial one. Fix this by configuring the dr-mode always, regadless of the one set at the driver probe). This fixes operation of USB gadget based drivers when they are initialized for the second time. Signed-off-by: Marek Szyprowski <m.szyprowski(a)samsung.com> --- drivers/usb/dwc3/dwc3-meson-g12a.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/usb/dwc3/dwc3-meson-g12a.c b/drivers/usb/dwc3/dwc3-meson-g12a.c index 6567502cdd1..6f0bac2a00c 100644 --- a/drivers/usb/dwc3/dwc3-meson-g12a.c +++ b/drivers/usb/dwc3/dwc3-meson-g12a.c @@ -269,9 +269,6 @@ int dwc3_meson_g12a_force_mode(struct udevice *dev, enum usb_dr_mode mode) if (!priv->phys[USB2_OTG_PHY].dev) return -EINVAL; - if (mode == priv->otg_mode) - return 0; - if (mode == USB_DR_MODE_HOST) debug("%s: switching to Host Mode\n", __func__); else -- 2.17.1

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[PATCH 0/6] IPQ40xx: Improve support
by Robert Marko 14 Dec '20

14 Dec '20

This is a third patch series working towards providing a usable U-boot support for Qualcomm IPQ40xx SoC-s. This patch series adds SPI driver so booting is finally possible, RNG driver for the built in pseudo RNG and MDIO driver to prepare for future ethernet support. Booting Linux is now possible. Signed-off-by: Robert Marko <robert.marko(a)sartura.hr> Cc: Luka Perkov <luka.perkov(a)sartura.hr> Robert Marko (6): spi: Add Qualcomm QUP SPI controller driver IPQ40xx: Add SPI support net: Add IPQ40xx MDIO driver IPQ40xx: Add support for MDIO rng: Add Qualcomm MSM PRNG driver IPQ40xx: Add PRNG support MAINTAINERS | 3 + arch/arm/dts/qcom-ipq4019.dtsi | 47 ++ arch/arm/mach-ipq40xx/clock-ipq4019.c | 21 +- arch/arm/mach-ipq40xx/pinctrl-ipq4019.c | 7 + doc/device-tree-bindings/spi/spi-qup.txt | 33 + drivers/net/Kconfig | 7 + drivers/net/Makefile | 1 + drivers/net/mdio-ipq4019.c | 146 +++++ drivers/rng/Kconfig | 7 + drivers/rng/Makefile | 1 + drivers/rng/msm_rng.c | 143 ++++ drivers/spi/Kconfig | 10 + drivers/spi/Makefile | 1 + drivers/spi/spi-qup.c | 803 +++++++++++++++++++++++ 14 files changed, 1228 insertions(+), 2 deletions(-) create mode 100644 doc/device-tree-bindings/spi/spi-qup.txt create mode 100644 drivers/net/mdio-ipq4019.c create mode 100644 drivers/rng/msm_rng.c create mode 100644 drivers/spi/spi-qup.c -- 2.28.0

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[PATCH 1/2] rng: Add iProc RNG200 driver
by matthias.bgg＠kernel.org 14 Dec '20

14 Dec '20

From: Matthias Brugger <mbrugger(a)suse.com> Add support for random number generator RNG200. This is for example found on RPi4. Signed-off-by: Matthias Brugger <mbrugger(a)suse.com> --- drivers/rng/Kconfig | 6 ++ drivers/rng/Makefile | 1 + drivers/rng/iproc_rng200.c | 186 +++++++++++++++++++++++++++++++++++++ 3 files changed, 193 insertions(+) create mode 100644 drivers/rng/iproc_rng200.c diff --git a/drivers/rng/Kconfig b/drivers/rng/Kconfig index 11001c8ae7..94915d45b3 100644 --- a/drivers/rng/Kconfig +++ b/drivers/rng/Kconfig @@ -46,4 +46,10 @@ config RNG_ROCKCHIP Enable random number generator for rockchip.This driver is support rng module of crypto v1 and crypto v2. +config RNG_IPROC200 + bool "Broadcom iProc RNG200 random number generator" + depends on DM_RNG + default n + help + Enable random number generator for RPI4. endif diff --git a/drivers/rng/Makefile b/drivers/rng/Makefile index 8953406882..39f7ee3f03 100644 --- a/drivers/rng/Makefile +++ b/drivers/rng/Makefile @@ -9,3 +9,4 @@ obj-$(CONFIG_RNG_SANDBOX) += sandbox_rng.o obj-$(CONFIG_RNG_MSM) += msm_rng.o obj-$(CONFIG_RNG_STM32MP1) += stm32mp1_rng.o obj-$(CONFIG_RNG_ROCKCHIP) += rockchip_rng.o +obj-$(CONFIG_RNG_IPROC200) += iproc_rng200.o diff --git a/drivers/rng/iproc_rng200.c b/drivers/rng/iproc_rng200.c new file mode 100644 index 0000000000..1063f43953 --- /dev/null +++ b/drivers/rng/iproc_rng200.c @@ -0,0 +1,186 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2020, Matthias Brugger <mbrugger(a)suse.com> + * + * Driver for Raspberry Pi hardware random number generator + */ + +#include <common.h> +#include <dm.h> +#include <linux/delay.h> +#include <rng.h> +#include <asm/io.h> + +#define usleep_range(a, b) udelay((b)) + +#define RNG_CTRL_OFFSET 0x00 +#define RNG_CTRL_RNG_RBGEN_MASK 0x00001FFF +#define RNG_CTRL_RNG_RBGEN_ENABLE 0x00000001 +#define RNG_CTRL_RNG_RBGEN_DISABLE 0x00000000 + +#define RNG_SOFT_RESET_OFFSET 0x04 +#define RNG_SOFT_RESET 0x00000001 + +#define RBG_SOFT_RESET_OFFSET 0x08 +#define RBG_SOFT_RESET 0x00000001 + +#define RNG_INT_STATUS_OFFSET 0x18 +#define RNG_INT_STATUS_MASTER_FAIL_LOCKOUT_IRQ_MASK 0x80000000 +#define RNG_INT_STATUS_NIST_FAIL_IRQ_MASK 0x00000020 + +#define RNG_FIFO_DATA_OFFSET 0x20 + +#define RNG_FIFO_COUNT_OFFSET 0x24 +#define RNG_FIFO_COUNT_RNG_FIFO_COUNT_MASK 0x000000FF + +struct iproc_rng200_platdata { + fdt_addr_t base; +}; + +static void iproc_rng200_enable(struct iproc_rng200_platdata *pdata, bool enable) +{ + fdt_addr_t rng_base = pdata->base; + u32 val; + + val = readl(rng_base + RNG_CTRL_OFFSET); + val &= ~RNG_CTRL_RNG_RBGEN_MASK; + if (enable) + val |= RNG_CTRL_RNG_RBGEN_ENABLE; + else + val &= ~RNG_CTRL_RNG_RBGEN_ENABLE; + + writel(val, rng_base + RNG_CTRL_OFFSET); + +} + +static void iproc_rng200_restart(struct iproc_rng200_platdata *pdata) +{ + fdt_addr_t rng_base = pdata->base; + u32 val; + + iproc_rng200_enable(pdata, false); + + /* Clear all interrupt status */ + writel(0xFFFFFFFFUL, rng_base + RNG_INT_STATUS_OFFSET); + + /* Reset RNG and RBG */ + val = readl(rng_base + RBG_SOFT_RESET_OFFSET); + val |= RBG_SOFT_RESET; + writel(val, rng_base + RBG_SOFT_RESET_OFFSET); + + val = readl(rng_base + RNG_SOFT_RESET_OFFSET); + val |= RNG_SOFT_RESET; + writel(val, rng_base + RNG_SOFT_RESET_OFFSET); + + val = readl(rng_base + RNG_SOFT_RESET_OFFSET); + val &= ~RNG_SOFT_RESET; + writel(val, rng_base + RNG_SOFT_RESET_OFFSET); + + val = readl(rng_base + RBG_SOFT_RESET_OFFSET); + val &= ~RBG_SOFT_RESET; + writel(val, rng_base + RBG_SOFT_RESET_OFFSET); + + iproc_rng200_enable(pdata, true); +} + +static int iproc_rng200_read(struct udevice *dev, void *data, size_t len) +{ + struct iproc_rng200_platdata *priv = dev_get_platdata(dev); + char *buf = (char *)data; + u32 num_remaining = len; + u32 status; + + #define MAX_RESETS_PER_READ 1 + u32 num_resets = 0; + + while (num_remaining > 0) { + + /* Is RNG sane? If not, reset it. */ + status = readl(priv->base + RNG_INT_STATUS_OFFSET); + if ((status & (RNG_INT_STATUS_MASTER_FAIL_LOCKOUT_IRQ_MASK | + RNG_INT_STATUS_NIST_FAIL_IRQ_MASK)) != 0) { + + if (num_resets >= MAX_RESETS_PER_READ) + return len - num_remaining; + + iproc_rng200_restart(priv); + num_resets++; + } + + /* Are there any random numbers available? */ + if ((readl(priv->base + RNG_FIFO_COUNT_OFFSET) & + RNG_FIFO_COUNT_RNG_FIFO_COUNT_MASK) > 0) { + + if (num_remaining >= sizeof(u32)) { + /* Buffer has room to store entire word */ + *(u32 *)buf = readl(priv->base + + RNG_FIFO_DATA_OFFSET); + buf += sizeof(u32); + num_remaining -= sizeof(u32); + } else { + /* Buffer can only store partial word */ + u32 rnd_number = readl(priv->base + + RNG_FIFO_DATA_OFFSET); + memcpy(buf, &rnd_number, num_remaining); + buf += num_remaining; + num_remaining = 0; + } + + } else { + /* Can wait, give others chance to run */ + usleep_range(min(num_remaining * 10, 500U), 500); + } + } + + return 0; +} + +static int iproc_rng200_probe(struct udevice *dev) +{ + struct iproc_rng200_platdata *priv = dev_get_platdata(dev); + + iproc_rng200_enable(priv, true); + + return 0; +} + +static int iproc_rng200_remove(struct udevice *dev) +{ + struct iproc_rng200_platdata *priv = dev_get_platdata(dev); + + iproc_rng200_enable(priv, false); + + return 0; +} + +static int iproc_rng200_ofdata_to_platdata(struct udevice *dev) +{ + struct iproc_rng200_platdata *pdata = dev_get_platdata(dev); + + pdata->base = dev_read_addr(dev); + if (!pdata->base) + return -ENODEV; + + return 0; +} + +static const struct dm_rng_ops iproc_rng200_ops = { + .read = iproc_rng200_read, +}; + +static const struct udevice_id iproc_rng200_rng_match[] = { + { .compatible = "brcm,bcm2711-rng200", }, + { .compatible = "brcm,iproc-rng200", }, + {}, +}; + +U_BOOT_DRIVER(iproc_rng200_rng) = { + .name = "iproc_rng200-rng", + .id = UCLASS_RNG, + .of_match = iproc_rng200_rng_match, + .ops = &iproc_rng200_ops, + .probe = iproc_rng200_probe, + .remove = iproc_rng200_remove, + .platdata_auto_alloc_size = sizeof(struct iproc_rng200_platdata), + .ofdata_to_platdata = iproc_rng200_ofdata_to_platdata, +}; -- 2.29.2

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Run U-Boot as Legacy Bios payload?
by Köry Maincent 14 Dec '20

14 Dec '20

Hello, Does U-Boot can be built and run as a Legacy BIOS payload, like GRUB or SeaBios? Indeed GRUB or SeaBios have a stage 1 binary to be merge in GPT/MBR partition table. I did not find something like that with U-Boot. I do not want to use U-Boot with UEFI, I have already done it. I saw U-boot can be used as Coreboot payload, but I can not find how to use with BIOS. Regards, Köry

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[PATCH 0/6] Add MMC/SD support for S700
by Amit Singh Tomar 14 Dec '20

14 Dec '20

From: Amit Singh Tomar <amittomer25(a)gmail.com> At the moment on S700 based platforms, only way to load/boot the Kernel is from Ethernet, and with these patches one can now load/boot the Kernel from uSD card. Patches(1/6 and 2/6) adds changes needed for MMC/SD clock. It introduces set/get callback routine and get/set MMC/SD clock rate based on device id. Patch 4/6 adds MMC/SD node in U-boot specific dtsi file, which is used by MMC/SD driver to read controller base address later on. Patch 5/6 adds driver for MMC/SD controller present on S700 SoC, and its based on Mainline Linux driver and DMA related bits is picked and simpilified from vendor source. Final patch 6/6 enables the driver support along with MMC commands in Cubieboard7 config file. Also, while at it just took the opportunity to synchronize the S700 SoC DT with Linux in patch 3/6. This patch-set is tested on Cubieboard7-lite board with following results: U-Boot 2021.01-rc1-04434-g6589149-dirty (Dec 13 2020 - 13:51:07 +0530) cubieboard7 DRAM: 1 GiB PSCI: v0.2 MMC: mmc@e0210000: 0 In: serial@e0126000 Out: serial@e0126000 Err: serial@e0126000 Net: eth0: ethernet@e0220000 Hit any key to stop autoboot: 0 U-Boot => U-Boot => U-Boot => U-Boot => mmc info Device: mmc@e0210000 Manufacturer ID: 3 OEM: 5344 Name: SC16G Bus Speed: 50000000 Mode: SD High Speed (50MHz) Rd Block Len: 512 SD version 3.0 High Capacity: Yes Capacity: 14.8 GiB Bus Width: 4-bit Erase Group Size: 512 Bytes U-Boot => setenv bootargs console=ttyOWL3,115200n8 earlycon=owl,0xe0126000 init=/sbin/init root=/dev/mmcblk0p2 rw rootwait U-Boot => setenv kernel_addr_r 0x80000;setenv fdt_addr_r 0x10000000; U-Boot => fatload mmc 0:1 ${kernel_addr_r} image ;fatload mmc 0:1 ${fdt_addr_r} s700-cubieboard7.dtb 27480576 bytes read in 1041 ms (25.2 MiB/s) 7056 bytes read in 2 ms (3.4 MiB/s) U-Boot => booti $kernel_addr_r - $fdt_addr_r ## Flattened Device Tree blob at 10000000 Booting using the fdt blob at 0x10000000 Loading Device Tree to 000000003df56000, end 000000003df5ab8f ... OK Starting kernel ... [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034] [ 0.000000] Linux version 5.7.0-rc6-00022-g99f1c330923b-dirty (amit@amit-ThinkPad-X230) (gcc version 7.3.1 20180425 [linaro-7.3-2018.05 revision d29120a424ecfbc167ef90065c0eeb7f91977701] (Linaro GCC 7.3-2018.05), GNU ld (GNU Binutils for Ubuntu) 2.26.1) #474 SMP PREEMPT Thu Aug 13 15:27:10 IST 2020 [ 0.000000] Machine model: CubieBoard7 [ 0.000000] earlycon: owl0 at MMIO 0x00000000e0126000 (options '') [ 0.000000] printk: bootconsole [owl0] enabled [ 0.000000] efi: UEFI not found. [ 0.000000] cma: Reserved 32 MiB at 0x000000003e000000 Amit Singh Tomar (6): clk: actions: Introduce dummy get/set_rate callbacks clk: actions: Add SD/MMC clocks ARM: dts: sync Actions Semi S700 DT from Linux 5.10-rc7 ARM: dts: s700: add MMC/SD controller node mmc: actions: add MMC driver for Actions OWL S700 configs: Enable mmc support arch/arm/dts/s700-u-boot.dtsi | 10 + arch/arm/dts/s700.dtsi | 17 +- configs/cubieboard7_defconfig | 3 + drivers/clk/owl/clk_owl.c | 94 ++++++ drivers/clk/owl/clk_owl.h | 2 + drivers/mmc/Kconfig | 7 + drivers/mmc/Makefile | 1 + drivers/mmc/owl_mmc.c | 404 +++++++++++++++++++++++++ include/dt-bindings/power/owl-s700-powergate.h | 19 ++ 9 files changed, 556 insertions(+), 1 deletion(-) create mode 100644 drivers/mmc/owl_mmc.c create mode 100644 include/dt-bindings/power/owl-s700-powergate.h -- 2.7.4

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Re: [PATCH 2/6] clk: actions: Add SD/MMC clocks
by André Przywara 14 Dec '20

14 Dec '20

On 13/12/2020 09:44, Amit Singh Tomar wrote: Hi, > This commit adds SD/MMC clocks, and provides .set/get_rate callbacks > for SD/MMC device present on Actions OWL S700 SoCs. > > Signed-off-by: Amit Singh Tomar <amittomer25(a)gmail.com> > --- > drivers/clk/owl/clk_owl.c | 66 +++++++++++++++++++++++++++++++++++++++++++++++ > drivers/clk/owl/clk_owl.h | 2 ++ > 2 files changed, 68 insertions(+) > > diff --git a/drivers/clk/owl/clk_owl.c b/drivers/clk/owl/clk_owl.c > index c9bc5c2..49a492c 100644 > --- a/drivers/clk/owl/clk_owl.c > +++ b/drivers/clk/owl/clk_owl.c > @@ -92,6 +92,9 @@ int owl_clk_enable(struct clk *clk) > setbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_ETH); > setbits_le32(priv->base + CMU_ETHERNETPLL, 5); > break; > + case CLK_SD0: > + setbits_le32(priv->base + CMU_DEVCLKEN0, CMU_DEVCLKEN0_SD0); > + break; > default: > return -EINVAL; > } > @@ -121,6 +124,9 @@ int owl_clk_disable(struct clk *clk) > case CLK_ETHERNET: > clrbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_ETH); > break; > + case CLK_SD0: > + clrbits_le32(priv->base + CMU_DEVCLKEN0, CMU_DEVCLKEN0_SD0); > + break; > default: > return -EINVAL; > } > @@ -128,12 +134,69 @@ int owl_clk_disable(struct clk *clk) > return 0; > } > > +static ulong owl_get_sd_clk_rate(struct owl_clk_priv *priv, int sd_index) > +{ > + ulong parent_rate; > + uint div = 1; > + > + /* Clock output of DEV_PLL > + * Range: 48M ~ 756M > + * Frequency= DEVPLLCLK * 6 > + */ > + parent_rate = readl(priv->base + CMU_DEVPLL) & 0x7f; According to the datasheet the clock source could also be NAND_PLL, depending on bit 9. Both PLLs use the same rate calculation, so it's just matter of the PLL address offset to use for covering both. > + parent_rate *= 6000000; > + > + div += readl(priv->base + (CMU_SD0CLK + sd_index*0x4)) & 0x1f; > + > + return (parent_rate / div); > +} > + > +static ulong owl_set_sd_clk_rate(struct owl_clk_priv *priv, ulong rate, > + int sd_index) > +{ > + ulong parent_rate; > + uint div = 1, val; Unneeded initialisation, you overwrite this below. > + > + /* Clock output of DEV_PLL > + * Range: 48M ~ 756M > + * Frequency= DEVPLLCLK * 6 > + */ > + parent_rate = readl(priv->base + CMU_DEVPLL) & 0x7f; > + parent_rate *= 6000000; > + > + rate *= 2; Where does this come from? > + div = (parent_rate / rate) - 1; Please check rate being not zero before you dividing by it. And I would keep the real divider value for now, so drop the -1 here. > + > + if (div >= 128) > + div |= 0x100; This does not seem right. You would need to divide the value by 128, once you decided to use the "divide-by-128" bit (which is bit 8). What about moving this below, after you know the register value? Then you can divide by 128 and set bit 8. > + > + val = readl(priv->base + (CMU_SD0CLK + sd_index*0x4)); > + /* Bits 4..0 is used to program div value */ > + val &= ~0x1f; > + val |= div; Please mask div before applying. > + /* As per Manuals Bits 31..10 are reserved but Bits 11 and > + * 10 needed to be set for proper operation > + */ > + val |= 0xc00; Where does this come from? I don't see the Linux driver doing that? > + /* Bit 9 and 8 must be cleared */ Bit 9 is the parent clock selection, which you hard code to DEV_CLK. Bit 8 is the divide-by-128 bit. Please split those two up and explain it in a comment, maybe. Cheers, Andre > + if (div < 128) > + val &= ~0x300; > + else > + val &= ~0x200; > + writel(val, priv->base + (CMU_SD0CLK + sd_index*0x4)); > + > + return owl_get_sd_clk_rate(priv, 0); > +} > + > static ulong owl_clk_get_rate(struct clk *clk) > { > struct owl_clk_priv *priv = dev_get_priv(clk->dev); > ulong rate; > > switch (clk->id) { > + case CLK_SD0: > + rate = owl_get_sd_clk_rate(priv, 0); > + break; > default: > return -ENOENT; > } > @@ -147,6 +210,9 @@ static ulong owl_clk_set_rate(struct clk *clk, ulong rate) > ulong new_rate; > > switch (clk->id) { > + case CLK_SD0: > + new_rate = owl_set_sd_clk_rate(priv, rate, 0); > + break; > default: > return -ENOENT; > } > diff --git a/drivers/clk/owl/clk_owl.h b/drivers/clk/owl/clk_owl.h > index a01f81a..ee5eba4 100644 > --- a/drivers/clk/owl/clk_owl.h > +++ b/drivers/clk/owl/clk_owl.h > @@ -62,4 +62,6 @@ struct owl_clk_priv { > #define CMU_DEVCLKEN1_UART5 BIT(21) > #define CMU_DEVCLKEN1_UART3 BIT(11) > > +#define CMU_DEVCLKEN0_SD0 BIT(22) > + > #endif >

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Re: [PATCH 1/6] clk: actions: Introduce dummy get/set_rate callbacks
by André Przywara 14 Dec '20

14 Dec '20

On 13/12/2020 09:43, Amit Singh Tomar wrote: > This commit introduces get/set_rate callbacks, these are dummy at > the moment, and can be used to get/set clock for various devices > based on the clk id. > > Signed-off-by: Amit Singh Tomar <amittomer25(a)gmail.com> > --- > drivers/clk/owl/clk_owl.c | 28 ++++++++++++++++++++++++++++ > 1 file changed, 28 insertions(+) > > diff --git a/drivers/clk/owl/clk_owl.c b/drivers/clk/owl/clk_owl.c > index 1999c87..c9bc5c2 100644 > --- a/drivers/clk/owl/clk_owl.c > +++ b/drivers/clk/owl/clk_owl.c > @@ -128,6 +128,32 @@ int owl_clk_disable(struct clk *clk) > return 0; > } > > +static ulong owl_clk_get_rate(struct clk *clk) > +{ > + struct owl_clk_priv *priv = dev_get_priv(clk->dev); This is a bit premature and leads to compilation warnings. > + ulong rate; > + > + switch (clk->id) { > + default: > + return -ENOENT; > + } > + > + return rate; > +} > + > +static ulong owl_clk_set_rate(struct clk *clk, ulong rate) > +{ > + struct owl_clk_priv *priv = dev_get_priv(clk->dev); Same here. Cheers, Andre > + ulong new_rate; > + > + switch (clk->id) { > + default: > + return -ENOENT; > + } > + > + return new_rate; > +} > + > static int owl_clk_probe(struct udevice *dev) > { > struct owl_clk_priv *priv = dev_get_priv(dev); > @@ -145,6 +171,8 @@ static int owl_clk_probe(struct udevice *dev) > static const struct clk_ops owl_clk_ops = { > .enable = owl_clk_enable, > .disable = owl_clk_disable, > + .get_rate = owl_clk_get_rate, > + .set_rate = owl_clk_set_rate, > }; > > static const struct udevice_id owl_clk_ids[] = { >

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Issue with mkenvimage loading environ variables
by Ivan Castell 14 Dec '20

14 Dec '20

Hello all. Having strange issues when using mkenvimage tool. I have generated uEnv.txt with three variables defined: var1, var2 and var3. And I am trying to load it into U-boot. I have done two different tests: Test1 (null-terminated strings) OUT=uEnv.txt echo -ne "var1=1\0" > $OUT echo -ne "var2=1\0" >> $OUT echo -ne "var3=1\0" >> $OUT echo -ne "\0" >> $OUT mkenvimage -s 8000 -o uEnv_blob uEnv.txt => tftp 0x87000000 uEnv_blob Using FEC0 device TFTP from server 192.168.1.110; our IP address is 192.168.1.134 Filename 'uEnv_blob'. Load address: 0x87000000 Loading: # 1.1 MiB/s done Bytes transferred = 8000 (1f40 hex) => env import -b 0x87000000 8000 => printenv var2=1 var3=1 �ue�var1=1 Test2 (\n terminated strings) OUT=uEnv.txt echo "var1=1" > $OUT echo "var2=1" >> $OUT echo "var3=1" >> $OUT echo "" >> $OUT mkenvimage -s 8000 -o uEnv_blob uEnv.txt => tftp 0x87000000 uEnv_blob Using FEC0 device TFTP from server 192.168.1.110; our IP address is 192.168.1.134 Filename 'uEnv_blob'. Load address: 0x87000000 Loading: # 976.6 KiB/s done Bytes transferred = 8000 (1f40 hex) => env import -b 0x87000000 8000 => print Uل5var1=1 var2=1 var3=1 As you can see, in both cases, variable var1 is not loaded as expected. This is my current u-boot version: => version U-Boot 2017.03-mx6ul+g434eba6 (Dec 06 2017 - 13:31:34 +0200) arm-fslc-linux-gnueabi-gcc (GCC) 7.2.0 GNU ld (GNU Binutils) 2.29.0.20170912 And this is u-boot-tools package installed on Ubuntu 20.04 $ dpkg -l|grep boot-tools ii u-boot-tools 2019.07+dfsg-1ubuntu6 amd64 companion tools for Das U-Boot bootloader I am not sure if some step to clean the memory area where the uEnv_blob is loaded is missing before the tftp tranfer command. Or if this is simply a bug. Please explain what are the exact steps to follow in order to get this working. Thanks in advance!

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