December 2020 - U-Boot

[PATCH v2] efi_loader: Extra checks while opening an OPTEE session
by Ilias Apalodimas 23 Dec '20

23 Dec '20

When opening an OP-TEE session we need to check the internal return value of OP-TEE call arguments as well the return code of the function itself. The code was also ignoring to close the OP-TEE session in case the shared memory registration failed. Fixes: f042e47e8fb43 ("efi_loader: Implement EFI variable handling via OP-TEE") Signed-off-by: Ilias Apalodimas <ilias.apalodimas(a)linaro.org> --- changes since v1: - add a goto tag and use it on fails lib/efi_loader/efi_variable_tee.c | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/lib/efi_loader/efi_variable_tee.c b/lib/efi_loader/efi_variable_tee.c index be6f3dfad469..b8808fdecad3 100644 --- a/lib/efi_loader/efi_variable_tee.c +++ b/lib/efi_loader/efi_variable_tee.c @@ -36,20 +36,29 @@ static int get_connection(struct mm_connection *conn) static const struct tee_optee_ta_uuid uuid = PTA_STMM_UUID; struct udevice *tee = NULL; struct tee_open_session_arg arg; - int rc; + int rc = -ENODEV; tee = tee_find_device(tee, NULL, NULL, NULL); if (!tee) - return -ENODEV; + goto out; memset(&arg, 0, sizeof(arg)); tee_optee_ta_uuid_to_octets(arg.uuid, &uuid); rc = tee_open_session(tee, &arg, 0, NULL); - if (!rc) { - conn->tee = tee; - conn->session = arg.session; + if (rc) + goto out; + + /* Check the internal OP-TEE result */ + if (arg.ret != TEE_SUCCESS) { + rc = -EIO; + goto out; } + conn->tee = tee; + conn->session = arg.session; + + return 0; +out: return rc; } @@ -88,6 +97,7 @@ static efi_status_t optee_mm_communicate(void *comm_buf, ulong dsize) if (tee_shm_register(conn.tee, comm_buf, buf_size, 0, &shm)) { log_err("Unable to register shared memory\n"); + tee_close_session(conn.tee, conn.session); return EFI_UNSUPPORTED; } -- 2.30.0.rc1

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[PATCH] efi_loader: Extra checks while opening an OPTEE session
by Ilias Apalodimas 23 Dec '20

23 Dec '20

When opening an OP-TEE session we need to check the internal return value of OP-TEE call arguments as well the return code of the function itself. The code was also ignoring to close the OP-TEE session in case the shared memory registration failed. Fixes: f042e47e8fb43 ("efi_loader: Implement EFI variable handling via OP-TEE") Signed-off-by: Ilias Apalodimas <ilias.apalodimas(a)linaro.org> --- lib/efi_loader/efi_variable_tee.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/lib/efi_loader/efi_variable_tee.c b/lib/efi_loader/efi_variable_tee.c index be6f3dfad469..717d0b45e7cd 100644 --- a/lib/efi_loader/efi_variable_tee.c +++ b/lib/efi_loader/efi_variable_tee.c @@ -45,10 +45,11 @@ static int get_connection(struct mm_connection *conn) memset(&arg, 0, sizeof(arg)); tee_optee_ta_uuid_to_octets(arg.uuid, &uuid); rc = tee_open_session(tee, &arg, 0, NULL); - if (!rc) { - conn->tee = tee; - conn->session = arg.session; - } + if (rc || arg.ret != TEE_SUCCESS) + return rc == 0 ? -EIO : rc; + + conn->tee = tee; + conn->session = arg.session; return rc; } @@ -88,6 +89,7 @@ static efi_status_t optee_mm_communicate(void *comm_buf, ulong dsize) if (tee_shm_register(conn.tee, comm_buf, buf_size, 0, &shm)) { log_err("Unable to register shared memory\n"); + tee_close_session(conn.tee, conn.session); return EFI_UNSUPPORTED; } -- 2.30.0.rc1

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[PATCH 0/2] Add SIMATIC IOT2050 board support
by Jan Kiszka 23 Dec '20

23 Dec '20

This is the baseline support for the SIMATIC IOT2050 devices. Allows to boot mainline 5.10 kernels, but not the original BSP-derived kernel we currently ship as reference. This is due to the TI sysfw ABI breakages between 2.x and 3.x. We will soon provide a transitional kernel that allows booting both firmware ABIs - as long as full upstream kernel support is work in progress. Note that this baseline support lacks Ethernet drivers. We are working closely with TI to ensure that the to-be-upstreamed icssg-prueth driver will work both with new SR2.0 AM65x silicon as well as with SR1.0 which is used in the currently shipped IOT2050 devices. Related but not strictly needed for baseline support is [1], i.e. embedding of the watchdog firmware that is required on the AM65x. I will soon pick up that discussion again. A staging tree for complete IOT2050 support can be found at [2]. Full image integration is available via [3]. Jan [1] https://patchwork.ozlabs.org/project/uboot/patch/a42ab2dde9a588a8efc186474b… [2] https://github.com/siemens/u-boot/commits/jan/iot2050 [3] https://github.com/siemens/meta-iot2050 Jan Kiszka (2): arm: dts: Add IOT2050 device tree files board: siemens: Add support for SIMATIC IOT2050 devices arch/arm/dts/Makefile | 7 +- arch/arm/dts/iot2050-advanced.dts | 62 +++++ arch/arm/dts/iot2050-basic.dts | 61 +++++ arch/arm/dts/iot2050-boot-image.dtsi | 105 +++++++++ arch/arm/dts/iot2050-common.dtsi | 341 +++++++++++++++++++++++++++ arch/arm/dts/iot2050-spl.dts | 16 ++ arch/arm/mach-k3/Kconfig | 1 + board/siemens/iot2050/Kconfig | 28 +++ board/siemens/iot2050/MAINTAINERS | 8 + board/siemens/iot2050/Makefile | 10 + board/siemens/iot2050/README | 65 +++++ board/siemens/iot2050/board.c | 229 ++++++++++++++++++ board/siemens/iot2050/config.mk | 8 + configs/iot2050_defconfig | 136 +++++++++++ include/configs/iot2050.h | 60 +++++ 15 files changed, 1136 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/iot2050-advanced.dts create mode 100644 arch/arm/dts/iot2050-basic.dts create mode 100644 arch/arm/dts/iot2050-boot-image.dtsi create mode 100644 arch/arm/dts/iot2050-common.dtsi create mode 100644 arch/arm/dts/iot2050-spl.dts create mode 100644 board/siemens/iot2050/Kconfig create mode 100644 board/siemens/iot2050/MAINTAINERS create mode 100644 board/siemens/iot2050/Makefile create mode 100644 board/siemens/iot2050/README create mode 100644 board/siemens/iot2050/board.c create mode 100644 board/siemens/iot2050/config.mk create mode 100644 configs/iot2050_defconfig create mode 100644 include/configs/iot2050.h -- 2.26.2

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[PATCH v6 00/28] Add DM support for omap PWM backlight
by Dario Binacchi 23 Dec '20

23 Dec '20

The series was born from the need to manage the PWM backlight of the display connected to my beaglebone board. To hit the target, I had to develop drivers for PWM management which in turn relied on drivers for managing timers and clocks, all developed according to the driver model. My intention was to use the SoC-specific API only at strictly necessary points in the code. My previous patches for migrating the AM335x display driver to the driver model had required the implementation of additional functions outside the concerns of the driver, (settings for dividing the pixel clock rate, configuring the display DPLL rate, ....) not being able to use the API of the related clock drivers. This series shouldn't have repeated the same kind of mistake. Furthermore, I also wanted to fix that kind of forced choice. Almost everything should have been accessible via the driver model API. In the series there are also some patches that could be submitted separately, but which I have however inserted to avoid applying future patches to incorporate them. With this last consideration, I hope I have convincingly justified the large number of patches in the series. The patch enabling address translation into a CPU physical address from device-tree even in case of crossing levels with #size-cells = <0>, is crucial for the series. The previous implementation was unable to perform the address translation required by the am33xx device tree. I tried to apply in a conservative way as few changes as possible and to verify the execution of all the tests already developed, as well as the new ones I added for the new feature. The patch series can be cleanly applied to the HEAD of the master which at the time of release points to 12e396303c commit. Changes in v6: - Remove the 'am3-prcm' driver. - Add the 'simple-bus' compatible string to the prcm_clocks node. - Remove the 'am3-scm' driver. - Add the 'simple-bus' compatible string to the scm_clocks node. Changes in v5: - Create drivers/clk/ti directory. - Move the clk-ti-mux.c file to drivers/clk/ti and rename it clk-mux.c - Move the clk-ti-am3-dpll.c file to drivers/clk/ti with the name clk-am3-dpll.c. - Move the clk-ti-am3-dpll-x2.c file to drivers/clk/ti with the name clk-am3-dpll-x2.c. - Move the clk-ti.c file to drivers/clk/ti with the name clk.c. - Move the clk-ti.h file to drivers/clk/ti with the name clk.h. - Move the clk-ti-divider.c file to drivers/clk/ti with the name clk-divider.c. - Move the clk-ti-gate.c file to drivers/clk/ti with the name clk-gate.c. - Move the clk-ti-ctrl.c file to drivers/clk/ti with the name clk-ctrl.c. Changes in v4: - Include device_compat.h header for dev_xxx macros. - Remove a blank line at end of file arch/arm/dts/am33xx-l4.dtsi. - Update clk_round_rate description. - Add Sean Anderson review. - Include device_compat.h header for dev_xxx macros. - Include device_compat.h header for dev_xxx macros. - Fix compilation errors on the dev parameter of the dev_xx macros. - Include device_compat.h header for dev_xxx macros. - Fix compilation errors on the dev parameter of the dev_xx macros. - Include device_compat.h header for dev_xxx macros. - Include device_compat.h header for dev_xxx macros. - Fix compilation errors on the dev parameter of the dev_xx macros. - Include device_compat.h header for dev_xxx macros. - Add Sphinx documentation for dm_flags. - Convert GD_DM_FLG_* to enum. - Include device_compat.h header in test/dm/test-fdt.c for dev_xxx macros. - Include device_compat.h header for dev_xxx macros. - Include device_compat.h header for dev_xxx macros. - Include device_compat.h header for dev_xxx macros. - Add Simon Glass review. - Include device_compat.h header for dev_xxx macros. Changes in v3: - Remove doc/device-tree-bindings/clock/clock-bindings.txt. - Remove doc/device-tree-bindings/clock/ti,mux.txt. - Add to commit message the references to linux kernel dt binding documentation. - Remove doc/device-tree-bindings/clock/ti,dpll.txt. - Add to commit message the references to linux kernel dt binding documentation. - Remove doc/device-tree-bindings/clock/ti,autoidle.txt. - Remove doc/device-tree-bindings/clock/ti,divider.txt. - Add to commit message the references to linux kernel dt binding documentation. - Remove doc/device-tree-bindings/clock/gpio-gate-clock.txt. - Remove doc/device-tree-bindings/clock/ti,clockdomain.txt. - Remove doc/device-tree-bindings/clock/ti,gate.txt. - Add to commit message the references to linux kernel dt binding documentation. - Fix access to registers listed by device tree following resync of am33xx-clock.dtsi with Linux 5.9-rc7. - Remove doc/device-tree-bindings/clock/ti,clkctrl.txt. - Add to commit message the references to linux kernel dt binding documentation. - doc/device-tree-bindings/arm/omap,prcm.txt. - Add to commit message the references to linux kernel dt binding documentation. - Add to commit message the references to linux kernel dt binding documentation. - Comment dm_flags field in the global_data structure. - Remove doc/device-tree-bindings/arm/omap,ctrl.txt. - Remove doc/device-tree-bindings/pinctrl/pinctrl-single.txt. - Add to commit message the references to linux kernel dt binding documentation. - Adds PWM_TI_EHRPWM dependency on ARCH_OMAP2PLUS in Kconfig. - Add error message in case of invalid address. - Remove doc/device-tree-bindings/pwm/ti,ehrpwm.txt. - Add to commit message the references to linux kernel dt binding documentation. - Move Kconfig symbol from drivers/pwm to drivers/bus. - Remove the domain clock reference from the pwmss nodes of the device tree in am33xx.dtsi. The resync of am33xx.dtsi with Linux 5.9-rc7 already contains such references. - Remove domain clock enabling/disabling. Enabling the domain clock is performed by the sysc interconnect target module driver during the pwm device probing. - Remove doc/device-tree-bindings/pwm/ti,pwmss.txt. - Add to commit message the references to linux kernel dt binding documentation. - Update the DTS lcdc node of the am335x boards because of the am33xx.dtsi resynced with Linux 5.9-rc7. - Remove clock domain enabling/disabling. - Update the commit message. - Add clk.h header. - Fix an error code returned by the probe function. Changes in v2: - Add the clk_ prefix to the divider functions. - Add kernel-doc comments to the exported functions. - Merged to patch [09/31] clk: ti: refactor mux and divider clock drivers. - Remove the 'ti_am3_prcm_clocks' driver. Handle 'prcm_clocks' node in the 'ti_am3_prcm' driver. - Update the commit message. - Fix a missing line in the commit message. - Add dm_flags to global_data structure and GD_DM_FLG_SIZE_CELLS_0 macro to test without recompiling. - Update the OF_CHECK_COUNTS macro in order to have just one #define by bringing the GD_DM_FLG_SIZE_CELLS_0 into the expression. - Lower-case the 0xC019 hex number. - Remove the 'ti_am3_scm_clocks' driver. Handle 'scm_clocks' node in the 'ti_am3_scm' driver. - Update the commit message. Dario Binacchi (28): clk: export generic routines dt-bindings: bus: ti-sysc: resync with Linux 5.9-rc7 bus: ti: add minimal sysc interconnect target driver arm: dts: sync am33xx with Linux 5.9-rc7 clk: add clk_round_rate() clk: ti: add mux clock driver arm: ti: am33xx: add DPLL_EN_FAST_RELOCK_BYPASS macro clk: ti: am33xx: add DPLL clock drivers clk: ti: add divider clock driver clk: ti: add gate clock driver arm: dts: am335x: include am33xx-u-boot.dtsi ti: am33xx: fix do_enable_clocks() to accept NULL parameters clk: ti: add support for clkctrl clocks clk: ti: omap4: add clock manager driver arm: dts: am335x: enable prcm_clocks auto binding clk: move clk-ti-sci driver to 'ti' directory fdt: translate address if #size-cells = <0> omap: timer: fix the rate setting arm: dts: am335x: enable scm_clocks auto binding pwm: ti: am33xx: add enhanced pwm driver bus: ti: am33xx: add pwm subsystem driver dm: core: add a function to decode display timings video: omap: add panel driver video: omap: drop domain clock enabling by SOC api video: omap: set LCD clock rate through DM API video: omap: split the legacy code from the DM code video: omap: move drivers to 'ti' directory board: ti: am335x-ice: get CDCE913 clock device arch/arm/Kconfig | 1 + arch/arm/dts/am335x-brppt1-mmc.dts | 17 +- arch/arm/dts/am335x-brppt1-nand.dts | 17 +- arch/arm/dts/am335x-brppt1-spi.dts | 17 +- arch/arm/dts/am335x-brsmarc1.dts | 20 +- arch/arm/dts/am335x-brxre1.dts | 21 +- arch/arm/dts/am335x-chiliboard-u-boot.dtsi | 2 + arch/arm/dts/am335x-draco.dtsi | 11 +- arch/arm/dts/am335x-evm-u-boot.dtsi | 17 +- arch/arm/dts/am335x-evm.dts | 2 +- arch/arm/dts/am335x-evmsk-u-boot.dtsi | 16 +- arch/arm/dts/am335x-evmsk.dts | 2 +- arch/arm/dts/am335x-guardian-u-boot.dtsi | 25 +- arch/arm/dts/am335x-icev2-u-boot.dtsi | 3 + arch/arm/dts/am335x-pdu001-u-boot.dtsi | 20 +- arch/arm/dts/am335x-pxm2.dtsi | 2 +- arch/arm/dts/am335x-pxm50-u-boot.dtsi | 16 +- arch/arm/dts/am335x-regor-rdk-u-boot.dtsi | 2 + arch/arm/dts/am335x-rut-u-boot.dtsi | 16 +- arch/arm/dts/am335x-rut.dts | 2 +- arch/arm/dts/am335x-shc-u-boot.dtsi | 2 + arch/arm/dts/am335x-shc.dts | 2 +- arch/arm/dts/am335x-wega-rdk-u-boot.dtsi | 2 + arch/arm/dts/am33xx-clocks.dtsi | 106 +- arch/arm/dts/am33xx-l4.dtsi | 1962 ++++++++++++++++++++ arch/arm/dts/am33xx-u-boot.dtsi | 8 + arch/arm/dts/am33xx.dtsi | 721 +++---- arch/arm/dts/da850-evm-u-boot.dtsi | 18 +- arch/arm/include/asm/arch-am33xx/clock.h | 1 + arch/arm/mach-omap2/am33xx/clock.c | 10 +- arch/arm/mach-omap2/am33xx/clock_am33xx.c | 2 +- arch/sandbox/dts/test.dts | 67 + arch/sandbox/include/asm/clk.h | 9 + board/ti/am335x/board.c | 2 +- board/ti/am43xx/board.c | 2 +- common/fdt_support.c | 6 +- drivers/bus/Kconfig | 13 + drivers/bus/Makefile | 2 + drivers/bus/ti-pwmss.c | 21 + drivers/bus/ti-sysc.c | 166 ++ drivers/clk/Kconfig | 9 +- drivers/clk/Makefile | 2 +- drivers/clk/clk-divider.c | 24 +- drivers/clk/clk-uclass.c | 15 + drivers/clk/clk_sandbox.c | 17 + drivers/clk/clk_sandbox_test.c | 10 + drivers/clk/ti/Kconfig | 43 + drivers/clk/ti/Makefile | 13 + drivers/clk/ti/clk-am3-dpll-x2.c | 79 + drivers/clk/ti/clk-am3-dpll.c | 268 +++ drivers/clk/ti/clk-ctrl.c | 154 ++ drivers/clk/ti/clk-divider.c | 381 ++++ drivers/clk/ti/clk-gate.c | 93 + drivers/clk/ti/clk-mux.c | 253 +++ drivers/clk/{clk-ti-sci.c => ti/clk-sci.c} | 0 drivers/clk/ti/clk.c | 34 + drivers/clk/ti/clk.h | 13 + drivers/clk/ti/omap4-cm.c | 22 + drivers/core/Kconfig | 12 + drivers/core/fdtaddr.c | 2 +- drivers/core/of_addr.c | 14 +- drivers/core/ofnode.c | 7 +- drivers/core/read.c | 6 + drivers/core/root.c | 3 + drivers/pwm/Kconfig | 7 + drivers/pwm/Makefile | 1 + drivers/pwm/pwm-ti-ehrpwm.c | 468 +++++ drivers/timer/omap-timer.c | 6 +- drivers/video/Kconfig | 5 +- drivers/video/Makefile | 2 +- drivers/video/ti/Kconfig | 8 + drivers/video/ti/Makefile | 10 + drivers/video/{ => ti}/am335x-fb.c | 342 +--- drivers/video/{ => ti}/am335x-fb.h | 4 - drivers/video/ti/tilcdc-panel.c | 172 ++ drivers/video/ti/tilcdc-panel.h | 14 + drivers/video/ti/tilcdc.c | 425 +++++ drivers/video/ti/tilcdc.h | 38 + include/asm-generic/global_data.h | 18 + include/clk-uclass.h | 8 + include/clk.h | 28 + include/dm/read.h | 24 + include/dt-bindings/bus/ti-sysc.h | 6 + include/linux/clk-provider.h | 57 + test/dm/clk.c | 22 + test/dm/test-fdt.c | 149 +- 86 files changed, 5670 insertions(+), 969 deletions(-) create mode 100644 arch/arm/dts/am33xx-l4.dtsi create mode 100644 drivers/bus/ti-pwmss.c create mode 100644 drivers/bus/ti-sysc.c create mode 100644 drivers/clk/ti/Kconfig create mode 100644 drivers/clk/ti/Makefile create mode 100644 drivers/clk/ti/clk-am3-dpll-x2.c create mode 100644 drivers/clk/ti/clk-am3-dpll.c create mode 100644 drivers/clk/ti/clk-ctrl.c create mode 100644 drivers/clk/ti/clk-divider.c create mode 100644 drivers/clk/ti/clk-gate.c create mode 100644 drivers/clk/ti/clk-mux.c rename drivers/clk/{clk-ti-sci.c => ti/clk-sci.c} (100%) create mode 100644 drivers/clk/ti/clk.c create mode 100644 drivers/clk/ti/clk.h create mode 100644 drivers/clk/ti/omap4-cm.c create mode 100644 drivers/pwm/pwm-ti-ehrpwm.c create mode 100644 drivers/video/ti/Kconfig create mode 100644 drivers/video/ti/Makefile rename drivers/video/{ => ti}/am335x-fb.c (54%) rename drivers/video/{ => ti}/am335x-fb.h (97%) create mode 100644 drivers/video/ti/tilcdc-panel.c create mode 100644 drivers/video/ti/tilcdc-panel.h create mode 100644 drivers/video/ti/tilcdc.c create mode 100644 drivers/video/ti/tilcdc.h -- 2.17.1

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[RESEND PATCH 1/2] usb: xhci-mtk: support option to disable ports
by Chunfeng Yun 23 Dec '20

23 Dec '20

Add support to disable specific ports, it's useful for some scenarios: 1. usb3 PHY is shared whith PCIe or SATA, the corresponding usb3 port can be disabled; 2. some usb2 or usb3 ports are not used on special platforms, they should be disabled to save power. Signed-off-by: Chunfeng Yun <chunfeng.yun(a)mediatek.com> --- drivers/usb/host/xhci-mtk.c | 23 ++++++++++++++++++++--- 1 file changed, 20 insertions(+), 3 deletions(-) diff --git a/drivers/usb/host/xhci-mtk.c b/drivers/usb/host/xhci-mtk.c index f62e232d21..ebda80f2af 100644 --- a/drivers/usb/host/xhci-mtk.c +++ b/drivers/usb/host/xhci-mtk.c @@ -61,10 +61,13 @@ struct mtk_xhci { struct phy_bulk phys; int num_u2ports; int num_u3ports; + u32 u3p_dis_msk; + u32 u2p_dis_msk; }; static int xhci_mtk_host_enable(struct mtk_xhci *mtk) { + int u3_ports_disabed = 0; u32 value; u32 check_val; int ret; @@ -73,15 +76,23 @@ static int xhci_mtk_host_enable(struct mtk_xhci *mtk) /* power on host ip */ clrbits_le32(mtk->ippc + IPPC_IP_PW_CTRL1, CTRL1_IP_HOST_PDN); - /* power on and enable all u3 ports */ + /* power on and enable u3 ports except skipped ones */ for (i = 0; i < mtk->num_u3ports; i++) { + if (BIT(i) & mtk->u3p_dis_msk) { + u3_ports_disabed++; + continue; + } + clrsetbits_le32(mtk->ippc + IPPC_U3_CTRL(i), CTRL_U3_PORT_PDN | CTRL_U3_PORT_DIS, CTRL_U3_PORT_HOST_SEL); } - /* power on and enable all u2 ports */ + /* power on and enable u2 ports except skipped ones */ for (i = 0; i < mtk->num_u2ports; i++) { + if (BIT(i) & mtk->u2p_dis_msk) + continue; + clrsetbits_le32(mtk->ippc + IPPC_U2_CTRL(i), CTRL_U2_PORT_PDN | CTRL_U2_PORT_DIS, CTRL_U2_PORT_HOST_SEL); @@ -94,7 +105,7 @@ static int xhci_mtk_host_enable(struct mtk_xhci *mtk) check_val = STS1_SYSPLL_STABLE | STS1_REF_RST | STS1_SYS125_RST | STS1_XHCI_RST; - if (mtk->num_u3ports) + if (mtk->num_u3ports > u3_ports_disabed) check_val |= STS1_U3_MAC_RST; ret = readl_poll_timeout(mtk->ippc + IPPC_IP_PW_STS1, value, @@ -176,6 +187,12 @@ static int xhci_mtk_ofdata_get(struct mtk_xhci *mtk) if (ret) debug("can't get vbus regulator %d!\n", ret); + /* optional properties to disable ports, ignore the error */ + dev_read_u32(dev, "mediatek,u3p-dis-msk", &mtk->u3p_dis_msk); + dev_read_u32(dev, "mediatek,u2p-dis-msk", &mtk->u2p_dis_msk); + dev_info(dev, "ports disabled mask: u3p-0x%x, u2p-0x%x\n", + mtk->u3p_dis_msk, mtk->u2p_dis_msk); + return 0; } -- 2.18.0

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[PATCH] arm:pdu001: Use pseudo partition UUID for LINUX kernel boot paramter root
by Felix Brack 23 Dec '20

23 Dec '20

As more and more LINUX drivers are modified to use asynchronous probing instead of synchronous probing, relying on device names being equal in U-Boot and LINUX is not possible anymore. This is also true for block device names like mmc0, mmc1 ect. With LINUX kernel commit a1a4891 the probing type for the sdhci-omap driver has been set to asynchronous mode too (probe_type is now PROBE_PREFER_ASYNCHRONOUS). In the case of the PDU001 board this results in the devices mmc0 and mmc1 being swapped between U-Boot and LINUX. Device mmc0 in U-Boot becomes mmc1 in LINUX an vice versa. Hence using device name identifiers with LINUX kernel parameter root does not work anymore. This patch changes the LINUX kernel boot parameter root to use the pseudo (since we use MBR not GPT) partition UUID to locate the partition hosting the root file system. Signed-off-by: Felix Brack <fb(a)ltec.ch> --- include/configs/pdu001.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/configs/pdu001.h b/include/configs/pdu001.h index e4b14c5ecd..53342ce193 100644 --- a/include/configs/pdu001.h +++ b/include/configs/pdu001.h @@ -37,9 +37,10 @@ #define CONFIG_BOOTCOMMAND \ "run eval_boot_device;" \ + "part uuid mmc ${mmc_boot}:${root_fs_partition} root_fs_partuuid;" \ "setenv bootargs console=${console} " \ "vt.global_cursor_default=0 " \ - "root=/dev/mmcblk${mmc_boot}p${root_fs_partition} " \ + "root=PARTUUID=${root_fs_partuuid} " \ "rootfstype=ext4 " \ "rootwait " \ "rootdelay=1;" \ -- 2.25.1

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[PATCH] arm: dts: k3-j721e: ddr: Update to 0.5.0 version of DDR config tool
by praneeth＠ti.com 23 Dec '20

23 Dec '20

From: Praneeth Bajjuri <praneeth(a)ti.com> Update the ddr settings to use the DDR reg config tool rev 0.5.0. This enables 4266MTs DDR configuration. Signed-off-by: Praneeth Bajjuri <praneeth(a)ti.com> Signed-off-by: Kevin Scholz <k-scholz(a)ti.com> --- ...33.dtsi => k3-j721e-ddr-evm-lp4-4266.dtsi} | 436 +++++++++--------- .../arm/dts/k3-j721e-r5-common-proc-board.dts | 2 +- 2 files changed, 219 insertions(+), 219 deletions(-) rename arch/arm/dts/{k3-j721e-ddr-evm-lp4-3733.dtsi => k3-j721e-ddr-evm-lp4-4266.dtsi} (90%) diff --git a/arch/arm/dts/k3-j721e-ddr-evm-lp4-3733.dtsi b/arch/arm/dts/k3-j721e-ddr-evm-lp4-4266.dtsi similarity index 90% rename from arch/arm/dts/k3-j721e-ddr-evm-lp4-3733.dtsi rename to arch/arm/dts/k3-j721e-ddr-evm-lp4-4266.dtsi index 5ac32a0ffa..ca05e06e93 100644 --- a/arch/arm/dts/k3-j721e-ddr-evm-lp4-3733.dtsi +++ b/arch/arm/dts/k3-j721e-ddr-evm-lp4-4266.dtsi @@ -1,13 +1,13 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ - * This file was generated by the AM752x_DRA82x_TDA4x_DDRSS_RegConfigTool, Revision: 0.2.0 - * This file was generated on 10/09/2019 + * This file was generated by the Jacinto7_DDRSS_RegConfigTool, Revision: 0.5.0 + * This file was generated on 09/25/2020 */ #define DDRSS_PLL_FHS_CNT 10 -#define DDRSS_PLL_FREQUENCY_1 933000000 -#define DDRSS_PLL_FREQUENCY_2 933000000 +#define DDRSS_PLL_FREQUENCY_1 1066500000 +#define DDRSS_PLL_FREQUENCY_2 1066500000 #define DDRSS_CTL_00_DATA 0x00000B00 #define DDRSS_CTL_01_DATA 0x00000000 @@ -20,14 +20,14 @@ #define DDRSS_CTL_08_DATA 0x000186A0 #define DDRSS_CTL_09_DATA 0x00000005 #define DDRSS_CTL_10_DATA 0x00000064 -#define DDRSS_CTL_11_DATA 0x0005B18F -#define DDRSS_CTL_12_DATA 0x0038EF90 +#define DDRSS_CTL_11_DATA 0x000681C8 +#define DDRSS_CTL_12_DATA 0x004111C9 #define DDRSS_CTL_13_DATA 0x00000005 -#define DDRSS_CTL_14_DATA 0x00000E94 -#define DDRSS_CTL_15_DATA 0x0005B18F -#define DDRSS_CTL_16_DATA 0x0038EF90 +#define DDRSS_CTL_14_DATA 0x000010A9 +#define DDRSS_CTL_15_DATA 0x000681C8 +#define DDRSS_CTL_16_DATA 0x004111C9 #define DDRSS_CTL_17_DATA 0x00000005 -#define DDRSS_CTL_18_DATA 0x00000E94 +#define DDRSS_CTL_18_DATA 0x000010A9 #define DDRSS_CTL_19_DATA 0x01010000 #define DDRSS_CTL_20_DATA 0x02011001 #define DDRSS_CTL_21_DATA 0x02010000 @@ -37,66 +37,66 @@ #define DDRSS_CTL_25_DATA 0x00000000 #define DDRSS_CTL_26_DATA 0x00000000 #define DDRSS_CTL_27_DATA 0x02020200 -#define DDRSS_CTL_28_DATA 0x00004B4B +#define DDRSS_CTL_28_DATA 0x00005656 #define DDRSS_CTL_29_DATA 0x00100000 #define DDRSS_CTL_30_DATA 0x00000000 #define DDRSS_CTL_31_DATA 0x00000000 #define DDRSS_CTL_32_DATA 0x00000000 #define DDRSS_CTL_33_DATA 0x00000000 #define DDRSS_CTL_34_DATA 0x040C0000 -#define DDRSS_CTL_35_DATA 0x10401040 +#define DDRSS_CTL_35_DATA 0x12481248 #define DDRSS_CTL_36_DATA 0x00050804 #define DDRSS_CTL_37_DATA 0x09040008 -#define DDRSS_CTL_38_DATA 0x12000204 -#define DDRSS_CTL_39_DATA 0x1854007A -#define DDRSS_CTL_40_DATA 0x12003A26 -#define DDRSS_CTL_41_DATA 0x1854007A -#define DDRSS_CTL_42_DATA 0x20003A26 +#define DDRSS_CTL_38_DATA 0x15000204 +#define DDRSS_CTL_39_DATA 0x1B60008B +#define DDRSS_CTL_40_DATA 0x1500422B +#define DDRSS_CTL_41_DATA 0x1B60008B +#define DDRSS_CTL_42_DATA 0x2000422B #define DDRSS_CTL_43_DATA 0x000A0A09 #define DDRSS_CTL_44_DATA 0x040006DB -#define DDRSS_CTL_45_DATA 0x1B130F04 -#define DDRSS_CTL_46_DATA 0x0E00FFCD -#define DDRSS_CTL_47_DATA 0x1B130F0E -#define DDRSS_CTL_48_DATA 0x0E00FFCD -#define DDRSS_CTL_49_DATA 0x0203040E -#define DDRSS_CTL_50_DATA 0x26040500 -#define DDRSS_CTL_51_DATA 0x08282628 +#define DDRSS_CTL_45_DATA 0x1E161104 +#define DDRSS_CTL_46_DATA 0x10012458 +#define DDRSS_CTL_47_DATA 0x1E161110 +#define DDRSS_CTL_48_DATA 0x10012458 +#define DDRSS_CTL_49_DATA 0x02030410 +#define DDRSS_CTL_50_DATA 0x2C040500 +#define DDRSS_CTL_51_DATA 0x082D2C2D #define DDRSS_CTL_52_DATA 0x14000D0A -#define DDRSS_CTL_53_DATA 0x03010A0A -#define DDRSS_CTL_54_DATA 0x01010003 -#define DDRSS_CTL_55_DATA 0x044E4E08 -#define DDRSS_CTL_56_DATA 0x042B2B04 -#define DDRSS_CTL_57_DATA 0x00002B2B +#define DDRSS_CTL_53_DATA 0x04010A0A +#define DDRSS_CTL_54_DATA 0x01010004 +#define DDRSS_CTL_55_DATA 0x04585808 +#define DDRSS_CTL_56_DATA 0x04313104 +#define DDRSS_CTL_57_DATA 0x00003131 #define DDRSS_CTL_58_DATA 0x00010100 #define DDRSS_CTL_59_DATA 0x03010000 #define DDRSS_CTL_60_DATA 0x00000E08 #define DDRSS_CTL_61_DATA 0x000000BB -#define DDRSS_CTL_62_DATA 0x0000020B -#define DDRSS_CTL_63_DATA 0x00001C64 -#define DDRSS_CTL_64_DATA 0x0000020B -#define DDRSS_CTL_65_DATA 0x00001C64 +#define DDRSS_CTL_62_DATA 0x00000256 +#define DDRSS_CTL_63_DATA 0x00002073 +#define DDRSS_CTL_64_DATA 0x00000256 +#define DDRSS_CTL_65_DATA 0x00002073 #define DDRSS_CTL_66_DATA 0x00000005 #define DDRSS_CTL_67_DATA 0x00030000 -#define DDRSS_CTL_68_DATA 0x00830010 -#define DDRSS_CTL_69_DATA 0x00830386 -#define DDRSS_CTL_70_DATA 0x00400386 +#define DDRSS_CTL_68_DATA 0x00950010 +#define DDRSS_CTL_69_DATA 0x00950408 +#define DDRSS_CTL_70_DATA 0x00400408 #define DDRSS_CTL_71_DATA 0x00120103 -#define DDRSS_CTL_72_DATA 0x000E0005 -#define DDRSS_CTL_73_DATA 0x2908000E -#define DDRSS_CTL_74_DATA 0x05050129 +#define DDRSS_CTL_72_DATA 0x00100005 +#define DDRSS_CTL_73_DATA 0x2F080010 +#define DDRSS_CTL_74_DATA 0x0505012F #define DDRSS_CTL_75_DATA 0x0401030A -#define DDRSS_CTL_76_DATA 0x041B0E0A -#define DDRSS_CTL_77_DATA 0x0E0A0401 -#define DDRSS_CTL_78_DATA 0x0001041B +#define DDRSS_CTL_76_DATA 0x041E100B +#define DDRSS_CTL_77_DATA 0x100B0401 +#define DDRSS_CTL_78_DATA 0x0001041E #define DDRSS_CTL_79_DATA 0x000F000F -#define DDRSS_CTL_80_DATA 0x02190219 -#define DDRSS_CTL_81_DATA 0x02190219 +#define DDRSS_CTL_80_DATA 0x02660266 +#define DDRSS_CTL_81_DATA 0x02660266 #define DDRSS_CTL_82_DATA 0x03050505 #define DDRSS_CTL_83_DATA 0x03010303 -#define DDRSS_CTL_84_DATA 0x1C0A0E0A -#define DDRSS_CTL_85_DATA 0x04040E04 -#define DDRSS_CTL_86_DATA 0x1C0A0E0A -#define DDRSS_CTL_87_DATA 0x04040E04 +#define DDRSS_CTL_84_DATA 0x200B100B +#define DDRSS_CTL_85_DATA 0x04041004 +#define DDRSS_CTL_86_DATA 0x200B100B +#define DDRSS_CTL_87_DATA 0x04041004 #define DDRSS_CTL_88_DATA 0x03010000 #define DDRSS_CTL_89_DATA 0x00010000 #define DDRSS_CTL_90_DATA 0x00000000 @@ -118,20 +118,20 @@ #define DDRSS_CTL_106_DATA 0x00002EC0 #define DDRSS_CTL_107_DATA 0x00000000 #define DDRSS_CTL_108_DATA 0x0000051D -#define DDRSS_CTL_109_DATA 0x00071900 -#define DDRSS_CTL_110_DATA 0x00071900 -#define DDRSS_CTL_111_DATA 0x00071900 -#define DDRSS_CTL_112_DATA 0x00071900 -#define DDRSS_CTL_113_DATA 0x00071900 +#define DDRSS_CTL_109_DATA 0x00081CC0 +#define DDRSS_CTL_110_DATA 0x00081CC0 +#define DDRSS_CTL_111_DATA 0x00081CC0 +#define DDRSS_CTL_112_DATA 0x00081CC0 +#define DDRSS_CTL_113_DATA 0x00081CC0 #define DDRSS_CTL_114_DATA 0x00000000 -#define DDRSS_CTL_115_DATA 0x0000C6BC -#define DDRSS_CTL_116_DATA 0x00071900 -#define DDRSS_CTL_117_DATA 0x00071900 -#define DDRSS_CTL_118_DATA 0x00071900 -#define DDRSS_CTL_119_DATA 0x00071900 -#define DDRSS_CTL_120_DATA 0x00071900 +#define DDRSS_CTL_115_DATA 0x0000E325 +#define DDRSS_CTL_116_DATA 0x00081CC0 +#define DDRSS_CTL_117_DATA 0x00081CC0 +#define DDRSS_CTL_118_DATA 0x00081CC0 +#define DDRSS_CTL_119_DATA 0x00081CC0 +#define DDRSS_CTL_120_DATA 0x00081CC0 #define DDRSS_CTL_121_DATA 0x00000000 -#define DDRSS_CTL_122_DATA 0x0000C6BC +#define DDRSS_CTL_122_DATA 0x0000E325 #define DDRSS_CTL_123_DATA 0x00000000 #define DDRSS_CTL_124_DATA 0x00000000 #define DDRSS_CTL_125_DATA 0x00000000 @@ -140,8 +140,8 @@ #define DDRSS_CTL_128_DATA 0x00000000 #define DDRSS_CTL_129_DATA 0x00000000 #define DDRSS_CTL_130_DATA 0x00000000 -#define DDRSS_CTL_131_DATA 0x0A030500 -#define DDRSS_CTL_132_DATA 0x00040A04 +#define DDRSS_CTL_131_DATA 0x0B030500 +#define DDRSS_CTL_132_DATA 0x00040B04 #define DDRSS_CTL_133_DATA 0x0A090000 #define DDRSS_CTL_134_DATA 0x0A090701 #define DDRSS_CTL_135_DATA 0x0900000E @@ -176,23 +176,23 @@ #define DDRSS_CTL_164_DATA 0x000A0000 #define DDRSS_CTL_165_DATA 0x000D0005 #define DDRSS_CTL_166_DATA 0x000D0404 -#define DDRSS_CTL_167_DATA 0x00BB0176 -#define DDRSS_CTL_168_DATA 0x0E0E01D3 -#define DDRSS_CTL_169_DATA 0x017601D3 -#define DDRSS_CTL_170_DATA 0x01D300BB -#define DDRSS_CTL_171_DATA 0x01D30E0E +#define DDRSS_CTL_167_DATA 0x00D601AB +#define DDRSS_CTL_168_DATA 0x10100216 +#define DDRSS_CTL_169_DATA 0x01AB0216 +#define DDRSS_CTL_170_DATA 0x021600D6 +#define DDRSS_CTL_171_DATA 0x02161010 #define DDRSS_CTL_172_DATA 0x00000000 #define DDRSS_CTL_173_DATA 0x00000000 #define DDRSS_CTL_174_DATA 0x00000000 -#define DDRSS_CTL_175_DATA 0x36E40084 -#define DDRSS_CTL_176_DATA 0x330036E4 +#define DDRSS_CTL_175_DATA 0x3FF40084 +#define DDRSS_CTL_176_DATA 0x33003FF4 #define DDRSS_CTL_177_DATA 0x00003333 #define DDRSS_CTL_178_DATA 0x56000000 #define DDRSS_CTL_179_DATA 0x27270056 #define DDRSS_CTL_180_DATA 0x0F0F0000 #define DDRSS_CTL_181_DATA 0x00000000 #define DDRSS_CTL_182_DATA 0x00840606 -#define DDRSS_CTL_183_DATA 0x36E436E4 +#define DDRSS_CTL_183_DATA 0x3FF43FF4 #define DDRSS_CTL_184_DATA 0x33333300 #define DDRSS_CTL_185_DATA 0x00000000 #define DDRSS_CTL_186_DATA 0x00565600 @@ -270,12 +270,12 @@ #define DDRSS_CTL_258_DATA 0x00320040 #define DDRSS_CTL_259_DATA 0x00020008 #define DDRSS_CTL_260_DATA 0x00400100 -#define DDRSS_CTL_261_DATA 0x0038074A +#define DDRSS_CTL_261_DATA 0x00400855 #define DDRSS_CTL_262_DATA 0x01000200 -#define DDRSS_CTL_263_DATA 0x074A0040 -#define DDRSS_CTL_264_DATA 0x00000038 -#define DDRSS_CTL_265_DATA 0x005E0003 -#define DDRSS_CTL_266_DATA 0x0100005E +#define DDRSS_CTL_263_DATA 0x08550040 +#define DDRSS_CTL_264_DATA 0x00000040 +#define DDRSS_CTL_265_DATA 0x006B0003 +#define DDRSS_CTL_266_DATA 0x0100006B #define DDRSS_CTL_267_DATA 0x00000000 #define DDRSS_CTL_268_DATA 0x01010000 #define DDRSS_CTL_269_DATA 0x00000202 @@ -327,15 +327,15 @@ #define DDRSS_CTL_315_DATA 0x01000101 #define DDRSS_CTL_316_DATA 0x01010001 #define DDRSS_CTL_317_DATA 0x00010101 -#define DDRSS_CTL_318_DATA 0x05090903 -#define DDRSS_CTL_319_DATA 0x0E081B1B -#define DDRSS_CTL_320_DATA 0x0009030E -#define DDRSS_CTL_321_DATA 0x0A0D030F -#define DDRSS_CTL_322_DATA 0x0A0D0306 -#define DDRSS_CTL_323_DATA 0x0D090006 -#define DDRSS_CTL_324_DATA 0x0100000D -#define DDRSS_CTL_325_DATA 0x07030701 -#define DDRSS_CTL_326_DATA 0x00000003 +#define DDRSS_CTL_318_DATA 0x050A0A03 +#define DDRSS_CTL_319_DATA 0x10081F1F +#define DDRSS_CTL_320_DATA 0x00090310 +#define DDRSS_CTL_321_DATA 0x0B0C030F +#define DDRSS_CTL_322_DATA 0x0B0C0306 +#define DDRSS_CTL_323_DATA 0x0C090006 +#define DDRSS_CTL_324_DATA 0x0100000C +#define DDRSS_CTL_325_DATA 0x08040801 +#define DDRSS_CTL_326_DATA 0x00000004 #define DDRSS_CTL_327_DATA 0x00000000 #define DDRSS_CTL_328_DATA 0x00010000 #define DDRSS_CTL_329_DATA 0x00280D00 @@ -396,7 +396,7 @@ #define DDRSS_CTL_384_DATA 0x00000000 #define DDRSS_CTL_385_DATA 0x00000000 #define DDRSS_CTL_386_DATA 0x00000000 -#define DDRSS_CTL_387_DATA 0x37371B00 +#define DDRSS_CTL_387_DATA 0x3A3A1B00 #define DDRSS_CTL_388_DATA 0x000A0000 #define DDRSS_CTL_389_DATA 0x00000176 #define DDRSS_CTL_390_DATA 0x00000200 @@ -406,22 +406,22 @@ #define DDRSS_CTL_394_DATA 0x00000462 #define DDRSS_CTL_395_DATA 0x00000E9C #define DDRSS_CTL_396_DATA 0x00000204 -#define DDRSS_CTL_397_DATA 0x000038C8 +#define DDRSS_CTL_397_DATA 0x000040E6 #define DDRSS_CTL_398_DATA 0x00000200 #define DDRSS_CTL_399_DATA 0x00000200 #define DDRSS_CTL_400_DATA 0x00000200 #define DDRSS_CTL_401_DATA 0x00000200 -#define DDRSS_CTL_402_DATA 0x0000AA58 -#define DDRSS_CTL_403_DATA 0x000237D0 -#define DDRSS_CTL_404_DATA 0x00000C12 -#define DDRSS_CTL_405_DATA 0x000038C8 +#define DDRSS_CTL_402_DATA 0x0000C2B2 +#define DDRSS_CTL_403_DATA 0x000288FC +#define DDRSS_CTL_404_DATA 0x00000E15 +#define DDRSS_CTL_405_DATA 0x000040E6 #define DDRSS_CTL_406_DATA 0x00000200 #define DDRSS_CTL_407_DATA 0x00000200 #define DDRSS_CTL_408_DATA 0x00000200 #define DDRSS_CTL_409_DATA 0x00000200 -#define DDRSS_CTL_410_DATA 0x0000AA58 -#define DDRSS_CTL_411_DATA 0x000237D0 -#define DDRSS_CTL_412_DATA 0x02020C12 +#define DDRSS_CTL_410_DATA 0x0000C2B2 +#define DDRSS_CTL_411_DATA 0x000288FC +#define DDRSS_CTL_412_DATA 0x02020E15 #define DDRSS_CTL_413_DATA 0x03030202 #define DDRSS_CTL_414_DATA 0x00000022 #define DDRSS_CTL_415_DATA 0x00000000 @@ -432,13 +432,13 @@ #define DDRSS_CTL_420_DATA 0x00000000 #define DDRSS_CTL_421_DATA 0x00030000 #define DDRSS_CTL_422_DATA 0x0006001E -#define DDRSS_CTL_423_DATA 0x00190031 -#define DDRSS_CTL_424_DATA 0x00190031 +#define DDRSS_CTL_423_DATA 0x001B0033 +#define DDRSS_CTL_424_DATA 0x001B0033 #define DDRSS_CTL_425_DATA 0x00000000 #define DDRSS_CTL_426_DATA 0x00000000 #define DDRSS_CTL_427_DATA 0x02000000 #define DDRSS_CTL_428_DATA 0x01000404 -#define DDRSS_CTL_429_DATA 0x091A091A +#define DDRSS_CTL_429_DATA 0x0B1E0B1E #define DDRSS_CTL_430_DATA 0x00000105 #define DDRSS_CTL_431_DATA 0x00010101 #define DDRSS_CTL_432_DATA 0x00010101 @@ -447,8 +447,8 @@ #define DDRSS_CTL_435_DATA 0x02000201 #define DDRSS_CTL_436_DATA 0x02010000 #define DDRSS_CTL_437_DATA 0x00000200 -#define DDRSS_CTL_438_DATA 0x22060000 -#define DDRSS_CTL_439_DATA 0x00000122 +#define DDRSS_CTL_438_DATA 0x28060000 +#define DDRSS_CTL_439_DATA 0x00000128 #define DDRSS_CTL_440_DATA 0xFFFFFFFF #define DDRSS_CTL_441_DATA 0xFFFFFFFF #define DDRSS_CTL_442_DATA 0x00000000 @@ -515,7 +515,7 @@ #define DDRSS_PI_43_DATA 0x00000000 #define DDRSS_PI_44_DATA 0x00000000 #define DDRSS_PI_45_DATA 0x000F0F00 -#define DDRSS_PI_46_DATA 0x00000019 +#define DDRSS_PI_46_DATA 0x0000001B #define DDRSS_PI_47_DATA 0x000007D0 #define DDRSS_PI_48_DATA 0x00000300 #define DDRSS_PI_49_DATA 0x00000000 @@ -535,13 +535,13 @@ #define DDRSS_PI_63_DATA 0x01000404 #define DDRSS_PI_64_DATA 0x00000000 #define DDRSS_PI_65_DATA 0x00000000 -#define DDRSS_PI_66_DATA 0x00000101 +#define DDRSS_PI_66_DATA 0x00000100 #define DDRSS_PI_67_DATA 0x0001010F #define DDRSS_PI_68_DATA 0x00340000 #define DDRSS_PI_69_DATA 0x00000000 #define DDRSS_PI_70_DATA 0x00000000 -#define DDRSS_PI_71_DATA 0x00000000 -#define DDRSS_PI_72_DATA 0x01000000 +#define DDRSS_PI_71_DATA 0x0000FFFF +#define DDRSS_PI_72_DATA 0x00000000 #define DDRSS_PI_73_DATA 0x00080100 #define DDRSS_PI_74_DATA 0x02000200 #define DDRSS_PI_75_DATA 0x01000100 @@ -632,18 +632,18 @@ #define DDRSS_PI_160_DATA 0x00000000 #define DDRSS_PI_161_DATA 0x00010000 #define DDRSS_PI_162_DATA 0x00000000 -#define DDRSS_PI_163_DATA 0x26260100 +#define DDRSS_PI_163_DATA 0x2B2B0100 #define DDRSS_PI_164_DATA 0x00000034 -#define DDRSS_PI_165_DATA 0x0000005E -#define DDRSS_PI_166_DATA 0x0002005E +#define DDRSS_PI_165_DATA 0x00000064 +#define DDRSS_PI_166_DATA 0x00020064 #define DDRSS_PI_167_DATA 0x02000200 -#define DDRSS_PI_168_DATA 0x40100C04 -#define DDRSS_PI_169_DATA 0x000E4010 +#define DDRSS_PI_168_DATA 0x48120C04 +#define DDRSS_PI_169_DATA 0x000E4812 #define DDRSS_PI_170_DATA 0x000000BB -#define DDRSS_PI_171_DATA 0x0000020B -#define DDRSS_PI_172_DATA 0x00001C64 -#define DDRSS_PI_173_DATA 0x0000020B -#define DDRSS_PI_174_DATA 0x04001C64 +#define DDRSS_PI_171_DATA 0x00000256 +#define DDRSS_PI_172_DATA 0x00002073 +#define DDRSS_PI_173_DATA 0x00000256 +#define DDRSS_PI_174_DATA 0x04002073 #define DDRSS_PI_175_DATA 0x01010404 #define DDRSS_PI_176_DATA 0x00001501 #define DDRSS_PI_177_DATA 0x00150015 @@ -654,80 +654,80 @@ #define DDRSS_PI_182_DATA 0x00000101 #define DDRSS_PI_183_DATA 0x00000000 #define DDRSS_PI_184_DATA 0x00000000 -#define DDRSS_PI_185_DATA 0x12040000 -#define DDRSS_PI_186_DATA 0x0C0C0212 +#define DDRSS_PI_185_DATA 0x15040000 +#define DDRSS_PI_186_DATA 0x0E0E0215 #define DDRSS_PI_187_DATA 0x00040402 #define DDRSS_PI_188_DATA 0x000C8034 -#define DDRSS_PI_189_DATA 0x001F0047 -#define DDRSS_PI_190_DATA 0x001F0047 +#define DDRSS_PI_189_DATA 0x00218049 +#define DDRSS_PI_190_DATA 0x00218049 #define DDRSS_PI_191_DATA 0x01010101 -#define DDRSS_PI_192_DATA 0x0003000D -#define DDRSS_PI_193_DATA 0x000301D3 -#define DDRSS_PI_194_DATA 0x010001D3 +#define DDRSS_PI_192_DATA 0x0004000D +#define DDRSS_PI_193_DATA 0x00040216 +#define DDRSS_PI_194_DATA 0x01000216 #define DDRSS_PI_195_DATA 0x000E000E -#define DDRSS_PI_196_DATA 0x01D40100 -#define DDRSS_PI_197_DATA 0x010001D4 -#define DDRSS_PI_198_DATA 0x01D401D4 +#define DDRSS_PI_196_DATA 0x02170100 +#define DDRSS_PI_197_DATA 0x01000217 +#define DDRSS_PI_198_DATA 0x02170217 #define DDRSS_PI_199_DATA 0x32103200 #define DDRSS_PI_200_DATA 0x01013210 #define DDRSS_PI_201_DATA 0x0A070601 -#define DDRSS_PI_202_DATA 0x1C11090D -#define DDRSS_PI_203_DATA 0x1C110913 -#define DDRSS_PI_204_DATA 0x0000C013 +#define DDRSS_PI_202_DATA 0x1F130A0D +#define DDRSS_PI_203_DATA 0x1F130A14 +#define DDRSS_PI_204_DATA 0x0000C014 #define DDRSS_PI_205_DATA 0x00C01000 #define DDRSS_PI_206_DATA 0x00C01000 #define DDRSS_PI_207_DATA 0x00021000 -#define DDRSS_PI_208_DATA 0x0021000D -#define DDRSS_PI_209_DATA 0x002101D3 -#define DDRSS_PI_210_DATA 0x001101D3 +#define DDRSS_PI_208_DATA 0x0024000D +#define DDRSS_PI_209_DATA 0x00240216 +#define DDRSS_PI_210_DATA 0x00110216 #define DDRSS_PI_211_DATA 0x32000056 -#define DDRSS_PI_212_DATA 0x00000101 -#define DDRSS_PI_213_DATA 0x005A0035 -#define DDRSS_PI_214_DATA 0x01013212 -#define DDRSS_PI_215_DATA 0x00003500 -#define DDRSS_PI_216_DATA 0x3212005A -#define DDRSS_PI_217_DATA 0x09000101 +#define DDRSS_PI_212_DATA 0x00000301 +#define DDRSS_PI_213_DATA 0x005B003A +#define DDRSS_PI_214_DATA 0x03013212 +#define DDRSS_PI_215_DATA 0x00003A00 +#define DDRSS_PI_216_DATA 0x3212005B +#define DDRSS_PI_217_DATA 0x09000301 #define DDRSS_PI_218_DATA 0x04010504 #define DDRSS_PI_219_DATA 0x0400062B #define DDRSS_PI_220_DATA 0x0A032001 -#define DDRSS_PI_221_DATA 0x262B0F0A -#define DDRSS_PI_222_DATA 0x00002819 -#define DDRSS_PI_223_DATA 0x5400E638 -#define DDRSS_PI_224_DATA 0x1B1C2007 -#define DDRSS_PI_225_DATA 0x262B0F13 -#define DDRSS_PI_226_DATA 0x00002819 -#define DDRSS_PI_227_DATA 0x5400E638 -#define DDRSS_PI_228_DATA 0x1B1C2007 -#define DDRSS_PI_229_DATA 0x00017613 +#define DDRSS_PI_221_DATA 0x2C31110A +#define DDRSS_PI_222_DATA 0x00002D1C +#define DDRSS_PI_223_DATA 0x6001071C +#define DDRSS_PI_224_DATA 0x1E202008 +#define DDRSS_PI_225_DATA 0x2C311116 +#define DDRSS_PI_226_DATA 0x00002D1C +#define DDRSS_PI_227_DATA 0x6001071C +#define DDRSS_PI_228_DATA 0x1E202008 +#define DDRSS_PI_229_DATA 0x00017616 #define DDRSS_PI_230_DATA 0x00000E9C -#define DDRSS_PI_231_DATA 0x000038C8 -#define DDRSS_PI_232_DATA 0x000237D0 -#define DDRSS_PI_233_DATA 0x000038C8 -#define DDRSS_PI_234_DATA 0x000237D0 -#define DDRSS_PI_235_DATA 0x0219000F -#define DDRSS_PI_236_DATA 0x03030219 +#define DDRSS_PI_231_DATA 0x000040E6 +#define DDRSS_PI_232_DATA 0x000288FC +#define DDRSS_PI_233_DATA 0x000040E6 +#define DDRSS_PI_234_DATA 0x000288FC +#define DDRSS_PI_235_DATA 0x0266000F +#define DDRSS_PI_236_DATA 0x03030266 #define DDRSS_PI_237_DATA 0x00271003 #define DDRSS_PI_238_DATA 0x000186A0 #define DDRSS_PI_239_DATA 0x00000005 #define DDRSS_PI_240_DATA 0x00000064 #define DDRSS_PI_241_DATA 0x0000000F -#define DDRSS_PI_242_DATA 0x0005B18F +#define DDRSS_PI_242_DATA 0x000681C8 #define DDRSS_PI_243_DATA 0x000186A0 #define DDRSS_PI_244_DATA 0x00000005 -#define DDRSS_PI_245_DATA 0x00000E94 -#define DDRSS_PI_246_DATA 0x00000219 -#define DDRSS_PI_247_DATA 0x0005B18F +#define DDRSS_PI_245_DATA 0x000010A9 +#define DDRSS_PI_246_DATA 0x00000266 +#define DDRSS_PI_247_DATA 0x000681C8 #define DDRSS_PI_248_DATA 0x000186A0 #define DDRSS_PI_249_DATA 0x00000005 -#define DDRSS_PI_250_DATA 0x00000E94 -#define DDRSS_PI_251_DATA 0x01000219 +#define DDRSS_PI_250_DATA 0x000010A9 +#define DDRSS_PI_251_DATA 0x01000266 #define DDRSS_PI_252_DATA 0x00320040 #define DDRSS_PI_253_DATA 0x00010008 -#define DDRSS_PI_254_DATA 0x074A0040 -#define DDRSS_PI_255_DATA 0x00010038 -#define DDRSS_PI_256_DATA 0x074A0040 -#define DDRSS_PI_257_DATA 0x00000338 -#define DDRSS_PI_258_DATA 0x005E005E +#define DDRSS_PI_254_DATA 0x08550040 +#define DDRSS_PI_255_DATA 0x00010040 +#define DDRSS_PI_256_DATA 0x08550040 +#define DDRSS_PI_257_DATA 0x00000340 +#define DDRSS_PI_258_DATA 0x006B006B #define DDRSS_PI_259_DATA 0x00040404 #define DDRSS_PI_260_DATA 0x00000055 #define DDRSS_PI_261_DATA 0x55003C5A @@ -746,27 +746,27 @@ #define DDRSS_PI_274_DATA 0x00000000 #define DDRSS_PI_275_DATA 0x00330084 #define DDRSS_PI_276_DATA 0x00160000 -#define DDRSS_PI_277_DATA 0x563336E4 +#define DDRSS_PI_277_DATA 0x56333FF4 #define DDRSS_PI_278_DATA 0x00160F27 -#define DDRSS_PI_279_DATA 0x563336E4 +#define DDRSS_PI_279_DATA 0x56333FF4 #define DDRSS_PI_280_DATA 0x00160F27 #define DDRSS_PI_281_DATA 0x00330084 #define DDRSS_PI_282_DATA 0x00160000 -#define DDRSS_PI_283_DATA 0x563336E4 +#define DDRSS_PI_283_DATA 0x56333FF4 #define DDRSS_PI_284_DATA 0x00160F27 -#define DDRSS_PI_285_DATA 0x563336E4 +#define DDRSS_PI_285_DATA 0x56333FF4 #define DDRSS_PI_286_DATA 0x00160F27 #define DDRSS_PI_287_DATA 0x00330084 #define DDRSS_PI_288_DATA 0x00160000 -#define DDRSS_PI_289_DATA 0x563336E4 +#define DDRSS_PI_289_DATA 0x56333FF4 #define DDRSS_PI_290_DATA 0x00160F27 -#define DDRSS_PI_291_DATA 0x563336E4 +#define DDRSS_PI_291_DATA 0x56333FF4 #define DDRSS_PI_292_DATA 0x00160F27 #define DDRSS_PI_293_DATA 0x00330084 #define DDRSS_PI_294_DATA 0x00160000 -#define DDRSS_PI_295_DATA 0x563336E4 +#define DDRSS_PI_295_DATA 0x56333FF4 #define DDRSS_PI_296_DATA 0x00160F27 -#define DDRSS_PI_297_DATA 0x563336E4 +#define DDRSS_PI_297_DATA 0x56333FF4 #define DDRSS_PI_298_DATA 0x00160F27 #define DDRSS_PI_299_DATA 0x00000000 @@ -787,7 +787,7 @@ #define DDRSS_PHY_14_DATA 0x060100CC #define DDRSS_PHY_15_DATA 0x00030066 #define DDRSS_PHY_16_DATA 0x00000000 -#define DDRSS_PHY_17_DATA 0x00000001 +#define DDRSS_PHY_17_DATA 0x00000301 #define DDRSS_PHY_18_DATA 0x0000AAAA #define DDRSS_PHY_19_DATA 0x00005555 #define DDRSS_PHY_20_DATA 0x0000B5B5 @@ -803,7 +803,7 @@ #define DDRSS_PHY_30_DATA 0x0F000000 #define DDRSS_PHY_31_DATA 0x00000F0F #define DDRSS_PHY_32_DATA 0x10200000 -#define DDRSS_PHY_33_DATA 0x0C002004 +#define DDRSS_PHY_33_DATA 0x0C002007 #define DDRSS_PHY_34_DATA 0x00000000 #define DDRSS_PHY_35_DATA 0x00000000 #define DDRSS_PHY_36_DATA 0x55555555 @@ -855,35 +855,35 @@ #define DDRSS_PHY_82_DATA 0x00000000 #define DDRSS_PHY_83_DATA 0x00000100 #define DDRSS_PHY_84_DATA 0x01CC0C01 -#define DDRSS_PHY_85_DATA 0x0003CC0C +#define DDRSS_PHY_85_DATA 0x1003CC0C #define DDRSS_PHY_86_DATA 0x20000140 #define DDRSS_PHY_87_DATA 0x07FF0200 #define DDRSS_PHY_88_DATA 0x0000DD01 #define DDRSS_PHY_89_DATA 0x10100303 #define DDRSS_PHY_90_DATA 0x10101010 #define DDRSS_PHY_91_DATA 0x10101010 -#define DDRSS_PHY_92_DATA 0x00041010 +#define DDRSS_PHY_92_DATA 0x00021010 #define DDRSS_PHY_93_DATA 0x00100010 #define DDRSS_PHY_94_DATA 0x00100010 #define DDRSS_PHY_95_DATA 0x00100010 #define DDRSS_PHY_96_DATA 0x00100010 #define DDRSS_PHY_97_DATA 0x00050010 #define DDRSS_PHY_98_DATA 0x51517041 -#define DDRSS_PHY_99_DATA 0x31C06000 +#define DDRSS_PHY_99_DATA 0x31C06001 #define DDRSS_PHY_100_DATA 0x07AB0340 #define DDRSS_PHY_101_DATA 0x00C0C001 -#define DDRSS_PHY_102_DATA 0x0D0C0001 +#define DDRSS_PHY_102_DATA 0x0E0D0001 #define DDRSS_PHY_103_DATA 0x10001000 -#define DDRSS_PHY_104_DATA 0x0C063E42 -#define DDRSS_PHY_105_DATA 0x0F0C3201 +#define DDRSS_PHY_104_DATA 0x0C083E42 +#define DDRSS_PHY_105_DATA 0x0F0C3701 #define DDRSS_PHY_106_DATA 0x01000140 #define DDRSS_PHY_107_DATA 0x0C000420 -#define DDRSS_PHY_108_DATA 0x000002DD +#define DDRSS_PHY_108_DATA 0x00000322 #define DDRSS_PHY_109_DATA 0x0A0000D0 #define DDRSS_PHY_110_DATA 0x00030200 #define DDRSS_PHY_111_DATA 0x02800000 #define DDRSS_PHY_112_DATA 0x80800000 -#define DDRSS_PHY_113_DATA 0x000D2010 +#define DDRSS_PHY_113_DATA 0x000E2010 #define DDRSS_PHY_114_DATA 0x76543210 #define DDRSS_PHY_115_DATA 0x00000008 #define DDRSS_PHY_116_DATA 0x02800280 @@ -900,13 +900,13 @@ #define DDRSS_PHY_127_DATA 0x00A000A0 #define DDRSS_PHY_128_DATA 0x00A000A0 #define DDRSS_PHY_129_DATA 0x00A000A0 -#define DDRSS_PHY_130_DATA 0x006D00A0 +#define DDRSS_PHY_130_DATA 0x01C200A0 #define DDRSS_PHY_131_DATA 0x01A00005 #define DDRSS_PHY_132_DATA 0x00000000 #define DDRSS_PHY_133_DATA 0x00000000 #define DDRSS_PHY_134_DATA 0x00080200 #define DDRSS_PHY_135_DATA 0x00000000 -#define DDRSS_PHY_136_DATA 0x20202020 +#define DDRSS_PHY_136_DATA 0x20202000 #define DDRSS_PHY_137_DATA 0x20202020 #define DDRSS_PHY_138_DATA 0xF0F02020 #define DDRSS_PHY_139_DATA 0x00000000 @@ -1043,7 +1043,7 @@ #define DDRSS_PHY_270_DATA 0x060100CC #define DDRSS_PHY_271_DATA 0x00030066 #define DDRSS_PHY_272_DATA 0x00000000 -#define DDRSS_PHY_273_DATA 0x00000001 +#define DDRSS_PHY_273_DATA 0x00000301 #define DDRSS_PHY_274_DATA 0x0000AAAA #define DDRSS_PHY_275_DATA 0x00005555 #define DDRSS_PHY_276_DATA 0x0000B5B5 @@ -1059,7 +1059,7 @@ #define DDRSS_PHY_286_DATA 0x0F000000 #define DDRSS_PHY_287_DATA 0x00000F0F #define DDRSS_PHY_288_DATA 0x10200000 -#define DDRSS_PHY_289_DATA 0x0C002004 +#define DDRSS_PHY_289_DATA 0x0C002007 #define DDRSS_PHY_290_DATA 0x00000000 #define DDRSS_PHY_291_DATA 0x00000000 #define DDRSS_PHY_292_DATA 0x55555555 @@ -1111,35 +1111,35 @@ #define DDRSS_PHY_338_DATA 0x00000000 #define DDRSS_PHY_339_DATA 0x00000100 #define DDRSS_PHY_340_DATA 0x01CC0C01 -#define DDRSS_PHY_341_DATA 0x0003CC0C +#define DDRSS_PHY_341_DATA 0x1003CC0C #define DDRSS_PHY_342_DATA 0x20000140 #define DDRSS_PHY_343_DATA 0x07FF0200 #define DDRSS_PHY_344_DATA 0x0000DD01 #define DDRSS_PHY_345_DATA 0x10100303 #define DDRSS_PHY_346_DATA 0x10101010 #define DDRSS_PHY_347_DATA 0x10101010 -#define DDRSS_PHY_348_DATA 0x00041010 +#define DDRSS_PHY_348_DATA 0x00021010 #define DDRSS_PHY_349_DATA 0x00100010 #define DDRSS_PHY_350_DATA 0x00100010 #define DDRSS_PHY_351_DATA 0x00100010 #define DDRSS_PHY_352_DATA 0x00100010 #define DDRSS_PHY_353_DATA 0x00050010 #define DDRSS_PHY_354_DATA 0x51517041 -#define DDRSS_PHY_355_DATA 0x31C06000 +#define DDRSS_PHY_355_DATA 0x31C06001 #define DDRSS_PHY_356_DATA 0x07AB0340 #define DDRSS_PHY_357_DATA 0x00C0C001 -#define DDRSS_PHY_358_DATA 0x0D0C0001 +#define DDRSS_PHY_358_DATA 0x0E0D0001 #define DDRSS_PHY_359_DATA 0x10001000 -#define DDRSS_PHY_360_DATA 0x0C063E42 -#define DDRSS_PHY_361_DATA 0x0F0C3201 +#define DDRSS_PHY_360_DATA 0x0C083E42 +#define DDRSS_PHY_361_DATA 0x0F0C3701 #define DDRSS_PHY_362_DATA 0x01000140 #define DDRSS_PHY_363_DATA 0x0C000420 -#define DDRSS_PHY_364_DATA 0x000002DD +#define DDRSS_PHY_364_DATA 0x00000322 #define DDRSS_PHY_365_DATA 0x0A0000D0 #define DDRSS_PHY_366_DATA 0x00030200 #define DDRSS_PHY_367_DATA 0x02800000 #define DDRSS_PHY_368_DATA 0x80800000 -#define DDRSS_PHY_369_DATA 0x000D2010 +#define DDRSS_PHY_369_DATA 0x000E2010 #define DDRSS_PHY_370_DATA 0x76543210 #define DDRSS_PHY_371_DATA 0x00000008 #define DDRSS_PHY_372_DATA 0x02800280 @@ -1156,13 +1156,13 @@ #define DDRSS_PHY_383_DATA 0x00A000A0 #define DDRSS_PHY_384_DATA 0x00A000A0 #define DDRSS_PHY_385_DATA 0x00A000A0 -#define DDRSS_PHY_386_DATA 0x006D00A0 +#define DDRSS_PHY_386_DATA 0x01C200A0 #define DDRSS_PHY_387_DATA 0x01A00005 #define DDRSS_PHY_388_DATA 0x00000000 #define DDRSS_PHY_389_DATA 0x00000000 #define DDRSS_PHY_390_DATA 0x00080200 #define DDRSS_PHY_391_DATA 0x00000000 -#define DDRSS_PHY_392_DATA 0x20202020 +#define DDRSS_PHY_392_DATA 0x20202000 #define DDRSS_PHY_393_DATA 0x20202020 #define DDRSS_PHY_394_DATA 0xF0F02020 #define DDRSS_PHY_395_DATA 0x00000000 @@ -1299,7 +1299,7 @@ #define DDRSS_PHY_526_DATA 0x060100CC #define DDRSS_PHY_527_DATA 0x00030066 #define DDRSS_PHY_528_DATA 0x00000000 -#define DDRSS_PHY_529_DATA 0x00000001 +#define DDRSS_PHY_529_DATA 0x00000301 #define DDRSS_PHY_530_DATA 0x0000AAAA #define DDRSS_PHY_531_DATA 0x00005555 #define DDRSS_PHY_532_DATA 0x0000B5B5 @@ -1315,7 +1315,7 @@ #define DDRSS_PHY_542_DATA 0x0F000000 #define DDRSS_PHY_543_DATA 0x00000F0F #define DDRSS_PHY_544_DATA 0x10200000 -#define DDRSS_PHY_545_DATA 0x0C002004 +#define DDRSS_PHY_545_DATA 0x0C002007 #define DDRSS_PHY_546_DATA 0x00000000 #define DDRSS_PHY_547_DATA 0x00000000 #define DDRSS_PHY_548_DATA 0x55555555 @@ -1367,35 +1367,35 @@ #define DDRSS_PHY_594_DATA 0x00000000 #define DDRSS_PHY_595_DATA 0x00000100 #define DDRSS_PHY_596_DATA 0x01CC0C01 -#define DDRSS_PHY_597_DATA 0x0003CC0C +#define DDRSS_PHY_597_DATA 0x1003CC0C #define DDRSS_PHY_598_DATA 0x20000140 #define DDRSS_PHY_599_DATA 0x07FF0200 #define DDRSS_PHY_600_DATA 0x0000DD01 #define DDRSS_PHY_601_DATA 0x10100303 #define DDRSS_PHY_602_DATA 0x10101010 #define DDRSS_PHY_603_DATA 0x10101010 -#define DDRSS_PHY_604_DATA 0x00041010 +#define DDRSS_PHY_604_DATA 0x00021010 #define DDRSS_PHY_605_DATA 0x00100010 #define DDRSS_PHY_606_DATA 0x00100010 #define DDRSS_PHY_607_DATA 0x00100010 #define DDRSS_PHY_608_DATA 0x00100010 #define DDRSS_PHY_609_DATA 0x00050010 #define DDRSS_PHY_610_DATA 0x51517041 -#define DDRSS_PHY_611_DATA 0x31C06000 +#define DDRSS_PHY_611_DATA 0x31C06001 #define DDRSS_PHY_612_DATA 0x07AB0340 #define DDRSS_PHY_613_DATA 0x00C0C001 -#define DDRSS_PHY_614_DATA 0x0D0C0001 +#define DDRSS_PHY_614_DATA 0x0E0D0001 #define DDRSS_PHY_615_DATA 0x10001000 -#define DDRSS_PHY_616_DATA 0x0C063E42 -#define DDRSS_PHY_617_DATA 0x0F0C3201 +#define DDRSS_PHY_616_DATA 0x0C083E42 +#define DDRSS_PHY_617_DATA 0x0F0C3701 #define DDRSS_PHY_618_DATA 0x01000140 #define DDRSS_PHY_619_DATA 0x0C000420 -#define DDRSS_PHY_620_DATA 0x000002DD +#define DDRSS_PHY_620_DATA 0x00000322 #define DDRSS_PHY_621_DATA 0x0A0000D0 #define DDRSS_PHY_622_DATA 0x00030200 #define DDRSS_PHY_623_DATA 0x02800000 #define DDRSS_PHY_624_DATA 0x80800000 -#define DDRSS_PHY_625_DATA 0x000D2010 +#define DDRSS_PHY_625_DATA 0x000E2010 #define DDRSS_PHY_626_DATA 0x76543210 #define DDRSS_PHY_627_DATA 0x00000008 #define DDRSS_PHY_628_DATA 0x02800280 @@ -1412,13 +1412,13 @@ #define DDRSS_PHY_639_DATA 0x00A000A0 #define DDRSS_PHY_640_DATA 0x00A000A0 #define DDRSS_PHY_641_DATA 0x00A000A0 -#define DDRSS_PHY_642_DATA 0x006D00A0 +#define DDRSS_PHY_642_DATA 0x01C200A0 #define DDRSS_PHY_643_DATA 0x01A00005 #define DDRSS_PHY_644_DATA 0x00000000 #define DDRSS_PHY_645_DATA 0x00000000 #define DDRSS_PHY_646_DATA 0x00080200 #define DDRSS_PHY_647_DATA 0x00000000 -#define DDRSS_PHY_648_DATA 0x20202020 +#define DDRSS_PHY_648_DATA 0x20202000 #define DDRSS_PHY_649_DATA 0x20202020 #define DDRSS_PHY_650_DATA 0xF0F02020 #define DDRSS_PHY_651_DATA 0x00000000 @@ -1555,7 +1555,7 @@ #define DDRSS_PHY_782_DATA 0x060100CC #define DDRSS_PHY_783_DATA 0x00030066 #define DDRSS_PHY_784_DATA 0x00000000 -#define DDRSS_PHY_785_DATA 0x00000001 +#define DDRSS_PHY_785_DATA 0x00000301 #define DDRSS_PHY_786_DATA 0x0000AAAA #define DDRSS_PHY_787_DATA 0x00005555 #define DDRSS_PHY_788_DATA 0x0000B5B5 @@ -1571,7 +1571,7 @@ #define DDRSS_PHY_798_DATA 0x0F000000 #define DDRSS_PHY_799_DATA 0x00000F0F #define DDRSS_PHY_800_DATA 0x10200000 -#define DDRSS_PHY_801_DATA 0x0C002004 +#define DDRSS_PHY_801_DATA 0x0C002007 #define DDRSS_PHY_802_DATA 0x00000000 #define DDRSS_PHY_803_DATA 0x00000000 #define DDRSS_PHY_804_DATA 0x55555555 @@ -1623,35 +1623,35 @@ #define DDRSS_PHY_850_DATA 0x00000000 #define DDRSS_PHY_851_DATA 0x00000100 #define DDRSS_PHY_852_DATA 0x01CC0C01 -#define DDRSS_PHY_853_DATA 0x0003CC0C +#define DDRSS_PHY_853_DATA 0x1003CC0C #define DDRSS_PHY_854_DATA 0x20000140 #define DDRSS_PHY_855_DATA 0x07FF0200 #define DDRSS_PHY_856_DATA 0x0000DD01 #define DDRSS_PHY_857_DATA 0x10100303 #define DDRSS_PHY_858_DATA 0x10101010 #define DDRSS_PHY_859_DATA 0x10101010 -#define DDRSS_PHY_860_DATA 0x00041010 +#define DDRSS_PHY_860_DATA 0x00021010 #define DDRSS_PHY_861_DATA 0x00100010 #define DDRSS_PHY_862_DATA 0x00100010 #define DDRSS_PHY_863_DATA 0x00100010 #define DDRSS_PHY_864_DATA 0x00100010 #define DDRSS_PHY_865_DATA 0x00050010 #define DDRSS_PHY_866_DATA 0x51517041 -#define DDRSS_PHY_867_DATA 0x31C06000 +#define DDRSS_PHY_867_DATA 0x31C06001 #define DDRSS_PHY_868_DATA 0x07AB0340 #define DDRSS_PHY_869_DATA 0x00C0C001 -#define DDRSS_PHY_870_DATA 0x0D0C0001 +#define DDRSS_PHY_870_DATA 0x0E0D0001 #define DDRSS_PHY_871_DATA 0x10001000 -#define DDRSS_PHY_872_DATA 0x0C063E42 -#define DDRSS_PHY_873_DATA 0x0F0C3201 +#define DDRSS_PHY_872_DATA 0x0C083E42 +#define DDRSS_PHY_873_DATA 0x0F0C3701 #define DDRSS_PHY_874_DATA 0x01000140 #define DDRSS_PHY_875_DATA 0x0C000420 -#define DDRSS_PHY_876_DATA 0x000002DD +#define DDRSS_PHY_876_DATA 0x00000322 #define DDRSS_PHY_877_DATA 0x0A0000D0 #define DDRSS_PHY_878_DATA 0x00030200 #define DDRSS_PHY_879_DATA 0x02800000 #define DDRSS_PHY_880_DATA 0x80800000 -#define DDRSS_PHY_881_DATA 0x000D2010 +#define DDRSS_PHY_881_DATA 0x000E2010 #define DDRSS_PHY_882_DATA 0x76543210 #define DDRSS_PHY_883_DATA 0x00000008 #define DDRSS_PHY_884_DATA 0x02800280 @@ -1668,13 +1668,13 @@ #define DDRSS_PHY_895_DATA 0x00A000A0 #define DDRSS_PHY_896_DATA 0x00A000A0 #define DDRSS_PHY_897_DATA 0x00A000A0 -#define DDRSS_PHY_898_DATA 0x006D00A0 +#define DDRSS_PHY_898_DATA 0x01C200A0 #define DDRSS_PHY_899_DATA 0x01A00005 #define DDRSS_PHY_900_DATA 0x00000000 #define DDRSS_PHY_901_DATA 0x00000000 #define DDRSS_PHY_902_DATA 0x00080200 #define DDRSS_PHY_903_DATA 0x00000000 -#define DDRSS_PHY_904_DATA 0x20202020 +#define DDRSS_PHY_904_DATA 0x20202000 #define DDRSS_PHY_905_DATA 0x20202020 #define DDRSS_PHY_906_DATA 0xF0F02020 #define DDRSS_PHY_907_DATA 0x00000000 @@ -1834,7 +1834,7 @@ #define DDRSS_PHY_1061_DATA 0x00000000 #define DDRSS_PHY_1062_DATA 0x00000000 #define DDRSS_PHY_1063_DATA 0x00000000 -#define DDRSS_PHY_1064_DATA 0x000505FF +#define DDRSS_PHY_1064_DATA 0x000305FF #define DDRSS_PHY_1065_DATA 0x00030000 #define DDRSS_PHY_1066_DATA 0x00000300 #define DDRSS_PHY_1067_DATA 0x00000300 @@ -2163,8 +2163,8 @@ #define DDRSS_PHY_1390_DATA 0x00000000 #define DDRSS_PHY_1391_DATA 0x00000000 #define DDRSS_PHY_1392_DATA 0x00000000 -#define DDRSS_PHY_1393_DATA 0x0001F7C5 -#define DDRSS_PHY_1394_DATA 0x00000005 +#define DDRSS_PHY_1393_DATA 0x0001F7C0 +#define DDRSS_PHY_1394_DATA 0x00000003 #define DDRSS_PHY_1395_DATA 0x00000000 #define DDRSS_PHY_1396_DATA 0x00001142 #define DDRSS_PHY_1397_DATA 0x010207AB diff --git a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts index 2dde65d968..4cfaf8ca3c 100644 --- a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts +++ b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts @@ -6,7 +6,7 @@ /dts-v1/; #include "k3-j721e-som-p0.dtsi" -#include "k3-j721e-ddr-evm-lp4-3733.dtsi" +#include "k3-j721e-ddr-evm-lp4-4266.dtsi" #include "k3-j721e-ddr.dtsi" / { -- 2.17.1

2 1

[PATCH] spi: omap3_spi: Fix speed and mode selection
by Vignesh Raghavendra 23 Dec '20

23 Dec '20

McSPI IP provides per CS specific speed and mode selection. Therefore it is possible to apply these settings only after CS is known. But set_speed and set_mode can be called without bus being claimed, this would lead driver to set up wrong CS (or previously used CS). Fix this by apply set_speed and set_mode only if bus is already claimed. Signed-off-by: Vignesh Raghavendra <vigneshr(a)ti.com> --- drivers/spi/omap3_spi.c | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/drivers/spi/omap3_spi.c b/drivers/spi/omap3_spi.c index 56cb217486..fe73362945 100644 --- a/drivers/spi/omap3_spi.c +++ b/drivers/spi/omap3_spi.c @@ -37,6 +37,8 @@ struct omap3_spi_priv { unsigned int mode; unsigned int wordlen; unsigned int pin_dir:1; + + bool bus_claimed; }; static void omap3_spi_write_chconf(struct omap3_spi_priv *priv, int val) @@ -372,6 +374,8 @@ static void _omap3_spi_claim_bus(struct omap3_spi_priv *priv) conf |= OMAP3_MCSPI_MODULCTRL_SINGLE; writel(conf, &priv->regs->modulctrl); + + priv->bus_claimed = true; } static int omap3_spi_claim_bus(struct udevice *dev) @@ -381,9 +385,12 @@ static int omap3_spi_claim_bus(struct udevice *dev) struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); priv->cs = slave_plat->cs; - priv->freq = slave_plat->max_hz; + if (!priv->freq) + priv->freq = slave_plat->max_hz; _omap3_spi_claim_bus(priv); + _omap3_spi_set_speed(priv); + _omap3_spi_set_mode(priv); return 0; } @@ -395,6 +402,8 @@ static int omap3_spi_release_bus(struct udevice *dev) writel(OMAP3_MCSPI_MODULCTRL_MS, &priv->regs->modulctrl); + priv->bus_claimed = false; + return 0; } @@ -440,7 +449,8 @@ static int omap3_spi_set_speed(struct udevice *dev, unsigned int speed) struct omap3_spi_priv *priv = dev_get_priv(dev); priv->freq = speed; - _omap3_spi_set_speed(priv); + if (priv->bus_claimed) + _omap3_spi_set_speed(priv); return 0; } @@ -451,7 +461,8 @@ static int omap3_spi_set_mode(struct udevice *dev, uint mode) priv->mode = mode; - _omap3_spi_set_mode(priv); + if (priv->bus_claimed) + _omap3_spi_set_mode(priv); return 0; } -- 2.29.2

3 3

[PATCH] spi: ti_qspi: Fix "spi-max-frequency" error path in ti_qspi_ofdata_to_platdata
by Ovidiu Panait 23 Dec '20

23 Dec '20

struct ti_qspi_priv->max_hz is declared as unsigned int, so the following error path check will always be false, even when "spi-max-frequency" property is invalid/missing: priv->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", -1); if (priv->max_hz < 0) { ... } Replace the fdtdec call with dev_read_u32_default() and use 0 as the default value. Error out if max_hz is zero. Signed-off-by: Ovidiu Panait <ovidiu.panait(a)windriver.com> --- drivers/spi/ti_qspi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c index 5fdbb49442..91be18e0a7 100644 --- a/drivers/spi/ti_qspi.c +++ b/drivers/spi/ti_qspi.c @@ -467,8 +467,8 @@ static int ti_qspi_ofdata_to_platdata(struct udevice *bus) priv->memory_map = map_physmem(mmap_addr, mmap_size, MAP_NOCACHE); priv->mmap_size = mmap_size; - priv->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", -1); - if (priv->max_hz < 0) { + priv->max_hz = dev_read_u32_default(bus, "spi-max-frequency", 0); + if (!priv->max_hz) { debug("Error: Max frequency missing\n"); return -ENODEV; } -- 2.17.1

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[PATCH] gpio: tca642x: fix input subcommand for gpio banks > 0
by Tomas Novotny 23 Dec '20

23 Dec '20

The value of input pin for bank > 0 is always 0 for input subcommand. The reason is that gpio_bank variable is computed only for invert and output subcommands (it depends on number of arguments). The default value of zero causes to shift the mask away for banks > 0. Please note that info subcommand works as expected, because the input pin values are accessed differently. Fixes: 61c1775f16ed ("gpio: tca642x: Add the tca642x gpio expander driver") Cc: Dan Murphy <dmurphy(a)ti.com> Signed-off-by: Tomas Novotny <tomas(a)novotny.cz> --- drivers/gpio/tca642x.c | 49 ++++++++++++++++++++++++++++++------------ 1 file changed, 35 insertions(+), 14 deletions(-) diff --git a/drivers/gpio/tca642x.c b/drivers/gpio/tca642x.c index 463cfe879a..7007c7a002 100644 --- a/drivers/gpio/tca642x.c +++ b/drivers/gpio/tca642x.c @@ -213,6 +213,24 @@ static int tca642x_info(uchar chip) return 0; } +static int tca642x_get_bank(int pin) +{ + int gpio_bank; + + if (pin <= 7) { + gpio_bank = 0; + } else if ((pin >= 10) && (pin <= 17)) { + gpio_bank = 1; + } else if ((pin >= 20) && (pin <= 27)) { + gpio_bank = 2; + } else { + printf("Requested pin is not available\n"); + gpio_bank = -1; + } + + return gpio_bank; +} + static struct cmd_tbl cmd_tca642x[] = { U_BOOT_CMD_MKENT(device, 3, 0, (void *)TCA642X_CMD_DEVICE, "", ""), U_BOOT_CMD_MKENT(output, 4, 0, (void *)TCA642X_CMD_OUTPUT, "", ""), @@ -226,7 +244,7 @@ static int do_tca642x(struct cmd_tbl *cmdtp, int flag, int argc, { static uchar chip = CONFIG_SYS_I2C_TCA642X_ADDR; int ret = CMD_RET_USAGE, val; - uint8_t gpio_bank = 0; + int gpio_bank = 0; uint8_t bank_shift; ulong ul_arg2 = 0; ulong ul_arg3 = 0; @@ -247,20 +265,8 @@ static int do_tca642x(struct cmd_tbl *cmdtp, int flag, int argc, ul_arg2 = simple_strtoul(argv[2], NULL, 10); /* arg3 used as pin or invert value */ - if (argc > 3) { + if (argc > 3) ul_arg3 = simple_strtoul(argv[3], NULL, 10) & 0x1; - if (ul_arg2 <= 7) { - gpio_bank = 0; - } else if ((ul_arg2 >= 10) && (ul_arg2 <= 17)) { - gpio_bank = 1; - } else if ((ul_arg2 >= 20) && (ul_arg2 <= 27)) { - gpio_bank = 2; - } else { - printf("Requested pin is not available\n"); - ret = CMD_RET_FAILURE; - goto error; - } - } switch ((int)c->cmd) { case TCA642X_CMD_INFO: @@ -277,6 +283,11 @@ static int do_tca642x(struct cmd_tbl *cmdtp, int flag, int argc, break; case TCA642X_CMD_INPUT: + gpio_bank = tca642x_get_bank(ul_arg2); + if (gpio_bank < 0) { + ret = CMD_RET_FAILURE; + goto error; + } bank_shift = ul_arg2 - (gpio_bank * 10); ret = tca642x_set_dir(chip, gpio_bank, (1 << bank_shift), TCA642X_DIR_IN << bank_shift); @@ -291,6 +302,11 @@ static int do_tca642x(struct cmd_tbl *cmdtp, int flag, int argc, break; case TCA642X_CMD_OUTPUT: + gpio_bank = tca642x_get_bank(ul_arg2); + if (gpio_bank < 0) { + ret = CMD_RET_FAILURE; + goto error; + } bank_shift = ul_arg2 - (gpio_bank * 10); ret = tca642x_set_dir(chip, gpio_bank, (1 << bank_shift), (TCA642X_DIR_OUT << bank_shift)); @@ -303,6 +319,11 @@ static int do_tca642x(struct cmd_tbl *cmdtp, int flag, int argc, break; case TCA642X_CMD_INVERT: + gpio_bank = tca642x_get_bank(ul_arg2); + if (gpio_bank < 0) { + ret = CMD_RET_FAILURE; + goto error; + } bank_shift = ul_arg2 - (gpio_bank * 10); ret = tca642x_set_pol(chip, gpio_bank, (1 << bank_shift), (ul_arg3 << bank_shift)); -- 2.26.2

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