December 2020 - U-Boot

[PATCH] km/kirkwood: enable USB support and the host controller driver
by Holger Brunck 19 Jan '21

19 Jan '21

Our kirkwood device embeds a USB host controller that is now used on some boards. This enables the support of USB and the corresponding driver. Signed-off-by: Holger Brunck <holger.brunck(a)hitachi-powergrids.com> CC: Stefan Roese <sr(a)denx.de> --- board/keymile/km_arm/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/board/keymile/km_arm/Kconfig b/board/keymile/km_arm/Kconfig index 4b21db8573..6f55cfab86 100644 --- a/board/keymile/km_arm/Kconfig +++ b/board/keymile/km_arm/Kconfig @@ -58,8 +58,12 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DM_SERIAL select DM_SPI select DM_SPI_FLASH + select USB + select USB_EHCI_HCD + select USB_EHCI_MARVELL imply CMD_CRAMFS imply CMD_DIAG imply FS_CRAMFS + imply CMD_USB endif -- 2.26.0

3 2

[PATCH 1/3] gpio: do not include <asm/arch/gpio.h> on ARCH_QEMU
by Harm Berntsen 19 Jan '21

19 Jan '21

As no gpio.h is defined for this architecture, to avoid compilation failure, do not include <asm/arch/gpio.h> for QEMU. Signed-off-by: Harm Berntsen <harm.berntsen(a)nedap.com> --- arch/arm/include/asm/gpio.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/include/asm/gpio.h b/arch/arm/include/asm/gpio.h index 6ecb876eda..7609367884 100644 --- a/arch/arm/include/asm/gpio.h +++ b/arch/arm/include/asm/gpio.h @@ -3,7 +3,8 @@ !defined(CONFIG_ARCH_BCM6858) && !defined(CONFIG_ARCH_BCM63158) && \ !defined(CONFIG_ARCH_ROCKCHIP) && !defined(CONFIG_ARCH_ASPEED) && \ !defined(CONFIG_ARCH_U8500) && !defined(CONFIG_CORTINA_PLATFORM) && \ - !defined(CONFIG_TARGET_BCMNS3) && !defined(CONFIG_TARGET_TOTAL_COMPUTE) + !defined(CONFIG_TARGET_BCMNS3) && !defined(CONFIG_TARGET_TOTAL_COMPUTE) && \ + !defined(CONFIG_ARCH_QEMU) #include <asm/arch/gpio.h> #endif #include <asm-generic/gpio.h>

2 1

[PATCH] clk: mediatek: Add MT8183 clock driver
by Fabien Parent 19 Jan '21

19 Jan '21

Add the topckgen, apmixedsys and infracfg clock driver for the MT8183 SoC. Signed-off-by: Fabien Parent <fparent(a)baylibre.com> --- drivers/clk/mediatek/Makefile | 1 + drivers/clk/mediatek/clk-mt8183.c | 823 +++++++++++++++++++++++++ include/dt-bindings/clock/mt8183-clk.h | 329 ++++++++++ 3 files changed, 1153 insertions(+) create mode 100644 drivers/clk/mediatek/clk-mt8183.c create mode 100644 include/dt-bindings/clock/mt8183-clk.h diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index 237fd17f1670..522e72422144 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -7,5 +7,6 @@ obj-$(CONFIG_MT8512) += clk-mt8512.o obj-$(CONFIG_TARGET_MT7623) += clk-mt7623.o obj-$(CONFIG_TARGET_MT7622) += clk-mt7622.o obj-$(CONFIG_TARGET_MT7629) += clk-mt7629.o +obj-$(CONFIG_TARGET_MT8183) += clk-mt8183.o obj-$(CONFIG_TARGET_MT8516) += clk-mt8516.o obj-$(CONFIG_TARGET_MT8518) += clk-mt8518.o diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-mt8183.c new file mode 100644 index 000000000000..f25f5ee740c9 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8183.c @@ -0,0 +1,823 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * MediaTek clock driver for MT8183 SoC + * + * Copyright (C) 2020 BayLibre, SAS + * Copyright (c) 2020 MediaTek Inc. + * Author: Fabien Parent <fparent(a)baylibre.com> + * Author: Weiyi Lu <weiyi.lu(a)mediatek.com> + */ + +#include <common.h> +#include <dm.h> +#include <asm/io.h> +#include <dt-bindings/clock/mt8183-clk.h> + +#include "clk-mtk.h" + +#define MT8183_PLL_FMAX (3800UL * MHZ) +#define MT8183_PLL_FMIN (1500UL * MHZ) + +/* apmixedsys */ +#define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask, _pcwbits, \ + _pcwibits, _pd_reg, _pd_shift, _pcw_reg, _pcw_shift) { \ + .id = _id, \ + .reg = _reg, \ + .pwr_reg = _pwr_reg, \ + .en_mask = _en_mask, \ + .rst_bar_mask = _rst_bar_mask, \ + .fmax = MT8183_PLL_FMAX, \ + .fmin = MT8183_PLL_FMIN, \ + .flags = _flags, \ + .pcwbits = _pcwbits, \ + .pcwibits = _pcwibits, \ + .pd_reg = _pd_reg, \ + .pd_shift = _pd_shift, \ + .pcw_reg = _pcw_reg, \ + .pcw_shift = _pcw_shift, \ + } + +static const struct mtk_pll_data apmixed_plls[] = { + PLL(CLK_APMIXED_ARMPLL_LL, 0x0200, 0x020C, 0x00000001, + HAVE_RST_BAR, BIT(24), 22, 8, 0x0204, 24, + 0x0204, 0), + PLL(CLK_APMIXED_ARMPLL_L, 0x0210, 0x021C, 0x00000001, + HAVE_RST_BAR, BIT(24), 22, 8, 0x0214, 24, + 0x0214, 0), + PLL(CLK_APMIXED_CCIPLL, 0x0290, 0x029C, 0x00000001, + HAVE_RST_BAR, BIT(24), 22, 8, 0x0294, 24, + 0x0294, 0), + PLL(CLK_APMIXED_MAINPLL, 0x0220, 0x022C, 0x00000001, + HAVE_RST_BAR, BIT(24), 22, 8, 0x0224, 24, + 0x0224, 0), + PLL(CLK_APMIXED_UNIV2PLL, 0x0230, 0x023C, 0x00000001, + HAVE_RST_BAR, BIT(24), 22, 8, 0x0234, 24, + 0x0234, 0), + PLL(CLK_APMIXED_MSDCPLL, 0x0250, 0x025C, 0x00000001, + 0, 0, 22, 8, 0x0254, 24, 0x0254, 0), + PLL(CLK_APMIXED_MMPLL, 0x0270, 0x027C, 0x00000001, + HAVE_RST_BAR, BIT(23), 22, 8, 0x0274, 24, + 0x0274, 0), + PLL(CLK_APMIXED_MFGPLL, 0x0240, 0x024C, 0x00000001, + 0, 0, 22, 8, 0x0244, 24, 0x0244, 0), + PLL(CLK_APMIXED_TVDPLL, 0x0260, 0x026C, 0x00000001, + 0, 0, 22, 8, 0x0264, 24, 0x0264, 0), + PLL(CLK_APMIXED_APLL1, 0x02A0, 0x02B0, 0x00000001, + 0, 0, 32, 8, 0x02A0, 1, 0x02A4, 0), + PLL(CLK_APMIXED_APLL2, 0x02b4, 0x02c4, 0x00000001, + 0, 0, 32, 8, 0x02B4, 1, 0x02B8, 0), +}; + +static const struct mtk_fixed_clk top_fixed_clks[] = { + FIXED_CLK(CLK_TOP_CLK26M, CLK_XTAL, 26000000), + FIXED_CLK(CLK_TOP_ULPOSC, CLK_XTAL, 250000), + FIXED_CLK(CLK_TOP_UNIVP_192M, CLK_TOP_UNIVPLL, 192000000), +}; + +static const struct mtk_fixed_factor top_fixed_divs[] = { + FACTOR(CLK_TOP_CLK13M, CLK_TOP_CLK26M, 1, 2, CLK_PARENT_TOPCKGEN), + FACTOR(CLK_TOP_F26M_CK_D2, CLK_TOP_CLK26M, 1, 2, CLK_PARENT_TOPCKGEN), + FACTOR(CLK_TOP_SYSPLL_CK, CLK_APMIXED_MAINPLL, 1, + 1, CLK_PARENT_APMIXED), + FACTOR(CLK_TOP_SYSPLL_D2, CLK_TOP_SYSPLL_CK, 1, + 2, CLK_PARENT_TOPCKGEN), + FACTOR(CLK_TOP_SYSPLL_D3, CLK_APMIXED_MAINPLL, 1, + 3, CLK_PARENT_APMIXED), + FACTOR(CLK_TOP_SYSPLL_D5, CLK_APMIXED_MAINPLL, 1, + 5, CLK_PARENT_APMIXED), + FACTOR(CLK_TOP_SYSPLL_D7, CLK_APMIXED_MAINPLL, 1, + 7, CLK_PARENT_APMIXED), + FACTOR(CLK_TOP_SYSPLL_D2_D2, CLK_TOP_SYSPLL_D2, 1, + 2, CLK_PARENT_TOPCKGEN), + FACTOR(CLK_TOP_SYSPLL_D2_D4, CLK_TOP_SYSPLL_D2, 1, + 4, CLK_PARENT_TOPCKGEN), + FACTOR(CLK_TOP_SYSPLL_D2_D8, CLK_TOP_SYSPLL_D2, 1, + 8, CLK_PARENT_TOPCKGEN), + FACTOR(CLK_TOP_SYSPLL_D2_D16, CLK_TOP_SYSPLL_D2, 1, + 16, CLK_PARENT_TOPCKGEN), + FACTOR(CLK_TOP_SYSPLL_D3_D2, CLK_TOP_SYSPLL_D3, 1, + 2, CLK_PARENT_TOPCKGEN), + FACTOR(CLK_TOP_SYSPLL_D3_D4, CLK_TOP_SYSPLL_D3, 1, + 4, CLK_PARENT_TOPCKGEN), + FACTOR(CLK_TOP_SYSPLL_D3_D8, CLK_TOP_SYSPLL_D3, 1, + 8, CLK_PARENT_TOPCKGEN), + FACTOR(CLK_TOP_SYSPLL_D5_D2, CLK_TOP_SYSPLL_D5, 1, + 2, CLK_PARENT_TOPCKGEN), + FACTOR(CLK_TOP_SYSPLL_D5_D4, CLK_TOP_SYSPLL_D5, 1, + 4, CLK_PARENT_TOPCKGEN), + FACTOR(CLK_TOP_SYSPLL_D7_D2, CLK_TOP_SYSPLL_D7, 1, + 2, CLK_PARENT_TOPCKGEN), + FACTOR(CLK_TOP_SYSPLL_D7_D4, CLK_TOP_SYSPLL_D7, 1, + 4, CLK_PARENT_TOPCKGEN), + FACTOR(CLK_TOP_UNIVPLL_CK, CLK_TOP_UNIVPLL, 1, 1, CLK_PARENT_TOPCKGEN), + FACTOR(CLK_TOP_UNIVPLL_D2, CLK_TOP_UNIVPLL_CK, 1, + 2, CLK_PARENT_TOPCKGEN), + FACTOR(CLK_TOP_UNIVPLL_D3, CLK_TOP_UNIVPLL, 1, 3, CLK_PARENT_TOPCKGEN), + FACTOR(CLK_TOP_UNIVPLL_D5, CLK_TOP_UNIVPLL, 1, 5, CLK_PARENT_TOPCKGEN), + FACTOR(CLK_TOP_UNIVPLL_D7, CLK_TOP_UNIVPLL, 1, 7, CLK_PARENT_TOPCKGEN), + FACTOR(CLK_TOP_UNIVPLL_D2_D2, CLK_TOP_UNIVPLL_D2, 1, + 2, CLK_PARENT_TOPCKGEN), + FACTOR(CLK_TOP_UNIVPLL_D2_D4, CLK_TOP_UNIVPLL_D2, 1, + 4, CLK_PARENT_TOPCKGEN), + FACTOR(CLK_TOP_UNIVPLL_D2_D8, CLK_TOP_UNIVPLL_D2, 1, + 8, CLK_PARENT_TOPCKGEN), + FACTOR(CLK_TOP_UNIVPLL_D3_D2, CLK_TOP_UNIVPLL_D3, 1, + 2, CLK_PARENT_TOPCKGEN), + FACTOR(CLK_TOP_UNIVPLL_D3_D4, CLK_TOP_UNIVPLL_D3, 1, + 4, CLK_PARENT_TOPCKGEN), + FACTOR(CLK_TOP_UNIVPLL_D3_D8, CLK_TOP_UNIVPLL_D3, 1, + 8, CLK_PARENT_TOPCKGEN), + FACTOR(CLK_TOP_UNIVPLL_D5_D2, CLK_TOP_UNIVPLL_D5, 1, + 2, CLK_PARENT_TOPCKGEN), + FACTOR(CLK_TOP_UNIVPLL_D5_D4, CLK_TOP_UNIVPLL_D5, 1, + 4, CLK_PARENT_TOPCKGEN), + FACTOR(CLK_TOP_UNIVPLL_D5_D8, CLK_TOP_UNIVPLL_D5, 1, + 8, CLK_PARENT_TOPCKGEN), + FACTOR(CLK_TOP_UNIVP_192M_CK, CLK_TOP_UNIVP_192M, 1, 1, + CLK_PARENT_TOPCKGEN), + FACTOR(CLK_TOP_UNIVP_192M_D2, CLK_TOP_UNIVP_192M_CK, 1, + 2, CLK_PARENT_TOPCKGEN), + FACTOR(CLK_TOP_UNIVP_192M_D4, CLK_TOP_UNIVP_192M_CK, 1, + 4, CLK_PARENT_TOPCKGEN), + FACTOR(CLK_TOP_UNIVP_192M_D8, CLK_TOP_UNIVP_192M_CK, 1, + 8, CLK_PARENT_TOPCKGEN), + FACTOR(CLK_TOP_UNIVP_192M_D16, CLK_TOP_UNIVP_192M_CK, 1, + 16, CLK_PARENT_TOPCKGEN), + FACTOR(CLK_TOP_UNIVP_192M_D32, CLK_TOP_UNIVP_192M_CK, 1, + 32, CLK_PARENT_TOPCKGEN), + FACTOR(CLK_TOP_APLL1_CK, CLK_APMIXED_APLL1, 1, 1, CLK_PARENT_APMIXED), + FACTOR(CLK_TOP_APLL1_D2, CLK_APMIXED_APLL1, 1, 2, CLK_PARENT_APMIXED), + FACTOR(CLK_TOP_APLL1_D4, CLK_APMIXED_APLL1, 1, 4, CLK_PARENT_APMIXED), + FACTOR(CLK_TOP_APLL1_D8, CLK_APMIXED_APLL1, 1, 8, CLK_PARENT_APMIXED), + FACTOR(CLK_TOP_APLL2_CK, CLK_APMIXED_APLL2, 1, 1, CLK_PARENT_APMIXED), + FACTOR(CLK_TOP_APLL2_D2, CLK_APMIXED_APLL2, 1, 2, CLK_PARENT_APMIXED), + FACTOR(CLK_TOP_APLL2_D4, CLK_APMIXED_APLL2, 1, 4, CLK_PARENT_APMIXED), + FACTOR(CLK_TOP_APLL2_D8, CLK_APMIXED_APLL2, 1, 8, CLK_PARENT_APMIXED), + FACTOR(CLK_TOP_TVDPLL_CK, CLK_APMIXED_TVDPLL, 1, 1, CLK_PARENT_APMIXED), + FACTOR(CLK_TOP_TVDPLL_D2, CLK_TOP_TVDPLL_CK, 1, 2, CLK_PARENT_TOPCKGEN), + FACTOR(CLK_TOP_TVDPLL_D4, CLK_APMIXED_TVDPLL, 1, 4, CLK_PARENT_APMIXED), + FACTOR(CLK_TOP_TVDPLL_D8, CLK_APMIXED_TVDPLL, 1, 8, CLK_PARENT_APMIXED), + FACTOR(CLK_TOP_TVDPLL_D16, CLK_APMIXED_TVDPLL, 1, + 16, CLK_PARENT_APMIXED), + FACTOR(CLK_TOP_MMPLL_CK, CLK_APMIXED_MMPLL, 1, 1, CLK_PARENT_APMIXED), + FACTOR(CLK_TOP_MMPLL_D4, CLK_APMIXED_MMPLL, 1, 4, CLK_PARENT_APMIXED), + FACTOR(CLK_TOP_MMPLL_D4_D2, CLK_TOP_MMPLL_D4, 1, + 2, CLK_PARENT_TOPCKGEN), + FACTOR(CLK_TOP_MMPLL_D4_D4, CLK_TOP_MMPLL_D4, 1, 4, CLK_PARENT_TOPCKGEN), + FACTOR(CLK_TOP_MMPLL_D5, CLK_APMIXED_MMPLL, 1, 5, CLK_PARENT_APMIXED), + FACTOR(CLK_TOP_MMPLL_D5_D2, CLK_TOP_MMPLL_D5, 1, + 2, CLK_PARENT_TOPCKGEN), + FACTOR(CLK_TOP_MMPLL_D5_D4, CLK_TOP_MMPLL_D5, 1, + 4, CLK_PARENT_TOPCKGEN), + FACTOR(CLK_TOP_MMPLL_D6, CLK_APMIXED_MMPLL, 1, 6, CLK_PARENT_APMIXED), + FACTOR(CLK_TOP_MMPLL_D7, CLK_APMIXED_MMPLL, 1, 7, CLK_PARENT_APMIXED), + FACTOR(CLK_TOP_MFGPLL_CK, CLK_APMIXED_MFGPLL, 1, 1, CLK_PARENT_APMIXED), + FACTOR(CLK_TOP_MSDCPLL_CK, CLK_APMIXED_MSDCPLL, 1, + 1, CLK_PARENT_APMIXED), + FACTOR(CLK_TOP_MSDCPLL_D2, CLK_APMIXED_MSDCPLL, 1, + 2, CLK_PARENT_APMIXED), + FACTOR(CLK_TOP_MSDCPLL_D4, CLK_APMIXED_MSDCPLL, 1, + 4, CLK_PARENT_APMIXED), + FACTOR(CLK_TOP_MSDCPLL_D8, CLK_APMIXED_MSDCPLL, 1, + 8, CLK_PARENT_APMIXED), + FACTOR(CLK_TOP_MSDCPLL_D16, CLK_APMIXED_MSDCPLL, 1, + 16, CLK_PARENT_APMIXED), + FACTOR(CLK_TOP_AD_OSC_CK, CLK_TOP_ULPOSC, 1, 1, CLK_PARENT_TOPCKGEN), + FACTOR(CLK_TOP_OSC_D2, CLK_TOP_ULPOSC, 1, 2, CLK_PARENT_TOPCKGEN), + FACTOR(CLK_TOP_OSC_D4, CLK_TOP_ULPOSC, 1, 4, CLK_PARENT_TOPCKGEN), + FACTOR(CLK_TOP_OSC_D8, CLK_TOP_ULPOSC, 1, 8, CLK_PARENT_TOPCKGEN), + FACTOR(CLK_TOP_OSC_D16, CLK_TOP_ULPOSC, 1, 16, CLK_PARENT_TOPCKGEN), + FACTOR(CLK_TOP_UNIVPLL, CLK_APMIXED_UNIV2PLL, 1, 2, CLK_PARENT_APMIXED), + FACTOR(CLK_TOP_UNIVPLL_D3_D16, CLK_TOP_UNIVPLL_D3, 1, + 16, CLK_PARENT_TOPCKGEN), +}; + +static const int axi_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_SYSPLL_D2_D4, + CLK_TOP_SYSPLL_D7, + CLK_TOP_OSC_D4 +}; + +static const int mm_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_MMPLL_D7, + CLK_TOP_SYSPLL_D3, + CLK_TOP_UNIVPLL_D2_D2, + CLK_TOP_SYSPLL_D2_D2, + CLK_TOP_SYSPLL_D3_D2 +}; + +static const int img_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_MMPLL_D6, + CLK_TOP_UNIVPLL_D3, + CLK_TOP_SYSPLL_D3, + CLK_TOP_UNIVPLL_D2_D2, + CLK_TOP_SYSPLL_D2_D2, + CLK_TOP_UNIVPLL_D3_D2, + CLK_TOP_SYSPLL_D3_D2 +}; + +static const int cam_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_SYSPLL_D2, + CLK_TOP_MMPLL_D6, + CLK_TOP_SYSPLL_D3, + CLK_TOP_MMPLL_D7, + CLK_TOP_UNIVPLL_D3, + CLK_TOP_UNIVPLL_D2_D2, + CLK_TOP_SYSPLL_D2_D2, + CLK_TOP_SYSPLL_D3_D2, + CLK_TOP_UNIVPLL_D3_D2 +}; + +static const int dsp_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_MMPLL_D6, + CLK_TOP_MMPLL_D7, + CLK_TOP_UNIVPLL_D3, + CLK_TOP_SYSPLL_D3, + CLK_TOP_UNIVPLL_D2_D2, + CLK_TOP_SYSPLL_D2_D2, + CLK_TOP_UNIVPLL_D3_D2, + CLK_TOP_SYSPLL_D3_D2 +}; + +static const int dsp1_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_MMPLL_D6, + CLK_TOP_MMPLL_D7, + CLK_TOP_UNIVPLL_D3, + CLK_TOP_SYSPLL_D3, + CLK_TOP_UNIVPLL_D2_D2, + CLK_TOP_SYSPLL_D2_D2, + CLK_TOP_UNIVPLL_D3_D2, + CLK_TOP_SYSPLL_D3_D2 +}; + +static const int dsp2_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_MMPLL_D6, + CLK_TOP_MMPLL_D7, + CLK_TOP_UNIVPLL_D3, + CLK_TOP_SYSPLL_D3, + CLK_TOP_UNIVPLL_D2_D2, + CLK_TOP_SYSPLL_D2_D2, + CLK_TOP_UNIVPLL_D3_D2, + CLK_TOP_SYSPLL_D3_D2 +}; + +static const int ipu_if_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_MMPLL_D6, + CLK_TOP_MMPLL_D7, + CLK_TOP_UNIVPLL_D3, + CLK_TOP_SYSPLL_D3, + CLK_TOP_UNIVPLL_D2_D2, + CLK_TOP_SYSPLL_D2_D2, + CLK_TOP_UNIVPLL_D3_D2, + CLK_TOP_SYSPLL_D3_D2 +}; + +static const int mfg_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_MFGPLL_CK, + CLK_TOP_UNIVPLL_D3, + CLK_TOP_SYSPLL_D3 +}; + +static const int f52m_mfg_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_UNIVPLL_D3_D2, + CLK_TOP_UNIVPLL_D3_D4, + CLK_TOP_UNIVPLL_D3_D8 +}; + +static const int camtg_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_UNIVP_192M_D8, + CLK_TOP_UNIVPLL_D3_D8, + CLK_TOP_UNIVP_192M_D4, + CLK_TOP_UNIVPLL_D3_D16, + CLK_TOP_F26M_CK_D2, + CLK_TOP_UNIVP_192M_D16, + CLK_TOP_UNIVP_192M_D32 +}; + +static const int camtg2_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_UNIVP_192M_D8, + CLK_TOP_UNIVPLL_D3_D8, + CLK_TOP_UNIVP_192M_D4, + CLK_TOP_UNIVPLL_D3_D16, + CLK_TOP_F26M_CK_D2, + CLK_TOP_UNIVP_192M_D16, + CLK_TOP_UNIVP_192M_D32 +}; + +static const int camtg3_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_UNIVP_192M_D8, + CLK_TOP_UNIVPLL_D3_D8, + CLK_TOP_UNIVP_192M_D4, + CLK_TOP_UNIVPLL_D3_D16, + CLK_TOP_F26M_CK_D2, + CLK_TOP_UNIVP_192M_D16, + CLK_TOP_UNIVP_192M_D32 +}; + +static const int camtg4_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_UNIVP_192M_D8, + CLK_TOP_UNIVPLL_D3_D8, + CLK_TOP_UNIVP_192M_D4, + CLK_TOP_UNIVPLL_D3_D16, + CLK_TOP_F26M_CK_D2, + CLK_TOP_UNIVP_192M_D16, + CLK_TOP_UNIVP_192M_D32 +}; + +static const int uart_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_UNIVPLL_D3_D8 +}; + +static const int spi_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_SYSPLL_D5_D2, + CLK_TOP_SYSPLL_D3_D4, + CLK_TOP_MSDCPLL_D4 +}; + +static const int msdc50_hclk_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_SYSPLL_D2_D2, + CLK_TOP_SYSPLL_D3_D2 +}; + +static const int msdc50_0_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_MSDCPLL_CK, + CLK_TOP_MSDCPLL_D2, + CLK_TOP_UNIVPLL_D2_D4, + CLK_TOP_SYSPLL_D3_D2, + CLK_TOP_UNIVPLL_D2_D2 +}; + +static const int msdc30_1_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_UNIVPLL_D3_D2, + CLK_TOP_SYSPLL_D3_D2, + CLK_TOP_SYSPLL_D7, + CLK_TOP_MSDCPLL_D2 +}; + +static const int msdc30_2_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_UNIVPLL_D3_D2, + CLK_TOP_SYSPLL_D3_D2, + CLK_TOP_SYSPLL_D7, + CLK_TOP_MSDCPLL_D2 +}; + +static const int audio_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_SYSPLL_D5_D4, + CLK_TOP_SYSPLL_D7_D4, + CLK_TOP_SYSPLL_D2_D16 +}; + +static const int aud_intbus_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_SYSPLL_D2_D4, + CLK_TOP_SYSPLL_D7_D2 +}; + +static const int pmicspi_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_SYSPLL_D2_D8, + CLK_TOP_OSC_D8 +}; + +static const int fpwrap_ulposc_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_OSC_D16, + CLK_TOP_OSC_D4, + CLK_TOP_OSC_D8 +}; + +static const int atb_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_SYSPLL_D2_D2, + CLK_TOP_SYSPLL_D5 +}; + +static const int sspm_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_UNIVPLL_D2_D4, + CLK_TOP_SYSPLL_D2_D2, + CLK_TOP_UNIVPLL_D2_D2, + CLK_TOP_SYSPLL_D3 +}; + +static const int dpi0_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_TVDPLL_D2, + CLK_TOP_TVDPLL_D4, + CLK_TOP_TVDPLL_D8, + CLK_TOP_TVDPLL_D16, + CLK_TOP_UNIVPLL_D5_D2, + CLK_TOP_UNIVPLL_D3_D4, + CLK_TOP_SYSPLL_D3_D4, + CLK_TOP_UNIVPLL_D3_D8 +}; + +static const int scam_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_SYSPLL_D5_D2 +}; + +static const int disppwm_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_UNIVPLL_D3_D4, + CLK_TOP_OSC_D2, + CLK_TOP_OSC_D4, + CLK_TOP_OSC_D16 +}; + +static const int usb_top_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_UNIVPLL_D5_D4, + CLK_TOP_UNIVPLL_D3_D4, + CLK_TOP_UNIVPLL_D5_D2 +}; + +static const int ssusb_top_xhci_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_UNIVPLL_D5_D4, + CLK_TOP_UNIVPLL_D3_D4, + CLK_TOP_UNIVPLL_D5_D2 +}; + +static const int spm_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_SYSPLL_D2_D8 +}; + +static const int i2c_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_SYSPLL_D2_D8, + CLK_TOP_UNIVPLL_D5_D2 +}; + +static const int scp_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_UNIVPLL_D2_D8, + CLK_TOP_SYSPLL_D5, + CLK_TOP_SYSPLL_D2_D2, + CLK_TOP_UNIVPLL_D2_D2, + CLK_TOP_SYSPLL_D3, + CLK_TOP_UNIVPLL_D3 +}; + +static const int seninf_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_UNIVPLL_D2_D2, + CLK_TOP_UNIVPLL_D3_D2, + CLK_TOP_UNIVPLL_D2_D4 +}; + +static const int dxcc_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_SYSPLL_D2_D2, + CLK_TOP_SYSPLL_D2_D4, + CLK_TOP_SYSPLL_D2_D8 +}; + +static const int aud_engen1_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_APLL1_D2, + CLK_TOP_APLL1_D4, + CLK_TOP_APLL1_D8 +}; + +static const int aud_engen2_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_APLL2_D2, + CLK_TOP_APLL2_D4, + CLK_TOP_APLL2_D8 +}; + +static const int faes_ufsfde_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_SYSPLL_D2, + CLK_TOP_SYSPLL_D2_D2, + CLK_TOP_SYSPLL_D3, + CLK_TOP_SYSPLL_D2_D4, + CLK_TOP_UNIVPLL_D3 +}; + +static const int fufs_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_SYSPLL_D2_D4, + CLK_TOP_SYSPLL_D2_D8, + CLK_TOP_SYSPLL_D2_D16 +}; + +static const int aud_1_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_APLL1_CK +}; + +static const int aud_2_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_APLL2_CK +}; + +static const struct mtk_composite top_muxes[] = { + /* CLK_CFG_0 */ + MUX(CLK_TOP_MUX_AXI, axi_parents, 0x40, 0, 2), + MUX(CLK_TOP_MUX_MM, mm_parents, 0x40, 8, 3), + MUX(CLK_TOP_MUX_IMG, img_parents, 0x40, 16, 3), + MUX(CLK_TOP_MUX_CAM, cam_parents, 0x40, 24, 4), + /* CLK_CFG_1 */ + MUX(CLK_TOP_MUX_DSP, dsp_parents, 0x50, 0, 4), + MUX(CLK_TOP_MUX_DSP1, dsp1_parents, 0x50, 8, 4), + MUX(CLK_TOP_MUX_DSP2, dsp2_parents, 0x50, 16, 4), + MUX(CLK_TOP_MUX_IPU_IF, ipu_if_parents, 0x50, 24, 4), + /* CLK_CFG_2 */ + MUX(CLK_TOP_MUX_MFG, mfg_parents, 0x60, 0, 2), + MUX(CLK_TOP_MUX_F52M_MFG, f52m_mfg_parents, 0x60, 8, 2), + MUX(CLK_TOP_MUX_CAMTG, camtg_parents, 0x60, 16, 3), + MUX(CLK_TOP_MUX_CAMTG2, camtg2_parents, 0x60, 24, 3), + /* CLK_CFG_3 */ + MUX(CLK_TOP_MUX_CAMTG3, camtg3_parents, 0x70, 0, 3), + MUX(CLK_TOP_MUX_CAMTG4, camtg4_parents, 0x70, 8, 3), + MUX(CLK_TOP_MUX_UART, uart_parents, 0x70, 16, 1), + MUX(CLK_TOP_MUX_SPI, spi_parents, 0x70, 24, 2), + /* CLK_CFG_4 */ + MUX(CLK_TOP_MUX_MSDC50_0_HCLK, msdc50_hclk_parents, 0x80, 0, 2), + MUX(CLK_TOP_MUX_MSDC50_0, msdc50_0_parents, 0x80, 8, 3), + MUX(CLK_TOP_MUX_MSDC30_1, msdc30_1_parents, 0x80, 16, 3), + MUX(CLK_TOP_MUX_MSDC30_2, msdc30_2_parents, 0x80, 24, 3), + /* CLK_CFG_5 */ + MUX(CLK_TOP_MUX_AUDIO, audio_parents, 0x90, 0, 2), + MUX(CLK_TOP_MUX_AUD_INTBUS, aud_intbus_parents, 0x90, 8, 2), + MUX(CLK_TOP_MUX_PMICSPI, pmicspi_parents, 0x90, 16, 2), + MUX(CLK_TOP_MUX_FPWRAP_ULPOSC, fpwrap_ulposc_parents, 0x90, 24, 2), + /* CLK_CFG_6 */ + MUX(CLK_TOP_MUX_ATB, atb_parents, 0xa0, 0, 2), + MUX(CLK_TOP_MUX_SSPM, sspm_parents, 0xa0, 8, 3), + MUX(CLK_TOP_MUX_DPI0, dpi0_parents, 0xa0, 16, 4), + MUX(CLK_TOP_MUX_SCAM, scam_parents, 0xa0, 24, 1), + /* CLK_CFG_7 */ + MUX(CLK_TOP_MUX_DISP_PWM, disppwm_parents, 0xb0, 0, 3), + MUX(CLK_TOP_MUX_USB_TOP, usb_top_parents, 0xb0, 8, 2), + MUX(CLK_TOP_MUX_SSUSB_TOP_XHCI, ssusb_top_xhci_parents, 0xb0, 16, 2), + MUX(CLK_TOP_MUX_SPM, spm_parents, 0xb0, 24, 1), + /* CLK_CFG_8 */ + MUX(CLK_TOP_MUX_I2C, i2c_parents, 0xc0, 0, 2), + MUX(CLK_TOP_MUX_SCP, scp_parents, 0xc0, 8, 3), + MUX(CLK_TOP_MUX_SENINF, seninf_parents, 0xc0, 16, 2), + MUX(CLK_TOP_MUX_DXCC, dxcc_parents, 0xc0, 24, 2), + /* CLK_CFG_9 */ + MUX(CLK_TOP_MUX_AUD_ENG1, aud_engen1_parents, 0xd0, 0, 2), + MUX(CLK_TOP_MUX_AUD_ENG2, aud_engen2_parents, 0xd0, 8, 2), + MUX(CLK_TOP_MUX_FAES_UFSFDE, faes_ufsfde_parents, 0xd0, 16, 3), + MUX(CLK_TOP_MUX_FUFS, fufs_parents, 0xd0, 24, 2), + /* CLK_CFG_10 */ + MUX(CLK_TOP_MUX_AUD_1, aud_1_parents, 0xe0, 0, 1), + MUX(CLK_TOP_MUX_AUD_2, aud_2_parents, 0xe0, 8, 1), +}; + +static const struct mtk_clk_tree mt8183_clk_tree = { + .xtal_rate = 26 * MHZ, + .xtal2_rate = 26 * MHZ, + .fdivs_offs = CLK_TOP_CLK13M, + .muxes_offs = CLK_TOP_MUX_AXI, + .plls = apmixed_plls, + .fclks = top_fixed_clks, + .fdivs = top_fixed_divs, + .muxes = top_muxes, +}; + +static const struct mtk_gate_regs infra0_cg_regs = { + .set_ofs = 0x80, + .clr_ofs = 0x84, + .sta_ofs = 0x90, +}; + +static const struct mtk_gate_regs infra1_cg_regs = { + .set_ofs = 0x88, + .clr_ofs = 0x8c, + .sta_ofs = 0x94, +}; + +static const struct mtk_gate_regs infra2_cg_regs = { + .set_ofs = 0xa4, + .clr_ofs = 0xa8, + .sta_ofs = 0xac, +}; + +static const struct mtk_gate_regs infra3_cg_regs = { + .set_ofs = 0xc0, + .clr_ofs = 0xc4, + .sta_ofs = 0xc8, +}; + +#define GATE_INFRA0(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &infra0_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \ + } + +#define GATE_INFRA1(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &infra1_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \ + } + +#define GATE_INFRA2(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &infra2_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \ + } + +#define GATE_INFRA3(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &infra3_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \ + } + +static const struct mtk_gate infra_clks[] = { + /* INFRA0 */ + GATE_INFRA0(CLK_INFRA_PMIC_TMR, CLK_TOP_MUX_AXI, 0), + GATE_INFRA0(CLK_INFRA_PMIC_AP, CLK_TOP_MUX_AXI, 1), + GATE_INFRA0(CLK_INFRA_PMIC_MD, CLK_TOP_MUX_AXI, 2), + GATE_INFRA0(CLK_INFRA_PMIC_CONN, CLK_TOP_MUX_AXI, 3), + GATE_INFRA0(CLK_INFRA_SCPSYS, CLK_TOP_MUX_SCP, 4), + GATE_INFRA0(CLK_INFRA_SEJ, CLK_TOP_CLK26M, 5), + GATE_INFRA0(CLK_INFRA_APXGPT, CLK_TOP_MUX_AXI, 6), + GATE_INFRA0(CLK_INFRA_ICUSB, CLK_TOP_MUX_AXI, 8), + GATE_INFRA0(CLK_INFRA_GCE, CLK_TOP_MUX_AXI, 9), + GATE_INFRA0(CLK_INFRA_THERM, CLK_TOP_MUX_AXI, 10), + GATE_INFRA0(CLK_INFRA_I2C0, CLK_TOP_MUX_I2C, 11), + GATE_INFRA0(CLK_INFRA_I2C1, CLK_TOP_MUX_I2C, 12), + GATE_INFRA0(CLK_INFRA_I2C2, CLK_TOP_MUX_I2C, 13), + GATE_INFRA0(CLK_INFRA_I2C3, CLK_TOP_MUX_I2C, 14), + GATE_INFRA0(CLK_INFRA_PWM_HCLK, CLK_TOP_MUX_AXI, 15), + GATE_INFRA0(CLK_INFRA_PWM1, CLK_TOP_MUX_I2C, 16), + GATE_INFRA0(CLK_INFRA_PWM2, CLK_TOP_MUX_I2C, 17), + GATE_INFRA0(CLK_INFRA_PWM3, CLK_TOP_MUX_I2C, 18), + GATE_INFRA0(CLK_INFRA_PWM4, CLK_TOP_MUX_I2C, 19), + GATE_INFRA0(CLK_INFRA_PWM, CLK_TOP_MUX_I2C, 21), + GATE_INFRA0(CLK_INFRA_UART0, CLK_TOP_MUX_UART, 22), + GATE_INFRA0(CLK_INFRA_UART1, CLK_TOP_MUX_UART, 23), + GATE_INFRA0(CLK_INFRA_UART2, CLK_TOP_MUX_UART, 24), + GATE_INFRA0(CLK_INFRA_UART3, CLK_TOP_MUX_UART, 25), + GATE_INFRA0(CLK_INFRA_GCE_26M, CLK_TOP_MUX_AXI, 27), + GATE_INFRA0(CLK_INFRA_CQ_DMA_FPC, CLK_TOP_MUX_AXI, 28), + GATE_INFRA0(CLK_INFRA_BTIF, CLK_TOP_MUX_AXI, 31), + /* INFRA1 */ + GATE_INFRA1(CLK_INFRA_SPI0, CLK_TOP_MUX_SPI, 1), + GATE_INFRA1(CLK_INFRA_MSDC0, CLK_TOP_MUX_MSDC50_0_HCLK, 2), + GATE_INFRA1(CLK_INFRA_MSDC1, CLK_TOP_MUX_AXI, 4), + GATE_INFRA1(CLK_INFRA_MSDC2, CLK_TOP_MUX_AXI, 5), + GATE_INFRA1(CLK_INFRA_MSDC0_SCK, CLK_TOP_MUX_MSDC50_0, 6), + GATE_INFRA1(CLK_INFRA_DVFSRC, CLK_TOP_CLK26M, 7), + GATE_INFRA1(CLK_INFRA_GCPU, CLK_TOP_MUX_AXI, 8), + GATE_INFRA1(CLK_INFRA_TRNG, CLK_TOP_MUX_AXI, 9), + GATE_INFRA1(CLK_INFRA_AUXADC, CLK_TOP_CLK26M, 10), + GATE_INFRA1(CLK_INFRA_CPUM, CLK_TOP_MUX_AXI, 11), + GATE_INFRA1(CLK_INFRA_CCIF1_AP, CLK_TOP_MUX_AXI, 12), + GATE_INFRA1(CLK_INFRA_CCIF1_MD, CLK_TOP_MUX_AXI, 13), + GATE_INFRA1(CLK_INFRA_AUXADC_MD, CLK_TOP_CLK26M, 14), + GATE_INFRA1(CLK_INFRA_MSDC1_SCK, CLK_TOP_MUX_MSDC30_1, 16), + GATE_INFRA1(CLK_INFRA_MSDC2_SCK, CLK_TOP_MUX_MSDC30_2, 17), + GATE_INFRA1(CLK_INFRA_AP_DMA, CLK_TOP_MUX_AXI, 18), + GATE_INFRA1(CLK_INFRA_XIU, CLK_TOP_MUX_AXI, 19), + GATE_INFRA1(CLK_INFRA_DEVICE_APC, CLK_TOP_MUX_AXI, 20), + GATE_INFRA1(CLK_INFRA_CCIF_AP, CLK_TOP_MUX_AXI, 23), + GATE_INFRA1(CLK_INFRA_DEBUGSYS, CLK_TOP_MUX_AXI, 24), + GATE_INFRA1(CLK_INFRA_AUDIO, CLK_TOP_MUX_AXI, 25), + GATE_INFRA1(CLK_INFRA_CCIF_MD, CLK_TOP_MUX_AXI, 26), + GATE_INFRA1(CLK_INFRA_DXCC_SEC_CORE, CLK_TOP_MUX_DXCC, 27), + GATE_INFRA1(CLK_INFRA_DXCC_AO, CLK_TOP_MUX_DXCC, 28), + GATE_INFRA1(CLK_INFRA_DEVMPU_BCLK, CLK_TOP_MUX_AXI, 30), + GATE_INFRA1(CLK_INFRA_DRAMC_F26M, CLK_TOP_CLK26M, 31), + /* INFRA2 */ + GATE_INFRA2(CLK_INFRA_IRTX, CLK_TOP_CLK26M, 0), + GATE_INFRA2(CLK_INFRA_USB, CLK_TOP_MUX_USB_TOP, 1), + GATE_INFRA2(CLK_INFRA_DISP_PWM, CLK_TOP_MUX_AXI, 2), + GATE_INFRA2(CLK_INFRA_CLDMA_BCLK, CLK_TOP_MUX_AXI, 3), + GATE_INFRA2(CLK_INFRA_AUDIO_26M_BCLK, CLK_TOP_CLK26M, 4), + GATE_INFRA2(CLK_INFRA_SPI1, CLK_TOP_MUX_SPI, 6), + GATE_INFRA2(CLK_INFRA_I2C4, CLK_TOP_MUX_I2C, 7), + GATE_INFRA2(CLK_INFRA_MODEM_TEMP_SHARE, CLK_TOP_CLK26M, 8), + GATE_INFRA2(CLK_INFRA_SPI2, CLK_TOP_MUX_SPI, 9), + GATE_INFRA2(CLK_INFRA_SPI3, CLK_TOP_MUX_SPI, 10), + GATE_INFRA2(CLK_INFRA_UNIPRO_SCK, CLK_TOP_MUX_SSUSB_TOP_XHCI, 11), + GATE_INFRA2(CLK_INFRA_UNIPRO_TICK, CLK_TOP_MUX_FUFS, 12), + GATE_INFRA2(CLK_INFRA_UFS_MP_SAP_BCLK, CLK_TOP_MUX_FUFS, 13), + GATE_INFRA2(CLK_INFRA_MD32_BCLK, CLK_TOP_MUX_AXI, 14), + GATE_INFRA2(CLK_INFRA_UNIPRO_MBIST, CLK_TOP_MUX_AXI, 16), + GATE_INFRA2(CLK_INFRA_I2C5, CLK_TOP_MUX_I2C, 18), + GATE_INFRA2(CLK_INFRA_I2C5_ARBITER, CLK_TOP_MUX_I2C, 19), + GATE_INFRA2(CLK_INFRA_I2C5_IMM, CLK_TOP_MUX_I2C, 20), + GATE_INFRA2(CLK_INFRA_I2C1_ARBITER, CLK_TOP_MUX_I2C, 21), + GATE_INFRA2(CLK_INFRA_I2C1_IMM, CLK_TOP_MUX_I2C, 22), + GATE_INFRA2(CLK_INFRA_I2C2_ARBITER, CLK_TOP_MUX_I2C, 23), + GATE_INFRA2(CLK_INFRA_I2C2_IMM, CLK_TOP_MUX_I2C, 24), + GATE_INFRA2(CLK_INFRA_SPI4, CLK_TOP_MUX_SPI, 25), + GATE_INFRA2(CLK_INFRA_SPI5, CLK_TOP_MUX_SPI, 26), + GATE_INFRA2(CLK_INFRA_CQ_DMA, CLK_TOP_MUX_AXI, 27), + GATE_INFRA2(CLK_INFRA_UFS, CLK_TOP_MUX_FUFS, 28), + GATE_INFRA2(CLK_INFRA_AES_UFSFDE, CLK_TOP_MUX_FAES_UFSFDE, 29), + GATE_INFRA2(CLK_INFRA_UFS_TICK, CLK_TOP_MUX_FUFS, 30), + /* INFRA3 */ + GATE_INFRA3(CLK_INFRA_MSDC0_SELF, CLK_TOP_MUX_MSDC50_0, 0), + GATE_INFRA3(CLK_INFRA_MSDC1_SELF, CLK_TOP_MUX_MSDC50_0, 1), + GATE_INFRA3(CLK_INFRA_MSDC2_SELF, CLK_TOP_MUX_MSDC50_0, 2), + GATE_INFRA3(CLK_INFRA_UFS_AXI, CLK_TOP_MUX_AXI, 5), + GATE_INFRA3(CLK_INFRA_I2C6, CLK_TOP_MUX_I2C, 6), + GATE_INFRA3(CLK_INFRA_AP_MSDC0, CLK_TOP_MUX_MSDC50_0_HCLK, 7), + GATE_INFRA3(CLK_INFRA_MD_MSDC0, CLK_TOP_MUX_MSDC50_0_HCLK, 8), + GATE_INFRA3(CLK_INFRA_CCIF2_AP, CLK_TOP_MUX_AXI, 16), + GATE_INFRA3(CLK_INFRA_CCIF2_MD, CLK_TOP_MUX_AXI, 17), + GATE_INFRA3(CLK_INFRA_CCIF3_AP, CLK_TOP_MUX_AXI, 18), + GATE_INFRA3(CLK_INFRA_CCIF3_MD, CLK_TOP_MUX_AXI, 19), + GATE_INFRA3(CLK_INFRA_SEJ_F13M, CLK_TOP_CLK26M, 20), + GATE_INFRA3(CLK_INFRA_AES_BCLK, CLK_TOP_MUX_AXI, 21), + GATE_INFRA3(CLK_INFRA_I2C7, CLK_TOP_MUX_I2C, 22), + GATE_INFRA3(CLK_INFRA_I2C8, CLK_TOP_MUX_I2C, 23), + GATE_INFRA3(CLK_INFRA_FBIST2FPC, CLK_TOP_MUX_MSDC50_0, 24), +}; + +static int mt8183_apmixedsys_probe(struct udevice *dev) +{ + return mtk_common_clk_init(dev, &mt8183_clk_tree); +} + +static int mt8183_topckgen_probe(struct udevice *dev) +{ + return mtk_common_clk_init(dev, &mt8183_clk_tree); +} + +static int mt8183_infracfg_probe(struct udevice *dev) +{ + return mtk_common_clk_gate_init(dev, &mt8183_clk_tree, infra_clks); +} + +static const struct udevice_id mt8183_apmixed_compat[] = { + { .compatible = "mediatek,mt8183-apmixedsys", }, + { } +}; + +static const struct udevice_id mt8183_topckgen_compat[] = { + { .compatible = "mediatek,mt8183-topckgen", }, + { } +}; + +static const struct udevice_id mt8183_infracfg_compat[] = { + { .compatible = "mediatek,mt8183-infracfg", }, + { } +}; + +U_BOOT_DRIVER(mtk_clk_apmixedsys) = { + .name = "mt8183-apmixedsys", + .id = UCLASS_CLK, + .of_match = mt8183_apmixed_compat, + .probe = mt8183_apmixedsys_probe, + .priv_auto_alloc_size = sizeof(struct mtk_clk_priv), + .ops = &mtk_clk_apmixedsys_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +U_BOOT_DRIVER(mtk_clk_topckgen) = { + .name = "mt8183-topckgen", + .id = UCLASS_CLK, + .of_match = mt8183_topckgen_compat, + .probe = mt8183_topckgen_probe, + .priv_auto_alloc_size = sizeof(struct mtk_clk_priv), + .ops = &mtk_clk_topckgen_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +U_BOOT_DRIVER(mtk_clk_infracfg) = { + .name = "mt8183-infracfg", + .id = UCLASS_CLK, + .of_match = mt8183_infracfg_compat, + .probe = mt8183_infracfg_probe, + .priv_auto_alloc_size = sizeof(struct mtk_clk_priv), + .ops = &mtk_clk_gate_ops, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/include/dt-bindings/clock/mt8183-clk.h b/include/dt-bindings/clock/mt8183-clk.h new file mode 100644 index 000000000000..f7e6367ce844 --- /dev/null +++ b/include/dt-bindings/clock/mt8183-clk.h @@ -0,0 +1,329 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2020 MediaTek Inc. + * Author: Weiyi Lu <weiyi.lu(a)mediatek.com> + */ + +#ifndef _DT_BINDINGS_CLK_MT8183_H +#define _DT_BINDINGS_CLK_MT8183_H + +/* APMIXED */ +#define CLK_APMIXED_ARMPLL_LL 0 +#define CLK_APMIXED_ARMPLL_L 1 +#define CLK_APMIXED_CCIPLL 2 +#define CLK_APMIXED_MAINPLL 3 +#define CLK_APMIXED_UNIV2PLL 4 +#define CLK_APMIXED_MSDCPLL 5 +#define CLK_APMIXED_MMPLL 6 +#define CLK_APMIXED_MFGPLL 7 +#define CLK_APMIXED_TVDPLL 8 +#define CLK_APMIXED_APLL1 9 +#define CLK_APMIXED_APLL2 10 +#define CLK_APMIXED_SSUSB_26M 11 +#define CLK_APMIXED_APPLL_26M 12 +#define CLK_APMIXED_MIPIC0_26M 13 +#define CLK_APMIXED_MDPLLGP_26M 14 +#define CLK_APMIXED_MMSYS_26M 15 +#define CLK_APMIXED_UFS_26M 16 +#define CLK_APMIXED_MIPIC1_26M 17 +#define CLK_APMIXED_MEMPLL_26M 18 +#define CLK_APMIXED_CLKSQ_LVPLL_26M 19 +#define CLK_APMIXED_MIPID0_26M 20 +#define CLK_APMIXED_MIPID1_26M 21 +#define CLK_APMIXED_NR_CLK 22 + +/* TOPCKGEN */ +#define CLK_TOP_CLK26M 0 +#define CLK_TOP_ULPOSC 1 +#define CLK_TOP_UNIVP_192M 2 +#define CLK_TOP_CLK13M 3 +#define CLK_TOP_F26M_CK_D2 4 +#define CLK_TOP_SYSPLL_CK 5 +#define CLK_TOP_SYSPLL_D2 6 +#define CLK_TOP_SYSPLL_D3 7 +#define CLK_TOP_SYSPLL_D5 8 +#define CLK_TOP_SYSPLL_D7 9 +#define CLK_TOP_SYSPLL_D2_D2 10 +#define CLK_TOP_SYSPLL_D2_D4 11 +#define CLK_TOP_SYSPLL_D2_D8 12 +#define CLK_TOP_SYSPLL_D2_D16 13 +#define CLK_TOP_SYSPLL_D3_D2 14 +#define CLK_TOP_SYSPLL_D3_D4 15 +#define CLK_TOP_SYSPLL_D3_D8 16 +#define CLK_TOP_SYSPLL_D5_D2 17 +#define CLK_TOP_SYSPLL_D5_D4 18 +#define CLK_TOP_SYSPLL_D7_D2 19 +#define CLK_TOP_SYSPLL_D7_D4 20 +#define CLK_TOP_UNIVPLL_CK 21 +#define CLK_TOP_UNIVPLL_D2 22 +#define CLK_TOP_UNIVPLL_D3 23 +#define CLK_TOP_UNIVPLL_D5 24 +#define CLK_TOP_UNIVPLL_D7 25 +#define CLK_TOP_UNIVPLL_D2_D2 26 +#define CLK_TOP_UNIVPLL_D2_D4 27 +#define CLK_TOP_UNIVPLL_D2_D8 28 +#define CLK_TOP_UNIVPLL_D3_D2 29 +#define CLK_TOP_UNIVPLL_D3_D4 30 +#define CLK_TOP_UNIVPLL_D3_D8 31 +#define CLK_TOP_UNIVPLL_D5_D2 32 +#define CLK_TOP_UNIVPLL_D5_D4 33 +#define CLK_TOP_UNIVPLL_D5_D8 34 +#define CLK_TOP_UNIVP_192M_CK 35 +#define CLK_TOP_UNIVP_192M_D2 36 +#define CLK_TOP_UNIVP_192M_D4 37 +#define CLK_TOP_UNIVP_192M_D8 38 +#define CLK_TOP_UNIVP_192M_D16 39 +#define CLK_TOP_UNIVP_192M_D32 40 +#define CLK_TOP_APLL1_CK 41 +#define CLK_TOP_APLL1_D2 42 +#define CLK_TOP_APLL1_D4 43 +#define CLK_TOP_APLL1_D8 44 +#define CLK_TOP_APLL2_CK 45 +#define CLK_TOP_APLL2_D2 46 +#define CLK_TOP_APLL2_D4 47 +#define CLK_TOP_APLL2_D8 48 +#define CLK_TOP_TVDPLL_CK 49 +#define CLK_TOP_TVDPLL_D2 50 +#define CLK_TOP_TVDPLL_D4 51 +#define CLK_TOP_TVDPLL_D8 52 +#define CLK_TOP_TVDPLL_D16 53 +#define CLK_TOP_MMPLL_CK 54 +#define CLK_TOP_MMPLL_D4 55 +#define CLK_TOP_MMPLL_D4_D2 56 +#define CLK_TOP_MMPLL_D4_D4 57 +#define CLK_TOP_MMPLL_D5 58 +#define CLK_TOP_MMPLL_D5_D2 59 +#define CLK_TOP_MMPLL_D5_D4 60 +#define CLK_TOP_MMPLL_D6 61 +#define CLK_TOP_MMPLL_D7 62 +#define CLK_TOP_MFGPLL_CK 63 +#define CLK_TOP_MSDCPLL_CK 64 +#define CLK_TOP_MSDCPLL_D2 65 +#define CLK_TOP_MSDCPLL_D4 66 +#define CLK_TOP_MSDCPLL_D8 67 +#define CLK_TOP_MSDCPLL_D16 68 +#define CLK_TOP_AD_OSC_CK 69 +#define CLK_TOP_OSC_D2 70 +#define CLK_TOP_OSC_D4 71 +#define CLK_TOP_OSC_D8 72 +#define CLK_TOP_OSC_D16 73 +#define CLK_TOP_UNIVPLL 74 +#define CLK_TOP_UNIVPLL_D3_D16 75 +#define CLK_TOP_APLL12_DIV0 76 +#define CLK_TOP_APLL12_DIV1 77 +#define CLK_TOP_APLL12_DIV2 78 +#define CLK_TOP_APLL12_DIV3 79 +#define CLK_TOP_APLL12_DIV4 80 +#define CLK_TOP_APLL12_DIVB 81 +#define CLK_TOP_ARMPLL_DIV_PLL1 82 +#define CLK_TOP_ARMPLL_DIV_PLL2 83 +#define CLK_TOP_MUX_AXI 84 +#define CLK_TOP_MUX_MM 85 +#define CLK_TOP_MUX_IMG 86 +#define CLK_TOP_MUX_CAM 87 +#define CLK_TOP_MUX_DSP 88 +#define CLK_TOP_MUX_DSP1 89 +#define CLK_TOP_MUX_DSP2 90 +#define CLK_TOP_MUX_IPU_IF 91 +#define CLK_TOP_MUX_MFG 92 +#define CLK_TOP_MUX_F52M_MFG 93 +#define CLK_TOP_MUX_CAMTG 94 +#define CLK_TOP_MUX_CAMTG2 95 +#define CLK_TOP_MUX_CAMTG3 96 +#define CLK_TOP_MUX_CAMTG4 97 +#define CLK_TOP_MUX_UART 98 +#define CLK_TOP_MUX_SPI 99 +#define CLK_TOP_MUX_MSDC50_0_HCLK 100 +#define CLK_TOP_MUX_MSDC50_0 101 +#define CLK_TOP_MUX_MSDC30_1 102 +#define CLK_TOP_MUX_MSDC30_2 103 +#define CLK_TOP_MUX_AUDIO 104 +#define CLK_TOP_MUX_AUD_INTBUS 105 +#define CLK_TOP_MUX_PMICSPI 106 +#define CLK_TOP_MUX_FPWRAP_ULPOSC 107 +#define CLK_TOP_MUX_ATB 108 +#define CLK_TOP_MUX_SSPM 109 +#define CLK_TOP_MUX_DPI0 110 +#define CLK_TOP_MUX_SCAM 111 +#define CLK_TOP_MUX_DISP_PWM 112 +#define CLK_TOP_MUX_USB_TOP 113 +#define CLK_TOP_MUX_SSUSB_TOP_XHCI 114 +#define CLK_TOP_MUX_SPM 115 +#define CLK_TOP_MUX_I2C 116 +#define CLK_TOP_MUX_SCP 117 +#define CLK_TOP_MUX_SENINF 118 +#define CLK_TOP_MUX_DXCC 119 +#define CLK_TOP_MUX_AUD_ENG1 120 +#define CLK_TOP_MUX_AUD_ENG2 121 +#define CLK_TOP_MUX_FAES_UFSFDE 122 +#define CLK_TOP_MUX_FUFS 123 +#define CLK_TOP_MUX_AUD_1 124 +#define CLK_TOP_MUX_AUD_2 125 +#define CLK_TOP_MUX_APLL_I2S0 126 +#define CLK_TOP_MUX_APLL_I2S1 127 +#define CLK_TOP_MUX_APLL_I2S2 128 +#define CLK_TOP_MUX_APLL_I2S3 129 +#define CLK_TOP_MUX_APLL_I2S4 130 +#define CLK_TOP_MUX_APLL_I2S5 131 +#define CLK_TOP_NR_CLK 132 + +/* INFRACFG_AO */ +#define CLK_INFRA_PMIC_TMR 0 +#define CLK_INFRA_PMIC_AP 1 +#define CLK_INFRA_PMIC_MD 2 +#define CLK_INFRA_PMIC_CONN 3 +#define CLK_INFRA_SCPSYS 4 +#define CLK_INFRA_SEJ 5 +#define CLK_INFRA_APXGPT 6 +#define CLK_INFRA_ICUSB 7 +#define CLK_INFRA_GCE 8 +#define CLK_INFRA_THERM 9 +#define CLK_INFRA_I2C0 10 +#define CLK_INFRA_I2C1 11 +#define CLK_INFRA_I2C2 12 +#define CLK_INFRA_I2C3 13 +#define CLK_INFRA_PWM_HCLK 14 +#define CLK_INFRA_PWM1 15 +#define CLK_INFRA_PWM2 16 +#define CLK_INFRA_PWM3 17 +#define CLK_INFRA_PWM4 18 +#define CLK_INFRA_PWM 19 +#define CLK_INFRA_UART0 20 +#define CLK_INFRA_UART1 21 +#define CLK_INFRA_UART2 22 +#define CLK_INFRA_UART3 23 +#define CLK_INFRA_GCE_26M 24 +#define CLK_INFRA_CQ_DMA_FPC 25 +#define CLK_INFRA_BTIF 26 +#define CLK_INFRA_SPI0 27 +#define CLK_INFRA_MSDC0 28 +#define CLK_INFRA_MSDC1 29 +#define CLK_INFRA_MSDC2 30 +#define CLK_INFRA_MSDC0_SCK 31 +#define CLK_INFRA_DVFSRC 32 +#define CLK_INFRA_GCPU 33 +#define CLK_INFRA_TRNG 34 +#define CLK_INFRA_AUXADC 35 +#define CLK_INFRA_CPUM 36 +#define CLK_INFRA_CCIF1_AP 37 +#define CLK_INFRA_CCIF1_MD 38 +#define CLK_INFRA_AUXADC_MD 39 +#define CLK_INFRA_MSDC1_SCK 40 +#define CLK_INFRA_MSDC2_SCK 41 +#define CLK_INFRA_AP_DMA 42 +#define CLK_INFRA_XIU 43 +#define CLK_INFRA_DEVICE_APC 44 +#define CLK_INFRA_CCIF_AP 45 +#define CLK_INFRA_DEBUGSYS 46 +#define CLK_INFRA_AUDIO 47 +#define CLK_INFRA_CCIF_MD 48 +#define CLK_INFRA_DXCC_SEC_CORE 49 +#define CLK_INFRA_DXCC_AO 50 +#define CLK_INFRA_DRAMC_F26M 51 +#define CLK_INFRA_IRTX 52 +#define CLK_INFRA_DISP_PWM 53 +#define CLK_INFRA_CLDMA_BCLK 54 +#define CLK_INFRA_AUDIO_26M_BCLK 55 +#define CLK_INFRA_SPI1 56 +#define CLK_INFRA_I2C4 57 +#define CLK_INFRA_MODEM_TEMP_SHARE 58 +#define CLK_INFRA_SPI2 59 +#define CLK_INFRA_SPI3 60 +#define CLK_INFRA_UNIPRO_SCK 61 +#define CLK_INFRA_UNIPRO_TICK 62 +#define CLK_INFRA_UFS_MP_SAP_BCLK 63 +#define CLK_INFRA_MD32_BCLK 64 +#define CLK_INFRA_SSPM 65 +#define CLK_INFRA_UNIPRO_MBIST 66 +#define CLK_INFRA_SSPM_BUS_HCLK 67 +#define CLK_INFRA_I2C5 68 +#define CLK_INFRA_I2C5_ARBITER 69 +#define CLK_INFRA_I2C5_IMM 70 +#define CLK_INFRA_I2C1_ARBITER 71 +#define CLK_INFRA_I2C1_IMM 72 +#define CLK_INFRA_I2C2_ARBITER 73 +#define CLK_INFRA_I2C2_IMM 74 +#define CLK_INFRA_SPI4 75 +#define CLK_INFRA_SPI5 76 +#define CLK_INFRA_CQ_DMA 77 +#define CLK_INFRA_UFS 78 +#define CLK_INFRA_AES_UFSFDE 79 +#define CLK_INFRA_UFS_TICK 80 +#define CLK_INFRA_MSDC0_SELF 81 +#define CLK_INFRA_MSDC1_SELF 82 +#define CLK_INFRA_MSDC2_SELF 83 +#define CLK_INFRA_SSPM_26M_SELF 84 +#define CLK_INFRA_SSPM_32K_SELF 85 +#define CLK_INFRA_UFS_AXI 86 +#define CLK_INFRA_I2C6 87 +#define CLK_INFRA_AP_MSDC0 88 +#define CLK_INFRA_MD_MSDC0 89 +#define CLK_INFRA_USB 90 +#define CLK_INFRA_DEVMPU_BCLK 91 +#define CLK_INFRA_CCIF2_AP 92 +#define CLK_INFRA_CCIF2_MD 93 +#define CLK_INFRA_CCIF3_AP 94 +#define CLK_INFRA_CCIF3_MD 95 +#define CLK_INFRA_SEJ_F13M 96 +#define CLK_INFRA_AES_BCLK 97 +#define CLK_INFRA_I2C7 98 +#define CLK_INFRA_I2C8 99 +#define CLK_INFRA_FBIST2FPC 100 +#define CLK_INFRA_NR_CLK 101 + +/* MMSYS_CONFIG */ +#define CLK_MM_SMI_COMMON 0 +#define CLK_MM_SMI_LARB0 1 +#define CLK_MM_SMI_LARB1 2 +#define CLK_MM_GALS_COMM0 3 +#define CLK_MM_GALS_COMM1 4 +#define CLK_MM_GALS_CCU2MM 5 +#define CLK_MM_GALS_IPU12MM 6 +#define CLK_MM_GALS_IMG2MM 7 +#define CLK_MM_GALS_CAM2MM 8 +#define CLK_MM_GALS_IPU2MM 9 +#define CLK_MM_MDP_DL_TXCK 10 +#define CLK_MM_IPU_DL_TXCK 11 +#define CLK_MM_MDP_RDMA0 12 +#define CLK_MM_MDP_RDMA1 13 +#define CLK_MM_MDP_RSZ0 14 +#define CLK_MM_MDP_RSZ1 15 +#define CLK_MM_MDP_TDSHP 16 +#define CLK_MM_MDP_WROT0 17 +#define CLK_MM_FAKE_ENG 18 +#define CLK_MM_DISP_OVL0 19 +#define CLK_MM_DISP_OVL0_2L 20 +#define CLK_MM_DISP_OVL1_2L 21 +#define CLK_MM_DISP_RDMA0 22 +#define CLK_MM_DISP_RDMA1 23 +#define CLK_MM_DISP_WDMA0 24 +#define CLK_MM_DISP_COLOR0 25 +#define CLK_MM_DISP_CCORR0 26 +#define CLK_MM_DISP_AAL0 27 +#define CLK_MM_DISP_GAMMA0 28 +#define CLK_MM_DISP_DITHER0 29 +#define CLK_MM_DISP_SPLIT 30 +#define CLK_MM_DSI0_MM 31 +#define CLK_MM_DSI0_IF 32 +#define CLK_MM_DPI_MM 33 +#define CLK_MM_DPI_IF 34 +#define CLK_MM_FAKE_ENG2 35 +#define CLK_MM_MDP_DL_RX 36 +#define CLK_MM_IPU_DL_RX 37 +#define CLK_MM_26M 38 +#define CLK_MM_MMSYS_R2Y 39 +#define CLK_MM_DISP_RSZ 40 +#define CLK_MM_MDP_WDMA0 41 +#define CLK_MM_MDP_AAL 42 +#define CLK_MM_MDP_CCORR 43 +#define CLK_MM_DBI_MM 44 +#define CLK_MM_DBI_IF 45 +#define CLK_MM_NR_CLK 46 + +/* MCUCFG */ +#define CLK_MCU_MP0_SEL 0 +#define CLK_MCU_MP2_SEL 1 +#define CLK_MCU_BUS_SEL 2 +#define CLK_MCU_NR_CLK 3 + +#endif /* _DT_BINDINGS_CLK_MT8183_H */ -- 2.28.0

2 1

[PATCH] tools: mtk_image: add support for booting ARM64 images
by Fabien Parent 19 Jan '21

19 Jan '21

mkimage is only able to package aarch32 binaries. Add support for AArch64 images. One can create a ARM64 image using the following command line: mkimage -T mtk_image -a 0x201000 -e 0x201000 -n "media=emmc;arm64=1" -d bl2.bin bl2.img Signed-off-by: Fabien Parent <fparent(a)baylibre.com> --- tools/mtk_image.c | 28 ++++++++++++++++++++++++---- tools/mtk_image.h | 6 +++++- 2 files changed, 29 insertions(+), 5 deletions(-) diff --git a/tools/mtk_image.c b/tools/mtk_image.c index 2ca519483d33..bde1e5da4bec 100644 --- a/tools/mtk_image.c +++ b/tools/mtk_image.c @@ -246,6 +246,7 @@ static const struct brom_img_type { /* Image type selected by user */ static enum brlyt_img_type hdr_media; static int use_lk_hdr; +static bool is_arm64_image; /* LK image name */ static char lk_name[32] = "U-Boot"; @@ -276,6 +277,7 @@ static int mtk_brom_parse_imagename(const char *imagename) static const char *media = ""; static const char *nandinfo = ""; static const char *lk = ""; + static const char *arm64_param = ""; key = buf; while (key) { @@ -323,6 +325,9 @@ static int mtk_brom_parse_imagename(const char *imagename) if (!strcmp(key, "lkname")) snprintf(lk_name, sizeof(lk_name), "%s", val); + + if (!strcmp(key, "arm64")) + arm64_param = val; } if (next) @@ -354,6 +359,9 @@ static int mtk_brom_parse_imagename(const char *imagename) } } + if (arm64_param && arm64_param[0] == '1') + is_arm64_image = true; + free(buf); if (hdr_media == BRLYT_TYPE_INVALID) { @@ -458,6 +466,9 @@ static int mtk_image_verify_gen_header(const uint8_t *ptr, int print) le32_to_cpu(gfh->file_info.load_addr) + le32_to_cpu(gfh->file_info.jump_offset)); + if (print) + printf("Architecture: %s\n", is_arm64_image ? "ARM64" : "ARM"); + return 0; } @@ -523,6 +534,9 @@ static int mtk_image_verify_nand_header(const uint8_t *ptr, int print) le32_to_cpu(gfh->file_info.load_addr) + le32_to_cpu(gfh->file_info.jump_offset)); + if (print) + printf("Architecture: %s\n", is_arm64_image ? "ARM64" : "ARM"); + return 0; } @@ -581,6 +595,8 @@ static void put_ghf_common_header(struct gfh_common_header *gfh, int size, static void put_ghf_header(struct gfh_header *gfh, int file_size, int dev_hdr_size, int load_addr, int flash_type) { + uint32_t cfg_bits; + memset(gfh, 0, sizeof(struct gfh_header)); /* GFH_FILE_INFO header */ @@ -608,11 +624,15 @@ static void put_ghf_header(struct gfh_header *gfh, int file_size, /* GFH_BROM_CFG header */ put_ghf_common_header(&gfh->brom_cfg.gfh, sizeof(gfh->brom_cfg), GFH_TYPE_BROM_CFG, 3); - gfh->brom_cfg.cfg_bits = cpu_to_le32( - GFH_BROM_CFG_USBDL_AUTO_DETECT_DIS | - GFH_BROM_CFG_USBDL_BY_KCOL0_TIMEOUT_EN | - GFH_BROM_CFG_USBDL_BY_FLAG_TIMEOUT_EN); + cfg_bits = GFH_BROM_CFG_USBDL_AUTO_DETECT_DIS | + GFH_BROM_CFG_USBDL_BY_KCOL0_TIMEOUT_EN | + GFH_BROM_CFG_USBDL_BY_FLAG_TIMEOUT_EN; gfh->brom_cfg.usbdl_by_kcol0_timeout_ms = cpu_to_le32(5000); + if (is_arm64_image) { + gfh->brom_cfg.jump_bl_arm64 = GFH_BROM_CFG_JUMP_BL_ARM64; + cfg_bits |= GFH_BROM_CFG_JUMP_BL_ARM64_EN; + } + gfh->brom_cfg.cfg_bits = cpu_to_le32(cfg_bits); /* GFH_BL_SEC_KEY header */ put_ghf_common_header(&gfh->bl_sec_key.gfh, sizeof(gfh->bl_sec_key), diff --git a/tools/mtk_image.h b/tools/mtk_image.h index 4e78b3d0ff0b..7dda71ce88a5 100644 --- a/tools/mtk_image.h +++ b/tools/mtk_image.h @@ -136,7 +136,9 @@ struct gfh_brom_cfg { struct gfh_common_header gfh; uint32_t cfg_bits; uint32_t usbdl_by_auto_detect_timeout_ms; - uint8_t unused[0x48]; + uint8_t unused[0x45]; + uint8_t jump_bl_arm64; + uint8_t unused2[2]; uint32_t usbdl_by_kcol0_timeout_ms; uint32_t usbdl_by_flag_timeout_ms; uint32_t pad; @@ -146,6 +148,8 @@ struct gfh_brom_cfg { #define GFH_BROM_CFG_USBDL_AUTO_DETECT_DIS 0x10 #define GFH_BROM_CFG_USBDL_BY_KCOL0_TIMEOUT_EN 0x80 #define GFH_BROM_CFG_USBDL_BY_FLAG_TIMEOUT_EN 0x100 +#define GFH_BROM_CFG_JUMP_BL_ARM64_EN 0x1000 +#define GFH_BROM_CFG_JUMP_BL_ARM64 0x64 struct gfh_bl_sec_key { struct gfh_common_header gfh; -- 2.28.0

2 1

[PATCH v2 0/6] add support for sama7g5 ethernet interfaces
by Claudiu Beznea 19 Jan '21

19 Jan '21

Hi, This series add support for SAMA7G5 ethernet interfaces: one gigabit interface and one 10/100Mbps interface. Thank you, Claudiu Beznea Changes in v2: - fix compilation error on patch 6/6 for wb50n_defconfig Claudiu Beznea (6): net: macb: use dummy descriptor for RBQP net: macb: add user io config data structure net: macb: check clk_set_rate return value to be negative net: macb: add support for sama7g5 gmac net: macb: add support for sama7g5 emac net: macb: take into account all RGMII interface types drivers/net/macb.c | 101 +++++++++++++++++++++++++++++++++++++++++++++-------- drivers/net/macb.h | 2 ++ 2 files changed, 89 insertions(+), 14 deletions(-) -- 2.7.4

2 7

[v2 00/33] gpio: layerscape: fix gpio bug and enable gpio
by Biwen Li 19 Jan '21

19 Jan '21

From: Biwen Li <biwen.li(a)nxp.com> Change in v2: - fix warnings when check patches - enable gpio command for boards ls1021atwr, ls1021aqds Biwen Li (33): gpio: mpc8xxx_gpio: fix a bug on ls1046ardb arm: dts: ls1021a: add gpio node arm64: dts: ls1012a: add gpio node arm64: dts: ls1028a: add gpio node arm64: dts: ls1043a: add gpio node arm64: dts: ls1046a: add gpio node arm64: dts: ls1088a: add gpio node arm64: dts: ls208xa: add gpio node configs: ls1012a: enable CONFIG_MPC8XXX_GPIO configs: ls1043a: enable CONFIG_MPC8XXX_GPIO configs: ls1028a: enable CONFIG_MPC8XXX_GPIO configs: ls1088a: enable CONFIG_MPC8XXX_GPIO configs: ls208xa: enable CONFIG_MPC8XXX_GPIO configs: lx2160a: enable CONFIG_MPC8XXX_GPIO configs: ls1046a: enable MPC8XXX_GPIO configs: ls1021atwr: enable CONFIG_MPC8XXX_GPIO configs: ls1021aqds: enable CONFIG_MPC8XXX_GPIO configs: ls1012afrwy: enable CMD_GPIO configs: ls1012ardb: enable CMD_GPIO configs: ls1021aqds: enable CMD_GPIO configs: ls1021atwr: enable CMD_GPIO configs: ls1028aqds: enable CMD_GPIO configs: ls1028ardb: enable CMD_GPIO configs: ls1043aqds: enable CMD_GPIO configs: ls1043ardb: enable CMD_GPIO configs: ls1046ardb: enable CMD_GPIO configs: ls1046aqds: enable CMD_GPIO configs: ls2088ardb: enable DM_GPIO and CMD_GPIO configs: ls2088aqds: enable CMD_GPIO configs: ls1088aqds: enable DM_GPIO and CMD_GPIO configs: ls1088ardb: enable DM_GPIO and CMD_GPIO configs: lx2160ardb: enable CMD_GPIO configs: lx2160aqds: enable CMD_GPIO arch/arm/dts/fsl-ls1012a.dtsi | 20 ++++++++ arch/arm/dts/fsl-ls1028a.dtsi | 33 +++++++++++++ arch/arm/dts/fsl-ls1043a.dtsi | 40 ++++++++++++++++ arch/arm/dts/fsl-ls1046a.dtsi | 40 ++++++++++++++++ arch/arm/dts/fsl-ls1088a.dtsi | 46 +++++++++++++++++++ arch/arm/dts/fsl-ls2080a.dtsi | 45 ++++++++++++++++++ arch/arm/dts/ls1021a.dtsi | 40 ++++++++++++++++ .../asm/arch-fsl-layerscape/immap_lsch3.h | 10 ++++ .../ls1012afrwy_qspi_SECURE_BOOT_defconfig | 1 + configs/ls1012afrwy_qspi_defconfig | 1 + configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig | 1 + configs/ls1012afrwy_tfa_defconfig | 1 + configs/ls1012ardb_qspi_SECURE_BOOT_defconfig | 1 + configs/ls1012ardb_qspi_defconfig | 1 + configs/ls1012ardb_tfa_SECURE_BOOT_defconfig | 1 + configs/ls1012ardb_tfa_defconfig | 1 + configs/ls1021aqds_ddr4_nor_defconfig | 1 + configs/ls1021aqds_ddr4_nor_lpuart_defconfig | 1 + configs/ls1021aqds_nand_defconfig | 1 + configs/ls1021aqds_nor_SECURE_BOOT_defconfig | 1 + configs/ls1021aqds_nor_defconfig | 1 + configs/ls1021aqds_nor_lpuart_defconfig | 1 + configs/ls1021aqds_qspi_defconfig | 1 + configs/ls1021aqds_sdcard_ifc_defconfig | 1 + configs/ls1021aqds_sdcard_qspi_defconfig | 1 + configs/ls1021atwr_nor_SECURE_BOOT_defconfig | 1 + configs/ls1021atwr_nor_defconfig | 1 + configs/ls1021atwr_nor_lpuart_defconfig | 1 + configs/ls1021atwr_qspi_defconfig | 1 + ...s1021atwr_sdcard_ifc_SECURE_BOOT_defconfig | 1 + configs/ls1021atwr_sdcard_ifc_defconfig | 1 + configs/ls1021atwr_sdcard_qspi_defconfig | 1 + configs/ls1028aqds_tfa_SECURE_BOOT_defconfig | 1 + configs/ls1028aqds_tfa_defconfig | 1 + configs/ls1028aqds_tfa_lpuart_defconfig | 1 + configs/ls1028ardb_tfa_SECURE_BOOT_defconfig | 1 + configs/ls1028ardb_tfa_defconfig | 1 + configs/ls1043aqds_defconfig | 1 + configs/ls1043aqds_lpuart_defconfig | 1 + configs/ls1043aqds_nand_defconfig | 1 + configs/ls1043aqds_nor_ddr3_defconfig | 1 + configs/ls1043aqds_qspi_defconfig | 1 + configs/ls1043aqds_sdcard_ifc_defconfig | 1 + configs/ls1043aqds_sdcard_qspi_defconfig | 1 + configs/ls1043aqds_tfa_SECURE_BOOT_defconfig | 1 + configs/ls1043aqds_tfa_defconfig | 1 + configs/ls1043ardb_SECURE_BOOT_defconfig | 1 + configs/ls1043ardb_defconfig | 1 + configs/ls1043ardb_nand_SECURE_BOOT_defconfig | 1 + configs/ls1043ardb_nand_defconfig | 1 + .../ls1043ardb_sdcard_SECURE_BOOT_defconfig | 1 + configs/ls1043ardb_sdcard_defconfig | 1 + configs/ls1043ardb_tfa_SECURE_BOOT_defconfig | 1 + configs/ls1043ardb_tfa_defconfig | 1 + configs/ls1046aqds_SECURE_BOOT_defconfig | 1 + configs/ls1046aqds_defconfig | 1 + configs/ls1046aqds_lpuart_defconfig | 1 + configs/ls1046aqds_nand_defconfig | 1 + configs/ls1046aqds_qspi_defconfig | 1 + configs/ls1046aqds_sdcard_ifc_defconfig | 1 + configs/ls1046aqds_sdcard_qspi_defconfig | 1 + configs/ls1046aqds_tfa_SECURE_BOOT_defconfig | 1 + configs/ls1046aqds_tfa_defconfig | 1 + configs/ls1046ardb_emmc_defconfig | 1 + configs/ls1046ardb_qspi_SECURE_BOOT_defconfig | 1 + configs/ls1046ardb_qspi_defconfig | 1 + configs/ls1046ardb_qspi_spl_defconfig | 1 + .../ls1046ardb_sdcard_SECURE_BOOT_defconfig | 1 + configs/ls1046ardb_sdcard_defconfig | 1 + configs/ls1046ardb_tfa_SECURE_BOOT_defconfig | 1 + configs/ls1046ardb_tfa_defconfig | 1 + configs/ls1088aqds_defconfig | 2 + configs/ls1088aqds_qspi_SECURE_BOOT_defconfig | 2 + configs/ls1088aqds_qspi_defconfig | 2 + configs/ls1088aqds_sdcard_ifc_defconfig | 2 + configs/ls1088aqds_sdcard_qspi_defconfig | 2 + configs/ls1088aqds_tfa_defconfig | 1 + configs/ls1088ardb_qspi_SECURE_BOOT_defconfig | 2 + configs/ls1088ardb_qspi_defconfig | 2 + ...1088ardb_sdcard_qspi_SECURE_BOOT_defconfig | 2 + configs/ls1088ardb_sdcard_qspi_defconfig | 2 + configs/ls1088ardb_tfa_SECURE_BOOT_defconfig | 1 + configs/ls1088ardb_tfa_defconfig | 1 + configs/ls2088aqds_tfa_defconfig | 1 + configs/ls2088ardb_qspi_SECURE_BOOT_defconfig | 2 + configs/ls2088ardb_qspi_defconfig | 2 + configs/ls2088ardb_tfa_SECURE_BOOT_defconfig | 1 + configs/ls2088ardb_tfa_defconfig | 1 + configs/lx2160aqds_tfa_SECURE_BOOT_defconfig | 1 + configs/lx2160aqds_tfa_defconfig | 1 + configs/lx2160ardb_tfa_SECURE_BOOT_defconfig | 1 + configs/lx2160ardb_tfa_defconfig | 1 + configs/lx2160ardb_tfa_stmm_defconfig | 1 + drivers/gpio/mpc8xxx_gpio.c | 45 +++--------------- include/configs/ls1012a_common.h | 7 +++ include/configs/ls1021aqds.h | 7 +++ include/configs/ls1021atwr.h | 7 +++ include/configs/ls1028a_common.h | 7 +++ include/configs/ls1043a_common.h | 7 +++ include/configs/ls1046a_common.h | 7 +++ include/configs/ls1088a_common.h | 7 +++ include/configs/ls2080a_common.h | 7 +++ include/configs/lx2160a_common.h | 7 +++ 103 files changed, 440 insertions(+), 38 deletions(-) -- 2.17.1

2 34

[PATCH] lib: zlib: our putc() takes only one argument
by Heinrich Schuchardt 18 Jan '21

18 Jan '21

In contrast to the C99 standard [1] our putc() takes only one argument. [1] ISO/IEC 9899:1999 Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- lib/zlib/deflate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/zlib/deflate.c b/lib/zlib/deflate.c index 1fe58d5da6..63473359e4 100644 --- a/lib/zlib/deflate.c +++ b/lib/zlib/deflate.c @@ -1284,7 +1284,7 @@ local void check_match(s, start, match, length) } if (z_verbose > 1) { fprintf(stderr,"\\[%d,%d]", start-match, length); - do { putc(s->window[start++], stderr); } while (--length != 0); + do { putc(s->window[start++]); } while (--length != 0); } } #else -- 2.29.2

2 1

[PATCH 1/1] lib: zlib: include ctype.h
by Heinrich Schuchardt 18 Jan '21

18 Jan '21

Our ctype.h is in include/linux/ Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- lib/zlib/trees.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/zlib/trees.c b/lib/zlib/trees.c index 3e09517ed0..700c62f6d7 100644 --- a/lib/zlib/trees.c +++ b/lib/zlib/trees.c @@ -38,7 +38,7 @@ #include "deflate.h" #ifdef DEBUG -# include <ctype.h> +# include <linux/ctype.h> #endif /* =========================================================================== -- 2.29.2

2 1

[PATCH 1/1] lib: aes: build failure with DEBUG=1
by Heinrich Schuchardt 18 Jan '21

18 Jan '21

Building fails with DEBUG=1: lib/aes.c: In function ‘debug_print_vector’: lib/aes.c:622:45: error: cast from pointer to integer of different size [-Werror=pointer-to-int-cast] 622 | printf("%s [%d] @0x%08x", name, num_bytes, (u32)data); Pointers can only be cast to (uintptr_t). But anyway we have %p for printing pointers. Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- lib/aes.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/aes.c b/lib/aes.c index c998aecb3c..05ec235702 100644 --- a/lib/aes.c +++ b/lib/aes.c @@ -619,7 +619,7 @@ void aes_decrypt(u32 key_len, u8 *in, u8 *expkey, u8 *out) static void debug_print_vector(char *name, u32 num_bytes, u8 *data) { #ifdef DEBUG - printf("%s [%d] @0x%08x", name, num_bytes, (u32)data); + printf("%s [%d] @0x%p", name, num_bytes, data); print_buffer(0, data, 1, num_bytes, 16); #endif } -- 2.29.2

3 2

[PATCH 1/3] common: Makefile: drop duplicated line
by Peng Fan (OSS) 18 Jan '21

18 Jan '21

From: Peng Fan <peng.fan(a)nxp.com> obj-$(CONFIG_$(SPL_TPL_)YMODEM_SUPPORT) += xyzModem.o is there, no need obj-$(CONFIG_SPL_YMODEM_SUPPORT) += xyzModem.o Signed-off-by: Peng Fan <peng.fan(a)nxp.com> --- common/Makefile | 1 - 1 file changed, 1 deletion(-) diff --git a/common/Makefile b/common/Makefile index bcf352d016..daeea67cf2 100644 --- a/common/Makefile +++ b/common/Makefile @@ -68,7 +68,6 @@ obj-$(CONFIG_DFU_OVER_USB) += dfu.o endif obj-$(CONFIG_SPL_HASH_SUPPORT) += hash.o obj-$(CONFIG_TPL_HASH_SUPPORT) += hash.o -obj-$(CONFIG_SPL_YMODEM_SUPPORT) += xyzModem.o obj-$(CONFIG_SPL_LOAD_FIT) += common_fit.o obj-$(CONFIG_SPL_NET_SUPPORT) += miiphyutil.o obj-$(CONFIG_$(SPL_TPL_)OF_LIBFDT) += fdt_support.o -- 2.28.0

4 8