November 2020 - U-Boot

[PATCH RFC 00/20] MIPS: Add support for JZ4730 and Skytone Alpha 400
by Lubomir Rintel 18 Nov '20

18 Nov '20

Hi, chained to his message are patches that implement support for the Ingenic JZ4730 MIPS SoC and a laptop that's based around it. Please consider this RFC-quality: there are some known issues that need to be resolved before some of the patches could be applied (indicated in some of the patches themselves) and there are also certainly issues unknown to me that would be obvious to others given I haven't really submitted code to U-Boot apart from some very trifial stuff. I'll be very thankful for any feeback. The hardware support added by this patch set is essentially equivalent to vendor U-Boot that's shipped with the machine: boot off NAND works, MMC, UART and Ethernet are supported. LCD, GPIO matrix keyboard and OHCI USB don't work at this point. CONFIG_DISTRO_DEFAULT makes it convenient to run custom kernels in place of the vendor's one, but the compatibility with the vendor kernels is retained. The first three patches are not actually JZ4730 specific, but they are dependend on by the JZ4730 work: [PATCH RFC 01/20] config: Remove CONFIG_SYS_ID_EEPROM [PATCH RFC 02/20] mtd: Allow building nand_spl_simple w/o SPL_NAND_ECC [PATCH RFC 03/20] cmd/mac: Don't build unless CONFIG_CMD_MAC is enabled The rest of the patches implement JZ4730 hardware support: [PATCH RFC 04/20] mips: Don't access CP0_EBASE on JZ47XX [PATCH RFC 05/20] ns16550: Turn on the UME bit if on ARCH_JZ47XX [PATCH RFC 06/20] clk: Add driver for Ingenic JZ4730 CGU [PATCH RFC 07/20] timer-uclass: Tolerate failure to get clock rate in [PATCH RFC 08/20] timer: Add Ingenic JZ4730 timer driver [PATCH RFC 09/20] mmc: Default to JZ47XX_MMC=y on ARCH_JZ47XX [PATCH RFC 10/20] mmc/jz_mmc: Add a JZ4740 compatible string [PATCH RFC 11/20] mmc/jz_mmc: Support wp-gpio/cd-gpio [PATCH RFC 12/20] pinctrl: Add Ingenic JZ4730 pin control and GPIO driver [PATCH RFC 13/20] nand: Use correct prototype of board_nand_init() with [PATCH RFC 14/20] nand/raw: Add Ingenic JZ4730 NAND flash driver [PATCH RFC 15/20] watchdog: Add Ingenic JZ4730 watchdog timer driver [PATCH RFC 16/20] net: Add Ingenic JZ4730 Ethernet driver [PATCH RFC 17/20] mips: dts: Add Ingenic JZ4730 [PATCH RFC 18/20] mips/mach-jz47xx: Add Ingenic JZ4730 support [PATCH RFC 19/20] mips: dts: Add Skytone Alpha 400 [PATCH RFC 20/20] board: Add Skytone Alpha 400 In case someone finds git more convenient to work with than e-mail, here you go: git pull git://git.kernel.org/pub/scm/linux/kernel/git/lkundrak/u-boot.git lr/alpha400 Thank you Lubo

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Re: [U-Boot] [PATCH v2 4/4] Correct return code from builtin_run_command_list()
by Estilo y Alma Recordz 18 Nov '20

18 Nov '20

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Re: [U-Boot] [GIT PULL] fpga changes
by Estilo y Alma Recordz 18 Nov '20

18 Nov '20

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Re: [U-Boot] [PATCH 0/2] kbuild - trivial fixes
by Estilo y Alma Recordz 18 Nov '20

18 Nov '20

dc276b0113694ecc62913311e2580857754aa890173dfaa9d95afad6396bb741 " , " environmentId

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Re: [U-Boot] [PATCH v2 02/11] Do not apply: tools: add genkconfig
by Estilo y Alma Recordz 18 Nov '20

18 Nov '20

dc276b0113694ecc62913311e2580857754aa890173dfaa9d95afad6396bb741 " , " environmentId

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[PATCH v3] sunxi: add PineCube board
by Icenowy Zheng 18 Nov '20

18 Nov '20

PineCube is an IP camera development kit released by Pine64. It comes with the following compoents: - A mainboard with Sochip S3 SoC, a 16MByte SPI Flash, AXP209 PMIC, a power-only microUSB connector, a USB Type-A connector, a 10/100Mbps Ethernet port and FPC connectors for camera and daughter board. - An OV5640-based camera module which is connected to the parallel CSI bus of the mainboard. - A daughterboard with several buttons, a SD slot, some IR LEDs, a microphone and a speaker connector. As the device tree is synchronized in a previous commit, just add it to Makefile, create a new MAINTAINER item and provide a defconfig. Signed-off-by: Icenowy Zheng <icenowy(a)aosc.io> --- Changes since v2: - Add Makefile reference to DT. Changes since v1: - Dropped LDO3 quirk. arch/arm/dts/Makefile | 1 + board/sunxi/MAINTAINERS | 5 +++++ configs/pinecube_defconfig | 15 +++++++++++++++ 3 files changed, 21 insertions(+) create mode 100644 configs/pinecube_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 7d1a369845..e6993733b0 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -587,6 +587,7 @@ dtb-$(CONFIG_MACH_SUN8I_R40) += \ sun8i-r40-bananapi-m2-ultra.dtb \ sun8i-v40-bananapi-m2-berry.dtb dtb-$(CONFIG_MACH_SUN8I_V3S) += \ + sun8i-s3-pinecube.dtb \ sun8i-v3s-licheepi-zero.dtb dtb-$(CONFIG_MACH_SUN50I_H5) += \ sun50i-h5-bananapi-m2-plus.dtb \ diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index d3755ae41a..735801ae1d 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -440,6 +440,11 @@ M: Vasily Khoruzhick <anarsoul(a)gmail.com> S: Maintained F: configs/pinebook_defconfig +PINECUBE BOARD: +M: Icenowy Zheng <icenowy(a)aosc.io> +S: Maintained +F: configs/pinecube_defconfig + PINE64 BOARDS M: Andre Przywara <andre.przywara(a)arm.com> S: Maintained diff --git a/configs/pinecube_defconfig b/configs/pinecube_defconfig new file mode 100644 index 0000000000..a8c404f6b1 --- /dev/null +++ b/configs/pinecube_defconfig @@ -0,0 +1,15 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_SPL=y +CONFIG_MACH_SUN8I_V3S=y +CONFIG_SUNXI_DRAM_DDR3_1333=y +CONFIG_DRAM_CLK=504 +CONFIG_DRAM_ODT_EN=y +CONFIG_I2C0_ENABLE=y +CONFIG_DEFAULT_DEVICE_TREE="sun8i-s3-pinecube" +CONFIG_SPL_I2C_SUPPORT=y +# CONFIG_NETDEVICES is not set +CONFIG_AXP209_POWER=y +CONFIG_AXP_DCDC2_VOLT=1250 +CONFIG_AXP_DCDC3_VOLT=3300 +CONFIG_CONS_INDEX=3 -- 2.28.0

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[PATCH 00/26] TI J7 SoC HSM Rearch support series
by Tero Kristo 18 Nov '20

18 Nov '20

Hello, On TI J7 SoCs the device manager firmware is now split into two portions instead of the existing one which supported all services via a single firmware image running on DMSC core. Now, the existing DMSC core is dedicated for secure services only, and the PM and RM functionality is moved under a separate firmware image running on MCU R5 core. This is completely transparent for the firmware users, as the existing messaging mechanism (TI-SCI) routes everything to proper destination, except for anything that runs on MCU R5, and in our case it happens to be R5 SPL bootloader. To support the firmware split, R5 SPL implementation must be changed in a way that it implements its own PM features, as these are needed during boot time. This series thus implements a couple of new drivers, PLL clock driver for the SoCs, and also a generic clock provider driver which is used to attach device drivers to proper clock entries. Also implemented is a power domain driver to power up/down IP blocks. R5 SPL bootloader also now needs to load and start the new DM firmware image and this is handled in the series. There are also a number of fixes attached to the series for fixing issues noticed while implementing the new drivers, mostly on the generic clock drivers side. I decided to keep the series as a single chunk for now, as it probably makes it easier to see why certain things are done. Let me know if you want me to split this series somehow. -Tero -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki

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[PATCH v2] sunxi: add PineCube board
by Icenowy Zheng 18 Nov '20

18 Nov '20

PineCube is an IP camera development kit released by Pine64. It comes with the following compoents: - A mainboard with Sochip S3 SoC, a 16MByte SPI Flash, AXP209 PMIC, a power-only microUSB connector, a USB Type-A connector, a 10/100Mbps Ethernet port and FPC connectors for camera and daughter board. - An OV5640-based camera module which is connected to the parallel CSI bus of the mainboard. - A daughterboard with several buttons, a SD slot, some IR LEDs, a microphone and a speaker connector. As the device tree is synchronized in a previous commit, just add MAINTAINER item and a defconfig. Signed-off-by: Icenowy Zheng <icenowy(a)aosc.io> --- Changes in v2: - Removed LDO3 hack in U-Boot because LDO3 is kept disabled in U-Boot. board/sunxi/MAINTAINERS | 5 +++++ configs/pinecube_defconfig | 15 +++++++++++++++ 2 files changed, 20 insertions(+) create mode 100644 configs/pinecube_defconfig diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index d3755ae41a..735801ae1d 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -440,6 +440,11 @@ M: Vasily Khoruzhick <anarsoul(a)gmail.com> S: Maintained F: configs/pinebook_defconfig +PINECUBE BOARD: +M: Icenowy Zheng <icenowy(a)aosc.io> +S: Maintained +F: configs/pinecube_defconfig + PINE64 BOARDS M: Andre Przywara <andre.przywara(a)arm.com> S: Maintained diff --git a/configs/pinecube_defconfig b/configs/pinecube_defconfig new file mode 100644 index 0000000000..a8c404f6b1 --- /dev/null +++ b/configs/pinecube_defconfig @@ -0,0 +1,15 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_SPL=y +CONFIG_MACH_SUN8I_V3S=y +CONFIG_SUNXI_DRAM_DDR3_1333=y +CONFIG_DRAM_CLK=504 +CONFIG_DRAM_ODT_EN=y +CONFIG_I2C0_ENABLE=y +CONFIG_DEFAULT_DEVICE_TREE="sun8i-s3-pinecube" +CONFIG_SPL_I2C_SUPPORT=y +# CONFIG_NETDEVICES is not set +CONFIG_AXP209_POWER=y +CONFIG_AXP_DCDC2_VOLT=1250 +CONFIG_AXP_DCDC3_VOLT=3300 +CONFIG_CONS_INDEX=3 -- 2.28.0

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[PATCH] pinctrl: renesas: Add support for R8A774C0
by Lad Prabhakar 18 Nov '20

18 Nov '20

Renesas RZ/G2E (a.k.a. r8a774c0) is pin compatible with R-Car E3 (a.k.a. r8a77990), however it doesn't have several automotive specific peripherals. This patch hooks R8A774C0 SoC with the pfc driver. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj(a)bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz(a)bp.renesas.com> --- arch/arm/mach-rmobile/Kconfig.64 | 1 + drivers/pinctrl/renesas/Kconfig | 10 ++++++++++ drivers/pinctrl/renesas/Makefile | 1 + drivers/pinctrl/renesas/pfc.c | 11 +++++++++++ drivers/pinctrl/renesas/sh_pfc.h | 1 + 5 files changed, 24 insertions(+) diff --git a/arch/arm/mach-rmobile/Kconfig.64 b/arch/arm/mach-rmobile/Kconfig.64 index 56c522596a..90bc4acd08 100644 --- a/arch/arm/mach-rmobile/Kconfig.64 +++ b/arch/arm/mach-rmobile/Kconfig.64 @@ -15,6 +15,7 @@ config R8A774B1 config R8A774C0 bool "Renesas SoC R8A774C0" imply CLK_R8A774C0 + imply PINCTRL_PFC_R8A774C0 config R8A774E1 bool "Renesas SoC R8A774E1" diff --git a/drivers/pinctrl/renesas/Kconfig b/drivers/pinctrl/renesas/Kconfig index d2be4c84ba..8fb9cba387 100644 --- a/drivers/pinctrl/renesas/Kconfig +++ b/drivers/pinctrl/renesas/Kconfig @@ -77,6 +77,16 @@ config PINCTRL_PFC_R8A774B1 the GPIO definitions and pin control functions for each available multiplex function. +config PINCTRL_PFC_R8A774C0 + bool "Renesas RZ/G2 R8A774C0 pin control driver" + depends on PINCTRL_PFC + help + Support pin multiplexing control on Renesas RZ/G2E R8A774C0 SoCs. + + The driver is controlled by a device tree node which contains both + the GPIO definitions and pin control functions for each available + multiplex function. + config PINCTRL_PFC_R8A774E1 bool "Renesas RZ/G2 R8A774E1 pin control driver" depends on PINCTRL_PFC diff --git a/drivers/pinctrl/renesas/Makefile b/drivers/pinctrl/renesas/Makefile index 1d00752051..0e2ac3c513 100644 --- a/drivers/pinctrl/renesas/Makefile +++ b/drivers/pinctrl/renesas/Makefile @@ -1,6 +1,7 @@ obj-$(CONFIG_PINCTRL_PFC) += pfc.o obj-$(CONFIG_PINCTRL_PFC_R8A774A1) += pfc-r8a7796.o obj-$(CONFIG_PINCTRL_PFC_R8A774B1) += pfc-r8a77965.o +obj-$(CONFIG_PINCTRL_PFC_R8A774C0) += pfc-r8a77990.o obj-$(CONFIG_PINCTRL_PFC_R8A774E1) += pfc-r8a7795.o obj-$(CONFIG_PINCTRL_PFC_R8A7790) += pfc-r8a7790.o obj-$(CONFIG_PINCTRL_PFC_R8A7791) += pfc-r8a7791.o diff --git a/drivers/pinctrl/renesas/pfc.c b/drivers/pinctrl/renesas/pfc.c index 4c1e770422..8a566f7139 100644 --- a/drivers/pinctrl/renesas/pfc.c +++ b/drivers/pinctrl/renesas/pfc.c @@ -34,6 +34,7 @@ enum sh_pfc_model { SH_PFC_R8A7796, SH_PFC_R8A774A1, SH_PFC_R8A774B1, + SH_PFC_R8A774C0, SH_PFC_R8A774E1, SH_PFC_R8A77965, SH_PFC_R8A77970, @@ -909,6 +910,10 @@ static int sh_pfc_pinctrl_probe(struct udevice *dev) if (model == SH_PFC_R8A774B1) priv->pfc.info = &r8a774b1_pinmux_info; #endif +#ifdef CONFIG_PINCTRL_PFC_R8A774C0 + if (model == SH_PFC_R8A774C0) + priv->pfc.info = &r8a774c0_pinmux_info; +#endif #ifdef CONFIG_PINCTRL_PFC_R8A774E1 if (model == SH_PFC_R8A774E1) priv->pfc.info = &r8a774e1_pinmux_info; @@ -996,6 +1001,12 @@ static const struct udevice_id sh_pfc_pinctrl_ids[] = { .data = SH_PFC_R8A774B1, }, #endif +#ifdef CONFIG_PINCTRL_PFC_R8A774C0 + { + .compatible = "renesas,pfc-r8a774c0", + .data = SH_PFC_R8A774C0, + }, +#endif #ifdef CONFIG_PINCTRL_PFC_R8A774E1 { .compatible = "renesas,pfc-r8a774e1", diff --git a/drivers/pinctrl/renesas/sh_pfc.h b/drivers/pinctrl/renesas/sh_pfc.h index 22cc860f29..f563916f10 100644 --- a/drivers/pinctrl/renesas/sh_pfc.h +++ b/drivers/pinctrl/renesas/sh_pfc.h @@ -295,6 +295,7 @@ sh_pfc_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin, extern const struct sh_pfc_soc_info r8a774a1_pinmux_info; extern const struct sh_pfc_soc_info r8a774b1_pinmux_info; +extern const struct sh_pfc_soc_info r8a774c0_pinmux_info; extern const struct sh_pfc_soc_info r8a774e1_pinmux_info; extern const struct sh_pfc_soc_info r8a7790_pinmux_info; extern const struct sh_pfc_soc_info r8a7791_pinmux_info; -- 2.17.1

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[RESEND PATCH v3] usb: xhci: fix lack of short packet event trb handling
by Ran Wang 18 Nov '20

18 Nov '20

For bulk IN transfer, the codes will set ISP flag to request event TRB being generated by xHC for case of short packet. So for the case of buffer-cross-64K-boundary (which we will divide payload and enqueuqe more than 1 transfer TRB), if the first TRB ends up with a short packet condition it will trigger an short packet code transfer event per that flag and cause more than 1 event TRB generated for this transfer. However, current codes will only handle the first transfer event TRB then mark current transfer completed, causing next transfer failure due to event TRB mis-match. Such issue has been observed on some Layerscape platforms (LS1028A, LS1088A, etc) with USB ethernet device. This patch adds a loop to make sure the event TRB for last transfer TRB has been handled in time. Signed-off-by: Ran Wang <ran.wang_1(a)nxp.com> --- Change in v3: - Update commit message according to v2 feedback . - Replace (void *) with (uintptr_t) to fix below armv7 compile warning: ... drivers/usb/host/xhci-ring.c: In function 'xhci_bulk_tx': drivers/usb/host/xhci-ring.c:726:6: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] 726 | if ((void *)le64_to_cpu(event->trans_event.buffer) != last_transfer_trb_addr) { | ^ ... Change in v2: - Re-write commit message to describe context more clearly. - Add prefix 'le64_to_cpu' for 'event->trans_event.buffer'. drivers/usb/host/xhci-ring.c | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c index 13065d7..d708fc9 100644 --- a/drivers/usb/host/xhci-ring.c +++ b/drivers/usb/host/xhci-ring.c @@ -580,10 +580,13 @@ int xhci_bulk_tx(struct usb_device *udev, unsigned long pipe, int ret; u32 trb_fields[4]; u64 val_64 = virt_to_phys(buffer); + void *last_transfer_trb_addr; + int available_length; debug("dev=%p, pipe=%lx, buffer=%p, length=%d\n", udev, pipe, buffer, length); + available_length = length; ep_index = usb_pipe_ep_index(pipe); virt_dev = ctrl->devs[slot_id]; @@ -697,7 +700,7 @@ int xhci_bulk_tx(struct usb_device *udev, unsigned long pipe, trb_fields[2] = length_field; trb_fields[3] = field | TRB_TYPE(TRB_NORMAL); - queue_trb(ctrl, ring, (num_trbs > 1), trb_fields); + last_transfer_trb_addr = queue_trb(ctrl, ring, (num_trbs > 1), trb_fields); --num_trbs; @@ -710,6 +713,7 @@ int xhci_bulk_tx(struct usb_device *udev, unsigned long pipe, giveback_first_trb(udev, ep_index, start_cycle, start_trb); +again: event = xhci_wait_for_event(ctrl, TRB_TRANSFER); if (!event) { debug("XHCI bulk transfer timed out, aborting...\n"); @@ -718,12 +722,20 @@ int xhci_bulk_tx(struct usb_device *udev, unsigned long pipe, udev->act_len = 0; return -ETIMEDOUT; } - field = le32_to_cpu(event->trans_event.flags); + if ((uintptr_t)(le64_to_cpu(event->trans_event.buffer)) + != (uintptr_t)last_transfer_trb_addr) { + available_length -= + (int)EVENT_TRB_LEN(le32_to_cpu(event->trans_event.transfer_len)); + xhci_acknowledge_event(ctrl); + goto again; + } + + field = le32_to_cpu(event->trans_event.flags); BUG_ON(TRB_TO_SLOT_ID(field) != slot_id); BUG_ON(TRB_TO_EP_INDEX(field) != ep_index); - record_transfer_result(udev, event, length); + record_transfer_result(udev, event, available_length); xhci_acknowledge_event(ctrl); xhci_inval_cache((uintptr_t)buffer, length); -- 2.7.4

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