January 2020 - U-Boot

[RFC] azure: Move to vs2017-win2016 platform build host
by Tom Rini 03 Feb '20

03 Feb '20

Azure is moving to remove the vs2015-win2012r2 platform build host. The two suggested new platforms to use are vs2017-win2016 and windows-2019. For now, move up to vs2017-win2016. Cc: Bin Meng <bmeng.cn(a)gmail.com> Signed-off-by: Tom Rini <trini(a)konsulko.com> --- I'm sending this as RFC as it fails to build for i686 but builds for x86_64 and I'm out of my depth on fixing that. Can you please take a look Bin? Thanks! --- .azure-pipelines.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml index 916ab84ea0c4..a0713dd66c0a 100644 --- a/.azure-pipelines.yml +++ b/.azure-pipelines.yml @@ -1,5 +1,5 @@ variables: - windows_vm: vs2015-win2012r2 + windows_vm: vs2017-win2016 ubuntu_vm: ubuntu-18.04 ci_runner_image: trini/u-boot-gitlab-ci-runner:bionic-20200112-17Jan2020 # Add '-u 0' options for Azure pipelines, otherwise we get "permission -- 2.17.1

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[RFC PATCH] spi: ich: Drop while loop in hardware sequencing erase case
by Wolfgang Wallner 03 Feb '20

03 Feb '20

When ich_spi_exec_op_hwseq() is called to erase a 4k block (opcode = SPINOR_OP_BE_4K), it expects to find a length value in op->data.nbytes, but that value is always 0. As a result, the while loop is never executed and no erase is carried out. Fix this by dropping the loop code entirely, only keeping the relevant parts of the loop body. Signed-off-by: Wolfgang Wallner <wolfgang.wallner(a)br-automation.com> --- I tried using an SPI NOR flash on an Apollo Lake based board, but calling 'sf erase' fails to erase the flash memory, it looks like it does nothing. Debugging the issue I find that the function ich_spi_exec_op_hwseq() in drivers/spi/ich.c tries to loop over the provided number of bytes, but that value is always 0. The spi operation that is handled by ich_spi_exec_op_hwseq() is initially created in the function spi_nor_erase_sector(), and handed down via the following call stack: spi_nor_erase_sector() in drivers/mtd/spi/spi-nor-core.c spi_mem_exec_op() in drivers/spi/spi-mem.c spi_mem_exec_op() calls ops->mem_ops->exec_op() which points to ich_spi_exec_op() ich_spi_exec_op() in drivers/spi/ich.c ich_spi_exec_op_hwseq() in drivers/spi/ich.c The number of bytes (op.data.nbytes) is always set to 0 in spi_nor_erase_sector(), thus the loop in ich_spi_exec_op_hwseq can never be executed. I tried to fix this by dropping the loop code entirely, and with this change 'sf erase' works for me as expected. The code in spi_nor_erase_sector() that sets data.nbytes always to 0 was introduced in commit f909ddb3e177 ("mtd: spi: Replace ad-hoc default implementation with spi_mem_op"), but that commit is older then the code in ich_spi_exec_op_hwseq() which was introduced in commit 1facebd18fd7 ("spi: ich: Support hardware sequencing"). I would like to ask for feedback on the provided patch. drivers/spi/ich.c | 12 ++---------- 1 file changed, 2 insertions(+), 10 deletions(-) diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c index 133b25b72e..a9d7715a55 100644 --- a/drivers/spi/ich.c +++ b/drivers/spi/ich.c @@ -562,16 +562,8 @@ static int ich_spi_exec_op_hwseq(struct spi_slave *slave, return 0; /* ignore */ case SPINOR_OP_BE_4K: cycle = HSFSTS_CYCLE_4K_ERASE; - while (len) { - uint xfer_len = 0x1000; - - ret = exec_sync_hwseq_xfer(regs, cycle, offset, 0); - if (ret) - return ret; - offset += xfer_len; - len -= xfer_len; - } - return 0; + ret = exec_sync_hwseq_xfer(regs, cycle, offset, 0); + return ret; default: debug("Unknown cycle %x\n", op->cmd.opcode); return -EINVAL; -- 2.24.1

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[PATCH v1 1/2] x86: edison: Enable command line editing
by Andy Shevchenko 03 Feb '20

03 Feb '20

From: Marek Vasut <marex(a)denx.de> Enable command line editing, because it is extremely convenient. Signed-off-by: Marek Vasut <marex(a)denx.de> Signed-off-by: Andy Shevchenko <andriy.shevchenko(a)linux.intel.com> --- configs/edison_defconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/configs/edison_defconfig b/configs/edison_defconfig index 14b2eec3ba..124f0f628f 100644 --- a/configs/edison_defconfig +++ b/configs/edison_defconfig @@ -9,7 +9,6 @@ CONFIG_SMP=y CONFIG_BOARD_EARLY_INIT_R=y CONFIG_LAST_STAGE_INIT=y CONFIG_HUSH_PARSER=y -# CONFIG_CMDLINE_EDITING is not set CONFIG_CMD_CPU=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y -- 2.24.1

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[PATCH 1/1] doc: Chromebook Coral: fix build warnings
by Heinrich Schuchardt 03 Feb '20

03 Feb '20

Use valid restructured text to avoid warnings like WARNING: Title underline too short. WARNING: Block quote ends without a blank line; unexpected unindent. when building with `make htmldocs`. Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- doc/board/google/chromebook_coral.rst | 90 ++++++++++++++------------- 1 file changed, 46 insertions(+), 44 deletions(-) diff --git a/doc/board/google/chromebook_coral.rst b/doc/board/google/chromebook_coral.rst index 515fd06d76..5dc3c97c3d 100644 --- a/doc/board/google/chromebook_coral.rst +++ b/doc/board/google/chromebook_coral.rst @@ -112,7 +112,7 @@ U-Boot then shuts down CAR and jumps to its relocated version. Boot flow - U-Boot post-relocation ---------------------------------- +---------------------------------- U-Boot starts up normally, running near the top of RAM. After driver model is running, arch_fsp_init_r() is called which loads and runs the FSP-S binary. @@ -142,54 +142,56 @@ Performance ----------- Bootstage is used through all phases of U-Boot to keep accurate timimgs for -boot. Use 'bootstage report' in U-Boot to see the report, e.g.: - -Timer summary in microseconds (16 records): - Mark Elapsed Stage - 0 0 reset - 155,325 155,325 TPL - 204,014 48,689 end TPL - 204,385 371 SPL - 738,633 534,248 end SPL - 739,161 528 board_init_f - 842,764 103,603 board_init_r - 1,166,233 323,469 main_loop - 1,166,283 50 id=175 - -Accumulated time: - 62 fast_spi - 202 dm_r - 7,779 dm_spl - 15,555 dm_f - 208,357 fsp-m - 239,847 fsp-s - 292,143 mmap_spi - -CPU performance is about 3500 DMIPS: - -=> dhry -1000000 iterations in 161 ms: 6211180/s, 3535 DMIPS +boot. Use 'bootstage report' in U-Boot to see the report, e.g.:: + + Timer summary in microseconds (16 records): + Mark Elapsed Stage + 0 0 reset + 155,325 155,325 TPL + 204,014 48,689 end TPL + 204,385 371 SPL + 738,633 534,248 end SPL + 739,161 528 board_init_f + 842,764 103,603 board_init_r + 1,166,233 323,469 main_loop + 1,166,283 50 id=175 + + Accumulated time: + 62 fast_spi + 202 dm_r + 7,779 dm_spl + 15,555 dm_f + 208,357 fsp-m + 239,847 fsp-s + 292,143 mmap_spi + +CPU performance is about 3500 DMIPS:: + + => dhry + 1000000 iterations in 161 ms: 6211180/s, 3535 DMIPS Partial memory map ------------------ -ffffffff Top of ROM (and last byte of 32-bit address space) -ffff8000 TPL loaded here (from IFWI) -ff000000 Bottom of ROM -fefc000 Top of CAR region -fef96000 Stack for FSP-M -fef40000 59000 FSP-M -fef11000 SPL loaded here -fef10000 CONFIG_BLOBLIST_ADDR -fef10000 Stack top in TPL, SPL and U-Boot before relocation -fef00000 1000 CONFIG_BOOTSTAGE_STASH_ADDR -fef00000 Base of CAR region - - f0000 CONFIG_ROM_TABLE_ADDR - 120000 BSS (defined in u-boot-spl.lds) - 200000 FSP-S (which is run after U-Boot is relocated) - 1110000 CONFIG_SYS_TEXT_BASE +:: + + ffffffff Top of ROM (and last byte of 32-bit address space) + ffff8000 TPL loaded here (from IFWI) + ff000000 Bottom of ROM + fefc000 Top of CAR region + fef96000 Stack for FSP-M + fef40000 59000 FSP-M + fef11000 SPL loaded here + fef10000 CONFIG_BLOBLIST_ADDR + fef10000 Stack top in TPL, SPL and U-Boot before relocation + fef00000 1000 CONFIG_BOOTSTAGE_STASH_ADDR + fef00000 Base of CAR region + + f0000 CONFIG_ROM_TABLE_ADDR + 120000 BSS (defined in u-boot-spl.lds) + 200000 FSP-S (which is run after U-Boot is relocated) + 1110000 CONFIG_SYS_TEXT_BASE Supported peripherals -- 2.24.1

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[PATCH] x86: limit the fs segment to the pointer size
by Masahiro Yamada 03 Feb '20

03 Feb '20

The fs segment is only used to get the global data pointer. If it is accessed beyond sizeof(new_gd->arch.gd_addr), it is a bug. To specify the byte-granule limit size, drop the G bit, so the flag field is 0x8093 instead of 0xc093, and set the limit field to sizeof(new_gd->arch.gd_addr) - 1. Signed-off-by: Masahiro Yamada <masahiroy(a)kernel.org> --- arch/x86/cpu/i386/cpu.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/x86/cpu/i386/cpu.c b/arch/x86/cpu/i386/cpu.c index 2b27617ca3a4..72fefdd3adca 100644 --- a/arch/x86/cpu/i386/cpu.c +++ b/arch/x86/cpu/i386/cpu.c @@ -137,8 +137,9 @@ void arch_setup_gd(gd_t *new_gd) /* FS: data, read/write, 4 GB, base (Global Data Pointer) */ new_gd->arch.gd_addr = new_gd; - gdt_addr[X86_GDT_ENTRY_32BIT_FS] = GDT_ENTRY(0xc093, - (ulong)&new_gd->arch.gd_addr, 0xfffff); + gdt_addr[X86_GDT_ENTRY_32BIT_FS] = GDT_ENTRY(0x8093, + (ulong)&new_gd->arch.gd_addr, + sizeof(new_gd->arch.gd_addr) - 1); /* 16-bit CS: code, read/execute, 64 kB, base 0 */ gdt_addr[X86_GDT_ENTRY_16BIT_CS] = GDT_ENTRY(0x009b, 0, 0x0ffff); -- 2.17.1

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[PATCH] x86: use invd instead of wbinvd in real mode start code
by Masahiro Yamada 03 Feb '20

03 Feb '20

I do not know why the boot code immediately after the system reset should write-back the cache content. I think the cache invalidation should be enough. I tested this commit with qemu-x86_defconfig, and it worked for me. Signed-off-by: Masahiro Yamada <masahiroy(a)kernel.org> --- arch/x86/cpu/start.S | 2 +- arch/x86/cpu/start16.S | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/cpu/start.S b/arch/x86/cpu/start.S index 01524635e9c8..26cf995db2d0 100644 --- a/arch/x86/cpu/start.S +++ b/arch/x86/cpu/start.S @@ -50,7 +50,7 @@ _x86boot_start: movl %cr0, %eax orl $(X86_CR0_NW | X86_CR0_CD), %eax movl %eax, %cr0 - wbinvd + invd /* * Zero the BIST (Built-In Self Test) value since we don't have it. diff --git a/arch/x86/cpu/start16.S b/arch/x86/cpu/start16.S index 54f4ff6662a8..292e75050814 100644 --- a/arch/x86/cpu/start16.S +++ b/arch/x86/cpu/start16.S @@ -28,7 +28,7 @@ start16: movl %cr0, %eax orl $(X86_CR0_NW | X86_CR0_CD), %eax movl %eax, %cr0 - wbinvd + invd /* load the temporary Global Descriptor Table */ data32 cs lidt idt_ptr -- 2.17.1

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[PATCH 2/2] doc: intel: Update serial driver changes in slimbootloader.rst
by Park, Aiden 03 Feb '20

03 Feb '20

Now, Slim Bootloader uses NS16550_DYNAMIC to support serial port configuration at runtime, so no more code change is required. Therefore, remove unnecessary steps and fix minor typo. Signed-off-by: Aiden Park <aiden.park(a)intel.com> --- doc/board/intel/slimbootloader.rst | 35 +++++++----------------------- 1 file changed, 8 insertions(+), 27 deletions(-) diff --git a/doc/board/intel/slimbootloader.rst b/doc/board/intel/slimbootloader.rst index 375e676804..a8c41b1aa7 100644 --- a/doc/board/intel/slimbootloader.rst +++ b/doc/board/intel/slimbootloader.rst @@ -111,35 +111,16 @@ Download it from http://downloads.yoctoproject.org/releases/yocto/yocto-2.0/mach Build Instruction for Slim Bootloader for LeafHill (APL) target --------------------------------------------------------------- -LeafHill is using PCI UART2 device as a serial port. -For MEM32 serial port, CONFIG_SYS_NS16550_MEM32 needs to be enabled in U-Boot. +Prepare U-Boot and Slim Bootloader as described at the beginning of this page. +Also, the PayloadId needs to be set for APL board. -1. Enable CONFIG_SYS_NS16550_MEM32 in U-Boot:: - - $ vi include/configs/slimbootloader.h - +#define CONFIG_SYS_NS16550_MEM32 - #ifdef CONFIG_SYS_NS16550_MEM3 - -2. Build U-Boot:: - - $ make disclean - $ make slimbootloader_defconfig - $ make all - -3. Copy u-boot-dtb.bin to Slim Bootloader. - Slim Bootloader looks for a payload from the specific location. - Copy the build u-boot-dtb.bin to the expected location:: - - $ mkdir -p <Slim Bootloader Dir>/PayloadPkg/PayloadBins/ - $ cp <U-Boot Dir>/u-boot-dtb.bin <Slim Bootloader Dir>/PayloadPkg/PayloadBins/u-boot-dtb.bin - -4. Update PayloadId. Let's use 'U-BT' as an example:: +1. Update PayloadId. Let's use 'U-BT' as an example:: $ vi Platform/ApollolakeBoardPkg/CfgData/CfgData_Int_LeafHill.dlt -GEN_CFG_DATA.PayloadId | 'AUTO +GEN_CFG_DATA.PayloadId | 'U-BT' -5. Update payload text base. +2. Update payload text base. * PAYLOAD_EXE_BASE must be the same as U-Boot CONFIG_SYS_TEXT_BASE in board/intel/slimbootloader/Kconfig. @@ -149,18 +130,18 @@ For MEM32 serial port, CONFIG_SYS_NS16550_MEM32 needs to be enabled in U-Boot. + self.PAYLOAD_LOAD_HIGH = 0 + self.PAYLOAD_EXE_BASE = 0x00100000 -6. Build APL target. Make sure u-boot-dtb.bin and U-BT PayloadId +3. Build APL target. Make sure u-boot-dtb.bin and U-BT PayloadId in build command. The output is Outputs/apl/Stitch_Components.zip:: $ python BuildLoader.py build apl -p "OsLoader.efi:LLDR:Lz4;u-boot-dtb.bin:U-BT:Lzma" -7. Stitch IFWI. +4. Stitch IFWI. Refer to Apollolake_ page in Slim Bootloader document site:: $ python Platform/ApollolakeBoardPkg/Script/StitchLoader.py -i <Existing IFWI> -s Outputs/apl/Stitch_Components.zip -o <Output IFWI> -8. Flash IFWI. +5. Flash IFWI. Use DediProg to flash IFWI. You should reach at U-Boot serial console. @@ -175,7 +156,7 @@ Build Instruction to use ELF U-Boot 2. Build U-Boot:: - $ make disclean + $ make distclean $ make slimbootloader_defconfig $ make all $ strip u-boot (removing symbol for reduced size) -- 2.20.1

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[PATCH 1/2] x86: serial: Use NS16550_DYNAMIC in Slim Bootloader
by Park, Aiden 03 Feb '20

03 Feb '20

Slim Bootloader provides serial port info in its HOB to support both IO or MMIO serial ports, but it's controlled by SYS_NS16550_MEM32 or SYS_NS16550_PORT_MAPPED in U-Boot. To support both serial port configurations dynamically at runtime, Slim Bootloader serial driver leverages NS16550_DYNAMIC. Signed-off-by: Aiden Park <aiden.park(a)intel.com> --- arch/x86/cpu/slimbootloader/serial.c | 5 +++++ include/configs/slimbootloader.h | 13 ------------- 2 files changed, 5 insertions(+), 13 deletions(-) diff --git a/arch/x86/cpu/slimbootloader/serial.c b/arch/x86/cpu/slimbootloader/serial.c index 7b44a59bff..0f45b3ba72 100644 --- a/arch/x86/cpu/slimbootloader/serial.c +++ b/arch/x86/cpu/slimbootloader/serial.c @@ -45,7 +45,12 @@ static int slimbootloader_serial_ofdata_to_platdata(struct udevice *dev) plat->base = data->base; /* ns16550 uses reg_shift, then covert stride to shift */ plat->reg_shift = data->stride >> 1; + plat->reg_width = data->stride; plat->clock = data->clk; + plat->fcr = UART_FCR_DEFVAL; + plat->flags = 0; + if (data->type == 1) + plat->flags |= NS16550_FLAG_IO; return 0; } diff --git a/include/configs/slimbootloader.h b/include/configs/slimbootloader.h index e0011ed446..b8169072cc 100644 --- a/include/configs/slimbootloader.h +++ b/include/configs/slimbootloader.h @@ -8,19 +8,6 @@ #include <configs/x86-common.h> -/* - * By default, CONFIG_SYS_NS16550_PORT_MAPPED is enabled for port io serial. - * To use mmio base serial, enable CONFIG_SYS_NS16550_MEM32 and disable - * CONFIG_SYS_NS16550_PORT_MAPPED until ns16550 driver supports serial port - * configuration in run-time. - * - * #define CONFIG_SYS_NS16550_MEM32 - * #undef CONFIG_SYS_NS16550_PORT_MAPPED - */ -#ifdef CONFIG_SYS_NS16550_MEM32 -#undef CONFIG_SYS_NS16550_PORT_MAPPED -#endif - #define CONFIG_STD_DEVICES_SETTINGS \ "stdin=serial,i8042-kbd,usbkbd\0" \ "stdout=serial\0" \ -- 2.20.1

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SDL 2.0 in gitlab
by Simon Glass 03 Feb '20

03 Feb '20

Hi Tom, I have a series which changes sandbox over to use the newer SDL2. At present I cannot make it pass on gitlab since it seems to have SDL1.2 (only). Is it possible to change that? Regards, Simon

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[PATCH] riscv: Remove unnecessary instruction
by Sean Anderson 02 Feb '20

02 Feb '20

The add instruction on risc-v can have any three sources and targets, so there is no need for an intermediate mov. Signed-off-by: Sean Anderson <seanga2(a)gmail.com> --- arch/riscv/cpu/start.S | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index 1a55b7d570..365163ad19 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -359,9 +359,8 @@ relocate_secondary_harts: call_board_init_r: jal invalidate_icache_all jal flush_dcache_all - la t0, board_init_r - mv t4, t0 /* offset of board_init_r() */ - add t4, t4, t6 /* real address of board_init_r() */ + la t0, board_init_r /* offset of board_init_r() */ + add t4, t0, t6 /* real address of board_init_r() */ /* * setup parameters for board_init_r */ -- 2.25.0

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