August 2019 - U-Boot

[U-Boot] [PATCH 1/4] x86: Drop weak version board_get_usable_ram_top()
by Bin Meng 10 Sep '19

10 Sep '19

Every x86 platform provides board_get_usable_ram_top(), hence there is no need to provide a weak version board_get_usable_ram_top(), not to mention there is another weak version board_get_usable_ram_top() in common/board_f.c. Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- arch/x86/lib/init_helpers.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/arch/x86/lib/init_helpers.c b/arch/x86/lib/init_helpers.c index 5e19f13..4774a9b 100644 --- a/arch/x86/lib/init_helpers.c +++ b/arch/x86/lib/init_helpers.c @@ -10,12 +10,6 @@ DECLARE_GLOBAL_DATA_PTR; -/* Get the top of usable RAM */ -__weak ulong board_get_usable_ram_top(ulong total_size) -{ - return gd->ram_size; -} - int init_cache_f_r(void) { #if CONFIG_IS_ENABLED(X86_32BIT_INIT) && !defined(CONFIG_HAVE_FSP) && \ -- 2.7.4

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[U-Boot] [PATCH v1 1/7] mmc: fsl_esdhc: Add peripheral clock support
by Yinbo Zhu 10 Sep '19

10 Sep '19

This patch is to add peripheral clock support Signed-off-by: Yinbo Zhu <yinbo.zhu(a)nxp.com> --- .../armv8/fsl-layerscape/fsl_lsch2_speed.c | 49 ++++++++++++------- .../armv8/fsl-layerscape/fsl_lsch3_speed.c | 45 ++++++++++++++++- .../asm/arch-fsl-layerscape/immap_lsch2.h | 2 +- .../asm/arch-fsl-layerscape/immap_lsch3.h | 1 + 4 files changed, 78 insertions(+), 19 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c index 9ece4b90e6..23391398ed 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c @@ -22,10 +22,12 @@ DECLARE_GLOBAL_DATA_PTR; void get_sys_info(struct sys_info *sys_info) { struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); -#if (defined(CONFIG_FSL_ESDHC) &&\ - defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK)) ||\ - defined(CONFIG_SYS_DPAA_FMAN) - +/* rcw_tmp is needed to get FMan clock, or to get cluster group A + * mux 2 clock for LS1043A/LS1046A. + */ +#if defined(CONFIG_SYS_DPAA_FMAN) || \ + defined(CONFIG_TARGET_LS1046ARDB) || \ + defined(CONFIG_TARGET_LS1043ARDB) u32 rcw_tmp; #endif struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_CLK_ADDR); @@ -122,32 +124,32 @@ void get_sys_info(struct sys_info *sys_info) } #endif +#ifdef CONFIG_FSL_ESDHC #define HWA_CGA_M2_CLK_SEL 0x00000007 #define HWA_CGA_M2_CLK_SHIFT 0 -#ifdef CONFIG_FSL_ESDHC -#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK +#if defined(CONFIG_TARGET_LS1046ARDB) || defined(CONFIG_TARGET_LS1043ARDB) rcw_tmp = in_be32(&gur->rcwsr[15]); switch ((rcw_tmp & HWA_CGA_M2_CLK_SEL) >> HWA_CGA_M2_CLK_SHIFT) { case 1: - sys_info->freq_sdhc = freq_c_pll[1]; + sys_info->freq_cga_m2 = freq_c_pll[1]; break; +#if defined(CONFIG_TARGET_LS1046ARDB) case 2: - sys_info->freq_sdhc = freq_c_pll[1] / 2; + sys_info->freq_cga_m2 = freq_c_pll[1] / 2; break; +#endif case 3: - sys_info->freq_sdhc = freq_c_pll[1] / 3; + sys_info->freq_cga_m2 = freq_c_pll[1] / 3; break; +#if defined(CONFIG_TARGET_LS1046ARDB) case 6: - sys_info->freq_sdhc = freq_c_pll[0] / 2; + sys_info->freq_cga_m2 = freq_c_pll[0] / 2; break; +#endif default: - printf("Error: Unknown ESDHC clock select!\n"); + printf("Error: Unknown peripheral clock select!\n"); break; } -#else - sys_info->freq_sdhc = (sys_info->freq_systembus / - CONFIG_SYS_FSL_PCLK_DIV) / - CONFIG_SYS_FSL_SDHC_CLK_DIV; #endif #endif @@ -183,9 +185,22 @@ int get_clocks(void) gd->mem_clk = sys_info.freq_ddrbus; #ifdef CONFIG_FSL_ESDHC - gd->arch.sdhc_clk = sys_info.freq_sdhc; +#if defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK) +#if defined(CONFIG_TARGET_LS1046ARDB) + gd->arch.sdhc_clk = sys_info.freq_cga_m2 / 2; +#endif +#if defined(CONFIG_TARGET_LS1043ARDB) + gd->arch.sdhc_clk = sys_info.freq_cga_m2; +#endif +#if defined(CONFIG_TARGET_LS1012ARDB) + gd->arch.sdhc_clk = sys_info.freq_systembus; +#endif +#else + gd->arch.sdhc_clk = (sys_info.freq_systembus / + CONFIG_SYS_FSL_PCLK_DIV) / + CONFIG_SYS_FSL_SDHC_CLK_DIV; +#endif #endif - if (gd->cpu_clk != 0) return 0; else diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c index a5540f2b9d..b3e67321b4 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c @@ -64,6 +64,9 @@ void get_sys_info(struct sys_info *sys_info) }; uint i, cluster; +#if defined(CONFIG_TARGET_LS1028ARDB) || defined(CONFIG_TARGET_LS1088ARDB) + uint rcw_tmp; +#endif uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS]; uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS]; unsigned long sysclk = CONFIG_SYS_CLK_FREQ; @@ -127,8 +130,39 @@ void get_sys_info(struct sys_info *sys_info) sys_info->freq_localbus = sys_info->freq_systembus / CONFIG_SYS_FSL_IFC_CLK_DIV; #endif -} +#if defined(CONFIG_TARGET_LS1028ARDB) || defined(CONFIG_TARGET_LS1088ARDB) +#define HWA_CGA_M2_CLK_SEL 0x00380000 +#define HWA_CGA_M2_CLK_SHIFT 19 + rcw_tmp = in_le32(&gur->rcwsr[5]); + switch ((rcw_tmp & HWA_CGA_M2_CLK_SEL) >> HWA_CGA_M2_CLK_SHIFT) { + case 1: + sys_info->freq_cga_m2 = freq_c_pll[1]; + break; + case 2: + sys_info->freq_cga_m2 = freq_c_pll[1] / 2; + break; + case 3: + sys_info->freq_cga_m2 = freq_c_pll[1] / 3; + break; + case 4: + sys_info->freq_cga_m2 = freq_c_pll[1] / 4; + break; + case 6: + sys_info->freq_cga_m2 = freq_c_pll[0] / 2; + break; + case 7: + sys_info->freq_cga_m2 = freq_c_pll[0] / 3; + break; + default: + printf("Error: Unknown peripheral clock select!\n"); + break; + } +#endif +#if defined(CONFIG_TARGET_LX2160ARDB) || defined(CONFIG_TARGET_LS2080ARDB) + sys_info->freq_cga_m2 = sys_info->freq_systembus; +#endif +} int get_clocks(void) { @@ -141,7 +175,16 @@ int get_clocks(void) gd->arch.mem2_clk = sys_info.freq_ddrbus2; #endif #if defined(CONFIG_FSL_ESDHC) +#if defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK) +#if defined(CONFIG_TARGET_LS1028ARDB) || defined(CONFIG_TARGET_LX2160ARDB) + gd->arch.sdhc_clk = sys_info.freq_cga_m2 / 2; +#endif +#if defined(CONFIG_TARGET_LS2080ARDB) || defined(CONFIG_TARGET_LS1088ARDB) + gd->arch.sdhc_clk = sys_info.freq_cga_m2; +#endif +#else gd->arch.sdhc_clk = gd->bus_clk / CONFIG_SYS_FSL_SDHC_CLK_DIV; +#endif #endif /* defined(CONFIG_FSL_ESDHC) */ if (gd->cpu_clk != 0) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index b4b7c3492e..3a59abb10e 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -180,7 +180,7 @@ struct sys_info { unsigned long freq_systembus; unsigned long freq_ddrbus; unsigned long freq_localbus; - unsigned long freq_sdhc; + unsigned long freq_cga_m2; #ifdef CONFIG_SYS_DPAA_FMAN unsigned long freq_fman[CONFIG_SYS_NUM_FMAN]; #endif diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index ee9b33becf..3cea71ad75 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -255,6 +255,7 @@ struct sys_info { /* frequency of platform PLL */ unsigned long freq_systembus; unsigned long freq_ddrbus; + unsigned long freq_cga_m2; #ifdef CONFIG_SYS_FSL_HAS_DP_DDR unsigned long freq_ddrbus2; #endif -- 2.17.1

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[U-Boot] Regression after "distro: not taint environment variables if possible"
by Nuno Gonçalves 09 Sep '19

09 Sep '19

Hi, I found out that my Beaglebone didn't boot after: https://github.com/u-boot/u-boot/commit/13dd6665ed18f72380ca596931d609bc108… I digged out the reason that this patch makes devnum a local variable, and it ends up shadowed by other code that sets devnum as a env variable. For example to boot on the beaglebone I had to remove the setenv as in the patch below. This only fixes for my board. Many other will likely have regressions. Fixing it for all boards in a reliable way I think is very complex, unless the strategy is to wait for board maintainers to fix it as they need it, but I wonder how many latent bugs this will create for corner boot cases. Maybe this change is not worth it? Thanks, Nuno diff --git a/include/environment/ti/mmc.h b/include/environment/ti/mmc.h index 785fc15345..bb4af0a3d5 100644 --- a/include/environment/ti/mmc.h +++ b/include/environment/ti/mmc.h @@ -56,7 +56,7 @@ "bootz; " \ "fi;\0" \ "mmcboot=mmc dev ${mmcdev}; " \ - "setenv devnum ${mmcdev}; " \ + "devnum=${mmcdev}; " \ "setenv devtype mmc; " \ "if mmc rescan; then " \ "echo SD/MMC found on device ${mmcdev};" \

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Re: [U-Boot] [PATCH v4 2/4] USB: host: Add the USB3 host driver
by Sherry Sun 09 Sep '19

09 Sep '19

Hi Marek, > > On 8/20/19 10:31 AM, Sherry Sun wrote: > > Hi Marek, > > > >> > >> On 8/19/19 8:10 AM, Sherry Sun wrote: > >>> Add the USB3 host driver for NXP imx8 platform, and the cadence IP > >>> is in it. The USB3 host driver support DM mode, it will probe USB3 > >>> host node in dts. > >>> > >>> Signed-off-by: Sherry Sun <sherry.sun(a)nxp.com> > >> > >> [...] > >> > >>> +static void xhci_imx8_get_reg_addr(struct udevice *dev) { > >>> + imx8_data.usb3_ctrl_base = > >>> + (void __iomem *)devfdt_get_addr_index(dev, 0); > >>> + imx8_data.usb3_core_base = > >>> + (void __iomem *)devfdt_get_addr_index(dev, 4); } > >> > >> Inline this. > >> > >> Also, look at drivers/mtd/renesas_rpc_hf.c to handle both 32bit and > >> 64bit DTs with multiple "reg" entries. > >> > > > > Actually, I don't think it's needed to change the way getting reg in dts. > > For two reasons: > > 1. This xhci-imx8 driver is only target on imx8 platform which all use 64bit > dts. > > 2. devfdt_get_addr_index() can handle both 32/64 bits dts too. > > By hard-coding this "4" offset, you assume the DT is using 64bit addressing, > that's wrong, so please fix it. The iMX8 does support aarch32, right ? So > someone might pass in 32bit DT and this would break. Sorry, maybe there are some misunderstandings in the code. There five reg elements in dts node, which are none_core_regs/ xhci_regs/ dev_regs/ phy_regs/ otg_regs. devfdt_get_addr_index(dev, 4) only want to get the fifth reg value, instead of meanning 64bit address. 586 usbotg3: usb3@5b110000 { 587 compatible = "cdns,usb3"; 588 reg = <0x0 0x5B110000 0x0 0x10000>, 589 <0x0 0x5B130000 0x0 0x10000>, 590 <0x0 0x5B140000 0x0 0x10000>, 591 <0x0 0x5B160000 0x0 0x40000>, 592 <0x0 0x5B120000 0x0 0x10000>; > > >> [...] > >> > >>> +static const struct udevice_id xhci_usb_ids[] = { > >>> + { .compatible = "cdns,usb3-host", }, > >> > >> https://lore.ker > >> > nel.org%2Fpatchwork%2Fpatch%2F1059917%2F&data=02%7C01%7Cshe > >> > rry.sun%40nxp.com%7C70e116ce152a4060dbd508d724987b54%7C686ea1d > >> > 3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C637018109631327748&sd > >> > ata=GzX5KNQ8m0CCeBa9tPSV%2BOEwwuSsxDdAiJd1T6or8P0%3D&reser > >> ved=0 would suggest that > >> cdns,usb3-1.0.0 is the compatible. But I might be wrong. > > > > This patch has not been accepted by the kernel, right? > > So I think maybe we can do this change to synchronize with kernel > > after the cdns3 kernel patch been accepted. > > Or, we can start with at least reasonably OK DT compatible right away to > reasonably avoid ABI breakage. Sure, will change the compatible from "cdns,usb3" to "cdns,usb3-1.0.0". > > > And note that in uboot, one dts node can only bind with one driver, so > > we keep the cdns3 node for usb gadget driver, then add a usb host node > > for > > xhci-imx8 driver in *-uboot.dtsi. so here is no need to change the host driver > compatible. > > But the compatible in gadget driver should be changed later. > > We should try avoiding ABI breaks in DT. But the cdns3 usb gaget driver and host driver in different uclass need two dt nodes to bind with. And the compatible of the two node cannot be same. So for gadget driver, the compatible may use "cdns,usb3-1.0.0", for host driver, the compatible will use "cdns,usb3-1.0.0-host". What do you think about it? > > >>> + { } > >>> +}; > >>> + > >>> +U_BOOT_DRIVER(xhci_imx8) = { > >>> + .name = "xhci_imx8", > >>> + .id = UCLASS_USB, > >>> + .of_match = xhci_usb_ids, > >>> + .probe = xhci_imx8_probe, > >>> + .remove = xhci_imx8_remove, > >>> + .ops = &xhci_usb_ops, > >>> + .platdata_auto_alloc_size = sizeof(struct usb_platdata), > >>> + .priv_auto_alloc_size = sizeof(struct xhci_ctrl), > >>> + .flags = DM_FLAG_ALLOC_PRIV_DMA, > >> > >> I think you also need DM_FLAG_OS_PREPARE to trigger .remove before > >> booting Linux, but I might be wrong. Please check that. > > > > When use usb stop command to stop the usb host driver, > > device_remove(bus, DM_REMOVE_NORMAL) is called by usb_stop(), so > > normally we don’t need the DM_FLAG_OS_PREPARE flag. > > But considering some special circumstances, maybe add this flag is helpful. > > I'm not talking about "usb stop", I am talking about booting Linux. > That's when then .remove should be called to tear down the driver. Is it? I know what you mean. The only function of DM_FLAG_OS_PREPARE is to call .remove before booting kernel, to make sure the device is removed. But normally, the host device is removed every time after we use it. So even the flag is set, the .remove won't be called again before booting kernel because the device is checked to be removed already. Add the flag just make sure the device will be removed before booting kernel. Do you think so? Best regard Sherry sun

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[U-Boot] [PATCH v2 0/4] NC-SI PHY Support
by Samuel Mendoza-Jonas 09 Sep '19

09 Sep '19

This series introduces support for the NC-SI protocol to u-boot, functionality which so far has only been available in vendor trees. NC-SI (Network Controller Sideband Interface) is a protocol to manage a sideband connection to a proper network interface, for example a BMC (Baseboard Management Controller) sharing the NIC of the host system. Probing and configuration occurs by communicating with the "remote" NIC via NC-SI control frames (Ethernet header 0x88f8). Since the RFC[0] the changes have been split out into a few different patches to make the overall changes more obvious. Additionally a few small improvements have been added including adding a check to see if NC-SI is already configured, and marking the PHY bus "reset" as invalid since it does not define a bus. An example of NC-SI setup before a normal network command: => dhcp net_loop: configuring NCSI first ethernet@1e660000: link up, 100 Mbps full-duplex mac:0c:c4:7a:d5:48:43 NCSI: probing channels NCSI: configuring channel 0 NCSI: configuration done! BOOTP broadcast 1 BOOTP broadcast 2 DHCP client bound to address 10.61.161.188 (255 ms) [0]: https://patchwork.ozlabs.org/patch/1107087/ Changes in v2: - Fix endianess issue when setting MAC address - Make checksum offsets easier to read - Instantiate per-phy ncsi_priv structures - Update ncsi command help text - Used update ncsi-pkt.h version to include SPDX header Samuel Mendoza-Jonas (4): phy: Add support for the NC-SI protocol phy: Include NC-SI in phy setup net/ftgmac100: Add NC-SI mode support net: NC-SI setup and handling cmd/Kconfig | 8 + cmd/net.c | 18 + drivers/net/ftgmac100.c | 39 +- drivers/net/phy/Kconfig | 4 + drivers/net/phy/Makefile | 1 + drivers/net/phy/ncsi.c | 896 +++++++++++++++++++++++++++++++++++++++ drivers/net/phy/phy.c | 7 + include/net.h | 3 +- include/net/ncsi-pkt.h | 442 +++++++++++++++++++ include/net/ncsi.h | 14 + include/phy.h | 12 + include/phy_interface.h | 2 + net/net.c | 27 +- 13 files changed, 1461 insertions(+), 12 deletions(-) create mode 100644 drivers/net/phy/ncsi.c create mode 100644 include/net/ncsi-pkt.h create mode 100644 include/net/ncsi.h -- 2.21.0

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[U-Boot] [PATCH] Revert "spi: Kconfig: Mark MXS_SPI has DEPRECATED"
by Lukasz Majewski 07 Sep '19

07 Sep '19

This reverts commit d5ded320a14b0a2f97cbed072286748895ad18ac. The mxs_spi.c driver for i.MX2{38} devices has been converted: 'commit d99b018a6e3d ("spi: mxs: Add support DM/DTS for i.MX28 mxs SPI driver (DM_SPI conversion)")' to use Device Tree and Device Model, so the DEPRECATED Kconfig symbol can be now removed. Signed-off-by: Lukasz Majewski <lukma(a)denx.de> --- drivers/spi/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index f459c0a411..8dd3213d48 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -419,7 +419,6 @@ config MXC_SPI config MXS_SPI bool "MXS SPI Driver" - depends on DEPRECATED help Enable the MXS SPI controller driver. This driver can be used on the i.MX23 and i.MX28 SoCs. -- 2.11.0

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[U-Boot] [PATCH 1/2] dm: spi: Return 0 if driver does not implement ops->cs_info
by Bin Meng 07 Sep '19

07 Sep '19

If an SPI controller driver does not implement ops->cs_info, that probably means any chip select number could be valid, hence let's return 0 for spi_cs_info(). Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- drivers/spi/spi-uclass.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c index 88cb2a1..24de0b5 100644 --- a/drivers/spi/spi-uclass.c +++ b/drivers/spi/spi-uclass.c @@ -237,11 +237,10 @@ int spi_cs_info(struct udevice *bus, uint cs, struct spi_cs_info *info) return ops->cs_info(bus, cs, info); /* - * We could assume there is at least one valid chip select, but best - * to be sure and return an error in this case. The driver didn't - * care enough to tell us. + * We could assume there is at least one valid chip select. + * The driver didn't care enough to tell us. */ - return -ENODEV; + return 0; } int spi_find_bus_and_cs(int busnum, int cs, struct udevice **busp, -- 2.7.4

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[U-Boot] [PATCH 1/3] spi: Add spi_write_then_read
by Jagan Teki 07 Sep '19

07 Sep '19

Add support for SPI synchronous write followed by read, this is common interface call from spi-nor to spi drivers. Reviewed-by: Simon Glass <sjg(a)chromium.org> Signed-off-by: Jagan Teki <jagan(a)amarulasolutions.com> --- drivers/spi/spi-uclass.c | 24 ++++++++++++++++++++++++ include/spi.h | 20 ++++++++++++++++++++ 2 files changed, 44 insertions(+) diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c index 88cb2a1262..76c4b53c16 100644 --- a/drivers/spi/spi-uclass.c +++ b/drivers/spi/spi-uclass.c @@ -108,6 +108,30 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, return dm_spi_xfer(slave->dev, bitlen, dout, din, flags); } +int spi_write_then_read(struct spi_slave *slave, const u8 *opcode, + size_t n_opcode, const u8 *txbuf, u8 *rxbuf, + size_t n_buf) +{ + unsigned long flags = SPI_XFER_BEGIN; + int ret; + + if (n_buf == 0) + flags |= SPI_XFER_END; + + ret = spi_xfer(slave, n_opcode * 8, opcode, NULL, flags); + if (ret) { + debug("spi: failed to send command (%zu bytes): %d\n", + n_opcode, ret); + } else if (n_buf != 0) { + ret = spi_xfer(slave, n_buf * 8, txbuf, rxbuf, SPI_XFER_END); + if (ret) + debug("spi: failed to transfer %zu bytes of data: %d\n", + n_buf, ret); + } + + return ret; +} + #if !CONFIG_IS_ENABLED(OF_PLATDATA) static int spi_child_post_bind(struct udevice *dev) { diff --git a/include/spi.h b/include/spi.h index 378594163b..5eec0c4775 100644 --- a/include/spi.h +++ b/include/spi.h @@ -248,6 +248,26 @@ int spi_set_wordlen(struct spi_slave *slave, unsigned int wordlen); int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, void *din, unsigned long flags); +/** + * spi_write_then_read - SPI synchronous write followed by read + * + * This performs a half duplex transaction in which the first transaction + * is to send the opcode and if the length of buf is non-zero then it start + * the second transaction as tx or rx based on the need from respective slave. + * + * @slave: The SPI slave device with which opcode/data will be exchanged + * @opcode: opcode used for specific transfer + * @n_opcode: size of opcode, in bytes + * @txbuf: buffer into which data to be written + * @rxbuf: buffer into which data will be read + * @n_buf: size of buf (whether it's [tx|rx]buf), in bytes + * + * Returns: 0 on success, not 0 on failure + */ +int spi_write_then_read(struct spi_slave *slave, const u8 *opcode, + size_t n_opcode, const u8 *txbuf, u8 *rxbuf, + size_t n_buf); + /* Copy memory mapped data */ void spi_flash_copy_mmap(void *data, void *offset, size_t len); -- 2.18.0.321.gffc6fa0e3

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[U-Boot] [PATCH] spi: soft_spi: Fix data abort if slave is not probed
by Patrice Chotard 06 Sep '19

06 Sep '19

From: Christophe Kerello <christophe.kerello(a)st.com> In case spi_get_bus_and_cs callback is used, spi bus is first probed then slave devices are probed. To avoid a data abort in soft_spi probe function, we need to check that (slave != NULL). If slave is NULL, cs_flags and clk_flags will be initialized with respectively GPIOD_ACTIVE_LOW and 0. Signed-off-by: Christophe Kerello <christophe.kerello(a)st.com> Signed-off-by: Patrice Chotard <patrice.chotard(a)st.com> --- drivers/spi/soft_spi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/spi/soft_spi.c b/drivers/spi/soft_spi.c index b06883f9d0..b80f810bd1 100644 --- a/drivers/spi/soft_spi.c +++ b/drivers/spi/soft_spi.c @@ -215,8 +215,8 @@ static int soft_spi_probe(struct udevice *dev) int cs_flags, clk_flags; int ret; - cs_flags = (slave->mode & SPI_CS_HIGH) ? 0 : GPIOD_ACTIVE_LOW; - clk_flags = (slave->mode & SPI_CPOL) ? GPIOD_ACTIVE_LOW : 0; + cs_flags = (slave && slave->mode & SPI_CS_HIGH) ? 0 : GPIOD_ACTIVE_LOW; + clk_flags = (slave && slave->mode & SPI_CPOL) ? GPIOD_ACTIVE_LOW : 0; if (gpio_request_by_name(dev, "cs-gpios", 0, &plat->cs, GPIOD_IS_OUT | cs_flags) || -- 2.17.1

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[U-Boot] [PATCH] sunxi: Add H6 SPI SPL support
by Marek Kraus 06 Sep '19

06 Sep '19

Add H6 SPI addresses and masks (since H6 memory map is totally different). Tested on Pine H64 rev B with Winbond W25Q128FW, Signed-off-by: Marek Kraus <gamelaster(a)outlook.com> --- arch/arm/mach-sunxi/Kconfig | 2 +- arch/arm/mach-sunxi/spl_spi_sunxi.c | 123 ++++++++++++++++++++++++++++-------- configs/pine_h64_defconfig | 1 + 3 files changed, 98 insertions(+), 28 deletions(-) diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 74e234cded..81b5948454 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -972,7 +972,7 @@ config SPL_STACK_R_ADDR config SPL_SPI_SUNXI bool "Support for SPI Flash on Allwinner SoCs in SPL" - depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I + depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN50I_H6 help Enable support for SPI Flash. This option allows SPL to read from sunxi SPI Flash. It uses the same method as the boot ROM, so does diff --git a/arch/arm/mach-sunxi/spl_spi_sunxi.c b/arch/arm/mach-sunxi/spl_spi_sunxi.c index 043d9f6ead..cdf6d53ec5 100644 --- a/arch/arm/mach-sunxi/spl_spi_sunxi.c +++ b/arch/arm/mach-sunxi/spl_spi_sunxi.c @@ -28,7 +28,7 @@ * A10/A13/A20 (sun4i variant) and everything else (sun6i variant). * Both of them are supported. * - * The pin mixing part is SoC specific and only A10/A13/A20/H3/A64 are + * The pin mixing part is SoC specific and only A10/A13/A20/H3/A64/H6 are * supported at the moment. */ @@ -70,6 +70,25 @@ #define SUN6I_TCR_XCH BIT(31) /*****************************************************************************/ +/* SUN50I_H6 variant of the SPI controller */ +/*****************************************************************************/ + +#define SUN50I_H6_SPI0_CCTL (0x05010000 + 0x24) +#define SUN50I_H6_SPI0_GCR (0x05010000 + 0x04) +#define SUN50I_H6_SPI0_TCR (0x05010000 + 0x08) +#define SUN50I_H6_SPI0_FIFO_STA (0x05010000 + 0x1C) +#define SUN50I_H6_SPI0_MBC (0x05010000 + 0x30) +#define SUN50I_H6_SPI0_MTC (0x05010000 + 0x34) +#define SUN50I_H6_SPI0_BCC (0x05010000 + 0x38) +#define SUN50I_H6_SPI0_TXD (0x05010000 + 0x200) +#define SUN50I_H6_SPI0_RXD (0x05010000 + 0x300) + +#define SUN50I_H6_SPI_GATING_REG (0x03001000 + 0x96C) +#define SUN50I_H6_SPI0_RST BIT(16) +#define SUN50I_H6_SPI0_GATING_CLK BIT(0) +#define SUN50I_H6_CCU_SPI0_CLK (0x03001000 + 0x940) + +/*****************************************************************************/ #define CCM_AHB_GATING0 (0x01C20000 + 0x60) #define CCM_SPI0_CLK (0x01C20000 + 0xA0) @@ -85,19 +104,29 @@ /* * Allwinner A10/A20 SoCs were using pins PC0,PC1,PC2,PC23 for booting - * from SPI Flash, everything else is using pins PC0,PC1,PC2,PC3. + * from SPI Flash, H6 using PC0,PC2,PC3,PC5 , everything else is using + * pins PC0,PC1,PC2,PC3. */ static void spi0_pinmux_setup(unsigned int pin_function) { unsigned int pin; - for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(2); pin++) - sunxi_gpio_set_cfgpin(pin, pin_function); - if (IS_ENABLED(CONFIG_MACH_SUN4I) || IS_ENABLED(CONFIG_MACH_SUN7I)) - sunxi_gpio_set_cfgpin(SUNXI_GPC(23), pin_function); - else + if (IS_ENABLED(CONFIG_MACH_SUN50I_H6)) { + sunxi_gpio_set_cfgpin(SUNXI_GPC(0), pin_function); + sunxi_gpio_set_cfgpin(SUNXI_GPC(2), pin_function); sunxi_gpio_set_cfgpin(SUNXI_GPC(3), pin_function); + sunxi_gpio_set_cfgpin(SUNXI_GPC(5), pin_function); + } else { + for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(2); pin++) + sunxi_gpio_set_cfgpin(pin, pin_function); + + if (IS_ENABLED(CONFIG_MACH_SUN4I) || + IS_ENABLED(CONFIG_MACH_SUN7I)) + sunxi_gpio_set_cfgpin(SUNXI_GPC(23), pin_function); + else + sunxi_gpio_set_cfgpin(SUNXI_GPC(3), pin_function); + } } /* @@ -106,26 +135,43 @@ static void spi0_pinmux_setup(unsigned int pin_function) static void spi0_enable_clock(void) { /* Deassert SPI0 reset on SUN6I */ - if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) + if (IS_ENABLED(CONFIG_MACH_SUN50I_H6)) + setbits_le32(SUN50I_H6_SPI_GATING_REG, + SUN50I_H6_SPI0_RST); + else if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) setbits_le32(SUN6I_BUS_SOFT_RST_REG0, (1 << AHB_RESET_SPI0_SHIFT)); /* Open the SPI0 gate */ - setbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0)); + if (IS_ENABLED(CONFIG_MACH_SUN50I_H6)) + setbits_le32(SUN50I_H6_SPI_GATING_REG, + SUN50I_H6_SPI0_GATING_CLK); + else + setbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0)); /* Divide by 4 */ - writel(SPI0_CLK_DIV_BY_4, IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I) ? - SUN6I_SPI0_CCTL : SUN4I_SPI0_CCTL); + if (IS_ENABLED(CONFIG_MACH_SUN50I_H6)) + writel(SPI0_CLK_DIV_BY_4, SUN50I_H6_SPI0_CCTL); + else + writel(SPI0_CLK_DIV_BY_4, IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I) ? + SUN6I_SPI0_CCTL : SUN4I_SPI0_CCTL); + /* 24MHz from OSC24M */ - writel((1 << 31), CCM_SPI0_CLK); + writel((1 << 31), IS_ENABLED(CONFIG_MACH_SUN50I_H6) ? + SUN50I_H6_CCU_SPI0_CLK : CCM_SPI0_CLK); - if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) { + if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I) || + IS_ENABLED(CONFIG_MACH_SUN50I_H6)) { /* Enable SPI in the master mode and do a soft reset */ - setbits_le32(SUN6I_SPI0_GCR, SUN6I_CTL_MASTER | - SUN6I_CTL_ENABLE | - SUN6I_CTL_SRST); + setbits_le32(IS_ENABLED(CONFIG_MACH_SUN50I_H6) ? + SUN50I_H6_SPI0_GCR : SUN6I_SPI0_GCR, + SUN6I_CTL_MASTER | + SUN6I_CTL_ENABLE | + SUN6I_CTL_SRST); + /* Wait for completion */ - while (readl(SUN6I_SPI0_GCR) & SUN6I_CTL_SRST) + while (readl(IS_ENABLED(CONFIG_MACH_SUN50I_H6) ? + SUN50I_H6_SPI0_GCR : SUN6I_SPI0_GCR) & SUN6I_CTL_SRST) ; } else { /* Enable SPI in the master mode and reset FIFO */ @@ -139,22 +185,33 @@ static void spi0_enable_clock(void) static void spi0_disable_clock(void) { /* Disable the SPI0 controller */ - if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) - clrbits_le32(SUN6I_SPI0_GCR, SUN6I_CTL_MASTER | - SUN6I_CTL_ENABLE); + if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I) || + IS_ENABLED(CONFIG_MACH_SUN50I_H6)) + clrbits_le32(IS_ENABLED(CONFIG_MACH_SUN50I_H6) ? + SUN50I_H6_SPI0_GCR : SUN6I_SPI0_GCR, + SUN6I_CTL_MASTER | + SUN6I_CTL_ENABLE); else clrbits_le32(SUN4I_SPI0_CTL, SUN4I_CTL_MASTER | SUN4I_CTL_ENABLE); /* Disable the SPI0 clock */ - writel(0, CCM_SPI0_CLK); + writel(0, IS_ENABLED(CONFIG_MACH_SUN50I_H6) ? + SUN50I_H6_CCU_SPI0_CLK : CCM_SPI0_CLK); /* Close the SPI0 gate */ - clrbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0)); + if (IS_ENABLED(CONFIG_MACH_SUN50I_H6)) + clrbits_le32(SUN50I_H6_SPI_GATING_REG, + SUN50I_H6_SPI0_GATING_CLK); + else + clrbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0)); /* Assert SPI0 reset on SUN6I */ - if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) - clrbits_le32(SUN6I_BUS_SOFT_RST_REG0, + if (IS_ENABLED(CONFIG_MACH_SUN50I_H6)) + setbits_le32(SUN50I_H6_SPI_GATING_REG, + SUN50I_H6_SPI0_RST); + else if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) + setbits_le32(SUN6I_BUS_SOFT_RST_REG0, (1 << AHB_RESET_SPI0_SHIFT)); } @@ -162,7 +219,7 @@ static void spi0_init(void) { unsigned int pin_function = SUNXI_GPC_SPI0; - if (IS_ENABLED(CONFIG_MACH_SUN50I)) + if (IS_ENABLED(CONFIG_MACH_SUN50I) || IS_ENABLED(CONFIG_MACH_SUN50I_H6)) pin_function = SUN50I_GPC_SPI0; spi0_pinmux_setup(pin_function); @@ -173,7 +230,9 @@ static void spi0_deinit(void) { /* New SoCs can disable pins, older could only set them as input */ unsigned int pin_function = SUNXI_GPIO_INPUT; - if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) + + if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I) || + IS_ENABLED(CONFIG_MACH_SUN50I_H6)) pin_function = SUNXI_GPIO_DISABLE; spi0_disable_clock(); @@ -233,7 +292,17 @@ static void spi0_read_data(void *buf, u32 addr, u32 len) if (chunk_len > SPI_READ_MAX_SIZE) chunk_len = SPI_READ_MAX_SIZE; - if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) { + if (IS_ENABLED(CONFIG_MACH_SUN50I_H6)) { + sunxi_spi0_read_data(buf8, addr, chunk_len, + SUN50I_H6_SPI0_TCR, + SUN6I_TCR_XCH, + SUN50I_H6_SPI0_FIFO_STA, + SUN50I_H6_SPI0_TXD, + SUN50I_H6_SPI0_RXD, + SUN50I_H6_SPI0_MBC, + SUN50I_H6_SPI0_MTC, + SUN50I_H6_SPI0_BCC); + } else if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) { sunxi_spi0_read_data(buf8, addr, chunk_len, SUN6I_SPI0_TCR, SUN6I_TCR_XCH, diff --git a/configs/pine_h64_defconfig b/configs/pine_h64_defconfig index e34f4fd1e4..baddc33abb 100644 --- a/configs/pine_h64_defconfig +++ b/configs/pine_h64_defconfig @@ -6,6 +6,7 @@ CONFIG_MMC0_CD_PIN="PF6" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_PSCI_RESET is not set CONFIG_NR_DRAM_BANKS=1 +CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -- 2.11.0

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