December 2019 - U-Boot

[PATCH 1/1] efi_loader: adjust file system info
by Heinrich Schuchardt 08 Dec '19

08 Dec '19

When the GetInfo() method of the EFI_FILE_PROTOCOL is called to retrieve the file system info we claim that the volume is read only and has no free space. This leads to failures in programs that check this information before writing to the volume like SCT's InstallSct.efi. Currently there is no function to determine these parameters in U-Boot. So let's return optimistic values: Return that the volume is writable. Return the volume size as free space. Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- lib/efi_loader/efi_file.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/lib/efi_loader/efi_file.c b/lib/efi_loader/efi_file.c index 6d3f680e56..140116ddc4 100644 --- a/lib/efi_loader/efi_file.c +++ b/lib/efi_loader/efi_file.c @@ -656,9 +656,16 @@ static efi_status_t EFIAPI efi_file_getinfo(struct efi_file_handle *file, memset(info, 0, required_size); info->size = required_size; - info->read_only = true; + /* + * TODO: We cannot determine if the volume can be written to. + */ + info->read_only = false; info->volume_size = part.size * part.blksz; - info->free_space = 0; + /* + * TODO: We currently have no function to determine the free + * space. The volume size is the best upper bound we have. + */ + info->free_space = info->volume_size; info->block_size = part.blksz; /* * TODO: The volume label is not available in U-Boot. -- 2.24.0

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[PATCH v2 0/4] efi_loader: prepare for FIT images
by Heinrich Schuchardt 08 Dec '19

08 Dec '19

A patch series has been suggested to provide secure UEFI boot via FIT images. This patch series exports the functions needed for the implementation. v2: Resend the efi_install_fdt() rework patches. Export the efi_run_image() and efi_install_fdt(). Heinrich Schuchardt (4): efi_loader: pass address to efi_install_fdt() efi_loader: use hardware device tree by default efi_loader: carve out efi_run_image() efi_loader: export efi_install_fdt() cmd/bootefi.c | 101 ++++++++++++++++++++++++++----------------- include/efi_loader.h | 7 +++ 2 files changed, 69 insertions(+), 39 deletions(-) -- 2.24.0

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[PATCH 1/1] arch: arm: Program GIC LPI configuration table
by Vladimir Olovyannikov 06 Dec '19

06 Dec '19

From: Bharat Kumar Reddy Gooty <bharat.gooty(a)broadcom.com> Programs the following: 1. Redistributor PROCBASER configuration table (which is common for all redistributors) 2. Redistributor pending table (PENDBASER), for all the available redistributors. Signed-off-by: Bharat Kumar Reddy Gooty <bharat.gooty(a)broadcom.com> Signed-off-by: Vladimir Olovyannikov <vladimir.olovyannikov(a)broadcom.com> --- arch/arm/Kconfig | 11 +++ arch/arm/include/asm/gic-v3.h | 134 ++++++++++++++++++++++++++++++++++ arch/arm/lib/Makefile | 3 + arch/arm/lib/gic-v3-its.c | 100 +++++++++++++++++++++++++ 4 files changed, 248 insertions(+) create mode 100644 arch/arm/include/asm/gic-v3.h create mode 100644 arch/arm/lib/gic-v3-its.c diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f96841c777..cf46aa867d 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -61,6 +61,17 @@ config LNX_KRNL_IMG_TEXT_OFFSET_BASE endif endif +config GIC_V3_ITS + bool "ARM GICV3 ITS" + default n + help + ARM GICV3 Interrupt translation service (ITS). + Basic support for programming locality specific peripheral + interrupts (LPI) configuration tables and enable LPI tables. + LPI configuration table can be used by u-boot or Linux. + ARM GICV3 has limitation, once the LPI table is enabled, LPI + configuration table can not be re-programmed, unless GICV3 reset. + config STATIC_RELA bool default y if ARM64 && !POSITION_INDEPENDENT diff --git a/arch/arm/include/asm/gic-v3.h b/arch/arm/include/asm/gic-v3.h new file mode 100644 index 0000000000..ac6c9e7013 --- /dev/null +++ b/arch/arm/include/asm/gic-v3.h @@ -0,0 +1,134 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 Broadcom. + */ + +#ifndef __GIC_V3_H__ +#define __GIC_V3_H__ + +#define GICR_CTLR_ENABLE_LPIS BIT(0) +#define GICR_CTLR_RWP BIT(3) + +#define GICR_TYPER_CPU_NUMBER(r) (((r) >> 8) & 0xffff) + +#define GICR_WAKER_PROCESSORSLEEP BIT(1) +#define GICR_WAKER_CHILDRENASLEEP BIT(2) + +#define GIC_BASER_CACHE_NCNB 0ULL +#define GIC_BASER_CACHE_SAMEASINNER 0ULL +#define GIC_BASER_CACHE_NC 1ULL +#define GIC_BASER_CACHE_RAWT 2ULL +#define GIC_BASER_CACHE_RAWB 3ULL +#define GIC_BASER_CACHE_WAWT 4ULL +#define GIC_BASER_CACHE_WAWB 5ULL +#define GIC_BASER_CACHE_RAWAWT 6ULL +#define GIC_BASER_CACHE_RAWAWB 7ULL +#define GIC_BASER_CACHE_MASK 7ULL +#define GIC_BASER_NONSHAREABLE 0ULL +#define GIC_BASER_INNERSHAREABLE 1ULL +#define GIC_BASER_OUTERSHAREABLE 2ULL +#define GIC_BASER_SHAREABILITY_MASK 3ULL + +#define GIC_BASER_CACHEABILITY(reg, inner_outer, type) \ + (GIC_BASER_CACHE_##type << reg##_##inner_outer##_CACHEABILITY_SHIFT) + +#define GIC_BASER_SHAREABILITY(reg, type) \ + (GIC_BASER_##type << reg##_SHAREABILITY_SHIFT) + +/* encode a size field of width @w containing @n - 1 units */ +#define GIC_ENCODE_SZ(n, w) (((unsigned long)(n) - 1) &\ + GENMASK_ULL(((w) - 1), 0)) + +#define GICR_PROPBASER_SHAREABILITY_SHIFT (10) +#define GICR_PROPBASER_INNER_CACHEABILITY_SHIFT (7) +#define GICR_PROPBASER_OUTER_CACHEABILITY_SHIFT (56) +#define GICR_PROPBASER_SHAREABILITY_MASK \ + GIC_BASER_SHAREABILITY(GICR_PROPBASER, SHAREABILITY_MASK) +#define GICR_PROPBASER_INNER_CACHEABILITY_MASK \ + GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, MASK) +#define GICR_PROPBASER_OUTER_CACHEABILITY_MASK \ + GIC_BASER_CACHEABILITY(GICR_PROPBASER, OUTER, MASK) +#define GICR_PROPBASER_CACHEABILITY_MASK GICR_PROPBASER_INNER_CACHEABILITY_MASK + +#define GICR_PROPBASER_INNERSHAREABLE \ + GIC_BASER_SHAREABILITY(GICR_PROPBASER, INNERSHAREABLE) + +#define GICR_PROPBASER_NCNB \ + GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, NCNB) +#define GICR_PROPBASER_NC \ + GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, NC) +#define GICR_PROPBASER_RAWT \ + GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RAWT) +#define GICR_PROPBASER_RAWB \ + GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RAWB) +#define GICR_PROPBASER_WAWT \ + GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, WAWT) +#define GICR_PROPBASER_WAWB \ + GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, WAWB) +#define GICR_PROPBASER_RAWAWT \ + GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RAWAWT) +#define GICR_PROPBASER_RAWAWB \ + GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RAWAWB) + +#define GICR_PROPBASER_IDBITS_MASK (0x1f) +#define GICR_PROPBASER_ADDRESS(x) ((x) & GENMASK_ULL(51, 12)) +#define GICR_PENDBASER_ADDRESS(x) ((x) & GENMASK_ULL(51, 16)) + +#define GICR_PENDBASER_SHAREABILITY_SHIFT (10) +#define GICR_PENDBASER_INNER_CACHEABILITY_SHIFT (7) +#define GICR_PENDBASER_OUTER_CACHEABILITY_SHIFT (56) +#define GICR_PENDBASER_SHAREABILITY_MASK \ + GIC_BASER_SHAREABILITY(GICR_PENDBASER, SHAREABILITY_MASK) +#define GICR_PENDBASER_INNER_CACHEABILITY_MASK \ + GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, MASK) +#define GICR_PENDBASER_OUTER_CACHEABILITY_MASK \ + GIC_BASER_CACHEABILITY(GICR_PENDBASER, OUTER, MASK) +#define GICR_PENDBASER_CACHEABILITY_MASK \ + GICR_PENDBASER_INNER_CACHEABILITY_MASK + +#define GICR_PENDBASER_INNERSHAREABLE \ + GIC_BASER_SHAREABILITY(GICR_PENDBASER, INNERSHAREABLE) + +#define GICR_PENDBASER_NCNB \ + GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, NCNB) +#define GICR_PENDBASER_NC \ + GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, NC) +#define GICR_PENDBASER_RAWT \ + GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RAWT) +#define GICR_PENDBASER_RAWB \ + GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RAWB) +#define GICR_PENDBASER_WAWT \ + GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, WAWT) +#define GICR_PENDBASER_WAWB \ + GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, WAWB) +#define GICR_PENDBASER_RAWAWT \ + GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RAWAWT) +#define GICR_PENDBASER_RAWAWB \ + GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RAWAWB) + +#define GICR_PENDBASER_PTZ BIT_ULL(62) + +#define ITS_MAX_LPI_NRBITS 16 /* 64K LPIs */ + +#define GICD_TYPER_ID_BITS(typer) ((((typer) >> 19) & 0x1f) + 1) +#define GICD_TYPER_NUM_LPIS(typer) ((((typer) >> 11) & 0x1f) + 1) +#define GICD_TYPER_IRQS(typer) ((((typer) & 0x1f) + 1) * 32) + +/* Message based interrupts support */ +#define GICD_TYPER_MBIS BIT(16) +/* LPI support */ +#define GICD_TYPER_LPIS BIT(17) +#define GICD_TYPER_RSS BIT(26) + +#define GIC_REDISTRIBUTOR_OFFSET 0x20000 + +#ifdef CONFIG_GIC_V3_ITS +int gic_lpi_tables_init(u64 base, u32 max_redist); +#else +int gic_lpi_tables_init(u64 base, u32 max_redist) +{ + return 0; +} +#endif /* CONFIG_GIC_V3_ITS */ + +#endif /* __GIC_V3_H__ */ diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile index 9de9a9acee..942ed1c73a 100644 --- a/arch/arm/lib/Makefile +++ b/arch/arm/lib/Makefile @@ -52,6 +52,9 @@ obj-$(CONFIG_FSL_LAYERSCAPE) += ccn504.o ifneq ($(CONFIG_GICV2)$(CONFIG_GICV3),) obj-y += gic_64.o endif +ifdef CONFIG_GIC_V3_ITS +obj-y += gic-v3-its.o +endif obj-y += interrupts_64.o else obj-y += interrupts.o diff --git a/arch/arm/lib/gic-v3-its.c b/arch/arm/lib/gic-v3-its.c new file mode 100644 index 0000000000..e19ab01621 --- /dev/null +++ b/arch/arm/lib/gic-v3-its.c @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 Broadcom. + */ +#include <common.h> +#include <asm/gic.h> +#include <asm/gic-v3.h> +#include <asm/io.h> + +static u32 lpi_id_bits; + +#define LPI_NRBITS lpi_id_bits +#define LPI_PROPBASE_SZ ALIGN(BIT(LPI_NRBITS), SZ_64K) +#define LPI_PENDBASE_SZ ALIGN(BIT(LPI_NRBITS) / 8, SZ_64K) + +/* + * Program the GIC LPI configuration tables for all + * the re-distributors and enable the LPI table + * base: Configuration table address + * num_redist: number of redistributors + */ +int gic_lpi_tables_init(u64 base, u32 num_redist) +{ + u32 gicd_typer; + u64 val; + u64 tmp; + int i; + u64 redist_lpi_base; + u64 pend_base = GICR_BASE + GICR_PENDBASER; + + gicd_typer = readl(GICD_BASE + GICD_TYPER); + + /* GIC support for Locality specific peripheral interrupts (LPI's) */ + if (!(gicd_typer & GICD_TYPER_LPIS)) { + pr_err("GIC implementation does not support LPI's\n"); + return -EINVAL; + } + + /* + * Check for LPI is disabled for all the redistributors. + * Once the LPI table is enabled, can not program the + * LPI configuration tables again, unless the GIC is reset. + */ + for (i = 0; i < num_redist; i++) { + u32 offset = i * GIC_REDISTRIBUTOR_OFFSET; + + if ((readl((uintptr_t)(GICR_BASE + offset))) & + GICR_CTLR_ENABLE_LPIS) { + pr_err("Re-Distributor %d LPI is already enabled\n", + i); + return -EINVAL; + } + } + + /* lpi_id_bits to get LPI_PENDBASE_SZ and LPi_PROPBASE_SZ */ + lpi_id_bits = min_t(u32, GICD_TYPER_ID_BITS(gicd_typer), + ITS_MAX_LPI_NRBITS); + + /* Set PropBase */ + val = (base | + GICR_PROPBASER_INNERSHAREABLE | + GICR_PROPBASER_RAWAWB | + ((LPI_NRBITS - 1) & GICR_PROPBASER_IDBITS_MASK)); + + writeq(val, (GICR_BASE + GICR_PROPBASER)); + tmp = readl(GICR_BASE + GICR_PROPBASER); + if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) { + if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) { + val &= ~(GICR_PROPBASER_SHAREABILITY_MASK | + GICR_PROPBASER_CACHEABILITY_MASK); + val |= GICR_PROPBASER_NC; + writeq(val, (GICR_BASE + GICR_PROPBASER)); + } + } + + redist_lpi_base = base + LPI_PROPBASE_SZ; + + for (i = 0; i < num_redist; i++) { + u32 offset = i * GIC_REDISTRIBUTOR_OFFSET; + + val = ((redist_lpi_base + (i * LPI_PENDBASE_SZ)) | + GICR_PENDBASER_INNERSHAREABLE | + GICR_PENDBASER_RAWAWB); + + writeq(val, (uintptr_t)(pend_base + offset)); + tmp = readq((uintptr_t)(pend_base + offset)); + if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) { + val &= ~(GICR_PENDBASER_SHAREABILITY_MASK | + GICR_PENDBASER_CACHEABILITY_MASK); + val |= GICR_PENDBASER_NC; + writeq(val, (uintptr_t)(pend_base + offset)); + } + + /* Enable LPI for the redistributor */ + writel(GICR_CTLR_ENABLE_LPIS, (uintptr_t)(GICR_BASE + offset)); + } + + return 0; +} + -- 2.17.1

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[PATCH] Makefile: Ensure tools directory exists in output prior to use
by Tom Rini 06 Dec '19

06 Dec '19

With the change to make tools/version.h a file we need to make sure that the output directory exists first otherwise we will get a build failure. Reported-by: Peter Robinson <pbrobinson(a)gmail.com> Tested-by: Peter Robinson <pbrobinson(a)gmail.com> Fixes: 4d90f6cd9813 ("tools: Avoid creating symbolic links for tools/version.h") Signed-off-by: Tom Rini <trini(a)konsulko.com> --- Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/Makefile b/Makefile index 0ee0c701022a..960926caad45 100644 --- a/Makefile +++ b/Makefile @@ -1889,6 +1889,7 @@ checkarmreloc: u-boot fi tools/version.h: include/version.h + $(Q)mkdir -p $(dir $@) $(call if_changed,copy) envtools: scripts_basic $(version_h) $(timestamp_h) tools/version.h -- 2.17.1

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[U-Boot] [PATCH v3 0/6] cmd: remove NET and CMD_NET dependency for CMD_PXE
by Patrice Chotard 06 Dec '19

06 Dec '19

It allows to use sysboot command on board which have no NET support. Currently, sysboot command can't be used if CMD_NET and NET flags are not set, while sysboot allows to load extlinux.conf file from local filesystem, so it doesn't need to depend of CMD_NET and NET flags. - Move from_env() from pxe.c to nvedit.c. - As sysboot and pxe commands are sharing piece of code, put this common code into a new file pxe_utils.c. - Extract sysboot command's code outside pxe.c and create a new sysboot.c file. - Fix some checkpatch issues. Patrice Chotard (6): cmd: Migrate from_env() from pxe.c to nvedit.c cmd: Prepare sysboot command independence cmd: sysboot: Create a sysboot command dedicated file cmd: pxe_utils: Fix checkpatch WARNING/CHECK cmd: sysboot: Fix checkpatch WARNING/CHECK cmd: pxe: Fix checkpatch WARNING/CHECK Kconfig | 1 + cmd/Kconfig | 6 + cmd/Makefile | 3 +- cmd/nvedit.c | 17 + cmd/pxe.c | 1730 ++--------------------------------------------- cmd/pxe_utils.c | 1413 ++++++++++++++++++++++++++++++++++++++ cmd/pxe_utils.h | 90 +++ cmd/sysboot.c | 134 ++++ include/env.h | 10 + 9 files changed, 1726 insertions(+), 1678 deletions(-) create mode 100644 cmd/pxe_utils.c create mode 100644 cmd/pxe_utils.h create mode 100644 cmd/sysboot.c -- 2.17.1

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[PATCH] buildman: Ignore blank lines during size checks
by Tom Rini 06 Dec '19

06 Dec '19

Today when parsing the .sizes files we get a warning about an invalid line in the file as it's blank. Solve this by checking that we have a non-blank line prior to processing. Cc: Simon Glass <sjg(a)chromium.org> Signed-off-by: Tom Rini <trini(a)konsulko.com> --- tools/buildman/builder.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/tools/buildman/builder.py b/tools/buildman/builder.py index cfbe4c26b1a9..784c64122ba6 100644 --- a/tools/buildman/builder.py +++ b/tools/buildman/builder.py @@ -577,7 +577,8 @@ class Builder: sym = {} for line in fd.readlines(): try: - size, type, name = line[:-1].split() + if line.strip(): + size, type, name = line[:-1].split() except: Print("Invalid line in file '%s': '%s'" % (fname, line[:-1])) continue -- 2.17.1

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[U-Boot,0/8] Add support for MediaTek MT7622 SoC
by Sam Shih 06 Dec '19

06 Dec '19

This patch series adds basic boot support on eMMC/SD/spi-nor for the MediaTek MT7622 SoC based boards. This series add the clock, pinctrl drivers and the SoC initializaton code. Sam Shih (8): ARM: MediaTek: Add support for MediaTek MT7622 SoC pinctrl: mediatek: add driver for MT7622 pinctrl: mediatek: add support for different pinctrl clk: mediatek: add driver for MT7622 clk: mediatek: fix clock-rate overflow problem power: domain: add power domain support for MT7622 mmc: add mmc and sd support for MT7622 Add support for MT7622 reference board arch/arm/dts/Makefile | 1 + arch/arm/dts/mt7622-rfb.dts | 179 +++++ arch/arm/dts/mt7622.dtsi | 191 +++++ arch/arm/mach-mediatek/Kconfig | 9 + arch/arm/mach-mediatek/Makefile | 1 + arch/arm/mach-mediatek/mt7622/Makefile | 3 + arch/arm/mach-mediatek/mt7622/init.c | 51 ++ board/mediatek/mt7622/Kconfig | 17 + board/mediatek/mt7622/MAINTAINERS | 6 + board/mediatek/mt7622/Makefile | 4 + board/mediatek/mt7622/mt7622_rfb.c | 23 + configs/mt7622_rfb_defconfig | 57 ++ drivers/clk/mediatek/Makefile | 1 + drivers/clk/mediatek/clk-mt7622.c | 678 ++++++++++++++++ drivers/clk/mediatek/clk-mtk.c | 6 +- drivers/mmc/mtk-sd.c | 10 + drivers/pinctrl/mediatek/Kconfig | 4 + drivers/pinctrl/mediatek/Makefile | 1 + drivers/pinctrl/mediatek/pinctrl-mt7622.c | 754 ++++++++++++++++++ drivers/pinctrl/mediatek/pinctrl-mt7623.c | 2 + drivers/pinctrl/mediatek/pinctrl-mt7629.c | 2 + drivers/pinctrl/mediatek/pinctrl-mt8516.c | 2 + drivers/pinctrl/mediatek/pinctrl-mt8518.c | 2 + drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 122 ++- drivers/pinctrl/mediatek/pinctrl-mtk-common.h | 12 +- drivers/power/domain/mtk-power-domain.c | 6 + include/configs/mt7622.h | 46 ++ include/dt-bindings/clock/mt7622-clk.h | 271 +++++++ 28 files changed, 2439 insertions(+), 22 deletions(-) create mode 100644 arch/arm/dts/mt7622-rfb.dts create mode 100644 arch/arm/dts/mt7622.dtsi create mode 100644 arch/arm/mach-mediatek/mt7622/Makefile create mode 100644 arch/arm/mach-mediatek/mt7622/init.c create mode 100644 board/mediatek/mt7622/Kconfig create mode 100644 board/mediatek/mt7622/MAINTAINERS create mode 100644 board/mediatek/mt7622/Makefile create mode 100644 board/mediatek/mt7622/mt7622_rfb.c create mode 100644 configs/mt7622_rfb_defconfig create mode 100644 drivers/clk/mediatek/clk-mt7622.c create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt7622.c create mode 100644 include/configs/mt7622.h create mode 100644 include/dt-bindings/clock/mt7622-clk.h -- 2.17.1

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U-Boot 2020.01-rc4 - PCI support missing on Trimslice Pro
by Stuart Winter 06 Dec '19

06 Dec '19

Hello I've built U-Boot 2020.01-rc4 and found that the PCI bus isn't recognised on my Trimslice Pro. This is using the 'trimslice' default U-Boot configuration file ('make trimslice_config') I tried 2019.04 and a couple of other older versions, just in case - but nothing recent works. Is there anything I can do to debug this? The configuration file looks okay, in that the Tegra PCI support is selected. Thanks s. U-Boot 2020.01-rc4 (Dec 06 2019 - 14:08:52 +0000) SoC: tegra20 Model: Compulab TrimSlice board Board: Compulab Trimslice DRAM: 1 GiB MMC: sdhci@c8000000: 1, sdhci@c8000600: 0 Loading Environment from SPI Flash... SF: Detected w25q80bl with page size 256 Bytes, erase size 4 KiB, total 1 MiB *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial Net: No ethernet found. Hit any key to stop autoboot: 0 Tegra20 (TrimSlice) # Tegra20 (TrimSlice) # pci No such bus Tegra20 (TrimSlice) # Compare with the U-Boot from the vendor (Compulab): U-Boot 2012.04.01-1.02 (Feb 11 2013 - 16:11:37) TEGRA2 Board: Compulab Trimslice DRAM: 1 GiB MMC: Tegra2 SD/MMC: 0, Tegra2 SD/MMC: 1 SF: Detected W25Q80BL with page size 4 KiB, total 1 MiB In: serial Out: serial Err: serial Net: PCI device RTL8169#0: unknown chip version, assuming RTL-8169 PCI device: TxConfig = 0x2B1000C0 RTL8169#0 Hit any key to stop autoboot: 0 Tegra2 (TrimSlice) # Tegra2 (TrimSlice) # pci Scanning PCI devices on bus 0 BusDevFun VendorId DeviceId Device Class Sub-Class _____________________________________________________________ 00.00.00 0x10de 0x0bf0 Bridge device 0x04 Tegra2 (TrimSlice) # -- Stuart Winter

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Pull request: u-boot-rockchip-20191206
by Kever Yang 06 Dec '19

06 Dec '19

Hi Tom, Please pull the rockchip update: - rockchip pwm driver update to support all the SoCs - RK3308 GMAC and pinctrl support - More UART interface support on PX30 and pmugrf reg fix - Fixup on misc for eth_addr/serial# - Other updates on variant SoCs Travis: https://travis-ci.org/keveryang/u-boot/builds/621192067 Thanks, - Kever The following changes since commit 7e5ee346fc4c26c5f96ae13d599cf31d05fa6772: Merge git://git.denx.de/u-boot-sh (2019-12-04 18:10:04 -0500) are available in the Git repository at: https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip.git tags/u-boot-rockchip-20191206 for you to fetch changes up to b2e373d16b0345d3c3f4beefdf0889e83faf173d: rockchip: allow loading larger kernels (2019-12-06 00:06:23 +0800) ---------------------------------------------------------------- Andy Yan (4): doc: rockchip: Update build instruction for rk3308 rockchip: rk3308: enable spl-fifo-mode for emmc rockchip: px5: enable spl-fifo-mode for emmc for px5-evb rockchip: evb-px5: disable NET Ben Wolsieffer (2): rockchip: rk3328: rock64: enable CONFIG_MISC_INIT_R rockchip: allow loading larger kernels David Wu (6): net: gmac_rockchip: Add support for rk3308 arm: dts: Add mac node for rk3308 at dtsi level dts: rk3308: Enable ethernet function supported for Firefly ROC_RK3308_CC pwm: rk_pwm: Make PWM driver to support all Rockchip Socs arm: rockchip: rk3308: Initialize the iomux configuration pinctrl: rockchip: Add pinctrl support for rk3308 Heiko Stuebner (2): rockchip: misc: don't fail if eth_addr already set rockchip: misc: protect serial# from getting overwritten Kever Yang (1): rockchip: config: add support for firefly-px30 board Paul Kocialkowski (3): rockchip: px30: Fixup PMUGRF registers layout order rockchip: px30: Rename CONFIG_DEBUG_UART2_CHANNEL to CONFIG_DEBUG_UART_CHANNEL rockchip: px30: Add support for using UART3 as debug UART arch/arm/dts/rk3308-roc-cc.dts | 9 + arch/arm/dts/rk3308-u-boot.dtsi | 2 + arch/arm/dts/rk3308.dtsi | 22 ++ arch/arm/dts/rk3368-px5-evb-u-boot.dtsi | 2 + arch/arm/include/asm/arch-rockchip/cru_px30.h | 19 + arch/arm/include/asm/arch-rockchip/grf_px30.h | 16 +- arch/arm/include/asm/arch-rockchip/pwm.h | 17 +- arch/arm/mach-rockchip/misc.c | 13 +- arch/arm/mach-rockchip/px30/Kconfig | 6 +- arch/arm/mach-rockchip/px30/px30.c | 81 +++- arch/arm/mach-rockchip/rk3308/rk3308.c | 37 ++ board/rockchip/evb_px30/MAINTAINERS | 1 + configs/evb-px5_defconfig | 2 +- configs/firefly-px30_defconfig | 113 ++++++ configs/rock64-rk3328_defconfig | 1 + doc/README.rockchip | 1 - drivers/net/gmac_rockchip.c | 65 ++++ drivers/pinctrl/rockchip/Makefile | 1 + drivers/pinctrl/rockchip/pinctrl-rk3308.c | 464 +++++++++++++++++++++++ drivers/pinctrl/rockchip/pinctrl-rockchip-core.c | 3 +- drivers/pinctrl/rockchip/pinctrl-rockchip.h | 1 + drivers/pwm/rk_pwm.c | 138 ++++++- include/configs/rk3328_common.h | 2 +- include/configs/rk3399_common.h | 2 +- 24 files changed, 973 insertions(+), 45 deletions(-) create mode 100644 configs/firefly-px30_defconfig create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk3308.c

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Re: [PATCH 4/4] spl: opensbi: wait for ack from secondary harts before entering OpenSBI
by Rick Chen 06 Dec '19

06 Dec '19

Hi Lukas, > From: Lukas Auer [mailto:lukas.auer@aisec.fraunhofer.de] > Sent: Wednesday, December 04, 2019 5:40 AM > To: u-boot(a)lists.denx.de > Cc: Rick Jian-Zhi Chen(陳建志); Anup Patel; Bin Meng; Lukas Auer; Anup Patel > Subject: [PATCH 4/4] spl: opensbi: wait for ack from secondary harts before entering OpenSBI > > At the start, OpenSBI relocates itself to its link address. If the link address ranges of U-Boot SPL and OpenSBI overlap, the relocation can lead to code corruption if a hart is still running U-Boot SPL during relocation. To avoid this problem, the main hart is specified as the preferred boot hart to perform the relocation. This fixes the code corruption problems based on the assumption that since the main hart schedules the secondary harts to enter OpenSBI, it will be the last to enter OpenSBI. However it was reported that this assumption is not always correct. > > To make sure the assumption always holds true, wait for all secondary harts to acknowledge the call-function request before entering OpenSBI on the main hart. > > Reported-by: Rick Chen <rick(a)andestech.com> > Signed-off-by: Lukas Auer <lukas.auer(a)aisec.fraunhofer.de> > --- Reviewed-by: Rick Chen <rick(a)andestech.com> Tested-by: Rick Chen <rick(a)andestech.com> > > common/spl/spl_opensbi.c | 12 +++++++++++- > 1 file changed, 11 insertions(+), 1 deletion(-) > > diff --git a/common/spl/spl_opensbi.c b/common/spl/spl_opensbi.c index 91a411a3db..5ea59d423f 100644 > --- a/common/spl/spl_opensbi.c > +++ b/common/spl/spl_opensbi.c > @@ -75,9 +75,19 @@ void spl_invoke_opensbi(struct spl_image_info *spl_image) > invalidate_icache_all(); > > #ifdef CONFIG_SMP > + /* > + * Start OpenSBI on all secondary harts and wait for acknowledgment. > + * > + * OpenSBI first relocates itself to its link address. This is done by > + * the main hart. To make sure no hart is still running U-Boot SPL > + * during relocation, we wait for all secondary harts to acknowledge > + * the call-function request before entering OpenSBI on the main hart. > + * Otherwise, code corruption can occur if the link address ranges of > + * U-Boot SPL and OpenSBI overlap. > + */ > ret = smp_call_function((ulong)spl_image->entry_point, > (ulong)spl_image->fdt_addr, > - (ulong)&opensbi_info, 0); > + (ulong)&opensbi_info, 1); > if (ret) > hang(); > #endif > -- > 2.21.0 >

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