December 2019 - U-Boot

[PATCH v3 1/3] configs: ls1046afwry: Enable usb network cards support
by Yinbo Zhu 16 Dec '19

16 Dec '19

Enable RTL8152, AX88179 and AX8817X USB network cards support for ls1046afrwy Signed-off-by: Yinbo Zhu <yinbo.zhu(a)nxp.com> --- Change in v3: Update the commit information configs/ls1046afrwy_tfa_defconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/configs/ls1046afrwy_tfa_defconfig b/configs/ls1046afrwy_tfa_defconfig index 4137eda995..49240b051d 100644 --- a/configs/ls1046afrwy_tfa_defconfig +++ b/configs/ls1046afrwy_tfa_defconfig @@ -56,5 +56,9 @@ CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_RTL8152=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -- 2.17.1

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[PATCH] efi_selftest: Update .gitignore
by Sughosh Ganu 16 Dec '19

16 Dec '19

Add the following file to .gitignore efi_miniapp_file_image_exception.h Signed-off-by: Sughosh Ganu <sughosh.ganu(a)linaro.org> --- lib/efi_selftest/.gitignore | 1 + 1 file changed, 1 insertion(+) diff --git a/lib/efi_selftest/.gitignore b/lib/efi_selftest/.gitignore index 293a17b..9cac367 100644 --- a/lib/efi_selftest/.gitignore +++ b/lib/efi_selftest/.gitignore @@ -1,3 +1,4 @@ +efi_miniapp_file_image_exception.h efi_miniapp_file_image_exit.h efi_miniapp_file_image_return.h *.efi -- 2.7.4

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[PATCH v2 1/3] configs: ls1046afwry: Enable usb network card
by Yinbo Zhu 16 Dec '19

16 Dec '19

enable ls1046afwry usb network card r8152_eth AX88179 and AX8817X driver Signed-off-by: Yinbo Zhu <yinbo.zhu(a)nxp.com> --- Change in v2: update the commit information configs/ls1046afrwy_tfa_defconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/configs/ls1046afrwy_tfa_defconfig b/configs/ls1046afrwy_tfa_defconfig index 4137eda995..49240b051d 100644 --- a/configs/ls1046afrwy_tfa_defconfig +++ b/configs/ls1046afrwy_tfa_defconfig @@ -56,5 +56,9 @@ CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_RTL8152=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -- 2.17.1

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[PATCH v1 1/3] enable ls1046afwry usb network card
by Yinbo Zhu 16 Dec '19

16 Dec '19

enable ls1046afwry usb network card r8152_eth AX88179 and AX8817X driver Signed-off-by: Yinbo Zhu <yinbo.zhu(a)nxp.com> --- configs/ls1046afrwy_tfa_defconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/configs/ls1046afrwy_tfa_defconfig b/configs/ls1046afrwy_tfa_defconfig index 1d27408..550e521 100644 --- a/configs/ls1046afrwy_tfa_defconfig +++ b/configs/ls1046afrwy_tfa_defconfig @@ -52,5 +52,9 @@ CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_RTL8152=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -- 2.7.4

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[PATCH] ARM: dts: xilinx: Fix I2C and SPI bus warnings
by Florian Klink 16 Dec '19

16 Dec '19

Ported over from https://patchwork.kernel.org/patch/10599941/ Signed-off-by: Florian Klink <flokli(a)flokli.de> --- arch/arm/dts/zynq-zc702.dts | 12 ++++++------ arch/arm/dts/zynq-zc770-xm010.dts | 2 +- arch/arm/dts/zynq-zc770-xm013.dts | 2 +- 3 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm/dts/zynq-zc702.dts b/arch/arm/dts/zynq-zc702.dts index d10695740f..b043d341d6 100644 --- a/arch/arm/dts/zynq-zc702.dts +++ b/arch/arm/dts/zynq-zc702.dts @@ -181,17 +181,17 @@ #address-cells = <1>; #size-cells = <0>; reg = <7>; - hwmon@52 { + hwmon@34 { compatible = "ti,ucd9248"; - reg = <52>; + reg = <0x34>; }; - hwmon@53 { + hwmon@35 { compatible = "ti,ucd9248"; - reg = <53>; + reg = <0x35>; }; - hwmon@54 { + hwmon@36 { compatible = "ti,ucd9248"; - reg = <54>; + reg = <0x36>; }; }; }; diff --git a/arch/arm/dts/zynq-zc770-xm010.dts b/arch/arm/dts/zynq-zc770-xm010.dts index e1f34653ec..c547d7921d 100644 --- a/arch/arm/dts/zynq-zc770-xm010.dts +++ b/arch/arm/dts/zynq-zc770-xm010.dts @@ -72,7 +72,7 @@ status = "okay"; num-cs = <4>; is-decoded-cs = <0>; - flash@0 { + flash@1 { compatible = "sst25wf080", "jedec,spi-nor"; reg = <1>; spi-max-frequency = <1000000>; diff --git a/arch/arm/dts/zynq-zc770-xm013.dts b/arch/arm/dts/zynq-zc770-xm013.dts index 05a49982cc..bdf0c2f956 100644 --- a/arch/arm/dts/zynq-zc770-xm013.dts +++ b/arch/arm/dts/zynq-zc770-xm013.dts @@ -67,7 +67,7 @@ status = "okay"; num-cs = <4>; is-decoded-cs = <0>; - eeprom: eeprom@0 { + eeprom: eeprom@2 { at25,byte-len = <8192>; at25,addr-mode = <2>; at25,page-size = <32>; -- 2.24.1

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[PATCH 0/3] DM DSA driver for NXP SJA1105 Ethernet switch
by Vladimir Oltean 15 Dec '19

15 Dec '19

This is a driver for the SJA1105 automotive L2 switch. It uses the DSA uclass proposed by Alex Marginean (but not yet merged) here [0]. This is convenient because with this framework, the switch acts as a 4-port Ethernet multiplexer capable of TFTP, but does not do switching, which is not unnecessary in the bootloader, and which would also cause issues in complex networks that rely on STP to block loops. [0]: https://patchwork.ozlabs.org/patch/1203754/ Vladimir Oltean (3): lib: import packing API from Linux include: import if_vlan.h from Linux net: add driver for NXP SJA1105 DSA L2 switch drivers/net/Kconfig | 17 + drivers/net/Makefile | 1 + drivers/net/sja1105.c | 2309 +++++++++++++++++++++++++++++++++++++++ include/linux/if_vlan.h | 26 + include/linux/packing.h | 49 + lib/Kconfig | 17 + lib/Makefile | 1 + lib/packing.c | 208 ++++ 8 files changed, 2628 insertions(+) create mode 100644 drivers/net/sja1105.c create mode 100644 include/linux/if_vlan.h create mode 100644 include/linux/packing.h create mode 100644 lib/packing.c -- 2.17.1

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[GIT PULL] For socfpga-next
by Tan, Ley Foon 15 Dec '19

15 Dec '19

Hi Marek Please pull the following update for socfpga-next. Thanks. Regards Ley Foon The following changes since commit f412fa8c2b82eba609c0f4494bad0da38606aa77: configs: socfpga: fix building Stratix10 and Agilex (2019-12-13 01:58:15 +0100) are available in the Git repository at: https://github.com/lftan/u-boot.git for-marek-next for you to fetch changes up to 9063341301cc9400c7673d369249b0ae8514a07d: ddr: socfpga: Enable ARM64 Non-Secure SDRAM ECC Access (2019-12-13 17:25:37 +0800) ---------------------------------------------------------------- Thor Thayer (2): arm: socfpga: stratix10: Enable SMMU access ddr: socfpga: Enable ARM64 Non-Secure SDRAM ECC Access arch/arm/mach-socfpga/include/mach/firewall.h | 7 +++++++ drivers/ddr/altera/sdram_agilex.c | 6 +++--- drivers/ddr/altera/sdram_s10.c | 20 +++++++++++++++++--- 3 files changed, 27 insertions(+), 6 deletions(-)

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[PATCH v7 04/17] x86: apl: Add hostbridge driver
by Simon Glass 15 Dec '19

15 Dec '19

This driver models the hostbridge as a northbridge. It simply sets up the graphics BAR. It supports of-platdata. Signed-off-by: Simon Glass <sjg(a)chromium.org> Reviewed-by: Bin Meng <bmeng.cn(a)gmail.com> --- Changes in v7: None Changes in v6: - Fix comments for struct apl_hostbridge_platdata Changes in v5: None Changes in v4: - Avoid needing to know internals of pinctrl in this driver - Move code to pinctrl driver - Switch over to use pinctrl for pad init/config Changes in v3: - Move pad programming into the hostbridge to reduce TPL device-tree size - Use pci_get_devfn() Changes in v2: None arch/x86/cpu/apollolake/Makefile | 1 + arch/x86/cpu/apollolake/hostbridge.c | 179 +++++++++++++++++++++++++++ 2 files changed, 180 insertions(+) create mode 100644 arch/x86/cpu/apollolake/hostbridge.c diff --git a/arch/x86/cpu/apollolake/Makefile b/arch/x86/cpu/apollolake/Makefile index 3a8c2f66a3..4d3c08f84e 100644 --- a/arch/x86/cpu/apollolake/Makefile +++ b/arch/x86/cpu/apollolake/Makefile @@ -4,5 +4,6 @@ obj-$(CONFIG_SPL_BUILD) += systemagent.o +obj-y += hostbridge.o obj-y += pmc.o obj-y += uart.o diff --git a/arch/x86/cpu/apollolake/hostbridge.c b/arch/x86/cpu/apollolake/hostbridge.c new file mode 100644 index 0000000000..793853d5b5 --- /dev/null +++ b/arch/x86/cpu/apollolake/hostbridge.c @@ -0,0 +1,179 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2019 Google LLC + */ + +#include <common.h> +#include <dm.h> +#include <dt-structs.h> +#include <spl.h> +#include <asm/intel_pinctrl.h> +#include <asm/intel_regs.h> +#include <asm/pci.h> +#include <asm/arch/systemagent.h> + +/** + * struct apl_hostbridge_platdata - platform data for hostbridge + * + * @dtplat: Platform data for of-platdata + * @early_pads: Early pad data to set up, each (pad, cfg0, cfg1) + * @early_pads_count: Number of pads to process + * @pciex_region_size: BAR length in bytes + * @bdf: Bus/device/function of hostbridge + */ +struct apl_hostbridge_platdata { +#if CONFIG_IS_ENABLED(OF_PLATDATA) + struct dtd_intel_apl_hostbridge dtplat; +#endif + u32 *early_pads; + int early_pads_count; + uint pciex_region_size; + pci_dev_t bdf; +}; + +enum { + PCIEXBAR = 0x60, + PCIEXBAR_LENGTH_256MB = 0, + PCIEXBAR_LENGTH_128MB, + PCIEXBAR_LENGTH_64MB, + + PCIEXBAR_PCIEXBAREN = 1 << 0, + + TSEG = 0xb8, /* TSEG base */ +}; + +static int apl_hostbridge_early_init_pinctrl(struct udevice *dev) +{ + struct apl_hostbridge_platdata *plat = dev_get_platdata(dev); + struct udevice *pinctrl; + int ret; + + ret = uclass_first_device_err(UCLASS_PINCTRL, &pinctrl); + if (ret) + return log_msg_ret("no hostbridge pinctrl", ret); + + return pinctrl_config_pads(pinctrl, plat->early_pads, + plat->early_pads_count); +} + +static int apl_hostbridge_early_init(struct udevice *dev) +{ + struct apl_hostbridge_platdata *plat = dev_get_platdata(dev); + u32 region_size; + ulong base; + u32 reg; + int ret; + + /* Set up the MCHBAR */ + pci_x86_read_config(plat->bdf, MCHBAR, &base, PCI_SIZE_32); + base = MCH_BASE_ADDRESS; + pci_x86_write_config(plat->bdf, MCHBAR, base | 1, PCI_SIZE_32); + + /* + * The PCIEXBAR is assumed to live in the memory mapped IO space under + * 4GiB + */ + pci_x86_write_config(plat->bdf, PCIEXBAR + 4, 0, PCI_SIZE_32); + + switch (plat->pciex_region_size >> 20) { + default: + case 256: + region_size = PCIEXBAR_LENGTH_256MB; + break; + case 128: + region_size = PCIEXBAR_LENGTH_128MB; + break; + case 64: + region_size = PCIEXBAR_LENGTH_64MB; + break; + } + + reg = CONFIG_MMCONF_BASE_ADDRESS | (region_size << 1) + | PCIEXBAR_PCIEXBAREN; + pci_x86_write_config(plat->bdf, PCIEXBAR, reg, PCI_SIZE_32); + + /* + * TSEG defines the base of SMM range. BIOS determines the base + * of TSEG memory which must be at or below Graphics base of GTT + * Stolen memory, hence its better to clear TSEG register early + * to avoid power on default non-zero value (if any). + */ + pci_x86_write_config(plat->bdf, TSEG, 0, PCI_SIZE_32); + + ret = apl_hostbridge_early_init_pinctrl(dev); + if (ret) + return log_msg_ret("pinctrl", ret); + + return 0; +} + +static int apl_hostbridge_ofdata_to_platdata(struct udevice *dev) +{ + struct apl_hostbridge_platdata *plat = dev_get_platdata(dev); + struct udevice *pinctrl; + int ret; + + /* + * The host bridge holds the early pad data needed to get through TPL. + * This is a small amount of data, enough to fit in TPL, so we keep it + * separate from the full pad data, stored in the fsp-s subnode. That + * subnode is not present in TPL, to save space. + */ + ret = uclass_first_device_err(UCLASS_PINCTRL, &pinctrl); + if (ret) + return log_msg_ret("no hostbridge PINCTRL", ret); +#if !CONFIG_IS_ENABLED(OF_PLATDATA) + int root; + + /* Get length of PCI Express Region */ + plat->pciex_region_size = dev_read_u32_default(dev, "pciex-region-size", + 256 << 20); + + root = pci_get_devfn(dev); + if (root < 0) + return log_msg_ret("Cannot get host-bridge PCI address", root); + plat->bdf = root; + + ret = pinctrl_read_pads(pinctrl, dev_ofnode(dev), "early-pads", + &plat->early_pads, &plat->early_pads_count); + if (ret) + return log_msg_ret("early-pads", ret); +#else + struct dtd_intel_apl_hostbridge *dtplat = &plat->dtplat; + int size; + + plat->pciex_region_size = dtplat->pciex_region_size; + plat->bdf = pci_ofplat_get_devfn(dtplat->reg[0]); + + /* Assume that if everything is 0, it is empty */ + plat->early_pads = dtplat->early_pads; + size = ARRAY_SIZE(dtplat->early_pads); + plat->early_pads_count = pinctrl_count_pads(pinctrl, plat->early_pads, + size); + +#endif + + return 0; +} + +static int apl_hostbridge_probe(struct udevice *dev) +{ + if (spl_phase() == PHASE_TPL) + return apl_hostbridge_early_init(dev); + + return 0; +} + +static const struct udevice_id apl_hostbridge_ids[] = { + { .compatible = "intel,apl-hostbridge" }, + { } +}; + +U_BOOT_DRIVER(apl_hostbridge_drv) = { + .name = "intel_apl_hostbridge", + .id = UCLASS_NORTHBRIDGE, + .of_match = apl_hostbridge_ids, + .ofdata_to_platdata = apl_hostbridge_ofdata_to_platdata, + .probe = apl_hostbridge_probe, + .platdata_auto_alloc_size = sizeof(struct apl_hostbridge_platdata), +}; -- 2.24.0.393.g34dc348eaf-goog

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[PATCH v7 00/17] x86: Add initial support for apollolake
by Simon Glass 15 Dec '19

15 Dec '19

Apollo Lake is an Intel SoC generation aimed at relatively low-end embedded systems. It was released in 2016 but has become more popular recently with some embedded boards using it. This series adds support for Apollo Lake. As an example it adds an implementation of chromebook_coral (a large range of Chromebooks released in 2017). The series provides enough support to boot to a prompt. with LCD display, storage, USB, EC and keyboard. Since this is the first time U-Boot has used FSP2 there is quite a bit of refactoring needed. This series is available at u-boot-dm/coral-working Changes in v7: - Add a comment to enable_bios_reset_cpl() - Add the new documentation to the index file - Drop Glacier Lake code - Fix value of GPIO_28_IRQ - Update Kconfig to avoid using def_bool - Update comment in apl_p2sb_early_init() Changes in v6: - Add .driver_data in the designware_pci_supported array - Add a comment about VANILLA - Add a comment about the need for board_run_command() - Add new patch with methods to find the position/size of next SPL phase - Change comment to apl_hostbridge_early_init_pinctrl, not apl_gpio_early_init - Change commented-out enable_rtc_upper_bank() call to a TODO - Drop Glacier Lake code - Drop init of ComB since it is not used - Drop lpc_configure_pads() and probe() function, add a comment about pads - Drop mention of devicetree for VTD feature - Drop mention of ramstage - Drop platform data and pre-PCI code, since DM PCI is available in SPL - Drop unnecessary priv struct and probe method - Fix FSP-M and FSP-S in comments - Fix comments for struct apl_hostbridge_platdata - Fix various coding style problems - Make BOOT_FROM_FAST_SPI_FLASH a Kconfig option - Move image pos/size access functions and symbols to generic SPL code - Move lpss_reset_release() to this commit - Rename init_for_uart() to board_debug_uart_init() - Use 'No SPI' instead of 'SPI2' as a debug message - Use SZ_4G instead of open-coded shift - Use generic gpio compatible string Changes in v5: - Add L2 cache flush function - Add L2 cache flush functoin - Add gpio-controller to GPIO nodes - Allocate the FSP-S data instead of using the stack - Comment out GPIOs in the fsp_s node since we don't use them yet - Correct CPU ACPI IDs - Drop SAFETY_MARGIN - Drop unrelated change metioned by Heiko - Enable SMP - Rename APOLLOLAKE_USB2_PORT_MAX - Use a define for ACPI base address Changes in v4: - Add a comment for enable_bios_reset_cpl() - Add comments for exported functions - Add u-boot,skip-auto-config-until-reloc property to PCI - Adjust the comment for struct dw_i2c_speed_config - Allow pinctrl nodes to have subnodes (i.e. GPIO nodes) - Avoid needing to know internals of pinctrl in this driver - Change apollolake to apl - Detect zero mmio address - Drop GPIO_NUM_PAD_CFG_REGS - Drop duplicate commit 'Create a new sandbox_pci_read_bar() function' - Enable HAVE_X86_FIT - Enable INTEL_GPIO - Move code to pinctrl driver - Name this P-Unit instead of power unit, in the commit message - New GPIO driver binding - Rename arch_fsp_s_preinit() to arch_fsps_preinit() - Set up LPC pads early - Switch over to use pinctrl for pad init/config - Tidy up header guards - Tidy up mixed case in FSP code - Tidy up the header file a little - Update SPI flash protection only in SPL - Update documentation with more detailed memory map - Use 'Apollo Lake' - Use BIT() macro a bit more - Use BIT() macro bit more - Use existing VBT Kconfig option - Use hyphen for device-tree properties - Use tabs instead of spaces - apollolake -> Apollo Lake - use GENMASK() for VTBAR_MASK Changes in v3: - Ad FSP-S support - Add CONFIG_TPL_X86_ASSUME_CPUID to reduce code size - Add Chrome OS EC support - Add MMC, video, USB configs - Add VBT signature - Add a driver for APL SPI for TPL (using of-platdata) - Add a proper SPI node and make the SPI flash node a child - Add a weak function to avoid errors on other platforms - Add an APL_SPI_FLASH_BOOT option to enable non-mmap boot - Add bootstage support - Add bootstage timing for reading vbt - Add fspm_done() hook to handle FSP-S wierdness (it breaks SPI flash) - Add more documentation - Add snapshot/restore for IRQs - Add spi alias in device tree - Add structures for FSP-S also - Add two more defines for the CPU driver - Add various minor tidy-ups - Adjust fast_spi_cache_bios_region() to avoid using SPI driver - Disable the bootcommand since it does nothing useful on coral - Don't allow BOOT_FROM_FAST_SPI_FLASH with FSP-S - Don't enable SPI flash in TPL by default - Drop CONFIG_SPL_NET_SUPPORT - Drop calls to x86_cpu_init_f(), x86_cpu_reinit_f() - Drop patch '86: timer: Reduce timer code size in TPL on Intel CPUs' - Drop patch 'dm: core: Don't include ofnode functions with of-platdata' - Drop patch 'spi: sandbox: Add a test driver for sandbox SPI flash' - Drop patch 'spl: Allow SPL/TPL to use of-platdata without libfdt' - Drop patch 'x86: apollolake: Add definitions for the Intel Fast SPI interface' - Drop patch 'x86: timer: Set up the timer in timer_early_get_count()' - Drop struct fsp_usp_header as it is now in the API file - Drop unused code in lpc_configure_pads() - Enable video and USB3 - Expand comments for BOOT_FROM_FAST_SPI_FLASH - Fix build error when debug UART is disabled - Fix mixed case in GPIO defines - Fix the incorrect value of CPU_ADDR_BITS - Fix value of LPC_BC_LE - Init the p2sb before the northbridge since the latter so it can use GPIOs - Move location of fast_spi.h header file - Move pad programming into the hostbridge to reduce TPL device-tree size - Reduce amount of early-pad data in TPL - Rework how pads configuration is defined in TPL and SPL - Set boot_loader_tolum_size to 0 - Shorten log_msg_ret() calls since the function name is always printed - Support TPL without CONFIG_TPL_SPI_SUPPORT - Support TPL without CONFIG_TPL_SPI_SUPPORT (reduces code size) - Support bootstage timing - Tidy up the pad settings in the device tree - Use a zero-based tsc timer - Use pci_get_devfn() - Use the IRQ uclass instead of ITSS Changes in v2: - Drop probe() function - Implement set_spi_protect() Simon Glass (17): x86: apl: Add pinctrl driver i2c: designware: Add Apollo Lake support x86: apl: Add systemagent driver x86: apl: Add hostbridge driver x86: apl: Add ITSS driver x86: apl: Add LPC driver x86: apl: Add PCH driver x86: apl: Add PUNIT driver spl: Add methods to find the position/size of next phase x86: apl: Add SPL loaders x86: apl: Add a CPU driver x86: apl: Add SPL/TPL init x86: apl: Add P2SB driver x86: apl: Add Kconfig and Makefile x86: apl: Add FSP structures x86: apl: Add FSP support x86: Add chromebook_coral arch/x86/Kconfig | 1 + arch/x86/cpu/Makefile | 1 + arch/x86/cpu/apollolake/Kconfig | 96 ++ arch/x86/cpu/apollolake/Makefile | 21 + arch/x86/cpu/apollolake/cpu.c | 41 + arch/x86/cpu/apollolake/cpu_common.c | 17 + arch/x86/cpu/apollolake/cpu_spl.c | 271 ++++++ arch/x86/cpu/apollolake/fsp_m.c | 210 +++++ arch/x86/cpu/apollolake/fsp_s.c | 661 ++++++++++++++ arch/x86/cpu/apollolake/hostbridge.c | 179 ++++ arch/x86/cpu/apollolake/itss.c | 214 +++++ arch/x86/cpu/apollolake/lpc.c | 122 +++ arch/x86/cpu/apollolake/p2sb.c | 166 ++++ arch/x86/cpu/apollolake/pch.c | 36 + arch/x86/cpu/apollolake/punit.c | 94 ++ arch/x86/cpu/apollolake/spl.c | 178 ++++ arch/x86/cpu/apollolake/systemagent.c | 23 + arch/x86/dts/Makefile | 1 + arch/x86/dts/chromebook_coral.dts | 831 ++++++++++++++++++ arch/x86/include/asm/arch-apollolake/cpu.h | 20 + .../asm/arch-apollolake/fsp/fsp_configs.h | 14 + .../asm/arch-apollolake/fsp/fsp_m_upd.h | 123 +++ .../asm/arch-apollolake/fsp/fsp_s_upd.h | 292 ++++++ .../include/asm/arch-apollolake/fsp/fsp_vpd.h | 11 + arch/x86/include/asm/arch-apollolake/gpio.h | 485 ++++++++++ arch/x86/include/asm/arch-apollolake/itss.h | 43 + arch/x86/include/asm/arch-apollolake/lpc.h | 82 ++ arch/x86/include/asm/arch-apollolake/pch.h | 9 + .../include/asm/arch-apollolake/systemagent.h | 37 + arch/x86/include/asm/msr-index.h | 1 + board/google/Kconfig | 15 + board/google/chromebook_coral/Kconfig | 43 + board/google/chromebook_coral/MAINTAINERS | 6 + board/google/chromebook_coral/Makefile | 5 + board/google/chromebook_coral/coral.c | 19 + common/spl/spl.c | 20 + configs/chromebook_coral_defconfig | 102 +++ doc/board/google/chromebook_coral.rst | 241 +++++ doc/board/google/index.rst | 1 + drivers/i2c/designware_i2c_pci.c | 25 + drivers/pinctrl/intel/Kconfig | 16 +- drivers/pinctrl/intel/Makefile | 1 + drivers/pinctrl/intel/pinctrl_apl.c | 192 ++++ include/configs/chromebook_coral.h | 32 + include/spl.h | 21 +- 45 files changed, 5015 insertions(+), 4 deletions(-) create mode 100644 arch/x86/cpu/apollolake/Kconfig create mode 100644 arch/x86/cpu/apollolake/cpu.c create mode 100644 arch/x86/cpu/apollolake/cpu_common.c create mode 100644 arch/x86/cpu/apollolake/cpu_spl.c create mode 100644 arch/x86/cpu/apollolake/fsp_m.c create mode 100644 arch/x86/cpu/apollolake/fsp_s.c create mode 100644 arch/x86/cpu/apollolake/hostbridge.c create mode 100644 arch/x86/cpu/apollolake/itss.c create mode 100644 arch/x86/cpu/apollolake/lpc.c create mode 100644 arch/x86/cpu/apollolake/p2sb.c create mode 100644 arch/x86/cpu/apollolake/pch.c create mode 100644 arch/x86/cpu/apollolake/punit.c create mode 100644 arch/x86/cpu/apollolake/spl.c create mode 100644 arch/x86/cpu/apollolake/systemagent.c create mode 100644 arch/x86/dts/chromebook_coral.dts create mode 100644 arch/x86/include/asm/arch-apollolake/cpu.h create mode 100644 arch/x86/include/asm/arch-apollolake/fsp/fsp_configs.h create mode 100644 arch/x86/include/asm/arch-apollolake/fsp/fsp_m_upd.h create mode 100644 arch/x86/include/asm/arch-apollolake/fsp/fsp_s_upd.h create mode 100644 arch/x86/include/asm/arch-apollolake/fsp/fsp_vpd.h create mode 100644 arch/x86/include/asm/arch-apollolake/gpio.h create mode 100644 arch/x86/include/asm/arch-apollolake/itss.h create mode 100644 arch/x86/include/asm/arch-apollolake/lpc.h create mode 100644 arch/x86/include/asm/arch-apollolake/pch.h create mode 100644 arch/x86/include/asm/arch-apollolake/systemagent.h create mode 100644 board/google/chromebook_coral/Kconfig create mode 100644 board/google/chromebook_coral/MAINTAINERS create mode 100644 board/google/chromebook_coral/Makefile create mode 100644 board/google/chromebook_coral/coral.c create mode 100644 configs/chromebook_coral_defconfig create mode 100644 doc/board/google/chromebook_coral.rst create mode 100644 drivers/pinctrl/intel/pinctrl_apl.c create mode 100644 include/configs/chromebook_coral.h -- 2.24.0.393.g34dc348eaf-goog

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[PATCH v8 02/17] i2c: designware: Add Apollo Lake support
by Simon Glass 15 Dec '19

15 Dec '19

For Apollo Lake we need to take the I2C bus controller out of reset before using this. Add this functionality to the driver. Signed-off-by: Simon Glass <sjg(a)chromium.org> Reviewed-by: Heiko Schocher <hs(a)denx.de> Reviewed-by: Bin Meng <bmeng.cn(a)gmail.com> --- Changes in v8: - Add .data in compatible array Changes in v7: None Changes in v6: - Add .driver_data in the designware_pci_supported array - Add a comment about VANILLA - Move lpss_reset_release() to this commit Changes in v5: - Drop unrelated change metioned by Heiko Changes in v4: - apollolake -> Apollo Lake Changes in v3: - Add a weak function to avoid errors on other platforms Changes in v2: None drivers/i2c/designware_i2c_pci.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/drivers/i2c/designware_i2c_pci.c b/drivers/i2c/designware_i2c_pci.c index bb1f809af3..7f0625df66 100644 --- a/drivers/i2c/designware_i2c_pci.c +++ b/drivers/i2c/designware_i2c_pci.c @@ -8,8 +8,14 @@ #include <common.h> #include <dm.h> #include <spl.h> +#include <asm/lpss.h> #include "designware_i2c.h" +enum { + VANILLA = 0, /* standard I2C with no tweaks */ + INTEL_APL, /* Apollo Lake I2C */ +}; + /* BayTrail HCNT/LCNT/SDA hold time */ static struct dw_scl_sda_cfg byt_config = { .ss_hcnt = 0x200, @@ -19,6 +25,9 @@ static struct dw_scl_sda_cfg byt_config = { .sda_hold = 0x6, }; +/* Have a weak function for now - possibly should be a new uclass */ +__weak void lpss_reset_release(void *regs); + static int designware_i2c_pci_ofdata_to_platdata(struct udevice *dev) { struct dw_i2c *priv = dev_get_priv(dev); @@ -59,6 +68,15 @@ static int designware_i2c_pci_ofdata_to_platdata(struct udevice *dev) static int designware_i2c_pci_probe(struct udevice *dev) { + struct dw_i2c *priv = dev_get_priv(dev); + + if (dev_get_driver_data(dev) == INTEL_APL) { + /* Ensure controller is in D0 state */ + lpss_set_power_state(dev, STATE_D0); + + lpss_reset_release(priv->regs); + } + return designware_i2c_probe(dev); } @@ -88,6 +106,7 @@ static int designware_i2c_pci_bind(struct udevice *dev) static const struct udevice_id designware_i2c_pci_ids[] = { { .compatible = "snps,designware-i2c-pci" }, + { .compatible = "intel,apl-i2c", .data = INTEL_APL }, { } }; @@ -113,6 +132,12 @@ static struct pci_device_id designware_pci_supported[] = { { PCI_VDEVICE(INTEL, 0x0f45) }, { PCI_VDEVICE(INTEL, 0x0f46) }, { PCI_VDEVICE(INTEL, 0x0f47) }, + { PCI_VDEVICE(INTEL, 0x5aac), .driver_data = INTEL_APL }, + { PCI_VDEVICE(INTEL, 0x5aae), .driver_data = INTEL_APL }, + { PCI_VDEVICE(INTEL, 0x5ab0), .driver_data = INTEL_APL }, + { PCI_VDEVICE(INTEL, 0x5ab2), .driver_data = INTEL_APL }, + { PCI_VDEVICE(INTEL, 0x5ab4), .driver_data = INTEL_APL }, + { PCI_VDEVICE(INTEL, 0x5ab6), .driver_data = INTEL_APL }, {}, }; -- 2.24.0.525.g8f36a354ae-goog

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