December 2019 - U-Boot

Re: [PATCH] riscv: Add option to print registers on exception
by Rick Chen 19 Dec '19

19 Dec '19

Hi Sean > From: Sean Anderson [mailto:seanga2@gmail.com] > Sent: Wednesday, December 18, 2019 10:32 AM > To: u-boot(a)lists.denx.de > Cc: Rick Jian-Zhi Chen(陳建志) > Subject: [PATCH] riscv: Add option to print registers on exception > > When debugging, it can be helpful to see more information about an unhandled exception. This patch adds an option to view the registers at the time of the trap, similar to the linux output on a kernel panic. > > Signed-off-by: Sean Anderson <seanga2(a)gmail.com> > --- > arch/riscv/Kconfig | 3 +++ > arch/riscv/cpu/mtrap.S | 3 ++- > arch/riscv/lib/interrupts.c | 50 +++++++++++++++++++++++++++++-------- > 3 files changed, 44 insertions(+), 12 deletions(-) > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 85e15ebffa..3338b788f8 100644 > --- a/arch/riscv/Kconfig > +++ b/arch/riscv/Kconfig > @@ -222,6 +222,9 @@ config XIP > from a NOR flash memory without copying the code to ram. > Say yes here if U-Boot boots from flash directly. > > +config SHOW_REGS > + bool "Show registers on unhandled exception" > + > config STACK_SIZE_SHIFT > int > default 14 > diff --git a/arch/riscv/cpu/mtrap.S b/arch/riscv/cpu/mtrap.S index 407ecfa9c0..e40c7bd3f4 100644 > --- a/arch/riscv/cpu/mtrap.S > +++ b/arch/riscv/cpu/mtrap.S > @@ -64,7 +64,8 @@ trap_entry: > SREG x31, 31 * REGBYTES(sp) > csrr a0, MODE_PREFIX(cause) > csrr a1, MODE_PREFIX(epc) > - mv a2, sp > + csrr a2, MODE_PREFIX(tval) > + mv a3, sp > jal handle_trap > csrw MODE_PREFIX(epc), a0 > > diff --git a/arch/riscv/lib/interrupts.c b/arch/riscv/lib/interrupts.c index 3b25c5b7a7..0f1e5123d2 100644 > --- a/arch/riscv/lib/interrupts.c > +++ b/arch/riscv/lib/interrupts.c > @@ -5,6 +5,8 @@ > * > * Copyright (C) 2017 Andes Technology Corporation > * Rick Chen, Andes Technology Corporation <rick(a)andestech.com> > + * > + * Copyright (C) 2019 Sean Anderson <seanga2(a)gmail.com> > */ > > #include <common.h> > @@ -13,7 +15,34 @@ > #include <asm/system.h> > #include <asm/encoding.h> > > -static void _exit_trap(ulong code, ulong epc, struct pt_regs *regs) > +static void show_regs(struct pt_regs *regs) { #ifdef CONFIG_SHOW_REGS > + printf("RA: " REG_FMT " SP: " REG_FMT " GP: " REG_FMT "\n", > + regs->ra, regs->sp, regs->gp); > + printf("TP: " REG_FMT " T0: " REG_FMT " T1: " REG_FMT "\n", > + regs->tp, regs->t0, regs->t1); > + printf("T2: " REG_FMT " S0: " REG_FMT " S1: " REG_FMT "\n", > + regs->t2, regs->s0, regs->s1); > + printf("A0: " REG_FMT " A1: " REG_FMT " A2: " REG_FMT "\n", > + regs->a0, regs->a1, regs->a2); > + printf("A3: " REG_FMT " A4: " REG_FMT " A5: " REG_FMT "\n", > + regs->a3, regs->a4, regs->a5); > + printf("A6: " REG_FMT " A7: " REG_FMT " S2: " REG_FMT "\n", > + regs->a6, regs->a7, regs->s2); > + printf("S3: " REG_FMT " S4: " REG_FMT " S5: " REG_FMT "\n", > + regs->s3, regs->s4, regs->s5); > + printf("S6: " REG_FMT " S7: " REG_FMT " S8: " REG_FMT "\n", > + regs->s6, regs->s7, regs->s8); > + printf("S9: " REG_FMT " S10: " REG_FMT " S11: " REG_FMT "\n", > + regs->s9, regs->s10, regs->s11); > + printf("T3: " REG_FMT " T4: " REG_FMT " T5: " REG_FMT "\n", > + regs->t3, regs->t4, regs->t5); > + printf("T6: " REG_FMT "\n", regs->t6); #endif } > + > +static void _exit_trap(ulong code, ulong epc, ulong tval, struct > +pt_regs *regs) > { > static const char * const exception_code[] = { > "Instruction address misaligned", > @@ -34,14 +63,13 @@ static void _exit_trap(ulong code, ulong epc, struct pt_regs *regs) > "Store/AMO page fault", > }; > > - if (code < ARRAY_SIZE(exception_code)) { > - printf("exception code: %ld , %s , epc %lx , ra %lx\n", > - code, exception_code[code], epc, regs->ra); > - } else { > - printf("reserved exception code: %ld , epc %lx , ra %lx\n", > - code, epc, regs->ra); > - } > + if (code < ARRAY_SIZE(exception_code)) > + printf("Unhandled exception: %s\n", exception_code[code]); > + else > + printf("Unhandled exception code: %ld\n", code); > > + printf("PC: " REG_FMT " TVAL: " REG_FMT "\n", epc, tval); Please modify PC as EPC. LGTM. Other than that, Thanks Rick > + show_regs(regs); > hang(); > } > > @@ -65,7 +93,7 @@ int disable_interrupts(void) > return 0; > } > > -ulong handle_trap(ulong cause, ulong epc, struct pt_regs *regs) > +ulong handle_trap(ulong cause, ulong epc, ulong tval, struct pt_regs > +*regs) > { > ulong is_irq, irq; > > @@ -83,11 +111,11 @@ ulong handle_trap(ulong cause, ulong epc, struct pt_regs *regs) > timer_interrupt(0); /* handle timer interrupt */ > break; > default: > - _exit_trap(cause, epc, regs); > + _exit_trap(cause, epc, tval, regs); > break; > }; > } else { > - _exit_trap(cause, epc, regs); > + _exit_trap(cause, epc, tval, regs); > } > > return epc; > -- > 2.23.0 >

1 0

[PATCH v2 1/4] serial: ns16550: Support run-time configuration
by Simon Glass 19 Dec '19

19 Dec '19

At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg(a)chromium.org> --- Changes in v2: - runtime -> run-time - Enable run-time config for slimbootloader too - Improve Kconfig help based on Bin's comments - Use ns16550 in patch subject drivers/serial/Kconfig | 21 +++++++++++++++ drivers/serial/ns16550.c | 57 ++++++++++++++++++++++++++++++++++------ include/ns16550.h | 13 +++++++++ 3 files changed, 83 insertions(+), 8 deletions(-) diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index ece7d87d4c..472a9f0929 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -598,6 +598,27 @@ config SYS_NS16550 be used. It can be a constant or a function to get clock, eg, get_serial_clock(). +config NS16550_DYNAMIC + bool "Allow NS16550 to be configured at runtime" + default y if SYS_COREBOOT || SYS_SLIMBOOTLOADER + help + Enable this option to allow device-tree control of the driver. + + Normally this driver is controlled by the following options: + + CONFIG_SYS_NS16550_PORT_MAPPED - indicates that port I/O is used for + access. If not enabled, then the UART is memory-mapped. + CONFIG_SYS_NS16550_MEM32 - if memory-mapped, indicates that 32-bit + access should be used (instead of 8-bit) + CONFIG_SYS_NS16550_REG_SIZE - indicates register width and also + endianness. If positive, big-endian access is used. If negative, + little-endian is used. + + It is not a good practice for a driver to be statically configured, + since it prevents the same driver being used for different types of + UARTs in a system. This option avoids this problem at the cost of a + slightly increased code size. + config INTEL_MID_SERIAL bool "Intel MID platform UART support" depends on DM_SERIAL && OF_CONTROL diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index 754b6e9921..96c4471efd 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -92,19 +92,57 @@ static inline int serial_in_shift(void *addr, int shift) #define CONFIG_SYS_NS16550_CLK 0 #endif +static void serial_out_dynamic(struct ns16550_platdata *plat, u8 *addr, + int value) +{ + if (plat->flags & NS16550_FLAG_BE) { + if (plat->reg_width == 1) + writeb(value, addr + (1 << plat->reg_shift) - 1); + else if (plat->flags & NS16550_FLAG_IO) + out_be32(addr, value); + else + writel(value, addr); + } else { + if (plat->reg_width == 1) + writeb(value, addr); + else if (plat->flags & NS16550_FLAG_IO) + out_le32(addr, value); + else + writel(value, addr); + } +} + +static int serial_in_dynamic(struct ns16550_platdata *plat, u8 *addr) +{ + if (plat->flags & NS16550_FLAG_BE) { + if (plat->reg_width == 1) + return readb(addr + (1 << plat->reg_shift) - 1); + else if (plat->flags & NS16550_FLAG_IO) + return in_be32(addr); + else + return readl(addr); + } else { + if (plat->reg_width == 1) + return readb(addr); + else if (plat->flags & NS16550_FLAG_IO) + return in_le32(addr); + else + return readl(addr); + } +} + static void ns16550_writeb(NS16550_t port, int offset, int value) { struct ns16550_platdata *plat = port->plat; unsigned char *addr; offset *= 1 << plat->reg_shift; - addr = (unsigned char *)plat->base + offset; + addr = (unsigned char *)plat->base + offset + plat->reg_offset; - /* - * As far as we know it doesn't make sense to support selection of - * these options at run-time, so use the existing CONFIG options. - */ - serial_out_shift(addr + plat->reg_offset, plat->reg_shift, value); + if (IS_ENABLED(CONFIG_NS16550_DYNAMIC)) + serial_out_dynamic(plat, addr, value); + else + serial_out_shift(addr, plat->reg_shift, value); } static int ns16550_readb(NS16550_t port, int offset) @@ -113,9 +151,12 @@ static int ns16550_readb(NS16550_t port, int offset) unsigned char *addr; offset *= 1 << plat->reg_shift; - addr = (unsigned char *)plat->base + offset; + addr = (unsigned char *)plat->base + offset + plat->reg_offset; - return serial_in_shift(addr + plat->reg_offset, plat->reg_shift); + if (IS_ENABLED(CONFIG_NS16550_DYNAMIC)) + return serial_in_dynamic(plat, addr); + else + return serial_in_shift(addr, plat->reg_shift); } static u32 ns16550_getfcr(NS16550_t port) diff --git a/include/ns16550.h b/include/ns16550.h index 701efeea85..ba9b71962d 100644 --- a/include/ns16550.h +++ b/include/ns16550.h @@ -31,6 +31,9 @@ #define CONFIG_SYS_NS16550_REG_SIZE (-1) #endif +#ifdef CONFIG_NS16550_DYNAMIC +#define UART_REG(x) unsigned char x +#else #if !defined(CONFIG_SYS_NS16550_REG_SIZE) || (CONFIG_SYS_NS16550_REG_SIZE == 0) #error "Please define NS16550 registers size." #elif defined(CONFIG_SYS_NS16550_MEM32) && !defined(CONFIG_DM_SERIAL) @@ -44,6 +47,12 @@ unsigned char x; \ unsigned char postpad_##x[-CONFIG_SYS_NS16550_REG_SIZE - 1]; #endif +#endif /* CONFIG_NS16550_DYNAMIC */ + +enum ns16550_flags { + NS16550_FLAG_IO = 1 << 0, /* Use I/O access (else mem-mapped) */ + NS16550_FLAG_BE = 1 << 1, /* Use big-endian access (else little) */ +}; /** * struct ns16550_platdata - information about a NS16550 port @@ -51,7 +60,10 @@ * @base: Base register address * @reg_width: IO accesses size of registers (in bytes) * @reg_shift: Shift size of registers (0=byte, 1=16bit, 2=32bit...) + * @reg_offset: Offset to start of registers * @clock: UART base clock speed in Hz + * @fcr: Offset of FCR register (normally UART_FCR_DEFVAL) + * @flags: A few flags (enum ns16550_flags) * @bdf: PCI slot/function (pci_dev_t) */ struct ns16550_platdata { @@ -61,6 +73,7 @@ struct ns16550_platdata { int reg_offset; int clock; u32 fcr; + int flags; #if defined(CONFIG_PCI) && defined(CONFIG_SPL) int bdf; #endif -- 2.24.0.393.g34dc348eaf-goog

4 8

[PATCH] drivers: net: fsl_enetc: use write_hwaddr()
by Michael Walle 18 Dec '19

18 Dec '19

Intead of setting the MAC address in enetc_start() use the proper write_hwaddr(). U-Boot takes care of the random MAC address, too. Also, this will correctly handle ethNmacskip etc. Signed-off-by: Michael Walle <michael(a)walle.cc> --- drivers/net/fsl_enetc.c | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/drivers/net/fsl_enetc.c b/drivers/net/fsl_enetc.c index e86f3dddb5..1949530460 100644 --- a/drivers/net/fsl_enetc.c +++ b/drivers/net/fsl_enetc.c @@ -272,14 +272,19 @@ static int enetc_remove(struct udevice *dev) return 0; } -/* ENETC Port MAC address registers, accepts big-endian format */ -static void enetc_set_primary_mac_addr(struct enetc_priv *priv, const u8 *addr) +static int enetc_write_hwaddr(struct udevice *dev) { + struct eth_pdata *plat = dev_get_platdata(dev); + struct enetc_priv *priv = dev_get_priv(dev); + u8 *addr = plat->enetaddr; + u16 lower = *(const u16 *)(addr + 4); u32 upper = *(const u32 *)addr; enetc_write_port(priv, ENETC_PSIPMAR0, upper); enetc_write_port(priv, ENETC_PSIPMAR1, lower); + + return 0; } /* Configure port parameters (# of rings, frame size, enable port) */ @@ -410,7 +415,6 @@ static void enetc_setup_rx_bdr(struct udevice *dev) */ static int enetc_start(struct udevice *dev) { - struct eth_pdata *plat = dev_get_platdata(dev); struct enetc_priv *priv = dev_get_priv(dev); /* reset and enable the PCI device */ @@ -418,12 +422,6 @@ static int enetc_start(struct udevice *dev) dm_pci_clrset_config16(dev, PCI_COMMAND, 0, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); - if (!is_valid_ethaddr(plat->enetaddr)) { - enetc_dbg(dev, "invalid MAC address, generate random ...\n"); - net_random_ethaddr(plat->enetaddr); - } - enetc_set_primary_mac_addr(priv, plat->enetaddr); - enetc_enable_si_port(priv); /* setup Tx/Rx buffer descriptors */ @@ -549,6 +547,7 @@ static const struct eth_ops enetc_ops = { .send = enetc_send, .recv = enetc_recv, .stop = enetc_stop, + .write_hwaddr = enetc_write_hwaddr, }; U_BOOT_DRIVER(eth_enetc) = { -- 2.20.1

2 2

riscv: Sipeed Maix support
by Sean Anderson 18 Dec '19

18 Dec '19

I've been working on adding support for the Sipeed Maix-series boards, specifically the Bit <https://wiki.sipeed.com/en/maix/board/bit.html>. The majority of the work has been going toward the Kendryte K210 CPU, and should be generalizable to all of the Maix boards. I've gotten u-boot to reach the relocation stage (at which point if fails silently). However, before continuing, I'd like to get some feedback on what I've already written. My current code is located at <https://github.com/Forty-Bot/u-boot/tree/maix_v1>. How is the function fdtdec_setup_memory_banksize_fdt supposed to work? I've tried different combinations of having a single /memory node, having multiple /memory@X nodes, and having /memory/memory@foo nodes, but it never seems to detect anything other than a start and size of 0x0. I've added the device_type = "memory" property, but it doesn't seem to detect anything. The k210 has two banks of sram adjacent in address space, each with their own clock. Should these count toward NR_DRAM_BANKS? Should they be separate top-level memory nodes in the device tree, or part of a single memory node using ranges to keep the parent address space? What configuration should be located in board/*/*/Kconfig and what should be located in include/configs? It seems like generally only SYS_ configs are in include/configs, but some like SYS_BOARD or SYS_VENDOR are located in the board Kconfig. What should the max frequency be for the MicroSD card slot (located in arch/riscv/dts/k210-maix.dts)? Most other devicetrees I've seen have some kind of sdhci controller, but this slot is wired directly to one of the spi controllers. What does /cpus/timebase-frequency represent? How does it differ from /cpus/cpu@X/cpu-frequency? The instruction and data cache line sizes are not specified in the data sheet. Is it better to over- or underestimate them until they can be determined? I'm not sure which drivers (if any) correspond to the gpio, timer, watchdog, and rtc devices. There are also missing drivers for the kpu, fft, sha256, aes, dvp, and sysctl devices, but those seem like non-standard IP blocks at first glance. There are some good descriptions of the registers at <https://github.com/laanwj/k210-sdk-stuff/blob/master/doc/memory_map.md>, which are themselves derived from <https://github.com/kendryte/kendryte-standalone-sdk/>. Is the way the sysctl device (located on line 326 of arch/riscv/dts/k210.dtsi) described reasonable? The primary function of this device is to control clocks and resets, but there are also several other functions thrown in. For example, there are dma- and power-related registers located in that address range as well. Presumably a future k220 could add more (unrelated) functionality to this region. Which devices should have status = "disabled" in arch/riscv/dts/k210.dtsi? From looking at other dtsi files, it seems like only "core devices" should be left enabled, but I'm not sure how to make that decision for this cpu. How does the gpio/pin-controller model work? Should the device tree describe the default configuration, even if it can be changed at runtime? There is a region of memory used by the kpu (neural network accelerator) as scratch memory. When the kpu is disabled, this region may be treated like any other region of memory. I've left this region out of the device tree, but since the kpu is unlikely to be needed when u-boot is running, should this region of memory be added? Perhaps it should be documented as reserved-memory and referenced by the kpu device? There is a region of memory at 0x40000000 which is a non-cached version of memory at 0x80000000. How should this be described? I believe using this lower region of memory is necessary for interfacing with the DMA controller. This cpu uses both the Andes PLIC and SiFive Clint devices. Currently they both provide riscv_*_ipi functions, despite their other functionalities as interrupt controllers and counter controllers, respectively. Commit b380dbb adds a simple ifdef to disable the ipi functions of the Andes plic, as IPIs are handled by the clint on the k210. However, presumably this situation is not unique, and there could be other processors which include both devices. I think there should be some kind of kconfig for this, but I'm not sure how it should be worded. Part of this problem could be fixed by making both devices proper interrupt-controllers. The mcounteren CSR raises an exception when written to in arch/riscv/cpu/cpu.c (c.f. commit b768942). The datasheet claims the k210 "Support for different privilege levels to improve safety," so perhaps the k210 only has M and U privilege levels. The exact bits which cause a problem will need further investigation. The magic bytes for the device tree get zeroed-out by something prior to being parsed by u-boot. Trying to write to the magic byte location causes the device to become unresponsive. The tree is otherwise intact. The current fix is to just disable the check at runtime (commit 7dee06b), but this is obviously not ideal. I'd appreciate any suggestions for debugging this. --Sean

1 0

[PATCH] net: dwc_eth_qos: Pass -1 to phy_connect() to scan for all PHYs
by Marek Vasut 18 Dec '19

18 Dec '19

PHY address 0 is a valid PHY address, to scan for all PHYs, pass -1 to phy_connect(). Passing 0 used to work before be accident, but does no longer. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Joe Hershberger <joe.hershberger(a)ni.com> Cc: Patrice Chotard <patrice.chotard(a)st.com> Cc: Patrick Delaunay <patrick.delaunay(a)st.com> Cc: Ramon Fried <rfried.dev(a)gmail.com> --- drivers/net/dwc_eth_qos.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c index da5b696c9d..4632111635 100644 --- a/drivers/net/dwc_eth_qos.c +++ b/drivers/net/dwc_eth_qos.c @@ -1045,7 +1045,7 @@ static int eqos_start(struct udevice *dev) * don't need to reconnect/reconfigure again */ if (!eqos->phy) { - eqos->phy = phy_connect(eqos->mii, 0, dev, + eqos->phy = phy_connect(eqos->mii, -1, dev, eqos->config->interface(dev)); if (!eqos->phy) { pr_err("phy_connect() failed"); -- 2.24.1

5 4

[PATCH] ARM: stm32: Permit multiple board targets
by Marek Vasut 18 Dec '19

18 Dec '19

Setting TARGET_STM32MP1 in Kconfig always forces SYS_BOARD, SYS_VENDOR and SYS_CONFIG_NAME to values set by the ST reference platforms. Allow changing that by pulling out the TARGET_STM32MP157C_DK2 and making the ST reference platform settings conditional on TARGET_STM32MP157C_DK2 . Other platforms can now define a different TARGET_ and thus override the SYS_ settings in their Kconfig. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Patrick Delaunay <patrick.delaunay(a)st.com> Cc: Patrice Chotard <patrice.chotard(a)st.com> --- board/st/stm32mp1/Kconfig | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/board/st/stm32mp1/Kconfig b/board/st/stm32mp1/Kconfig index 4fa2360b4f..c84aa41f06 100644 --- a/board/st/stm32mp1/Kconfig +++ b/board/st/stm32mp1/Kconfig @@ -1,4 +1,8 @@ -if TARGET_STM32MP1 +config TARGET_STM32MP157C_DK2 + bool "support of STMicroelectronics STM32MP157C-DK2 Discovery Board" + default y + +if TARGET_STM32MP157C_DK2 config SYS_BOARD default "stm32mp1" @@ -22,8 +26,4 @@ config CMD_STBOARD This compile the stboard command to read and write the board in the OTP. -config TARGET_STM32MP157C_DK2 - bool "support of STMicroelectronics STM32MP157C-DK2 Discovery Board" - default y - endif -- 2.24.1

2 5

[PATCH v3 0/5] Add support for booting EFI FIT images
by Cristian Ciocaltea 18 Dec '19

18 Dec '19

Currently the only way to run an EFI binary like GRUB2 is via the 'bootefi' command, which cannot be used in a verified boot scenario. The obvious solution to this limitation is to add support for booting FIT images containing those EFI binaries. The implementation relies on a new image type - IH_OS_EFI - which can be created by using 'os = "efi"' inside an ITS file: / { #address-cells = <1>; images { efi-grub { description = "GRUB EFI"; data = /incbin/("bootarm.efi"); type = "kernel_noload"; arch = "arm"; os = "efi"; compression = "none"; load = <0x0>; entry = <0x0>; hash-1 { algo = "sha256"; }; }; }; configurations { default = "config-grub"; config-grub { kernel = "efi-grub"; signature-1 { algo = "sha256,rsa2048"; sign-images = "kernel"; }; }; }; }; The bootm command has been extended to handle the IH_OS_EFI images. To enable this feature, a new configuration option has been added: BOOTM_EFI I tested the solution using the 'qemu_arm' board: => load scsi 0:1 ${kernel_addr_r} efi-image.fit => bootm ${kernel_addr_r}#config-grub Changes in v3: * Rebase patches on Heinrich Schuchardt's patch series v3: efi_loader: prepare for FIT images https://lists.denx.de/pipermail/u-boot/2019-December/393677.html This fixes implicitly the sandbox issue 'phys_to_virt: Cannot map sandbox address' since efi_install_fdt() is now expecting a pointer to addressable memory instead of a physical address. * Get rid of 'EFI/BOOT/' prefix used in ITS samples * Add a python test to verify the implementation in sandbox environment Changes in v2: * Rebase patches on Heinrich Schuchardt's patch series: efi_loader: prepare for FIT images https://lists.denx.de/pipermail/u-boot/2019-December/393192.html * Add sample configuration: doc/uImage.FIT/uefi.its * Update uefi documentation: doc/uefi/uefi.rst Cristian Ciocaltea (5): image: Add IH_OS_EFI for EFI chain-load boot bootm: Add a bootm command for type IH_OS_EFI doc: Add sample uefi.its image description file doc: uefi.rst: Document launching UEFI binaries from FIT images test/py: Create a test for launching UEFI binaries from FIT images cmd/Kconfig | 7 + common/bootm_os.c | 56 ++++++++ common/image-fit.c | 3 +- common/image.c | 1 + doc/uImage.FIT/uefi.its | 67 ++++++++++ doc/uefi/uefi.rst | 34 +++++ include/image.h | 1 + test/py/tests/test_efi_fit.py | 233 ++++++++++++++++++++++++++++++++++ 8 files changed, 401 insertions(+), 1 deletion(-) create mode 100644 doc/uImage.FIT/uefi.its create mode 100644 test/py/tests/test_efi_fit.py -- 2.17.1

2 14

[PATCH 1/1] sunxi: remove __packed from struct sunxi_prcm_reg
by Heinrich Schuchardt 18 Dec '19

18 Dec '19

struct sunxi_prcm_reg is naturally packed. There is no need to define it as packed. Defining it as packed leads to compilation errors with GCC 9.2.1: CC arch/arm/lib/reloc_arm_efi.o arch/arm/cpu/armv7/sunxi/psci.c: In function ‘sunxi_cpu_set_power’: :qarch/arm/cpu/armv7/sunxi/psci.c:163:21: error: taking address of packed member of ‘struct sunxi_prcm_reg’ may result in an unaligned pointer value [-Werror=address-of-packed-member] 163 | sunxi_power_switch(&prcm->cpu_pwr_clamp[cpu], &prcm->cpu_pwroff, | ^~~~~~~~~~~~~~~~~~~~~~~~~ Remove __packed attribute from struct sunxi_prcm_reg. Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- arch/arm/include/asm/arch-sunxi/prcm.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/include/asm/arch-sunxi/prcm.h b/arch/arm/include/asm/arch-sunxi/prcm.h index 58a36895e6..767d1ff98d 100644 --- a/arch/arm/include/asm/arch-sunxi/prcm.h +++ b/arch/arm/include/asm/arch-sunxi/prcm.h @@ -202,7 +202,7 @@ #ifndef __ASSEMBLY__ #include <linux/compiler.h> -struct __packed sunxi_prcm_reg { +struct sunxi_prcm_reg { u32 cpus_cfg; /* 0x000 */ u8 res0[0x8]; /* 0x004 */ u32 apb0_ratio; /* 0x00c */ -- 2.24.0

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[PATCH] ARM: stm32: Fill in missing loadaddr
by Marek Vasut 18 Dec '19

18 Dec '19

Since CONFIG_LOADADDR is not set, the default value of $loadaddr variable is not set in the environment either. Set the default load address to 256 MiB from the start of DRAM. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Patrick Delaunay <patrick.delaunay(a)st.com> Cc: Patrice Chotard <patrice.chotard(a)st.com> --- include/configs/stm32mp1.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/stm32mp1.h b/include/configs/stm32mp1.h index dfc397c63c..59a86aee79 100644 --- a/include/configs/stm32mp1.h +++ b/include/configs/stm32mp1.h @@ -36,6 +36,7 @@ * Needed by "loadb" */ #define CONFIG_SYS_LOAD_ADDR STM32_DDR_BASE +#define CONFIG_LOADADDR 0xd0000000 /* ATAGs */ #define CONFIG_CMDLINE_TAG -- 2.24.1

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[PULL] Pull request: u-boot-stm32 u-boot-stm32-20191218
by Patrick DELAUNAY 18 Dec '19

18 Dec '19

Hi Tom Please pull the last STM32 related patches for v2020.01 Travis CI status: https://travis-ci.org/patrickdelaunay/u-boot/builds/626655770 With the following fixes: - fix crash for stm32mp1: remove the BOOTSTAGE feature - fix warning for stm32mp1: add the missing cls command And I also resync the stm32mp1 defconfig. Thanks, Patrick git request-pull origin/master https://gitlab.denx.de/u-boot/custodians/u-boot-stm.git u-boot-stm32-20191218 warn: No match for commit eddd79291d2026f8fefebc3f5d39928d7c649241 found at https://gitlab.denx.de/u-boot/custodians/u-boot-stm.git warn: Are you sure you pushed 'u-boot-stm32-20191218' there? The following changes since commit ef7c2af65966a57c98d3c47e6c2fe1ce2103b7f6: Prepare v2020.01-rc5 (2019-12-16 07:39:56 -0500) are available in the Git repository at: https://gitlab.denx.de/u-boot/custodians/u-boot-stm.git u-boot-stm32-20191218 for you to fetch changes up to eddd79291d2026f8fefebc3f5d39928d7c649241: stm32mp1: configs: Resync with savedefconfig (2019-12-18 11:58:36 +0100) ---------------------------------------------------------------- - Fix stm32mp1 crash (bootstage) and warning (cls) ---------------------------------------------------------------- Patrick Delaunay (3): stm32mp1: imply CMD_CLS stm32mp1: remove the imply BOOTSTAGE stm32mp1: configs: Resync with savedefconfig arch/arm/mach-stm32mp/Kconfig | 3 +-- configs/stm32mp15_basic_defconfig | 2 +- configs/stm32mp15_optee_defconfig | 2 +- configs/stm32mp15_trusted_defconfig | 2 +- 4 files changed, 4 insertions(+), 5 deletions(-)

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