December 2019 - U-Boot

[PATCH v1] mach-imx: nandbcb: improve cmd help
by Igor Opaniuk 04 Jan '20

04 Jan '20

From: Igor Opaniuk <igor.opaniuk(a)toradex.com> Add info about supported i.MX7, improve details the usage of bcbonly subcommand. Signed-off-by: Igor Opaniuk <igor.opaniuk(a)toradex.com> --- arch/arm/mach-imx/cmd_nandbcb.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-imx/cmd_nandbcb.c b/arch/arm/mach-imx/cmd_nandbcb.c index 9d3ed1aac3..334cc0766e 100644 --- a/arch/arm/mach-imx/cmd_nandbcb.c +++ b/arch/arm/mach-imx/cmd_nandbcb.c @@ -590,11 +590,14 @@ static char nandbcb_help_text[] = "update addr off|partition len - update 'len' bytes starting at\n" " 'off|part' to memory address 'addr', skipping bad blocks\n" "bcbonly fw-size fw1-off [fw2-off] - write only BCB (FCB and DBBT)\n" - " where `fw-size` is fw sizes in bytes, `fw1-off` and\n" - " and `fw2-off` - firmware offsets "; + " where `fw-size` is fw sizes in bytes, `fw1-off`\n" + " and `fw2-off` - firmware offsets\n" + " FIY, BCB isn't erased automatically, so mtd erase should\n" + " be called in advance before writing new BCB:\n" + " > mtd erase mx7-bcb"; #endif U_BOOT_CMD(nandbcb, 5, 1, do_nandbcb, - "i.MX6 Nand BCB", + "i.MX6/i.MX7 NAND Boot Control Blocks write", nandbcb_help_text ); -- 2.17.1

3 2

[PATCH] arm: imx: Default to SYS_THUMB_BUILD for i.MX6/7
by Tom Rini 04 Jan '20

04 Jan '20

In the case of i.MX6 and i.MX7 family SoCs it is safe (from an errata point of view) to use thumb2 by default to save space. Cc: Stefano Babic <sbabic(a)denx.de> Cc: Fabio Estevam <festevam(a)gmail.com> Signed-off-by: Tom Rini <trini(a)konsulko.com> --- arch/arm/Kconfig | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f9dab073ea14..31c07d9b0b4a 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -823,6 +823,7 @@ config ARCH_MX7ULP select CPU_V7A select ROM_UNIFIED_SECTIONS imply MXC_GPIO + imply SYS_THUMB_BUILD config ARCH_MX7 bool "Freescale MX7" @@ -833,6 +834,7 @@ config ARCH_MX7 select SYS_FSL_SEC_COMPAT_4 select SYS_FSL_SEC_LE imply MXC_GPIO + imply SYS_THUMB_BUILD config ARCH_MX6 bool "Freescale MX6" @@ -840,8 +842,8 @@ config ARCH_MX6 select SYS_FSL_HAS_SEC if IMX_HAB select SYS_FSL_SEC_COMPAT_4 select SYS_FSL_SEC_LE - select SYS_THUMB_BUILD if SPL imply MXC_GPIO + imply SYS_THUMB_BUILD if ARCH_MX6 config SPL_LDSCRIPT -- 2.17.1

3 3

[PATCH] imx8mm_evk: Adjust the environment for booting a mainline kernel
by Fabio Estevam 04 Jan '20

04 Jan '20

Adjust the environment for booting a mainline kernel by default. Signed-off-by: Fabio Estevam <festevam(a)gmail.com> --- configs/imx8mm_evk_defconfig | 1 - include/configs/imx8mm_evk.h | 8 ++++---- 2 files changed, 4 insertions(+), 5 deletions(-) diff --git a/configs/imx8mm_evk_defconfig b/configs/imx8mm_evk_defconfig index 87560ef989..e007766e84 100644 --- a/configs/imx8mm_evk_defconfig +++ b/configs/imx8mm_evk_defconfig @@ -21,7 +21,6 @@ CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" CONFIG_OF_SYSTEM_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg" -CONFIG_DEFAULT_FDT_FILE="fsl-imx8mm-evk.dtb" CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SEPARATE_BSS=y diff --git a/include/configs/imx8mm_evk.h b/include/configs/imx8mm_evk.h index acbab05ae9..b134351c8c 100644 --- a/include/configs/imx8mm_evk.h +++ b/include/configs/imx8mm_evk.h @@ -38,12 +38,12 @@ /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ - "image=Image.itb\0" \ + "image=Image\0" \ "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200\0" \ "fdt_addr=0x43000000\0" \ "fdt_high=0xffffffffffffffff\0" \ - "boot_fit=try\0" \ - "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "boot_fit=no\0" \ + "fdt_file=imx8mm-evk.dtb\0" \ "initrd_addr=0x43800000\0" \ "initrd_high=0xffffffffffffffff\0" \ "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ @@ -113,7 +113,7 @@ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) #define CONFIG_ENV_OVERWRITE -#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC2 */ +#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ /* Size of malloc() pool */ -- 2.17.1

3 2

[PATCH v3] mach-imx: bootaux: elf firmware support
by Igor Opaniuk 04 Jan '20

04 Jan '20

From: Igor Opaniuk <igor.opaniuk(a)toradex.com> Currently imx-specific bootaux command doesn't support ELF format firmware for Cortex-M4 core. This patches introduces a PoC implementation of handling elf firmware (load_elf_image_phdr() was copy-pasted from elf.c just for PoC). ELF64 binaries isn't supported yet. This has the advantage that the user does not need to know to which address the binary has been linked to. However, in order to handle and load the elf sections to the right address, we need to translate the Cortex-M4 core memory addresses to primary/host CPU memory addresses (Cortex A7/A9 cores). This allows to boot firmwares from any location with just using bootaux, e.g.: > tftp ${loadaddr} hello_world.elf && bootaux ${loadaddr} Similar translation table can be found in the Linux remoteproc driver [1]. [1] https://elixir.bootlin.com/linux/latest/source/drivers/remoteproc/imx_rproc… Signed-off-by: Igor Opaniuk <igor.opaniuk(a)toradex.com> Signed-off-by: Stefan Agner <stefan.agner(a)toradex.com> Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov(a)toradex.com> --- arch/arm/include/asm/mach-imx/sys_proto.h | 7 ++ arch/arm/mach-imx/imx_bootaux.c | 96 +++++++++++++++++++++-- arch/arm/mach-imx/mx7/soc.c | 28 +++++++ 3 files changed, 126 insertions(+), 5 deletions(-) diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h index c9b509e6a7..fff4800808 100644 --- a/arch/arm/include/asm/mach-imx/sys_proto.h +++ b/arch/arm/include/asm/mach-imx/sys_proto.h @@ -106,6 +106,13 @@ void gpr_init(void); #endif /* CONFIG_MX6 */ +/* address translation table */ +struct rproc_att { + u32 da; /* device address (From Cortex M4 view) */ + u32 sa; /* system bus address */ + u32 size; /* size of reg range */ +}; + #ifdef CONFIG_IMX8M struct rom_api { u16 ver; diff --git a/arch/arm/mach-imx/imx_bootaux.c b/arch/arm/mach-imx/imx_bootaux.c index 7c8195e715..21e96f8c88 100644 --- a/arch/arm/mach-imx/imx_bootaux.c +++ b/arch/arm/mach-imx/imx_bootaux.c @@ -7,20 +7,106 @@ #include <asm/io.h> #include <asm/mach-imx/sys_proto.h> #include <command.h> +#include <elf.h> #include <imx_sip.h> #include <linux/compiler.h> #include <cpu_func.h> -int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data) +#ifndef CONFIG_IMX8M +const __weak struct rproc_att hostmap[] = { }; + +static const struct rproc_att *get_host_mapping(unsigned long auxcore) +{ + const struct rproc_att *mmap = hostmap; + + while (mmap && mmap->size) { + if (mmap->da <= auxcore && + mmap->da + mmap->size > auxcore) + return mmap; + mmap++; + } + + return NULL; +} + +/* + * A very simple elf loader, assumes the image is valid, returns the + * entry point address. + */ +static unsigned long load_elf_image_phdr(unsigned long addr) +{ + Elf32_Ehdr *ehdr; /* ELF header structure pointer */ + Elf32_Phdr *phdr; /* Program header structure pointer */ + int i; + + ehdr = (Elf32_Ehdr *)addr; + phdr = (Elf32_Phdr *)(addr + ehdr->e_phoff); + + /* Load each program header */ + for (i = 0; i < ehdr->e_phnum; ++i, ++phdr) { + const struct rproc_att *mmap = get_host_mapping(phdr->p_paddr); + void *dst, *src; + + if (phdr->p_type != PT_LOAD) + continue; + + if (!mmap) { + printf("Invalid aux core address: %08x", + phdr->p_paddr); + return 0; + } + + dst = (void *)(phdr->p_paddr - mmap->da) + mmap->sa; + src = (void *)addr + phdr->p_offset; + + debug("Loading phdr %i to 0x%p (%i bytes)\n", + i, dst, phdr->p_filesz); + + if (phdr->p_filesz) + memcpy(dst, src, phdr->p_filesz); + if (phdr->p_filesz != phdr->p_memsz) + memset(dst + phdr->p_filesz, 0x00, + phdr->p_memsz - phdr->p_filesz); + flush_cache((unsigned long)dst & + ~(CONFIG_SYS_CACHELINE_SIZE - 1), + ALIGN(phdr->p_filesz, CONFIG_SYS_CACHELINE_SIZE)); + } + + return ehdr->e_entry; +} +#endif + +int arch_auxiliary_core_up(u32 core_id, ulong addr) { ulong stack, pc; - if (!boot_private_data) + if (!addr) return -EINVAL; - stack = *(u32 *)boot_private_data; - pc = *(u32 *)(boot_private_data + 4); - +#ifdef CONFIG_IMX8M + stack = *(u32 *)addr; + pc = *(u32 *)(addr + 4); +#else + /* + * handling ELF64 binaries + * isn't supported yet. + */ + if (valid_elf_image(addr)) { + stack = 0x0; + pc = load_elf_image_phdr(addr); + if (!pc) + return CMD_RET_FAILURE; + + } else { + /* + * Assume binary file with vector table at the beginning. + * Cortex-M4 vector tables start with the stack pointer (SP) + * and reset vector (initial PC). + */ + stack = *(u32 *)addr; + pc = *(u32 *)(addr + 4); + } +#endif printf("## Starting auxiliary core stack = 0x%08lX, pc = 0x%08lX...\n", stack, pc); diff --git a/arch/arm/mach-imx/mx7/soc.c b/arch/arm/mach-imx/mx7/soc.c index 35160f4b37..4aafeed188 100644 --- a/arch/arm/mach-imx/mx7/soc.c +++ b/arch/arm/mach-imx/mx7/soc.c @@ -193,6 +193,34 @@ static void init_cpu_basic(void) #endif } +#ifdef CONFIG_IMX_BOOTAUX +/* + * Table of mappings of physical mem regions in both + * Cortex-A7 and Cortex-M4 address spaces. + * + * For additional details check sections 2.1.2 and 2.1.3 in + * i.MX7Dual Applications Processor Reference Manual + * + */ +const struct rproc_att hostmap[] = { + /* aux core , host core, size */ + { 0x00000000, 0x00180000, 0x8000 }, /* OCRAM_S */ + { 0x00180000, 0x00180000, 0x8000 }, /* OCRAM_S */ + { 0x20180000, 0x00180000, 0x8000 }, /* OCRAM_S */ + { 0x1fff8000, 0x007f8000, 0x8000 }, /* TCML */ + { 0x20000000, 0x00800000, 0x8000 }, /* TCMU */ + { 0x00900000, 0x00900000, 0x20000 }, /* OCRAM_128KB */ + { 0x20200000, 0x00900000, 0x20000 }, /* OCRAM_128KB */ + { 0x00920000, 0x00920000, 0x20000 }, /* OCRAM_EPDC */ + { 0x20220000, 0x00920000, 0x20000 }, /* OCRAM_EPDC */ + { 0x00940000, 0x00940000, 0x20000 }, /* OCRAM_PXP */ + { 0x20240000, 0x00940000, 0x20000 }, /* OCRAM_PXP */ + { 0x10000000, 0x80000000, 0x0fff0000 }, /* DDR Code alias */ + { 0x80000000, 0x80000000, 0xe0000000 }, /* DDRC */ + { /* sentinel */ } +}; +#endif + #ifndef CONFIG_SKIP_LOWLEVEL_INIT /* enable all periherial can be accessed in nosec mode */ static void init_csu(void) -- 2.17.1

2 1

[PATCH] video: add wrappers for ttf type files to .gitignore
by Dario Binacchi 04 Jan '20

04 Jan '20

The scripts/Makefile.lib generates an assembler file (*.S) to wrap the font data for each file of type ttf defined in Kconfig. Signed-off-by: Dario Binacchi <dariobin(a)libero.it> --- drivers/video/fonts/.gitignore | 1 + 1 file changed, 1 insertion(+) create mode 100644 drivers/video/fonts/.gitignore diff --git a/drivers/video/fonts/.gitignore b/drivers/video/fonts/.gitignore new file mode 100644 index 0000000000..86ec950f64 --- /dev/null +++ b/drivers/video/fonts/.gitignore @@ -0,0 +1 @@ +*.S -- 2.24.0

2 1

[PATCH 0/5] video: Avoid #ifdef to increase build coverage
by Simon Glass 04 Jan '20

04 Jan '20

A recent change to the video subsystem added more #ifdefs to the code but these are not necessary. In fact we can often rely on the compiler to drop dead code. Using the IS_ENABLED() macros with if() can produce the same result while reducing the number of build combinations in the code. This series removes most #ifdefs from the core video code. Code size for wandaboard (for example) does not change. It also includes a patch to enable 32bpp video on x86, since video is currently broken. Simon Glass (5): video: x86: Enable 32-bit graphics by default video: Avoid using #ifdef in video blitting code video: Avoid using #ifdef in console_rotate.c video: Avoid using #ifdef in vidconsole-uclass.c video: Avoid using #ifdef in video-uclass.c drivers/video/Kconfig | 5 +- drivers/video/console_normal.c | 125 ++++++------ drivers/video/console_rotate.c | 325 +++++++++++++++--------------- drivers/video/vidconsole-uclass.c | 22 +- drivers/video/video-uclass.c | 54 +++-- 5 files changed, 256 insertions(+), 275 deletions(-) -- 2.24.1.735.g03f4e72817-goog

2 6

[PATCH v5 0/7] rockchip: Add Binman support
by Jagan Teki 03 Jan '20

03 Jan '20

This is v5 set for Binman support in rockchip, [1] here is previous patchset. This series add single boot image with binman for arm32 and pad_cat for arm64 rockchip platforms both TPL + SPL and SPL-alone targets. Changes for v5: - collect kever review tag - drop idbloader.img from clean target Changes for v4: - support all rockchip platforms - add new patches for dtsi changes - update documentation - format proper commit message - rebase on master Changes for v3: - rebase on master - add binman for rk3288, rk3328, rk3368, rk3399 - added rst documentation for rockchip Changes for v2: - Add few clean target patches - update bl31.elf env handling code, with logging - support puma itb, via BL31 and PMUM0 env - enable BUILD_TARGET for ROCKCHIP_RK3399 [1] https://patchwork.ozlabs.org/cover/1182449/ Any inputs? Jagan. Jagan Teki (7): Makefile: Add rockchip image type Makefile: rockchip: Suffix platform type with tpl name Makefile: rockchip: Support SPL-alone mkimage Makefile: rockchip: Use u-boot preferred spl name arm: dts: rk3036: Add rk3036-u-boot.dtsi rockchip: Add Single boot image (with binman, pad_cat) doc: boards: Add rockchip documentation Makefile | 39 +++++++-- arch/arm/Kconfig | 1 + arch/arm/dts/rk3036-sdk-u-boot.dtsi | 2 + arch/arm/dts/rk3036-u-boot.dtsi | 6 ++ arch/arm/dts/rk3288-u-boot.dtsi | 2 + arch/arm/dts/rockchip-u-boot.dtsi | 21 +++++ doc/board/rockchip/index.rst | 10 +++ doc/board/rockchip/rockchip.rst | 128 ++++++++++++++++++++++++++++ include/configs/rockchip-common.h | 2 + 9 files changed, 204 insertions(+), 7 deletions(-) create mode 100644 arch/arm/dts/rk3036-u-boot.dtsi create mode 100644 arch/arm/dts/rockchip-u-boot.dtsi create mode 100644 doc/board/rockchip/index.rst create mode 100644 doc/board/rockchip/rockchip.rst -- 2.18.0.321.gffc6fa0e3

2 13

[U-Boot] [PATCH 0/4] omapl138_lcdk: fix MMC boot
by Bartosz Golaszewski 03 Jan '20

03 Jan '20

From: Bartosz Golaszewski <bgolaszewski(a)baylibre.com> Booting from MMC on omapl138-lcdk is currently broken after we enabled driver-model in SPL. While I know what's wrong - the bind() callback not being called - I can't for the life of me figure out how to fix it. I'm still working on proper changes, but for now, I'd like to propose this series which fixes MMC boot with a workaround in which we call mmc_boot() manually from probe. First two patches drop some legacy code that's no longer needed. The third patch adds a U_BOOT_DEVICE() for mmc as we don't yet have full DT support (also in-progress). The last patch adds the workaround to the davinci mmc driver. This series depends on Adam Ford's patch increasing the pre-reloc malloc pool. [1] https://patchwork.ozlabs.org/patch/1192574/ Bartosz Golaszewski (4): mmc: davinci: drop support for ti,dm6441-mmc mmc: davinci: drop struct davinci_mmc_plat board: omapl138_lcdk: add the mmc device to SPL mmc: davinci: fix mmc boot in SPL arch/arm/mach-davinci/Kconfig | 1 + .../mach-davinci/include/mach/sdmmc_defs.h | 6 -- board/davinci/da8xxevm/omapl138_lcdk.c | 10 ++- drivers/mmc/davinci_mmc.c | 73 +++++++------------ 4 files changed, 36 insertions(+), 54 deletions(-) -- 2.23.0

3 14

[PATCH 0/8] i.MX6: Engicam fixes/updates
by Jagan Teki 03 Jan '20

03 Jan '20

Series of patches that fixes dt and board changes in i.MX6 based Engicam board. Any inputs? Jagan. Jagan Teki (3): dt-bindings: sound: Add fsl-imx-audmux.h from v5.4 ARM: dts: icorem6: Sync engicam device trees from v5.4 ARM: dts: imx6q-icore-mipi: Use 1.5 version of i.Core MX6DL Michael Trimarchi (5): board: engicam: Cleanup fdt file and board mapping board: engicam: Fix the ethernet clock initialization configs: imx6-engicam: Drop fec phy address and mode ARM: dts: imx6qdl-icore-1.5: Remove duplicate phy reset methods ARM: dts: imx6qdli-icore: Add fec phy-handle arch/arm/dts/imx6dl-icore-mipi.dts | 13 +- arch/arm/dts/imx6dl-icore-rqs.dts | 43 +-- arch/arm/dts/imx6dl-icore.dts | 47 +-- arch/arm/dts/imx6q-icore-mipi.dts | 19 +- arch/arm/dts/imx6q-icore-ofcap10.dts | 40 +++ arch/arm/dts/imx6q-icore-ofcap12.dts | 43 +++ arch/arm/dts/imx6q-icore-rqs.dts | 43 +-- arch/arm/dts/imx6q-icore.dts | 72 +++-- arch/arm/dts/imx6qdl-icore-1.5.dtsi | 32 ++ arch/arm/dts/imx6qdl-icore-rqs.dtsi | 326 ++++++++++++++++++--- arch/arm/dts/imx6qdl-icore.dtsi | 270 ++++++++++++++--- board/engicam/common/board.c | 96 +++++- include/configs/imx6-engicam.h | 11 - include/dt-bindings/sound/fsl-imx-audmux.h | 64 ++++ 14 files changed, 850 insertions(+), 269 deletions(-) create mode 100644 arch/arm/dts/imx6q-icore-ofcap10.dts create mode 100644 arch/arm/dts/imx6q-icore-ofcap12.dts create mode 100644 arch/arm/dts/imx6qdl-icore-1.5.dtsi create mode 100644 include/dt-bindings/sound/fsl-imx-audmux.h -- 2.18.0.321.gffc6fa0e3

3 12

[PATCH v2] riscv: Add option to print registers on exception
by Sean Anderson 03 Jan '20

03 Jan '20

When debugging, it can be helpful to see more information about an unhandled exception. This patch adds an option to view the registers at the time of the trap, similar to the linux output on a kernel panic. Signed-off-by: Sean Anderson <seanga2(a)gmail.com> --- Changes for v2: - Renamed "PC" to "EPC" arch/riscv/Kconfig | 3 +++ arch/riscv/cpu/mtrap.S | 3 ++- arch/riscv/lib/interrupts.c | 50 +++++++++++++++++++++++++++++-------- 3 files changed, 44 insertions(+), 12 deletions(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 85e15ebffa..3338b788f8 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -222,6 +222,9 @@ config XIP from a NOR flash memory without copying the code to ram. Say yes here if U-Boot boots from flash directly. +config SHOW_REGS + bool "Show registers on unhandled exception" + config STACK_SIZE_SHIFT int default 14 diff --git a/arch/riscv/cpu/mtrap.S b/arch/riscv/cpu/mtrap.S index 407ecfa9c0..e40c7bd3f4 100644 --- a/arch/riscv/cpu/mtrap.S +++ b/arch/riscv/cpu/mtrap.S @@ -64,7 +64,8 @@ trap_entry: SREG x31, 31 * REGBYTES(sp) csrr a0, MODE_PREFIX(cause) csrr a1, MODE_PREFIX(epc) - mv a2, sp + csrr a2, MODE_PREFIX(tval) + mv a3, sp jal handle_trap csrw MODE_PREFIX(epc), a0 diff --git a/arch/riscv/lib/interrupts.c b/arch/riscv/lib/interrupts.c index 3b25c5b7a7..8352468f22 100644 --- a/arch/riscv/lib/interrupts.c +++ b/arch/riscv/lib/interrupts.c @@ -5,6 +5,8 @@ * * Copyright (C) 2017 Andes Technology Corporation * Rick Chen, Andes Technology Corporation <rick(a)andestech.com> + * + * Copyright (C) 2019 Sean Anderson <seanga2(a)gmail.com> */ #include <common.h> @@ -13,7 +15,34 @@ #include <asm/system.h> #include <asm/encoding.h> -static void _exit_trap(ulong code, ulong epc, struct pt_regs *regs) +static void show_regs(struct pt_regs *regs) +{ +#ifdef CONFIG_SHOW_REGS + printf("RA: " REG_FMT " SP: " REG_FMT " GP: " REG_FMT "\n", + regs->ra, regs->sp, regs->gp); + printf("TP: " REG_FMT " T0: " REG_FMT " T1: " REG_FMT "\n", + regs->tp, regs->t0, regs->t1); + printf("T2: " REG_FMT " S0: " REG_FMT " S1: " REG_FMT "\n", + regs->t2, regs->s0, regs->s1); + printf("A0: " REG_FMT " A1: " REG_FMT " A2: " REG_FMT "\n", + regs->a0, regs->a1, regs->a2); + printf("A3: " REG_FMT " A4: " REG_FMT " A5: " REG_FMT "\n", + regs->a3, regs->a4, regs->a5); + printf("A6: " REG_FMT " A7: " REG_FMT " S2: " REG_FMT "\n", + regs->a6, regs->a7, regs->s2); + printf("S3: " REG_FMT " S4: " REG_FMT " S5: " REG_FMT "\n", + regs->s3, regs->s4, regs->s5); + printf("S6: " REG_FMT " S7: " REG_FMT " S8: " REG_FMT "\n", + regs->s6, regs->s7, regs->s8); + printf("S9: " REG_FMT " S10: " REG_FMT " S11: " REG_FMT "\n", + regs->s9, regs->s10, regs->s11); + printf("T3: " REG_FMT " T4: " REG_FMT " T5: " REG_FMT "\n", + regs->t3, regs->t4, regs->t5); + printf("T6: " REG_FMT "\n", regs->t6); +#endif +} + +static void _exit_trap(ulong code, ulong epc, ulong tval, struct pt_regs *regs) { static const char * const exception_code[] = { "Instruction address misaligned", @@ -34,14 +63,13 @@ static void _exit_trap(ulong code, ulong epc, struct pt_regs *regs) "Store/AMO page fault", }; - if (code < ARRAY_SIZE(exception_code)) { - printf("exception code: %ld , %s , epc %lx , ra %lx\n", - code, exception_code[code], epc, regs->ra); - } else { - printf("reserved exception code: %ld , epc %lx , ra %lx\n", - code, epc, regs->ra); - } + if (code < ARRAY_SIZE(exception_code)) + printf("Unhandled exception: %s\n", exception_code[code]); + else + printf("Unhandled exception code: %ld\n", code); + printf("EPC: " REG_FMT " TVAL: " REG_FMT "\n", epc, tval); + show_regs(regs); hang(); } @@ -65,7 +93,7 @@ int disable_interrupts(void) return 0; } -ulong handle_trap(ulong cause, ulong epc, struct pt_regs *regs) +ulong handle_trap(ulong cause, ulong epc, ulong tval, struct pt_regs *regs) { ulong is_irq, irq; @@ -83,11 +111,11 @@ ulong handle_trap(ulong cause, ulong epc, struct pt_regs *regs) timer_interrupt(0); /* handle timer interrupt */ break; default: - _exit_trap(cause, epc, regs); + _exit_trap(cause, epc, tval, regs); break; }; } else { - _exit_trap(cause, epc, regs); + _exit_trap(cause, epc, tval, regs); } return epc; -- 2.24.1

2 1