December 2019 - U-Boot

[U-Boot] [PATCH 1/1] arm: cpu: armv8: add support for arm psci reset2.
by Vladimir Olovyannikov 10 Jan '20

10 Jan '20

From: Rajesh Ravi <rajesh.ravi(a)broadcom.com> Current U-Boot has only support for psci reset. Adding support for arm psci reset2 allows passing of reset level and other platform sepcific parameters like strap settings to lowlevel psci implementation. Signed-off-by: Rajesh Ravi <rajesh.ravi(a)broadcom.com> Signed-off-by: Vladimir Olovyannikov <vladimir.olovyannikov(a)broadcom.com> --- arch/arm/cpu/armv8/fwcall.c | 16 ++++++++++++++++ arch/arm/include/asm/psci.h | 4 ++++ arch/arm/include/asm/system.h | 1 + 3 files changed, 21 insertions(+) diff --git a/arch/arm/cpu/armv8/fwcall.c b/arch/arm/cpu/armv8/fwcall.c index b0aca1b72a..cbd35b7f4a 100644 --- a/arch/arm/cpu/armv8/fwcall.c +++ b/arch/arm/cpu/armv8/fwcall.c @@ -98,6 +98,22 @@ void __noreturn psci_system_reset(void) ; } +void __noreturn psci_system_reset2(u32 reset_level, u32 cookie) +{ + struct pt_regs regs; + + regs.regs[0] = ARM_PSCI_0_2_FN64_SYSTEM_RESET2; + regs.regs[1] = PSCI_RESET2_TYPE_VENDOR | reset_level; + regs.regs[2] = cookie; + if (use_smc_for_psci) + smc_call(&regs); + else + hvc_call(&regs); + + while (1) + ; +} + void __noreturn psci_system_off(void) { struct pt_regs regs; diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h index 95f18e8cbc..3ddcd95a26 100644 --- a/arch/arm/include/asm/psci.h +++ b/arch/arm/include/asm/psci.h @@ -64,6 +64,7 @@ #define ARM_PSCI_0_2_FN64_AFFINITY_INFO ARM_PSCI_0_2_FN64(4) #define ARM_PSCI_0_2_FN64_MIGRATE ARM_PSCI_0_2_FN64(5) #define ARM_PSCI_0_2_FN64_MIGRATE_INFO_UP_CPU ARM_PSCI_0_2_FN64(7) +#define ARM_PSCI_0_2_FN64_SYSTEM_RESET2 ARM_PSCI_0_2_FN64(18) /* PSCI 1.0 interface */ #define ARM_PSCI_1_0_FN_PSCI_FEATURES ARM_PSCI_0_2_FN(10) @@ -90,6 +91,9 @@ #define PSCI_AFFINITY_LEVEL_OFF 1 #define PSCI_AFFINITY_LEVEL_ON_PENDING 2 +#define PSCI_RESET2_TYPE_VENDOR_SHIFT 31 +#define PSCI_RESET2_TYPE_VENDOR BIT(PSCI_RESET2_TYPE_VENDOR_SHIFT) + #ifndef __ASSEMBLY__ #include <asm/types.h> diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index a1a5e35ef6..81ccead112 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -254,6 +254,7 @@ void mmu_change_region_attr(phys_addr_t start, size_t size, u64 attrs); void smc_call(struct pt_regs *args); void __noreturn psci_system_reset(void); +void __noreturn psci_system_reset2(u32 reset_level, u32 cookie); void __noreturn psci_system_off(void); #ifdef CONFIG_ARMV8_PSCI -- 2.17.1

2 1

[U-Boot] [PATCH] poweroff: add poweroff for mt6323 pmic
by Frank Wunderlich 10 Jan '20

10 Jan '20

this adds poweroff to bananapi r2 / mt7623 / mt6323 pmic Signed-off-by: Frank Wunderlich <frank-w(a)public-files.de> --- drivers/power/Kconfig | 7 +++++++ drivers/power/Makefile | 1 + drivers/power/mt6323.c | 37 +++++++++++++++++++++++++++++++++++++ 3 files changed, 45 insertions(+) create mode 100644 drivers/power/mt6323.c diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig index 9495dca33b..0ac906e86d 100644 --- a/drivers/power/Kconfig +++ b/drivers/power/Kconfig @@ -364,4 +364,11 @@ config TWL4030_POWER The TWL4030 in a combination audio CODEC/power management with GPIO and it is commonly used with the OMAP3 family of processors +config POWER_MT6323 + bool "Poweroff driver for mediatek mt6323" + select CMD_POWEROFF + help + This adds poweroff driver for mt6323 + this pmic is used on mt7623 / Bananapi R2 + endmenu diff --git a/drivers/power/Makefile b/drivers/power/Makefile index dd5bc0dc44..2dcc7bb99d 100644 --- a/drivers/power/Makefile +++ b/drivers/power/Makefile @@ -20,3 +20,4 @@ obj-$(CONFIG_DIALOG_POWER) += power_dialog.o obj-$(CONFIG_POWER_FSL) += power_fsl.o obj-$(CONFIG_POWER_I2C) += power_i2c.o obj-$(CONFIG_POWER_SPI) += power_spi.o +obj-$(CONFIG_POWER_MT6323) += mt6323.o diff --git a/drivers/power/mt6323.c b/drivers/power/mt6323.c new file mode 100644 index 0000000000..566be5f39e --- /dev/null +++ b/drivers/power/mt6323.c @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Frank Wunderlich <frank-w(a)public-files.de> + */ + +#include <common.h> +#include <command.h> +#include <asm/io.h> + +#define PWRAP_BASE 0x1000d000 +#define PWRAP_WACS2_CMD 0x9c + +#define PWRAP_CALC(adr, wdata) ((1 << 31) | (((adr) >> 1) << 16) | (wdata)) + +#define MT6323_PWRC_BASE 0x8000 +#define RTC_BBPU 0x0000 +#define RTC_BBPU_KEY (0x43 << 8) +#define RTC_WRTGR 0x003c + +int do_poweroff(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + u32 addr, val; + + addr = PWRAP_BASE + PWRAP_WACS2_CMD; + val = PWRAP_CALC(MT6323_PWRC_BASE + RTC_BBPU, RTC_BBPU_KEY); + writel(val, addr); + + mdelay(10); + + val = PWRAP_CALC(MT6323_PWRC_BASE + RTC_WRTGR, 1); + writel(val, addr); + + // wait some time and then print error + mdelay(10000); + printf("Failed to power off!!!\n"); + return 1; +} -- 2.17.1

2 3

[U-Boot] [PATCH 1/9] m68k: add fec base node to devicetrees
by Angelo Dureghello 10 Jan '20

10 Jan '20

From: Angelo Durgehello <angelo.dureghello(a)timesys.com> Add basic ethernet controller devicetree nodes for all ColdFire families. Signed-off-by: Angelo Durgehello <angelo.dureghello(a)timesys.com> --- arch/m68k/dts/mcf5208.dtsi | 10 ++++++++++ arch/m68k/dts/mcf523x.dtsi | 12 ++++++++++++ arch/m68k/dts/mcf5271.dtsi | 10 ++++++++++ arch/m68k/dts/mcf5272.dtsi | 10 ++++++++++ arch/m68k/dts/mcf5275.dtsi | 22 +++++++++++++++++++++- arch/m68k/dts/mcf5282.dtsi | 10 ++++++++++ arch/m68k/dts/mcf5301x.dtsi | 21 +++++++++++++++++++++ arch/m68k/dts/mcf5329.dtsi | 10 ++++++++++ arch/m68k/dts/mcf537x.dtsi | 10 ++++++++++ arch/m68k/dts/mcf5441x.dtsi | 20 ++++++++++++++++++++ arch/m68k/dts/mcf5445x.dtsi | 20 ++++++++++++++++++++ arch/m68k/dts/mcf54xx.dtsi | 32 ++++++++++++++++++++++++++++++++ 12 files changed, 186 insertions(+), 1 deletion(-) diff --git a/arch/m68k/dts/mcf5208.dtsi b/arch/m68k/dts/mcf5208.dtsi index 558d8bf41a..4802dd3074 100644 --- a/arch/m68k/dts/mcf5208.dtsi +++ b/arch/m68k/dts/mcf5208.dtsi @@ -8,6 +8,7 @@ aliases { serial0 = &uart0; + fec0 = &fec0; }; soc { @@ -32,5 +33,14 @@ reg = <0xfc068000 0x40>; status = "disabled"; }; + + fec0: ethernet@fc030000 { + compatible = "fsl,mcf-fec"; + reg = <0xfc030000 0x400>; + mii-base = <0>; + max-speed = <100>; + timeout-loop = <50000>; + status = "disabled"; + }; }; }; diff --git a/arch/m68k/dts/mcf523x.dtsi b/arch/m68k/dts/mcf523x.dtsi index 9e79d472ec..550e824cb1 100644 --- a/arch/m68k/dts/mcf523x.dtsi +++ b/arch/m68k/dts/mcf523x.dtsi @@ -8,6 +8,7 @@ aliases { serial0 = &uart0; + fec0 = &fec0; }; soc { @@ -39,6 +40,17 @@ reg = <0x280 0x40>; status = "disabled"; }; + + fec0: ethernet@1000 { + compatible = "fsl,mcf-fec"; + #address-cells=<2>; + #size-cells=<1>; + reg = <0x1000 0x400>; + mii-base = <0>; + max-speed = <100>; + timeout-loop = <50000>; + status = "disabled"; + }; }; }; }; diff --git a/arch/m68k/dts/mcf5271.dtsi b/arch/m68k/dts/mcf5271.dtsi index 29355528d0..b3484c2c84 100644 --- a/arch/m68k/dts/mcf5271.dtsi +++ b/arch/m68k/dts/mcf5271.dtsi @@ -8,6 +8,7 @@ aliases { serial0 = &uart0; + fec0 = &fec0; }; soc { @@ -39,6 +40,15 @@ reg = <0x280 0x40>; status = "disabled"; }; + + fec0: ethernet@1000 { + compatible = "fsl,mcf-fec"; + reg = <0x1000 0x400>; + mii-base = <0>; + max-speed = <100>; + timeout-loop = <50000>; + status = "disabled"; + }; }; }; }; diff --git a/arch/m68k/dts/mcf5272.dtsi b/arch/m68k/dts/mcf5272.dtsi index a56117728b..173baaba3f 100644 --- a/arch/m68k/dts/mcf5272.dtsi +++ b/arch/m68k/dts/mcf5272.dtsi @@ -8,6 +8,7 @@ aliases { serial0 = &uart0; + fec0 = &fec0; }; soc { @@ -33,6 +34,15 @@ reg = <0x140 0x40>; status = "disabled"; }; + + fec0: ethernet@840 { + compatible = "fsl,mcf-fec"; + reg = <0x840 0x400>; + mii-base = <0>; + max-speed = <100>; + timeout-loop = <50000>; + status = "disabled"; + }; }; }; }; diff --git a/arch/m68k/dts/mcf5275.dtsi b/arch/m68k/dts/mcf5275.dtsi index b375609d4a..99dd7d3924 100644 --- a/arch/m68k/dts/mcf5275.dtsi +++ b/arch/m68k/dts/mcf5275.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2018 Angelo Dureghello <angelo(a)sysam.it> + * Copyright (C) 2019 Angelo Dureghello <angelo(a)sysam.it> */ / { @@ -8,6 +8,8 @@ aliases { serial0 = &uart0; + fec0 = &fec0; + fec1 = &fec1; }; soc { @@ -39,6 +41,24 @@ reg = <0x280 0x40>; status = "disabled"; }; + + fec0: ethernet@1000 { + compatible = "fsl,mcf-fec"; + reg = <0x1000 0x800>; + max-speed = <100>; + phy-addr = <(-1)>; + timeout-loop = <50000>; + status = "disabled"; + }; + + fec1: ethernet@1800 { + compatible = "fsl,mcf-fec"; + reg = <0x1800 0x800>; + mii-base = <0>; + max-speed = <100>; + timeout-loop = <50000>; + status = "disabled"; + }; }; }; }; diff --git a/arch/m68k/dts/mcf5282.dtsi b/arch/m68k/dts/mcf5282.dtsi index 3ad1be7bb5..d9916b1cd9 100644 --- a/arch/m68k/dts/mcf5282.dtsi +++ b/arch/m68k/dts/mcf5282.dtsi @@ -8,6 +8,7 @@ aliases { serial0 = &uart0; + fec0 = &fec0; }; soc { @@ -39,6 +40,15 @@ reg = <0x280 0x40>; status = "disabled"; }; + + fec0: ethernet@1000 { + compatible = "fsl,mcf-fec"; + reg = <0x1000 0x800>; + mii-base = <0>; + max-speed = <100>; + timeout-loop = <50000>; + status = "disabled"; + }; }; }; }; diff --git a/arch/m68k/dts/mcf5301x.dtsi b/arch/m68k/dts/mcf5301x.dtsi index 0891e4dfd5..f60898aa4a 100644 --- a/arch/m68k/dts/mcf5301x.dtsi +++ b/arch/m68k/dts/mcf5301x.dtsi @@ -9,6 +9,8 @@ aliases { serial0 = &uart0; spi0 = &dspi0; + fec0 = &fec0; + fec1 = &fec1; }; soc { @@ -44,5 +46,24 @@ spi-mode = <0>; status = "disabled"; }; + + fec0: ethernet@fc030000 { + compatible = "fsl,mcf-fec"; + reg = <0xfc030000 0x200>; + mii-base = <0>; + max-speed = <100>; + phy-addr = <(-1)>; + timeout-loop = <50000>; + status = "disabled"; + }; + + fec1: ethernet@fc034000 { + compatible = "fsl,mcf-fec"; + reg = <0xfc034000 0x800>; + mii-base = <1>; + max-speed = <100>; + timeout-loop = <50000>; + status = "disabled"; + }; }; }; diff --git a/arch/m68k/dts/mcf5329.dtsi b/arch/m68k/dts/mcf5329.dtsi index aeaa6430af..de348968b5 100644 --- a/arch/m68k/dts/mcf5329.dtsi +++ b/arch/m68k/dts/mcf5329.dtsi @@ -8,6 +8,7 @@ aliases { serial0 = &uart0; + fec0 = &fec0; }; soc { @@ -32,5 +33,14 @@ reg = <0xfc068000 0x40>; status = "disabled"; }; + + fec0: ethernet@fc030000 { + compatible = "fsl,mcf-fec"; + reg = <0xfc030000 0x800>; + mii-base = <0>; + max-speed = <100>; + timeout-loop = <50000>; + status = "disabled"; + }; }; }; diff --git a/arch/m68k/dts/mcf537x.dtsi b/arch/m68k/dts/mcf537x.dtsi index aeaa6430af..2a2a32a59b 100644 --- a/arch/m68k/dts/mcf537x.dtsi +++ b/arch/m68k/dts/mcf537x.dtsi @@ -8,6 +8,7 @@ aliases { serial0 = &uart0; + fec0 = &fec0; }; soc { @@ -32,5 +33,14 @@ reg = <0xfc068000 0x40>; status = "disabled"; }; + + fec0: ethernet@fc030000 { + compatible = "fsl,mcf-fec"; + reg = <0xfc030000 0x400>; + mii-base = <0>; + max-speed = <100>; + timeout-loop = <50000>; + status = "disabled"; + }; }; }; diff --git a/arch/m68k/dts/mcf5441x.dtsi b/arch/m68k/dts/mcf5441x.dtsi index 71b392adc3..6769bdc270 100644 --- a/arch/m68k/dts/mcf5441x.dtsi +++ b/arch/m68k/dts/mcf5441x.dtsi @@ -9,6 +9,8 @@ aliases { serial0 = &uart0; spi0 = &dspi0; + fec0 = &fec0; + fec1 = &fec1; }; soc { @@ -83,5 +85,23 @@ spi-mode = <0>; status = "disabled"; }; + + fec0: ethernet@fc0d4000 { + compatible = "fsl,mcf-fec"; + reg = <0xfc0d4000 0x4000>; + mii-base = <0>; + max-speed = <100>; + timeout-loop = <50000>; + status = "disabled"; + }; + + fec1: ethernet@fc0d8000 { + compatible = "fsl,mcf-fec"; + reg = <0xfc0d8000 0x4000>; + mii-base = <1>; + max-speed = <100>; + timeout-loop = <50000>; + status = "disabled"; + }; }; }; diff --git a/arch/m68k/dts/mcf5445x.dtsi b/arch/m68k/dts/mcf5445x.dtsi index ccbee29a6c..b7ecc99c09 100644 --- a/arch/m68k/dts/mcf5445x.dtsi +++ b/arch/m68k/dts/mcf5445x.dtsi @@ -9,6 +9,8 @@ aliases { serial0 = &uart0; spi0 = &dspi0; + fec0 = &fec0; + fec1 = &fec1; }; soc { @@ -44,5 +46,23 @@ spi-mode = <0>; status = "disabled"; }; + + fec0: ethernet@fc030000 { + compatible = "fsl,mcf-fec"; + reg = <0xfc030000 0x4000>; + mii-base = <0>; + max-speed = <100>; + timeout-loop = <50000>; + status = "disabled"; + }; + + fec1: ethernet@fc034000 { + compatible = "fsl,mcf-fec"; + reg = <0xfc034000 0x4000>; + mii-base = <1>; + max-speed = <100>; + timeout-loop = <50000>; + status = "disabled"; + }; }; }; diff --git a/arch/m68k/dts/mcf54xx.dtsi b/arch/m68k/dts/mcf54xx.dtsi index 537bb424f3..e9cebb9f74 100644 --- a/arch/m68k/dts/mcf54xx.dtsi +++ b/arch/m68k/dts/mcf54xx.dtsi @@ -11,6 +11,8 @@ * no UARTS. */ spi0 = &dspi0; + fec0 = &fec0; + fec1 = &fec1; }; soc { @@ -35,6 +37,36 @@ spi-mode = <0>; status = "disabled"; }; + + fec0: ethernet@9000 { + compatible = "fsl,mcf-dma-fec"; + reg = <0x9000 0x800>; + mii-base = <0>; + max-speed = <100>; + timeout-loop = <50000>; + rx-task = <0>; + tx-task = <1>; + rx-piority = <6>; + tx-piority = <7>; + rx-init = <16>; + tx-init = <17>; + status = "disabled"; + }; + + fec1: ethernet@9800 { + compatible = "fsl,mcf-dma-fec"; + reg = <0x9800 0x800>; + mii-base = <1>; + max-speed = <100>; + timeout-loop = <50000>; + rx-task = <2>; + tx-task = <3>; + rx-piority = <6>; + tx-piority = <7>; + rx-init = <30>; + tx-init = <31>; + status = "disabled"; + }; }; }; }; -- 2.24.0

2 17

[U-Boot] [PATCH] rtc: add support for DS3232 device
by Han Nandor 10 Jan '20

10 Jan '20

DS3232 is an i2c RTC with 236 bytes of battery-backed SRAM. Add an RTC driver for DS3232 device, which provides time and date support. Also read and write functions are provided, which can be used to access the SRAM memory. Signed-off-by: Nandor Han <nandor.han(a)vaisala.com> --- Notes: Description ---------- Add support for RTC DS3232 device. Testing ------ 1. Check that date/time can be reset: PASS U-Boot> date reset Reset RTC... Date: 2000-01-01 (Saturday) Time: 0:00:00 2. Check that setting the date/time is successful: PASS U-Boot> date 040114012019.00 Date: 2019-04-01 (Monday) Time: 14:01:00 3. Check that getting the date/time is successful: PASS U-Boot> date Date: 2019-04-01 (Monday) Time: 14:01:58 4. Verify that the date configured in U-Boot is the same read in Kernel. doc/device-tree-bindings/rtc/ds3232.txt | 15 ++ drivers/rtc/Kconfig | 8 + drivers/rtc/Makefile | 1 + drivers/rtc/ds3232.c | 274 ++++++++++++++++++++++++ 4 files changed, 298 insertions(+) create mode 100644 doc/device-tree-bindings/rtc/ds3232.txt create mode 100644 drivers/rtc/ds3232.c diff --git a/doc/device-tree-bindings/rtc/ds3232.txt b/doc/device-tree-bindings/rtc/ds3232.txt new file mode 100644 index 0000000000..254b7bc3c3 --- /dev/null +++ b/doc/device-tree-bindings/rtc/ds3232.txt @@ -0,0 +1,15 @@ +DS3232 Real-Time Clock with SRAM + +The RTC driver provides time and date functionality. Also read and write +functions are provided that can be used to access the SRAM memory. + +Required properties: +- compatible : should contain "dallas,ds3232" +- reg : the I2C RTC address + +Example: + +rtc@68 { + compatible = "dallas,ds3232"; + reg = <0x68>; +}; diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index 8778cc7b26..a82f79bf16 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -54,6 +54,14 @@ config RTC_DS1307 Support for Dallas Semiconductor (now Maxim) DS1307 and DS1338/9 and compatible Real Time Clock devices. +config RTC_DS3232 + bool "Enable DS3232 driver" + depends on DM_RTC + depends on DM_I2C + help + Support for Dallas Semiconductor (now Maxim) DS3232 compatible + Real Time Clock devices. + config RTC_ISL1208 bool "Enable ISL1208 driver" depends on DM_RTC diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index f97a669982..e89de73b11 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -22,6 +22,7 @@ obj-$(CONFIG_RTC_DS1556) += ds1556.o obj-$(CONFIG_RTC_DS164x) += ds164x.o obj-$(CONFIG_RTC_DS174x) += ds174x.o obj-$(CONFIG_RTC_DS3231) += ds3231.o +obj-$(CONFIG_RTC_DS3232) += ds3232.o obj-$(CONFIG_RTC_FTRTC010) += ftrtc010.o obj-$(CONFIG_SANDBOX) += i2c_rtc_emul.o obj-$(CONFIG_RTC_IMXDI) += imxdi.o diff --git a/drivers/rtc/ds3232.c b/drivers/rtc/ds3232.c new file mode 100644 index 0000000000..09a106aa4e --- /dev/null +++ b/drivers/rtc/ds3232.c @@ -0,0 +1,274 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2019, Vaisala Oyj + */ + +#include <common.h> +#include <command.h> +#include <dm.h> +#include <i2c.h> +#include <rtc.h> + +/* + * RTC register addresses + */ +#define RTC_SEC_REG_ADDR 0x00 +#define RTC_MIN_REG_ADDR 0x01 +#define RTC_HR_REG_ADDR 0x02 +#define RTC_DAY_REG_ADDR 0x03 +#define RTC_DATE_REG_ADDR 0x04 +#define RTC_MON_REG_ADDR 0x05 +#define RTC_YR_REG_ADDR 0x06 +#define RTC_CTL_REG_ADDR 0x0e +#define RTC_STAT_REG_ADDR 0x0f +#define RTC_TEST_REG_ADDR 0x13 + +/* + * RTC control register bits + */ +#define RTC_CTL_BIT_A1IE BIT(0) /* Alarm 1 interrupt enable */ +#define RTC_CTL_BIT_A2IE BIT(1) /* Alarm 2 interrupt enable */ +#define RTC_CTL_BIT_INTCN BIT(2) /* Interrupt control */ +#define RTC_CTL_BIT_DOSC BIT(7) /* Disable Oscillator */ + +/* + * RTC status register bits + */ +#define RTC_STAT_BIT_A1F BIT(0) /* Alarm 1 flag */ +#define RTC_STAT_BIT_A2F BIT(1) /* Alarm 2 flag */ +#define RTC_STAT_BIT_EN32KHZ BIT(3) /* Enable 32KHz Output */ +#define RTC_STAT_BIT_BB32KHZ BIT(6) /* Battery backed 32KHz Output */ +#define RTC_STAT_BIT_OSF BIT(7) /* Oscillator stop flag */ + +/* + * RTC test register bits + */ +#define RTC_TEST_BIT_SWRST BIT(7) /* Software reset */ + +#define RTC_DATE_TIME_REG_SIZE 7 +#define RTC_SRAM_START 0x14 +#define RTC_SRAM_END 0xFF +#define RTC_SRAM_SIZE 236 + +struct ds3232_priv_data { + u8 max_register; + u8 sram_start; + int sram_size; +}; + +static int ds3232_rtc_read8(struct udevice *dev, unsigned int reg) +{ + int ret; + u8 buf; + struct ds3232_priv_data *priv_data; + + priv_data = dev_get_priv(dev); + if (!priv_data) + return -EINVAL; + + if (reg > priv_data->max_register) + return -EINVAL; + + ret = dm_i2c_read(dev, reg, &buf, sizeof(buf)); + if (ret < 0) + return ret; + + return buf; +} + +static int ds3232_rtc_write8(struct udevice *dev, unsigned int reg, int val) +{ + u8 buf = (u8)val; + struct ds3232_priv_data *priv_data; + + priv_data = dev_get_priv(dev); + if (!priv_data) + return -EINVAL; + + if (reg > priv_data->max_register) + return -EINVAL; + + return dm_i2c_write(dev, reg, &buf, sizeof(buf)); +} + +static int reset_sram(struct udevice *dev) +{ + int ret, sram_end, reg; + struct ds3232_priv_data *priv_data; + + priv_data = dev_get_priv(dev); + if (!priv_data) + return -EINVAL; + + sram_end = priv_data->sram_start + priv_data->sram_size; + + for (reg = priv_data->sram_start; reg < sram_end; reg++) { + ret = ds3232_rtc_write8(dev, reg, 0x00); + if (ret < 0) + return ret; + } + + return 0; +} + +static int verify_osc(struct udevice *dev) +{ + int ret, rtc_status; + + ret = ds3232_rtc_read8(dev, RTC_STAT_REG_ADDR); + if (ret < 0) + return ret; + + rtc_status = ret; + + if (rtc_status & RTC_STAT_BIT_OSF) { + dev_warn(dev, + "oscillator discontinuity flagged, time unreliable\n"); + /* + * In case OSC was off we cannot trust the SRAM data anymore. + * Reset it to 0x00. + */ + ret = reset_sram(dev); + if (ret < 0) + return ret; + } + + return 0; +} + +static int ds3232_rtc_set(struct udevice *dev, const struct rtc_time *tm) +{ + u8 buf[RTC_DATE_TIME_REG_SIZE]; + u8 is_century; + + if (tm->tm_year < 1900 || tm->tm_year > 2099) + dev_warn(dev, "WARNING: year should be between 1900 and 2099!\n"); + + is_century = (tm->tm_year >= 2000) ? 0x80 : 0; + + buf[RTC_SEC_REG_ADDR] = bin2bcd(tm->tm_sec); + buf[RTC_MIN_REG_ADDR] = bin2bcd(tm->tm_min); + buf[RTC_HR_REG_ADDR] = bin2bcd(tm->tm_hour); + buf[RTC_DAY_REG_ADDR] = bin2bcd(tm->tm_wday + 1); + buf[RTC_DATE_REG_ADDR] = bin2bcd(tm->tm_mday); + buf[RTC_MON_REG_ADDR] = bin2bcd(tm->tm_mon) | is_century; + buf[RTC_YR_REG_ADDR] = bin2bcd(tm->tm_year % 100); + + return dm_i2c_write(dev, 0, buf, sizeof(buf)); +} + +static int ds3232_rtc_get(struct udevice *dev, struct rtc_time *tm) +{ + int ret; + u8 buf[RTC_DATE_TIME_REG_SIZE]; + u8 is_twelve_hr; + u8 is_pm; + u8 is_century; + + ret = verify_osc(dev); + if (ret < 0) + return ret; + + ret = dm_i2c_read(dev, 0, buf, sizeof(buf)); + if (ret < 0) + return ret; + + /* Extract additional information for AM/PM and century */ + is_twelve_hr = buf[RTC_HR_REG_ADDR] & 0x40; + is_pm = buf[RTC_HR_REG_ADDR] & 0x20; + is_century = buf[RTC_MON_REG_ADDR] & 0x80; + + tm->tm_sec = bcd2bin(buf[RTC_SEC_REG_ADDR] & 0x7F); + tm->tm_min = bcd2bin(buf[RTC_MIN_REG_ADDR] & 0x7F); + + if (is_twelve_hr) + tm->tm_hour = bcd2bin(buf[RTC_HR_REG_ADDR] & 0x1F) + + (is_pm ? 12 : 0); + else + tm->tm_hour = bcd2bin(buf[RTC_HR_REG_ADDR]); + + tm->tm_wday = bcd2bin((buf[RTC_DAY_REG_ADDR] & 0x07) - 1); + tm->tm_mday = bcd2bin(buf[RTC_DATE_REG_ADDR] & 0x3F); + tm->tm_mon = bcd2bin((buf[RTC_MON_REG_ADDR] & 0x7F)); + tm->tm_year = bcd2bin(buf[RTC_YR_REG_ADDR]) + + (is_century ? 2000 : 1900); + tm->tm_yday = 0; + tm->tm_isdst = 0; + + return 0; +} + +static int ds3232_rtc_reset(struct udevice *dev) +{ + int ret; + + ret = reset_sram(dev); + if (ret < 0) + return ret; + + /* + * From datasheet + * (https://datasheets.maximintegrated.com/en/ds/DS3232M.pdf): + * + * The device reset occurs during the normal acknowledge time slot + * following the receipt of the data byte carrying that + * SWRST instruction a NACK occurs due to the resetting action. + * + * Therefore we don't verify the result of I2C write operation since it + * will fail due the NACK. + */ + ds3232_rtc_write8(dev, RTC_TEST_REG_ADDR, RTC_TEST_BIT_SWRST); + + return 0; +} + +static int ds3232_probe(struct udevice *dev) +{ + int rtc_status; + int ret; + struct ds3232_priv_data *priv_data; + + priv_data = dev_get_priv(dev); + if (!priv_data) + return -EINVAL; + + priv_data->sram_start = RTC_SRAM_START; + priv_data->max_register = RTC_SRAM_END; + priv_data->sram_size = RTC_SRAM_SIZE; + + ret = ds3232_rtc_read8(dev, RTC_STAT_REG_ADDR); + if (ret < 0) + return ret; + + rtc_status = ret; + + ret = verify_osc(dev); + if (ret < 0) + return ret; + + rtc_status &= ~(RTC_STAT_BIT_OSF | RTC_STAT_BIT_A1F | RTC_STAT_BIT_A2F); + + return ds3232_rtc_write8(dev, RTC_STAT_REG_ADDR, rtc_status); +} + +static const struct rtc_ops ds3232_rtc_ops = { + .get = ds3232_rtc_get, + .set = ds3232_rtc_set, + .reset = ds3232_rtc_reset, + .read8 = ds3232_rtc_read8, + .write8 = ds3232_rtc_write8 +}; + +static const struct udevice_id ds3232_rtc_ids[] = { + { .compatible = "dallas,ds3232" }, + { } +}; + +U_BOOT_DRIVER(rtc_ds3232) = { + .name = "rtc-ds3232", + .id = UCLASS_RTC, + .probe = ds3232_probe, + .of_match = ds3232_rtc_ids, + .ops = &ds3232_rtc_ops, + .priv_auto_alloc_size = sizeof(struct ds3232_priv_data), +}; -- 2.20.1

2 1

[U-Boot] [PATCH] spl: fix stack usage check if gd is not initialized
by Simon Goldschmidt 10 Jan '20

10 Jan '20

Most platforms do not set up gd->start_addr_sp in SPL. Since this is required for CONFIG_SPL_SYS_REPORT_SACK_F_USAGE to work correctly, set up gd->start_addr_sp in SPL to the value passed to board_init_f_init_reserve if it is not set yet. Fixes: d8c0332031 ("spl: implement stack usage check") Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt(a)gmail.com> --- common/init/board_init.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/common/init/board_init.c b/common/init/board_init.c index e52106966d..3bc7994586 100644 --- a/common/init/board_init.c +++ b/common/init/board_init.c @@ -18,6 +18,19 @@ __weak void arch_setup_gd(struct global_data *gd_ptr) } #endif /* !CONFIG_X86 && !CONFIG_ARM */ +/** + * This function is called from board_init_f_init_reserve to set up + * gd->start_addr_sp for stack protection if not already set otherwise + */ +__weak void board_init_f_init_stack_protection_addr(ulong base) +{ +#if CONFIG_IS_ENABLED(SYS_REPORT_STACK_F_USAGE) + /* set up stack pointer for stack usage if not set yet */ + if (!gd->start_addr_sp) + gd->start_addr_sp = base; +#endif +} + /** * This function is called after the position of the initial stack is * determined in gd->start_addr_sp. Boards can override it to set up @@ -129,6 +142,10 @@ void board_init_f_init_reserve(ulong base) #if !defined(CONFIG_ARM) arch_setup_gd(gd_ptr); #endif + + if (CONFIG_IS_ENABLED(SYS_REPORT_STACK_F_USAGE)) + board_init_f_init_stack_protection_addr(base); + /* next alloc will be higher by one GD plus 16-byte alignment */ base += roundup(sizeof(struct global_data), 16); -- 2.20.1

2 1

[U-Boot] [PATCH] m68k: Drop CONFIG_MCFPIT support
by Tom Rini 10 Jan '20

10 Jan '20

All platforms currently use the "MCFTMR" DMA timer rather than the PIT timer, so drop the MCFPIT code. Cc: Huan Wang <alison.wang(a)nxp.com> Cc: Angelo Dureghello <angelo(a)sysam.it> Cc: TsiChung Liew <Tsi-Chung.Liew(a)nxp.com> Cc: Wolfgang Wegner <w.wegner(a)astro-kom.de> Signed-off-by: Tom Rini <trini(a)konsulko.com> --- arch/m68k/include/asm/immap.h | 42 --------------------- arch/m68k/lib/time.c | 63 -------------------------------- board/freescale/m52277evb/README | 1 - board/freescale/m53017evb/README | 1 - board/freescale/m5373evb/README | 1 - board/freescale/m54455evb/README | 1 - include/configs/M5208EVBE.h | 1 - include/configs/M52277EVB.h | 1 - include/configs/M5235EVB.h | 1 - include/configs/M53017EVB.h | 1 - include/configs/M5329EVB.h | 1 - include/configs/M5373EVB.h | 1 - include/configs/M54418TWR.h | 1 - include/configs/M54451EVB.h | 1 - include/configs/M54455EVB.h | 1 - include/configs/astro_mcf5373l.h | 1 - include/configs/stmark2.h | 1 - scripts/config_whitelist.txt | 1 - 18 files changed, 121 deletions(-) diff --git a/arch/m68k/include/asm/immap.h b/arch/m68k/include/asm/immap.h index 80fa25769b27..9e84fb9d260c 100644 --- a/arch/m68k/include/asm/immap.h +++ b/arch/m68k/include/asm/immap.h @@ -28,12 +28,6 @@ #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) #endif -#ifdef CONFIG_MCFPIT -#define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0) -#define CONFIG_SYS_PIT_BASE (MMAP_PIT1) -#define CONFIG_SYS_PIT_PRESCALE (6) -#endif - #define CONFIG_SYS_INTR_BASE (MMAP_INTC0) #define CONFIG_SYS_NUM_IRQS (128) #endif /* CONFIG_M520x */ @@ -62,12 +56,6 @@ #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) #endif -#ifdef CONFIG_MCFPIT -#define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0) -#define CONFIG_SYS_PIT_BASE (MMAP_PIT1) -#define CONFIG_SYS_PIT_PRESCALE (6) -#endif - #define CONFIG_SYS_INTR_BASE (MMAP_INTC0) #define CONFIG_SYS_NUM_IRQS (128) #endif /* CONFIG_M52277 */ @@ -91,12 +79,6 @@ #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) #endif -#ifdef CONFIG_MCFPIT -#define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0) -#define CONFIG_SYS_PIT_BASE (MMAP_PIT1) -#define CONFIG_SYS_PIT_PRESCALE (6) -#endif - #define CONFIG_SYS_INTR_BASE (MMAP_INTC0) #define CONFIG_SYS_NUM_IRQS (128) #endif /* CONFIG_M5235 */ @@ -285,12 +267,6 @@ #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) #endif -#ifdef CONFIG_MCFPIT -#define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0) -#define CONFIG_SYS_PIT_BASE (MMAP_PIT1) -#define CONFIG_SYS_PIT_PRESCALE (6) -#endif - #define CONFIG_SYS_INTR_BASE (MMAP_INTC0) #define CONFIG_SYS_NUM_IRQS (128) #endif /* CONFIG_M5301x */ @@ -315,12 +291,6 @@ #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) #endif -#ifdef CONFIG_MCFPIT -#define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0) -#define CONFIG_SYS_PIT_BASE (MMAP_PIT1) -#define CONFIG_SYS_PIT_PRESCALE (6) -#endif - #define CONFIG_SYS_INTR_BASE (MMAP_INTC0) #define CONFIG_SYS_NUM_IRQS (128) #endif /* CONFIG_M5329 && CONFIG_M5373 */ @@ -355,12 +325,6 @@ #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) #endif -#ifdef CONFIG_MCFPIT -#define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0) -#define CONFIG_SYS_PIT_BASE (MMAP_PIT1) -#define CONFIG_SYS_PIT_PRESCALE (6) -#endif - #define CONFIG_SYS_INTR_BASE (MMAP_INTC0) #define CONFIG_SYS_NUM_IRQS (192) @@ -391,12 +355,6 @@ #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) #endif -#ifdef CONFIG_MCFPIT -#define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0) -#define CONFIG_SYS_PIT_BASE (MMAP_PIT1) -#define CONFIG_SYS_PIT_PRESCALE (6) -#endif - #define CONFIG_SYS_INTR_BASE (MMAP_INTC0) #define CONFIG_SYS_NUM_IRQS (128) diff --git a/arch/m68k/lib/time.c b/arch/m68k/lib/time.c index a6345a0bc9c0..52f6dd753321 100644 --- a/arch/m68k/lib/time.c +++ b/arch/m68k/lib/time.c @@ -108,69 +108,6 @@ ulong get_timer(ulong base) #endif /* CONFIG_MCFTMR */ -#if defined(CONFIG_MCFPIT) -#if !defined(CONFIG_SYS_PIT_BASE) -# error "CONFIG_SYS_PIT_BASE not defined!" -#endif - -static unsigned short lastinc; - -void __udelay(unsigned long usec) -{ - volatile pit_t *timerp = (pit_t *) (CONFIG_SYS_UDELAY_BASE); - uint tmp; - - while (usec > 0) { - if (usec > 65000) - tmp = 65000; - else - tmp = usec; - usec = usec - tmp; - - /* Set up TIMER 3 as timebase clock */ - timerp->pcsr = PIT_PCSR_OVW; - timerp->pmr = 0; - /* set period to 1 us */ - timerp->pcsr |= PIT_PCSR_PRE(CONFIG_SYS_PIT_PRESCALE) | PIT_PCSR_EN; - - timerp->pmr = tmp; - while (timerp->pcntr > 0) ; - } -} - -void timer_init(void) -{ - volatile pit_t *timerp = (pit_t *) (CONFIG_SYS_PIT_BASE); - timestamp = 0; - - /* Set up TIMER 4 as poll clock */ - timerp->pcsr = PIT_PCSR_OVW; - timerp->pmr = lastinc = 0; - timerp->pcsr |= PIT_PCSR_PRE(CONFIG_SYS_PIT_PRESCALE) | PIT_PCSR_EN; - - return 0; -} - -ulong get_timer(ulong base) -{ - unsigned short now, diff; - volatile pit_t *timerp = (pit_t *) (CONFIG_SYS_PIT_BASE); - - now = timerp->pcntr; - diff = -(now - lastinc); - - timestamp += diff; - lastinc = now; - return timestamp - base; -} - -void wait_ticks(unsigned long ticks) -{ - u32 start = get_timer(0); - while (get_timer(start) < ticks) ; -} -#endif /* CONFIG_MCFPIT */ - /* * This function is derived from PowerPC code (read timebase as long long). * On M68K it just returns the timer value. diff --git a/board/freescale/m52277evb/README b/board/freescale/m52277evb/README index b7ceb5993e7a..76f4789335bf 100644 --- a/board/freescale/m52277evb/README +++ b/board/freescale/m52277evb/README @@ -79,7 +79,6 @@ RTC_DEBUG -- define to show RTC debug message CONFIG_CMD_DATE -- enable to use date feature in U-Boot CONFIG_MCFTMR -- define to use DMA timer -CONFIG_MCFPIT -- define to use PIT timer CONFIG_SYS_I2C_FSL -- define to use FSL common I2C driver CONFIG_SYS_I2C_SOFT -- define for I2C bit-banged diff --git a/board/freescale/m53017evb/README b/board/freescale/m53017evb/README index 2fca12c41706..a7074c9b7179 100644 --- a/board/freescale/m53017evb/README +++ b/board/freescale/m53017evb/README @@ -88,7 +88,6 @@ CONFIG_SYS_FEC0_MIIBASE -- Set FEC0 MII base register MCFFEC_TOUT_LOOP -- set FEC timeout loop CONFIG_MCFTMR -- define to use DMA timer -CONFIG_MCFPIT -- define to use PIT timer CONFIG_SYS_I2C_FSL -- define to use FSL common I2C driver CONFIG_SYS_I2C_SOFT -- define for I2C bit-banged diff --git a/board/freescale/m5373evb/README b/board/freescale/m5373evb/README index 757f0abdd744..f0a0631c94b3 100644 --- a/board/freescale/m5373evb/README +++ b/board/freescale/m5373evb/README @@ -87,7 +87,6 @@ CONFIG_SYS_FEC0_MIIBASE -- Set FEC0 MII base register MCFFEC_TOUT_LOOP -- set FEC timeout loop CONFIG_MCFTMR -- define to use DMA timer -CONFIG_MCFPIT -- define to use PIT timer CONFIG_SYS_I2C_FSL -- define to use FSL common I2C driver CONFIG_SYS_I2C_SOFT -- define for I2C bit-banged diff --git a/board/freescale/m54455evb/README b/board/freescale/m54455evb/README index 4a8719333ac5..260aec9f1bec 100644 --- a/board/freescale/m54455evb/README +++ b/board/freescale/m54455evb/README @@ -110,7 +110,6 @@ CONFIG_SYS_ATA_STRIDE -- define for Interval between registers _IO_BASE -- define for IO base address CONFIG_MCFTMR -- define to use DMA timer -CONFIG_MCFPIT -- define to use PIT timer CONFIG_SYS_FSL_I2C -- define to use FSL common I2C driver CONFIG_SYS_I2C_SOFT -- define for I2C bit-banged diff --git a/include/configs/M5208EVBE.h b/include/configs/M5208EVBE.h index 867ae8be6de9..92dad6ba6548 100644 --- a/include/configs/M5208EVBE.h +++ b/include/configs/M5208EVBE.h @@ -43,7 +43,6 @@ /* Timer */ #define CONFIG_MCFTMR -#undef CONFIG_MCFPIT /* I2C */ #define CONFIG_SYS_I2C diff --git a/include/configs/M52277EVB.h b/include/configs/M52277EVB.h index a5a1c38f6e7d..884ed11dbab9 100644 --- a/include/configs/M52277EVB.h +++ b/include/configs/M52277EVB.h @@ -90,7 +90,6 @@ /* Timer */ #define CONFIG_MCFTMR -#undef CONFIG_MCFPIT /* I2c */ #define CONFIG_SYS_I2C diff --git a/include/configs/M5235EVB.h b/include/configs/M5235EVB.h index 3c56cec425c4..360f7e242583 100644 --- a/include/configs/M5235EVB.h +++ b/include/configs/M5235EVB.h @@ -52,7 +52,6 @@ /* Timer */ #define CONFIG_MCFTMR -#undef CONFIG_MCFPIT /* I2C */ #define CONFIG_SYS_I2C diff --git a/include/configs/M53017EVB.h b/include/configs/M53017EVB.h index 24eb36159b30..ce3402ca0b3b 100644 --- a/include/configs/M53017EVB.h +++ b/include/configs/M53017EVB.h @@ -60,7 +60,6 @@ /* Timer */ #define CONFIG_MCFTMR -#undef CONFIG_MCFPIT /* I2C */ #define CONFIG_SYS_I2C diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h index 2cff0d6cf602..ba7ed13da550 100644 --- a/include/configs/M5329EVB.h +++ b/include/configs/M5329EVB.h @@ -52,7 +52,6 @@ /* Timer */ #define CONFIG_MCFTMR -#undef CONFIG_MCFPIT /* I2C */ #define CONFIG_SYS_I2C diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h index 576c075a174c..390bcf957e63 100644 --- a/include/configs/M5373EVB.h +++ b/include/configs/M5373EVB.h @@ -52,7 +52,6 @@ /* Timer */ #define CONFIG_MCFTMR -#undef CONFIG_MCFPIT /* I2C */ #define CONFIG_SYS_I2C diff --git a/include/configs/M54418TWR.h b/include/configs/M54418TWR.h index 72cc13ab79fc..2dbfb1d5ec44 100644 --- a/include/configs/M54418TWR.h +++ b/include/configs/M54418TWR.h @@ -137,7 +137,6 @@ /* Timer */ #define CONFIG_MCFTMR -#undef CONFIG_MCFPIT /* I2c */ #undef CONFIG_SYS_FSL_I2C diff --git a/include/configs/M54451EVB.h b/include/configs/M54451EVB.h index 5482edeb2d91..2473377edbd7 100644 --- a/include/configs/M54451EVB.h +++ b/include/configs/M54451EVB.h @@ -103,7 +103,6 @@ /* Timer */ #define CONFIG_MCFTMR -#undef CONFIG_MCFPIT /* I2c */ #define CONFIG_SYS_I2C diff --git a/include/configs/M54455EVB.h b/include/configs/M54455EVB.h index 9434cc278e2c..ea62d914b064 100644 --- a/include/configs/M54455EVB.h +++ b/include/configs/M54455EVB.h @@ -130,7 +130,6 @@ /* Timer */ #define CONFIG_MCFTMR -#undef CONFIG_MCFPIT /* I2c */ #define CONFIG_SYS_I2C diff --git a/include/configs/astro_mcf5373l.h b/include/configs/astro_mcf5373l.h index 3d79311d625f..e1128043b02a 100644 --- a/include/configs/astro_mcf5373l.h +++ b/include/configs/astro_mcf5373l.h @@ -57,7 +57,6 @@ /* Timer */ #define CONFIG_MCFTMR -#undef CONFIG_MCFPIT /* I2C */ #define CONFIG_SYS_I2C diff --git a/include/configs/stmark2.h b/include/configs/stmark2.h index a08d9950bd87..4f1e947d8631 100644 --- a/include/configs/stmark2.h +++ b/include/configs/stmark2.h @@ -60,7 +60,6 @@ /* Timer */ #define CONFIG_MCFTMR -#undef CONFIG_MCFPIT /* DSPI and Serial Flash */ #define CONFIG_CF_DSPI diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 284fb62e54c1..1da6bce9fd10 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -1092,7 +1092,6 @@ CONFIG_MAX_RAM_BANK_SIZE CONFIG_MCF5249 CONFIG_MCF5253 CONFIG_MCFFEC -CONFIG_MCFPIT CONFIG_MCFRTC CONFIG_MCFTMR CONFIG_MCLK_DIS -- 2.17.1

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[U-Boot] [PATCH] bootcount: add a DM i2c eeprom backing store for bootcount
by Robert Beckett 10 Jan '20

10 Jan '20

This driver allows the use of i2c eeprom device or partition as backing store for boot counter values with DM enabled. Signed-off-by: Robert Beckett <bob.beckett(a)collabora.com> --- drivers/bootcount/Kconfig | 10 ++++ drivers/bootcount/Makefile | 1 + drivers/bootcount/i2c-eeprom.c | 95 ++++++++++++++++++++++++++++++++++ 3 files changed, 106 insertions(+) create mode 100644 drivers/bootcount/i2c-eeprom.c diff --git a/drivers/bootcount/Kconfig b/drivers/bootcount/Kconfig index b7c29f2fd3..0e506c9ea2 100644 --- a/drivers/bootcount/Kconfig +++ b/drivers/bootcount/Kconfig @@ -96,6 +96,16 @@ config DM_BOOTCOUNT_RTC Accesses to the backing store are performed using the write16 and read16 ops of DM RTC devices. +config DM_BOOTCOUNT_I2C_EEPROM + bool "Support i2c eeprom devices as a backing store for bootcount" + depends on I2C_EEPROM + help + Enabled reading/writing the bootcount in a DM i2c eeprom device. + The wrapper device is to be specified with the compatible string + 'u-boot,bootcount-i2c-eeprom' and the 'i2c-eeprom'-property (a phandle + pointing to the underlying i2c eeprom device) and an optional 'offset' + property are supported. + endmenu endif diff --git a/drivers/bootcount/Makefile b/drivers/bootcount/Makefile index f9841d8615..73ccfb5a08 100644 --- a/drivers/bootcount/Makefile +++ b/drivers/bootcount/Makefile @@ -10,3 +10,4 @@ obj-$(CONFIG_BOOTCOUNT_EXT) += bootcount_ext.o obj-$(CONFIG_DM_BOOTCOUNT) += bootcount-uclass.o obj-$(CONFIG_DM_BOOTCOUNT_RTC) += rtc.o +obj-$(CONFIG_DM_BOOTCOUNT_I2C_EEPROM) += i2c-eeprom.o diff --git a/drivers/bootcount/i2c-eeprom.c b/drivers/bootcount/i2c-eeprom.c new file mode 100644 index 0000000000..ee760a2742 --- /dev/null +++ b/drivers/bootcount/i2c-eeprom.c @@ -0,0 +1,95 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2019 Collabora + * (C) Copyright 2019 GE + */ + +#include <common.h> +#include <bootcount.h> +#include <dm.h> +#include <i2c_eeprom.h> + +static const u8 bootcount_magic = 0xbc; + +struct bootcount_i2c_eeprom_priv { + struct udevice *i2c_eeprom; + u32 offset; +}; + +static int bootcount_i2c_eeprom_set(struct udevice *dev, const u32 a) +{ + struct bootcount_i2c_eeprom_priv *priv = dev_get_priv(dev); + const u16 val = bootcount_magic << 8 | (a & 0xff); + + if (i2c_eeprom_write(priv->i2c_eeprom, priv->offset, + (uint8_t *)&val, 2) < 0) { + debug("%s: write failed\n", __func__); + return -EIO; + } + + return 0; +} + +static int bootcount_i2c_eeprom_get(struct udevice *dev, u32 *a) +{ + struct bootcount_i2c_eeprom_priv *priv = dev_get_priv(dev); + u16 val; + + if (i2c_eeprom_read(priv->i2c_eeprom, priv->offset, + (uint8_t *)&val, 2) < 0) { + debug("%s: read failed\n", __func__); + return -EIO; + } + + if (val >> 8 == bootcount_magic) { + *a = val & 0xff; + return 0; + } + + debug("%s: bootcount magic does not match on %04x\n", __func__, val); + return -EIO; +} + +static int bootcount_i2c_eeprom_probe(struct udevice *dev) +{ + struct ofnode_phandle_args phandle_args; + struct bootcount_i2c_eeprom_priv *priv = dev_get_priv(dev); + struct udevice *i2c_eeprom; + + if (dev_read_phandle_with_args(dev, "i2c-eeprom", NULL, 0, 0, + &phandle_args)) { + debug("%s: i2c-eeprom backing device not specified\n", + dev->name); + return -ENOENT; + } + + if (uclass_get_device_by_ofnode(UCLASS_I2C_EEPROM, phandle_args.node, + &i2c_eeprom)) { + debug("%s: could not get backing device\n", dev->name); + return -ENODEV; + } + + priv->i2c_eeprom = i2c_eeprom; + priv->offset = dev_read_u32_default(dev, "offset", 0); + + return 0; +} + +static const struct bootcount_ops bootcount_i2c_eeprom_ops = { + .get = bootcount_i2c_eeprom_get, + .set = bootcount_i2c_eeprom_set, +}; + +static const struct udevice_id bootcount_i2c_eeprom_ids[] = { + { .compatible = "u-boot,bootcount-i2c-eeprom" }, + { } +}; + +U_BOOT_DRIVER(bootcount_spi_flash) = { + .name = "bootcount-i2c-eeprom", + .id = UCLASS_BOOTCOUNT, + .priv_auto_alloc_size = sizeof(struct bootcount_i2c_eeprom_priv), + .probe = bootcount_i2c_eeprom_probe, + .of_match = bootcount_i2c_eeprom_ids, + .ops = &bootcount_i2c_eeprom_ops, +}; -- 2.20.1

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[U-Boot] [PATCH 0/6] J721e HS device support
by Andrew F. Davis 10 Jan '20

10 Jan '20

Hello all, This series brings up High-Security (HS) device support on the J721e platform. Support for this K3 HS device is much like the existing AM65x HS and this series leverages much of that support. There are also a couple tangentially related fixups that I noticed while adding this support and testing. Although not strictly needed they do allow J721e HS to just work out-of-box by the time the last patch adds the defconfigs. Thanks, Andrew Andrew F. Davis (6): configs: j721e_evm.h: Sync J721e environment configuration with AM65x configs: ti: Factor out call to 'args_mmc' into MMC common environment arm: K3: Fix header comment match AM6 specific file function arm: K3: Disable ROM configured firewalls arm: K3: Increase default SYSFW image size allocation configs: Add configs for J721e High Security EVM arch/arm/mach-k3/Kconfig | 2 +- arch/arm/mach-k3/am6_init.c | 28 +++++++- arch/arm/mach-k3/common.c | 30 ++++++++ arch/arm/mach-k3/common.h | 7 ++ arch/arm/mach-k3/j721e_init.c | 52 ++++++++++++++ configs/j721e_hs_evm_a72_defconfig | 106 +++++++++++++++++++++++++++++ configs/j721e_hs_evm_r5_defconfig | 102 +++++++++++++++++++++++++++ include/configs/j721e_evm.h | 16 ++++- include/configs/ti_armv7_common.h | 1 - include/environment/ti/mmc.h | 5 +- 10 files changed, 341 insertions(+), 8 deletions(-) create mode 100644 configs/j721e_hs_evm_a72_defconfig create mode 100644 configs/j721e_hs_evm_r5_defconfig -- 2.17.1

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[PATCH 01/35] common: Drop mdm_init()
by Simon Glass 10 Jan '20

10 Jan '20

This is not used in U-Boot. Drop it. Signed-off-by: Simon Glass <sjg(a)chromium.org> --- include/common.h | 1 - 1 file changed, 1 deletion(-) diff --git a/include/common.h b/include/common.h index 8b37b58747..fecfa27747 100644 --- a/include/common.h +++ b/include/common.h @@ -71,7 +71,6 @@ int checkflash(void); int checkdram(void); extern u8 __dtb_dt_begin[]; /* embedded device tree blob */ extern u8 __dtb_dt_spl_begin[]; /* embedded device tree blob for SPL/TPL */ -int mdm_init(void); /** * arch_fixup_fdt() - Write arch-specific information to fdt -- 2.24.0.525.g8f36a354ae-goog

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[PATCH 00/20] Add i.MXRT family support
by Giulio Benetti 10 Jan '20

10 Jan '20

This patchset add support for i.MXRT family starting from i.MXRT1050 SoC. It provides: - i.MXRT1050 SoC entry - i.MXRT pinctrl driver - i.MXRT serial driver tweaking - i.MXRT sdram controller driver - i.MXRT usdhc driver tweaking - i.MXRT1050-evk initial support It uses all DM clocks all around and it loads correctly a basic Linux zImage. Giulio Benetti (20): armv7m: cache: add mmu_set_region_dcache_behaviour() stub for compatibility spl: fix entry_point equal to load_addr clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB clk: imx: pllv3: add enable() support clk: imx: pllv3: add disable() support clk: imx: pllv3: add set_rate() support clk: imx: pllv3: add PLLV3_SYS support clk: imx: pllv3: add support for PLLV3_AV type clk: imx: pfd: add set_rate() clk: imx: add i.IMXRT1050 clk driver pinctrl: add i.MXRT driver ARM: dts: imxrt1050: add dtsi file serial_lpuart: add clock enable if CONFIG_CLK is defined serial_lpuart: add support for i.MXRT ram: add SDRAM driver for i.MXRT SoCs mmc: fsl_esdhc: make if(CONFIG_IS_ENABLED(CLK)) an #if statement mmc: fsl_esdhc: add compatible for fsl, imxrt-usdhc imx: Add basic support for the NXP IMXRT10xx SoC family imx: imxrt1050-evk: Add support for the NXP i.MXRT1050-EVK arch/arm/Kconfig | 10 + arch/arm/Makefile | 4 +- arch/arm/cpu/armv7m/cache.c | 6 + arch/arm/dts/Makefile | 2 + arch/arm/dts/imxrt1050-evk.dts | 209 ++++ arch/arm/dts/imxrt1050.dtsi | 146 +++ arch/arm/include/asm/arch-imxrt/clock.h | 10 + arch/arm/include/asm/arch-imxrt/gpio.h | 19 + arch/arm/include/asm/arch-imxrt/imx-regs.h | 20 + arch/arm/include/asm/arch-imxrt/imxrt.h | 11 + arch/arm/include/asm/arch-imxrt/sys_proto.h | 11 + arch/arm/mach-imx/Makefile | 3 +- arch/arm/mach-imx/imxrt/Kconfig | 21 + arch/arm/mach-imx/imxrt/Makefile | 7 + arch/arm/mach-imx/imxrt/soc.c | 35 + board/freescale/imxrt1050-evk/Kconfig | 22 + board/freescale/imxrt1050-evk/MAINTAINERS | 6 + board/freescale/imxrt1050-evk/Makefile | 6 + board/freescale/imxrt1050-evk/README | 31 + board/freescale/imxrt1050-evk/imximage.cfg | 36 + board/freescale/imxrt1050-evk/imxrt1050-evk.c | 81 ++ common/spl/spl.c | 4 +- configs/imxrt1050-evk_defconfig | 74 ++ drivers/clk/imx/Kconfig | 16 + drivers/clk/imx/Makefile | 2 + drivers/clk/imx/clk-imxrt1050.c | 292 +++++ drivers/clk/imx/clk-pfd.c | 22 + drivers/clk/imx/clk-pllv3.c | 218 +++- drivers/mmc/Kconfig | 2 +- drivers/mmc/fsl_esdhc_imx.c | 41 +- drivers/pinctrl/nxp/Kconfig | 14 + drivers/pinctrl/nxp/Makefile | 1 + drivers/pinctrl/nxp/pinctrl-imxrt.c | 40 + drivers/ram/Kconfig | 8 + drivers/ram/Makefile | 2 + drivers/ram/imxrt_sdram.c | 439 ++++++++ drivers/serial/serial_lpuart.c | 28 +- include/configs/imxrt1050-evk.h | 59 ++ include/dt-bindings/clock/imxrt1050-clock.h | 65 ++ include/dt-bindings/memory/imxrt-sdram.h | 100 ++ include/dt-bindings/pinctrl/pins-imxrt1050.h | 993 ++++++++++++++++++ include/fsl_lpuart.h | 3 +- 42 files changed, 3083 insertions(+), 36 deletions(-) create mode 100644 arch/arm/dts/imxrt1050-evk.dts create mode 100644 arch/arm/dts/imxrt1050.dtsi create mode 100644 arch/arm/include/asm/arch-imxrt/clock.h create mode 100644 arch/arm/include/asm/arch-imxrt/gpio.h create mode 100644 arch/arm/include/asm/arch-imxrt/imx-regs.h create mode 100644 arch/arm/include/asm/arch-imxrt/imxrt.h create mode 100644 arch/arm/include/asm/arch-imxrt/sys_proto.h create mode 100644 arch/arm/mach-imx/imxrt/Kconfig create mode 100644 arch/arm/mach-imx/imxrt/Makefile create mode 100644 arch/arm/mach-imx/imxrt/soc.c create mode 100644 board/freescale/imxrt1050-evk/Kconfig create mode 100644 board/freescale/imxrt1050-evk/MAINTAINERS create mode 100644 board/freescale/imxrt1050-evk/Makefile create mode 100644 board/freescale/imxrt1050-evk/README create mode 100644 board/freescale/imxrt1050-evk/imximage.cfg create mode 100644 board/freescale/imxrt1050-evk/imxrt1050-evk.c create mode 100644 configs/imxrt1050-evk_defconfig create mode 100644 drivers/clk/imx/clk-imxrt1050.c create mode 100644 drivers/pinctrl/nxp/pinctrl-imxrt.c create mode 100644 drivers/ram/imxrt_sdram.c create mode 100644 include/configs/imxrt1050-evk.h create mode 100644 include/dt-bindings/clock/imxrt1050-clock.h create mode 100644 include/dt-bindings/memory/imxrt-sdram.h create mode 100644 include/dt-bindings/pinctrl/pins-imxrt1050.h -- 2.20.1

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