November 2019 - U-Boot

[U-Boot] [PATCH v1 0/5] regmap: Add a managed API, custom read/write callbacks and support for regmap fields
by Jean-Jacques Hiblot 04 Nov '19

04 Nov '19

This is the first of a few series, the goal of which is to facilitate porting drivers from the linux kernel. Most of the series will be about adding managed API to existing infrastructure (GPIO, reset, phy,...) This particular series is about regmaps. It adds the managed API, using the same API as linux. It also adds support for regmap fields and for custom read/write callbacks. Jean-Jacques Hiblot (5): regmap: Fix potential overflow in regmap_update_bits() regmap: Add devm_regmap_init() regmap: Allow providing read/write callbacks through struct regmap_config regmap: Add support for regmap fields test: dm: Add tests for regmap managed API and regmap fields arch/sandbox/dts/test.dts | 13 +++ drivers/core/regmap.c | 117 ++++++++++++++++++++++- include/regmap.h | 147 +++++++++++++++++++++++++++++ test/dm/regmap.c | 189 ++++++++++++++++++++++++++++++++++++++ 4 files changed, 465 insertions(+), 1 deletion(-) -- 2.17.1

2 11

[U-Boot] [PATCH 1/4] mx6: clock: Allow enable_ipu_clock() to be built for SPL code
by Fabio Estevam 04 Nov '19

04 Nov '19

Allow enable_ipu_clock() to be built for SPL code. This is done in preparation for configuring the NoC registers on i.MX6QP in SPL. Signed-off-by: Fabio Estevam <festevam(a)gmail.com> --- arch/arm/mach-imx/mx6/clock.c | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/arch/arm/mach-imx/mx6/clock.c b/arch/arm/mach-imx/mx6/clock.c index 366a4e3c6b..5af1ae7cf3 100644 --- a/arch/arm/mach-imx/mx6/clock.c +++ b/arch/arm/mach-imx/mx6/clock.c @@ -1275,6 +1275,22 @@ unsigned int mxc_get_clock(enum mxc_clock clk) return 0; } +#ifndef CONFIG_MX6SX +void enable_ipu_clock(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + int reg; + reg = readl(&mxc_ccm->CCGR3); + reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK; + writel(reg, &mxc_ccm->CCGR3); + + if (is_mx6dqp()) { + setbits_le32(&mxc_ccm->CCGR6, MXC_CCM_CCGR6_PRG_CLK0_MASK); + setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU2_IPU_MASK); + } +} +#endif + #ifndef CONFIG_SPL_BUILD /* * Dump some core clockes. @@ -1311,22 +1327,6 @@ int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 0; } -#ifndef CONFIG_MX6SX -void enable_ipu_clock(void) -{ - struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; - int reg; - reg = readl(&mxc_ccm->CCGR3); - reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK; - writel(reg, &mxc_ccm->CCGR3); - - if (is_mx6dqp()) { - setbits_le32(&mxc_ccm->CCGR6, MXC_CCM_CCGR6_PRG_CLK0_MASK); - setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU2_IPU_MASK); - } -} -#endif - #if defined(CONFIG_MX6Q) || defined(CONFIG_MX6D) || defined(CONFIG_MX6DL) || \ defined(CONFIG_MX6S) static void disable_ldb_di_clock_sources(void) -- 2.17.1

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[U-Boot] [PATCH] usb: composite: add BOS descriptor support to composite framework
by Michal Simek 04 Nov '19

04 Nov '19

From: T Karthik Reddy <t.karthik.reddy(a)xilinx.com> To add usb-3.0 support to peripheral device add BOS & SS capability descriptors to gadget composite framework. Signed-off-by: T Karthik Reddy <t.karthik.reddy(a)xilinx.com> Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu(a)xilinx.com> Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- drivers/usb/gadget/composite.c | 61 ++++++++++++++++++++++++++++++---- include/linux/usb/ch9.h | 3 ++ include/linux/usb/gadget.h | 9 +++++ 3 files changed, 67 insertions(+), 6 deletions(-) diff --git a/drivers/usb/gadget/composite.c b/drivers/usb/gadget/composite.c index c7e762374752..618a7d5016ee 100644 --- a/drivers/usb/gadget/composite.c +++ b/drivers/usb/gadget/composite.c @@ -688,6 +688,57 @@ static void composite_setup_complete(struct usb_ep *ep, struct usb_request *req) req->status, req->actual, req->length); } +static int bos_desc(struct usb_composite_dev *cdev) +{ + struct usb_ext_cap_descriptor *usb_ext; + struct usb_bos_descriptor *bos = cdev->req->buf; + + bos->bLength = USB_DT_BOS_SIZE; + bos->bDescriptorType = USB_DT_BOS; + + bos->wTotalLength = cpu_to_le16(USB_DT_BOS_SIZE); + bos->bNumDeviceCaps = 0; + + /* + * A SuperSpeed device shall include the USB2.0 extension descriptor + * and shall support LPM when operating in USB2.0 HS mode. + */ + usb_ext = cdev->req->buf + le16_to_cpu(bos->wTotalLength); + bos->bNumDeviceCaps++; + le16_add_cpu(&bos->wTotalLength, USB_DT_USB_EXT_CAP_SIZE); + usb_ext->bLength = USB_DT_USB_EXT_CAP_SIZE; + usb_ext->bDescriptorType = USB_DT_DEVICE_CAPABILITY; + usb_ext->bDevCapabilityType = USB_CAP_TYPE_EXT; + usb_ext->bmAttributes = + cpu_to_le32(USB_LPM_SUPPORT | USB_BESL_SUPPORT); + + /* + * The Superspeed USB Capability descriptor shall be implemented + * by all SuperSpeed devices. + */ + if (gadget_is_superspeed(cdev->gadget)) { + struct usb_ss_cap_descriptor *ss_cap; + + ss_cap = cdev->req->buf + le16_to_cpu(bos->wTotalLength); + bos->bNumDeviceCaps++; + le16_add_cpu(&bos->wTotalLength, USB_DT_USB_SS_CAP_SIZE); + ss_cap->bLength = USB_DT_USB_SS_CAP_SIZE; + ss_cap->bDescriptorType = USB_DT_DEVICE_CAPABILITY; + ss_cap->bDevCapabilityType = USB_SS_CAP_TYPE; + ss_cap->bmAttributes = 0; /* LTM is not supported yet */ + ss_cap->wSpeedSupported = + cpu_to_le16(USB_LOW_SPEED_OPERATION | + USB_FULL_SPEED_OPERATION | + USB_HIGH_SPEED_OPERATION | + USB_5GBPS_OPERATION); + ss_cap->bFunctionalitySupport = USB_LOW_SPEED_OPERATION; + ss_cap->bU1devExitLat = USB_DEFAULT_U1_DEV_EXIT_LAT; + ss_cap->bU2DevExitLat = + cpu_to_le16(USB_DEFAULT_U2_DEV_EXIT_LAT); + } + return le16_to_cpu(bos->wTotalLength); +} + /* * The setup() callback implements all the ep0 functionality that's * not handled lower down, in hardware or the hardware driver(like @@ -776,12 +827,10 @@ composite_setup(struct usb_gadget *gadget, const struct usb_ctrlrequest *ctrl) value = min(w_length, (u16) value); break; case USB_DT_BOS: - /* - * The USB compliance test (USB 2.0 Command Verifier) - * issues this request. We should not run into the - * default path here. But return for now until - * the superspeed support is added. - */ + if (gadget_is_superspeed(cdev->gadget)) + value = bos_desc(cdev); + if (value >= 0) + value = min(w_length, (u16)value); break; default: goto unknown; diff --git a/include/linux/usb/ch9.h b/include/linux/usb/ch9.h index 264c9712a33a..989a5fcbd966 100644 --- a/include/linux/usb/ch9.h +++ b/include/linux/usb/ch9.h @@ -878,6 +878,9 @@ struct usb_ss_cap_descriptor { /* Link Power Management */ __le16 bU2DevExitLat; } __attribute__((packed)); +#define USB_DEFAULT_U1_DEV_EXIT_LAT 0x01 /* Less then 1 microsec */ +#define USB_DEFAULT_U2_DEV_EXIT_LAT 0x01F4 /* Less then 500 microsec */ + #define USB_DT_USB_SS_CAP_SIZE 10 /* diff --git a/include/linux/usb/gadget.h b/include/linux/usb/gadget.h index 497798a32a87..58bfaddd036a 100644 --- a/include/linux/usb/gadget.h +++ b/include/linux/usb/gadget.h @@ -566,6 +566,15 @@ static inline int gadget_is_otg(struct usb_gadget *g) #endif } +/** + * gadget_is_superspeed() - return true if the hardware handles superspeed + * @g: controller that might support superspeed + */ +static inline int gadget_is_superspeed(struct usb_gadget *g) +{ + return g->max_speed >= USB_SPEED_SUPER; +} + /** * usb_gadget_frame_number - returns the current frame number * @gadget: controller that reports the frame number -- 2.17.1

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[U-Boot] [PATCH 0/7] mmc: fsl_esdhc: clean up and shrink the driver
by Yangbo Lu 04 Nov '19

04 Nov '19

This patch-set is to clean up and shrink the fsl_esdhc driver. Yangbo Lu (7): mmc: fsl_esdhc: drop controller initialization in fsl_esdhc_init() mmc: fsl_esdhc: fix voltage validation mmc: fsl_esdhc: clean up bus width configuration code mmc: fsl_esdhc: convert to use fsl_esdhc_get_cfg_common() mmc: fsl_esdhc: drop redundant code for non-removable feature mmc: fsl_esdhc: always check write protect state mmc: fsl_esdhc: clean up DM and non-DM code drivers/mmc/fsl_esdhc.c | 370 ++++++++++++++++-------------------------------- include/fsl_esdhc.h | 14 +- 2 files changed, 129 insertions(+), 255 deletions(-) -- 2.7.4

2 8

[U-Boot] [PATCH 1/2] mmc: fsl_esdhc_imx: drop redundant clock settings
by Peng Fan 04 Nov '19

04 Nov '19

During mmc initialization, there are several calls to mmc_set_clock and mmc_set_ios. When mmc_power_off, the mmc->clock will be set, but the imx driver will use 400KHz. So the following calls to mmc_set_ios will set the clock several times which is redundant in fsl_esdhc_imx driver. So let's simplify to remove redundant clock settings. Signed-off-by: Peng Fan <peng.fan(a)nxp.com> --- drivers/mmc/fsl_esdhc_imx.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c index 43106dec75..67549036d4 100644 --- a/drivers/mmc/fsl_esdhc_imx.c +++ b/drivers/mmc/fsl_esdhc_imx.c @@ -627,9 +627,6 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock) int sdhc_clk = priv->sdhc_clk; uint clk; - if (clock < mmc->cfg->f_min) - clock = mmc->cfg->f_min; - while (sdhc_clk / (16 * pre_div * ddr_pre_div) > clock && pre_div < 256) pre_div *= 2; @@ -958,6 +955,7 @@ static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc) { struct fsl_esdhc *regs = priv->esdhc_regs; int ret __maybe_unused; + u32 clock; #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK /* Select to use peripheral clock */ @@ -966,8 +964,12 @@ static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc) esdhc_clock_control(priv, true); #endif /* Set the clock speed */ - if (priv->clock != mmc->clock) - set_sysctl(priv, mmc, mmc->clock); + clock = mmc->clock; + if (clock < mmc->cfg->f_min) + clock = mmc->cfg->f_min; + + if (priv->clock != clock) + set_sysctl(priv, mmc, clock); #ifdef MMC_SUPPORTS_TUNING if (mmc->clk_disable) { -- 2.16.4

1 1

[U-Boot] [PATCH 0/2] imx watchdog updates
by Robert Hancock 04 Nov '19

04 Nov '19

Update the iMX watchdog driver functionality to more closely match the Linux driver by controlling the external reset bits according to the device tree settings, and using the immediate reset bits when told to expire now. Robert Hancock (2): watchdog: imx: Add DT ext-reset handling watchdog: imx: Use immediate reset bits for expire_now drivers/watchdog/imx_watchdog.c | 41 ++++++++++++++++++++++++++++------------- 1 file changed, 28 insertions(+), 13 deletions(-) -- 1.8.3.1

4 9

[U-Boot] [PATCH v3] board/BuR/brppt2: initial commit
by Hannes Schmelzer 04 Nov '19

04 Nov '19

This commit adds support for the brppt2 board. The board is based on the i.mx6 dual-lite SoC. Signed-off-by: Hannes Schmelzer <hannes.schmelzer(a)br-automation.com> --- Changes in v3: - rebase to current master Changes in v2: - fix SDPX tag in Make-files/rules arch/arm/dts/Makefile | 5 +- arch/arm/dts/imx6dl-brppt2.dts | 278 +++++++++++++++++++++ arch/arm/mach-imx/mx6/Kconfig | 19 ++ board/BuR/brppt2/Kconfig | 18 ++ board/BuR/brppt2/MAINTAINERS | 6 + board/BuR/brppt2/Makefile | 8 + board/BuR/brppt2/board.c | 542 +++++++++++++++++++++++++++++++++++++++++ board/BuR/brppt2/config.mk | 36 +++ configs/brppt2_defconfig | 92 +++++++ include/configs/brppt2.h | 125 ++++++++++ 10 files changed, 1128 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/imx6dl-brppt2.dts create mode 100644 board/BuR/brppt2/Kconfig create mode 100644 board/BuR/brppt2/MAINTAINERS create mode 100644 board/BuR/brppt2/Makefile create mode 100644 board/BuR/brppt2/board.c create mode 100644 board/BuR/brppt2/config.mk create mode 100644 configs/brppt2_defconfig create mode 100644 include/configs/brppt2.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 20dbc2f..dd4d091 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -564,7 +564,10 @@ dtb-$(CONFIG_MX6QDL) += \ imx6q-wandboard-revb1.dtb \ imx6qp-sabreauto.dtb \ imx6qp-sabresd.dtb \ - imx6qp-wandboard-revd1.dtb + imx6dl-brppt2.dtb + +dtb-$(CONFIG_TARGET_WANDBOARD) += \ + imx6dl-wandboard-revb1.dtb dtb-$(CONFIG_MX6SL) += imx6sl-evk.dtb diff --git a/arch/arm/dts/imx6dl-brppt2.dts b/arch/arm/dts/imx6dl-brppt2.dts new file mode 100644 index 0000000..4f1c52b --- /dev/null +++ b/arch/arm/dts/imx6dl-brppt2.dts @@ -0,0 +1,278 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 B&R Industrial Automation GmbH + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include "imx6dl.dtsi" +#include "imx6qdl-u-boot.dtsi" +#include <dt-bindings/pwm/pwm.h> +#include <include/dt-bindings/gpio/gpio.h> + +/ { + model = "PPT50"; + compatible = "fsl,imx6dl"; + + config { + u-boot,spl-payload-offset = <0x100000>; + }; + + fset: factory-settings { + bl-version = "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789"; + order-no = "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789"; + hw-revision = "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789"; + serial-no = <0>; + device-id = <0x0>; + parent-id = <0x0>; + hw-variant = <0x0>; + }; + + aliases { + ds1timing0 = &timing0; + ds1timing1 = &timing1; + ds1bkl = &backlight; + fset = &fset; + mxcfb0 = &mxcfb0; + touch0 = &touch0; + touch1 = &touch1; + touch2 = &touch2; + display_regulator = &display_regulator; + ldb = &ldb; + mmc0 = &usdhc4; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + mxcfb0: fb@0 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "ldb"; + interface_pix_fmt = "RGB24"; + default_bpp = <32>; + int_clk = <0>; + late_init = <0>; + rotation = <0>; + status = "okay"; + }; + + lcd@0 { + compatible = "fsl,lcd"; + vlcd-supply = <&display_regulator>; + ipu_id = <0>; + disp_id = <0>; + default_ifmt = "RGB24"; + status = "disabled"; + + display-timings { + native-mode = <&timing1>; + timing1: lcd { + }; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 5000000>; + brightness-levels = <0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100>; + default-brightness-level = <0>; + status = "okay"; + + enable-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; + }; + + beeper: pwm-beep { + compatible = "pwm-beeper"; + pwms = <&pwm3 0 0 0>; + }; + + vbus1_regulator: regulator@1 { + u-boot,dm-preloc; + compatible = "regulator-fixed"; + regulator-name = "vbus1_regulator"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + vbus2_regulator: regulator@2 { + compatible = "regulator-fixed"; + regulator-name = "vbus2_regulator"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + usbhub_regulator: gpio-regulator@3 { + compatible = "regulator-gpio"; + regulator-name = "ushbub_regulator"; + enable-gpio = <&gpio1 16 GPIO_ACTIVE_HIGH>; + enable-active-high; + enable-at-boot; + states = <0 0 1 1>; + }; + display_regulator: regulator@4 { + compatible = "regulator-fixed"; + regulator-name = "display_regulator"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio5 18 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <1000>; + }; +}; + +&fec { + phy-mode = "rgmii-id"; + status = "okay"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&uart1 { + u-boot,dm-spl; + u-boot,dm-preloc; + status = "okay"; +}; + +&pwm3 { + status = "okay"; +}; + +&pwm4 { + status = "okay"; +}; + +&ldb { + status = "disabled"; + vldb-supply = <&display_regulator>; + + lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <24>; + primary; + status = "okay"; + crtc = "ipu1-di0"; + + display-timings { + native-mode = <&timing0>; + timing0: lcd { + }; + }; + }; +}; + +&usdhc4 { + non-removable; + bus-width = <8>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <&vbus1_regulator>; + dr_mode = "host"; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <&vbus2_regulator>; + dr_mode = "host"; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <400000>; + status = "okay"; + + touch0: egalax_i2c@2a { + compatible = "eeti,egalax_i2c"; + reg = <0x2a>; + interrupt-parent = <&gpio4>; + interrupts = <9 2>; + int-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>; + }; + + touch1: gt911@5d { + compatible = "goodix,gt911"; + reg = <0x5d>; + interrupt-parent = <&gpio4>; + interrupts = <9 2>; + irq-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; + + touch2: i2c-hid-dev@2c { + compatible = "hid-over-i2c"; + reg = <0x2c>; + hid-descr-addr = <0x0001>; + interrupt-parent = <&gpio4>; + interrupts = <9 2>; + status = "disabled"; + }; +}; + +&gpio1 { + u-boot,dm-spl; + status = "okay"; +}; + +&gpio2 { + u-boot,dm-spl; + status = "okay"; +}; + +&gpio3 { + u-boot,dm-spl; + status = "okay"; +}; + +&gpio4 { + u-boot,dm-spl; + status = "okay"; +}; + +&usdhc4 { + status = "okay"; +}; + +&ecspi1 { + u-boot,dm-spl; + cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>, <&gpio3 19 GPIO_ACTIVE_LOW>; + status = "okay"; + spi-max-frequency = <25000000>; + + m25p32@1 { + u-boot,dm-spl; + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,m25p", "jedec,spi-nor"; + spi-max-frequency = <25000000>; + reg = <1>; + }; +}; diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index fe5991e..d829dbb 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -554,6 +554,24 @@ config TARGET_ZC5601 select SUPPORT_SPL imply CMD_DM +config TARGET_BRPPT2 + bool "brppt2" + select BOARD_LATE_INIT + select MX6QDL + select OF_CONTROL + select SPL_OF_LIBFDT + select DM + select DM_ETH + select DM_GPIO + select DM_I2C + select DM_MMC + select SUPPORT_SPL + select SPL_DM if SPL + select SPL_OF_CONTROL if SPL + help + Support + B&R BRPPT2 platform + based on Freescale's iMX6 SoC endchoice config SYS_SOC @@ -610,5 +628,6 @@ source "board/udoo/Kconfig" source "board/udoo/neo/Kconfig" source "board/wandboard/Kconfig" source "board/warp/Kconfig" +source "board/BuR/brppt2/Kconfig" endif diff --git a/board/BuR/brppt2/Kconfig b/board/BuR/brppt2/Kconfig new file mode 100644 index 0000000..aa39d66 --- /dev/null +++ b/board/BuR/brppt2/Kconfig @@ -0,0 +1,18 @@ +if TARGET_BRPPT2 + +config SYS_BOARD + default "brppt2" + +config SYS_VENDOR + default "BuR" + +config SYS_SOC + default "mx6" + +config SYS_CONFIG_NAME + default "brppt2" + +config SPL_DM_SPI + def_bool y + +endif diff --git a/board/BuR/brppt2/MAINTAINERS b/board/BuR/brppt2/MAINTAINERS new file mode 100644 index 0000000..a1b5bd4 --- /dev/null +++ b/board/BuR/brppt2/MAINTAINERS @@ -0,0 +1,6 @@ +BUR_PPT2 BOARD +M: Hannes Schmelzer <hannes.schmelzer(a)br-automation.com> +S: Maintained +F: board/BuR/brppt2/ +F: include/configs/brppt2.h +F: configs/brppt2_defconfig diff --git a/board/BuR/brppt2/Makefile b/board/BuR/brppt2/Makefile new file mode 100644 index 0000000..7f3c7cd --- /dev/null +++ b/board/BuR/brppt2/Makefile @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0+ + +# Copyright (C) 2019 +# B&R Industrial Automation GmbH - http://www.br-automation.com +# + +obj-y := ../common/common.o +obj-y += board.o diff --git a/board/BuR/brppt2/board.c b/board/BuR/brppt2/board.c new file mode 100644 index 0000000..3284ff0 --- /dev/null +++ b/board/BuR/brppt2/board.c @@ -0,0 +1,542 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Board functions for BuR BRPPT2 board + * + * Copyright (C) 2019 + * B&R Industrial Automation GmbH - http://www.br-automation.com/ + * + */ +#include <common.h> +#include <spl.h> +#include <dm.h> +#include <miiphy.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/iomux.h> +#include <asm/arch/mx6-pins.h> +#ifdef CONFIG_SPL_BUILD +# include <asm/arch/mx6-ddr.h> +#endif +#include <asm/arch/clock.h> +#include <asm/io.h> +#include <asm/gpio.h> + +#define USBHUB_RSTN IMX_GPIO_NR(1, 16) +#define BKLT_EN IMX_GPIO_NR(1, 15) +#define CAPT_INT IMX_GPIO_NR(4, 9) +#define CAPT_RESETN IMX_GPIO_NR(4, 11) +#define SW_INTN IMX_GPIO_NR(3, 26) +#define VCCDISP_EN IMX_GPIO_NR(5, 18) +#define EMMC_RSTN IMX_GPIO_NR(6, 8) +#define PMIC_IRQN IMX_GPIO_NR(5, 22) +#define TASTER IMX_GPIO_NR(5, 23) + +#define ETH0_LINK IMX_GPIO_NR(1, 27) +#define ETH1_LINK IMX_GPIO_NR(1, 28) + +#define UART_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_48ohm | \ + PAD_CTL_SRE_SLOW | PAD_CTL_HYS) + +#define I2C_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_48ohm | \ + PAD_CTL_SRE_SLOW | PAD_CTL_HYS) + +#define ECSPI_PAD_CTRL (PAD_CTL_PUS_100K_DOWN | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_48ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) +#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_48ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_60ohm | \ + PAD_CTL_SRE_SLOW | PAD_CTL_HYS) + +#define ENET_PAD_CTRL1 (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_34ohm | \ + PAD_CTL_SRE_SLOW | PAD_CTL_HYS) + +#define ENET_PAD_CTRL_PU (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_80ohm | \ + PAD_CTL_SRE_SLOW | PAD_CTL_HYS) + +#define ENET_PAD_CTRL_CLK ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_60ohm | \ + PAD_CTL_SRE_FAST) + +#define GPIO_PAD_CTRL_PU (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_48ohm | \ + PAD_CTL_SRE_SLOW | PAD_CTL_HYS) + +#define GPIO_PAD_CTRL_PD (PAD_CTL_PUS_100K_DOWN | \ + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_48ohm | \ + PAD_CTL_SRE_SLOW | PAD_CTL_HYS) + +#define LCDCMOS_PAD_CTRL (PAD_CTL_PUS_100K_DOWN | \ + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_120ohm |\ + PAD_CTL_SRE_SLOW | PAD_CTL_HYS) + +#define MUXDESC(pad, ctrl) IOMUX_PADS(pad | MUX_PAD_CTRL(ctrl)) + +#if !defined(CONFIG_SPL_BUILD) +static iomux_v3_cfg_t const eth_pads[] = { + /* + * Gigabit Ethernet + */ + /* CLKs */ + MUXDESC(PAD_GPIO_16__ENET_REF_CLK, ENET_PAD_CTRL_CLK), + MUXDESC(PAD_ENET_REF_CLK__ENET_TX_CLK, ENET_PAD_CTRL_CLK), + /* MDIO */ + MUXDESC(PAD_ENET_MDIO__ENET_MDIO, ENET_PAD_CTRL_PU), + MUXDESC(PAD_ENET_MDC__ENET_MDC, ENET_PAD_CTRL_PU), + /* RGMII */ + MUXDESC(PAD_RGMII_TXC__RGMII_TXC, ENET_PAD_CTRL1), + MUXDESC(PAD_RGMII_TD0__RGMII_TD0, ENET_PAD_CTRL), + MUXDESC(PAD_RGMII_TD1__RGMII_TD1, ENET_PAD_CTRL), + MUXDESC(PAD_RGMII_TD2__RGMII_TD2, ENET_PAD_CTRL), + MUXDESC(PAD_RGMII_TD3__RGMII_TD3, ENET_PAD_CTRL), + MUXDESC(PAD_RGMII_TX_CTL__RGMII_TX_CTL, ENET_PAD_CTRL), + MUXDESC(PAD_RGMII_RXC__RGMII_RXC, ENET_PAD_CTRL_PU), + MUXDESC(PAD_RGMII_RD0__RGMII_RD0, ENET_PAD_CTRL_PU), + MUXDESC(PAD_RGMII_RD1__RGMII_RD1, ENET_PAD_CTRL_PU), + MUXDESC(PAD_RGMII_RD2__RGMII_RD2, ENET_PAD_CTRL_PU), + MUXDESC(PAD_RGMII_RD3__RGMII_RD3, ENET_PAD_CTRL_PU), + MUXDESC(PAD_RGMII_RX_CTL__RGMII_RX_CTL, ENET_PAD_CTRL_PU), + /* ETH0_LINK */ + MUXDESC(PAD_ENET_RXD0__GPIO1_IO27, GPIO_PAD_CTRL_PD), + /* ETH1_LINK */ + MUXDESC(PAD_ENET_TX_EN__GPIO1_IO28, GPIO_PAD_CTRL_PD), +}; + +static iomux_v3_cfg_t const board_pads[] = { + /* + * I2C #3, #4 + */ + MUXDESC(PAD_GPIO_3__I2C3_SCL, I2C_PAD_CTRL), + MUXDESC(PAD_GPIO_6__I2C3_SDA, I2C_PAD_CTRL), + + /* + * UART#4 PADS + * UART_Tasten + */ + MUXDESC(PAD_CSI0_DAT12__UART4_TX_DATA, UART_PAD_CTRL), + MUXDESC(PAD_CSI0_DAT13__UART4_RX_DATA, UART_PAD_CTRL), + MUXDESC(PAD_CSI0_DAT17__UART4_CTS_B, UART_PAD_CTRL), + MUXDESC(PAD_CSI0_DAT16__UART4_RTS_B, UART_PAD_CTRL), + /* + * ESCPI#1 + * M25P32 NOR-Flash + */ + MUXDESC(PAD_EIM_D16__ECSPI1_SCLK, ECSPI_PAD_CTRL), + MUXDESC(PAD_EIM_D17__ECSPI1_MISO, ECSPI_PAD_CTRL), + MUXDESC(PAD_EIM_D18__ECSPI1_MOSI, ECSPI_PAD_CTRL), + MUXDESC(PAD_EIM_D19__GPIO3_IO19, ECSPI_PAD_CTRL), + /* + * ESCPI#2 + * resTouch SPI ADC + */ + MUXDESC(PAD_CSI0_DAT8__ECSPI2_SCLK, ECSPI_PAD_CTRL), + MUXDESC(PAD_EIM_OE__ECSPI2_MISO, ECSPI_PAD_CTRL), + MUXDESC(PAD_CSI0_DAT9__ECSPI2_MOSI, ECSPI_PAD_CTRL), + MUXDESC(PAD_EIM_D24__GPIO3_IO24, ECSPI_PAD_CTRL), + /* + * USDHC#4 + */ + MUXDESC(PAD_SD4_CLK__SD4_CLK, USDHC_PAD_CTRL), + MUXDESC(PAD_SD4_CMD__SD4_CMD, USDHC_PAD_CTRL), + MUXDESC(PAD_SD4_DAT0__SD4_DATA0, USDHC_PAD_CTRL), + MUXDESC(PAD_SD4_DAT1__SD4_DATA1, USDHC_PAD_CTRL), + MUXDESC(PAD_SD4_DAT2__SD4_DATA2, USDHC_PAD_CTRL), + MUXDESC(PAD_SD4_DAT3__SD4_DATA3, USDHC_PAD_CTRL), + MUXDESC(PAD_SD4_DAT4__SD4_DATA4, USDHC_PAD_CTRL), + MUXDESC(PAD_SD4_DAT5__SD4_DATA5, USDHC_PAD_CTRL), + MUXDESC(PAD_SD4_DAT6__SD4_DATA6, USDHC_PAD_CTRL), + MUXDESC(PAD_SD4_DAT7__SD4_DATA7, USDHC_PAD_CTRL), + /* + * USB OTG power & ID + */ + /* USB_OTG_5V_EN */ + MUXDESC(PAD_EIM_D22__GPIO3_IO22, GPIO_PAD_CTRL_PD), + MUXDESC(PAD_EIM_D31__GPIO3_IO31, GPIO_PAD_CTRL_PD), + /* USB_OTG_JUMPER */ + MUXDESC(PAD_ENET_RX_ER__USB_OTG_ID, GPIO_PAD_CTRL_PD), + /* + * PWM-Pins + */ + /* BKLT_CTL */ + MUXDESC(PAD_SD1_CMD__PWM4_OUT, GPIO_PAD_CTRL_PD), + /* SPEAKER */ + MUXDESC(PAD_SD1_DAT1__PWM3_OUT, GPIO_PAD_CTRL_PD), + /* + * GPIOs + */ + /* USB_HUB_nRESET */ + MUXDESC(PAD_SD1_DAT0__GPIO1_IO16, GPIO_PAD_CTRL_PD), + /* BKLT_EN */ + MUXDESC(PAD_SD2_DAT0__GPIO1_IO15, GPIO_PAD_CTRL_PD), + /* capTouch_INT */ + MUXDESC(PAD_KEY_ROW1__GPIO4_IO09, GPIO_PAD_CTRL_PD), + /* capTouch_nRESET */ + MUXDESC(PAD_KEY_ROW2__GPIO4_IO11, GPIO_PAD_CTRL_PD), + /* SW_nINT */ + MUXDESC(PAD_EIM_D26__GPIO3_IO26, GPIO_PAD_CTRL_PU), + /* VCC_DISP_EN */ + MUXDESC(PAD_CSI0_PIXCLK__GPIO5_IO18, GPIO_PAD_CTRL_PD), + /* eMMC_nRESET */ + MUXDESC(PAD_NANDF_ALE__GPIO6_IO08, GPIO_PAD_CTRL_PD), + /* HWID*/ + MUXDESC(PAD_NANDF_D0__GPIO2_IO00, GPIO_PAD_CTRL_PU), + MUXDESC(PAD_NANDF_D1__GPIO2_IO01, GPIO_PAD_CTRL_PU), + MUXDESC(PAD_NANDF_D2__GPIO2_IO02, GPIO_PAD_CTRL_PU), + MUXDESC(PAD_NANDF_D3__GPIO2_IO03, GPIO_PAD_CTRL_PU), + /* PMIC_nIRQ */ + MUXDESC(PAD_CSI0_DAT4__GPIO5_IO22, GPIO_PAD_CTRL_PU), + /* nTASTER */ + MUXDESC(PAD_CSI0_DAT5__GPIO5_IO23, GPIO_PAD_CTRL_PU), + /* RGB LCD Display */ + MUXDESC(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, LCDCMOS_PAD_CTRL), + MUXDESC(PAD_DI0_PIN2__IPU1_DI0_PIN02, LCDCMOS_PAD_CTRL), + MUXDESC(PAD_DI0_PIN3__IPU1_DI0_PIN03, LCDCMOS_PAD_CTRL), + MUXDESC(PAD_DI0_PIN4__IPU1_DI0_PIN04, LCDCMOS_PAD_CTRL), + MUXDESC(PAD_DI0_PIN15__IPU1_DI0_PIN15, LCDCMOS_PAD_CTRL), + MUXDESC(PAD_DISP0_DAT0__IPU1_DISP0_DATA00, LCDCMOS_PAD_CTRL), + MUXDESC(PAD_DISP0_DAT1__IPU1_DISP0_DATA01, LCDCMOS_PAD_CTRL), + MUXDESC(PAD_DISP0_DAT2__IPU1_DISP0_DATA02, LCDCMOS_PAD_CTRL), + MUXDESC(PAD_DISP0_DAT3__IPU1_DISP0_DATA03, LCDCMOS_PAD_CTRL), + MUXDESC(PAD_DISP0_DAT4__IPU1_DISP0_DATA04, LCDCMOS_PAD_CTRL), + MUXDESC(PAD_DISP0_DAT5__IPU1_DISP0_DATA05, LCDCMOS_PAD_CTRL), + MUXDESC(PAD_DISP0_DAT6__IPU1_DISP0_DATA06, LCDCMOS_PAD_CTRL), + MUXDESC(PAD_DISP0_DAT7__IPU1_DISP0_DATA07, LCDCMOS_PAD_CTRL), + MUXDESC(PAD_DISP0_DAT8__IPU1_DISP0_DATA08, LCDCMOS_PAD_CTRL), + MUXDESC(PAD_DISP0_DAT9__IPU1_DISP0_DATA09, LCDCMOS_PAD_CTRL), + MUXDESC(PAD_DISP0_DAT10__IPU1_DISP0_DATA10, LCDCMOS_PAD_CTRL), + MUXDESC(PAD_DISP0_DAT11__IPU1_DISP0_DATA11, LCDCMOS_PAD_CTRL), + MUXDESC(PAD_DISP0_DAT12__IPU1_DISP0_DATA12, LCDCMOS_PAD_CTRL), + MUXDESC(PAD_DISP0_DAT13__IPU1_DISP0_DATA13, LCDCMOS_PAD_CTRL), + MUXDESC(PAD_DISP0_DAT14__IPU1_DISP0_DATA14, LCDCMOS_PAD_CTRL), + MUXDESC(PAD_DISP0_DAT15__IPU1_DISP0_DATA15, LCDCMOS_PAD_CTRL), + MUXDESC(PAD_DISP0_DAT16__IPU1_DISP0_DATA16, LCDCMOS_PAD_CTRL), + MUXDESC(PAD_DISP0_DAT17__IPU1_DISP0_DATA17, LCDCMOS_PAD_CTRL), + MUXDESC(PAD_DISP0_DAT18__IPU1_DISP0_DATA18, LCDCMOS_PAD_CTRL), + MUXDESC(PAD_DISP0_DAT19__IPU1_DISP0_DATA19, LCDCMOS_PAD_CTRL), + MUXDESC(PAD_DISP0_DAT20__IPU1_DISP0_DATA20, LCDCMOS_PAD_CTRL), + MUXDESC(PAD_DISP0_DAT21__IPU1_DISP0_DATA21, LCDCMOS_PAD_CTRL), + MUXDESC(PAD_DISP0_DAT22__IPU1_DISP0_DATA22, LCDCMOS_PAD_CTRL), + MUXDESC(PAD_DISP0_DAT23__IPU1_DISP0_DATA23, LCDCMOS_PAD_CTRL), +}; + +int board_ehci_hcd_init(int port) +{ + gpio_direction_output(USBHUB_RSTN, 1); + + return 0; +} + +int board_late_init(void) +{ + ulong b_mode = 4; + + if (gpio_get_value(TASTER) == 0) + b_mode = 12; + + env_set_ulong("b_mode", b_mode); + + return 0; +} + +int board_init(void) +{ + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + + if (gpio_request(BKLT_EN, "BKLT_EN")) + printf("Warning: BKLT_EN setup failed\n"); + gpio_direction_output(BKLT_EN, 0); + + if (gpio_request(USBHUB_RSTN, "USBHUB_nRST")) + printf("Warning: USBHUB_nRST setup failed\n"); + gpio_direction_output(USBHUB_RSTN, 0); + + if (gpio_request(TASTER, "TASTER")) + printf("Warning: TASTER setup failed\n"); + gpio_direction_input(TASTER); + + return 0; +} + +int board_early_init_f(void) +{ + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + + SETUP_IOMUX_PADS(board_pads); + SETUP_IOMUX_PADS(eth_pads); + + /* set GPIO_16 as ENET_REF_CLK_OUT running at 25 MHz */ + setbits_le32(&iomux->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK); + enable_fec_anatop_clock(0, ENET_25MHZ); + enable_enet_clk(1); + + return 0; +} + +int dram_init(void) +{ + gd->ram_size = imx_ddr_size(); + + return 0; +} +#else +/* configure MX6SOLO/DUALLITE mmdc DDR io registers */ +static struct mx6sdl_iomux_ddr_regs ddr_iomux_s = { + /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */ + .dram_sdclk_0 = 0x00020030, + .dram_sdclk_1 = 0x00020030, + .dram_cas = 0x00020030, + .dram_ras = 0x00020030, + .dram_reset = 0x00020030, + /* SDCKE[0:1]: 100k pull-up */ + .dram_sdcke0 = 0x00003000, + .dram_sdcke1 = 0x00003000, + /* SDBA2: pull-up disabled */ + .dram_sdba2 = 0x00000000, + /* SDODT[0:1]: 100k pull-up, 40 ohm */ + .dram_sdodt0 = 0x00003030, + .dram_sdodt1 = 0x00003030, + /* SDQS[0:7]: Differential input, 40 ohm */ + .dram_sdqs0 = 0x00000030, + .dram_sdqs1 = 0x00000030, + .dram_sdqs2 = 0x00000030, + .dram_sdqs3 = 0x00000030, + .dram_sdqs4 = 0x00000030, + .dram_sdqs5 = 0x00000030, + .dram_sdqs6 = 0x00000030, + .dram_sdqs7 = 0x00000030, + /* DQM[0:7]: Differential input, 40 ohm */ + .dram_dqm0 = 0x00020030, + .dram_dqm1 = 0x00020030, + .dram_dqm2 = 0x00020030, + .dram_dqm3 = 0x00020030, + .dram_dqm4 = 0x00020030, + .dram_dqm5 = 0x00020030, + .dram_dqm6 = 0x00020030, + .dram_dqm7 = 0x00020030, +}; + +/* configure MX6SOLO/DUALLITE mmdc GRP io registers */ +static struct mx6sdl_iomux_grp_regs grp_iomux_s = { + /* DDR3 */ + .grp_ddr_type = 0x000c0000, + .grp_ddrmode_ctl = 0x00020000, + /* disable DDR pullups */ + .grp_ddrpke = 0x00000000, + /* ADDR[00:16], SDBA[0:1]: 40 ohm */ + .grp_addds = 0x00000030, + /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */ + .grp_ctlds = 0x00000030, + /* DATA[00:63]: Differential input, 40 ohm */ + .grp_ddrmode = 0x00020000, + .grp_b0ds = 0x00000030, + .grp_b1ds = 0x00000030, + .grp_b2ds = 0x00000030, + .grp_b3ds = 0x00000030, + .grp_b4ds = 0x00000030, + .grp_b5ds = 0x00000030, + .grp_b6ds = 0x00000030, + .grp_b7ds = 0x00000030, +}; + +/* + * DDR3 desriptions - these are the memory chips we support + */ + +/* NT5CC128M16FP-DII */ +static struct mx6_ddr3_cfg cfg_nt5cc128m16fp_dii = { + .mem_speed = 1600, + .density = 2, + .width = 16, + .banks = 8, + .rowaddr = 14, + .coladdr = 10, + .pagesz = 2, + .trcd = 1375, + .trcmin = 4875, + .trasmin = 3500, +}; + +/* measured on board TSERIES_ARM/1 V_LVDS_DL64 */ +static struct mx6_mmdc_calibration cal_nt5cc128m16fp_dii_128x64_s = { + /* write leveling calibration determine, MR1-value = 0x0002 */ + .p0_mpwldectrl0 = 0x003F003E, + .p0_mpwldectrl1 = 0x003A003A, + .p1_mpwldectrl0 = 0x001B001C, + .p1_mpwldectrl1 = 0x00190031, + /* Read DQS Gating calibration */ + .p0_mpdgctrl0 = 0x02640264, + .p0_mpdgctrl1 = 0x02440250, + .p1_mpdgctrl0 = 0x02400250, + .p1_mpdgctrl1 = 0x0238023C, + /* Read Calibration: DQS delay relative to DQ read access */ + .p0_mprddlctl = 0x40464644, + .p1_mprddlctl = 0x464A4842, + /* Write Calibration: DQ/DM delay relative to DQS write access */ + .p0_mpwrdlctl = 0x38343034, + .p1_mpwrdlctl = 0x36323830, +}; + +/* measured on board TSERIES_ARM/1 V_LVDS_S32 */ +static struct mx6_mmdc_calibration cal_nt5cc128m16fp_dii_128x32_s = { + /* write leveling calibration determine, MR1-value = 0x0002 */ + .p0_mpwldectrl0 = 0x00410043, + .p0_mpwldectrl1 = 0x003A003C, + /* Read DQS Gating calibration */ + .p0_mpdgctrl0 = 0x023C0244, + .p0_mpdgctrl1 = 0x02240230, + /* Read Calibration: DQS delay relative to DQ read access */ + .p0_mprddlctl = 0x484C4A48, + /* Write Calibration: DQ/DM delay relative to DQS write access */ + .p0_mpwrdlctl = 0x3C363434, +}; + +static void spl_dram_init(void) +{ + struct gpio_regs *gpio = (struct gpio_regs *)GPIO2_BASE_ADDR; + u32 val, dram_strap = 0; + struct mx6_ddr3_cfg *mem = NULL; + struct mx6_mmdc_calibration *calib = NULL; + struct mx6_ddr_sysinfo sysinfo = { + /* width of data bus:0=16,1=32,2=64 */ + .dsize = -1, /* CPU type specific (overwritten) */ + /* config for full 4GB range so that get_mem_size() works */ + .cs_density = 32, /* 32Gb per CS */ + .ncs = 1, /* single chip select */ + .cs1_mirror = 0, + .rtt_wr = 1, /* DDR3_RTT_60_OHM, RTT_Wr = RZQ/4 */ + .rtt_nom = 1, /* DDR3_RTT_60_OHM, RTT_Nom = RZQ/4 */ + .walat = 1, /* Write additional latency */ + .ralat = 5, /* Read additional latency */ + .mif3_mode = 3, /* Command prediction working mode */ + .bi_on = 1, /* Bank interleaving enabled */ + .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ + .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ + .ddr_type = 0, /* DDR3 */ + }; + + /* + * MMDC Calibration requires the following data: + * mx6_mmdc_calibration - board-specific calibration (routing delays) + * these calibration values depend on board routing, SoC, and DDR + * mx6_ddr_sysinfo - board-specific memory architecture (width/cs/etc) + * mx6_ddr_cfg - chip specific timing/layout details + */ + + /* setup HWID3-2 to input */ + val = readl(&gpio->gpio_dir); + val &= ~(0x1 << 0 | 0x1 << 1); + writel(val, &gpio->gpio_dir); + + /* read DRAM strapping from HWID3/2 (bit 1 and bit 0) */ + dram_strap = readl(&gpio->gpio_psr) & 0x3; + + switch (dram_strap) { + /* 1 GiB, 64 bit, 4 NT5CC128M16FP chips */ + case 0: + puts("DRAM strap 00\n"); + mem = &cfg_nt5cc128m16fp_dii; + sysinfo.dsize = 2; + calib = &cal_nt5cc128m16fp_dii_128x64_s; + break; + /* 512 MiB, 32 bit, 2 NT5CC128M16FP chips */ + case 1: + puts("DRAM strap 01\n"); + mem = &cfg_nt5cc128m16fp_dii; + sysinfo.dsize = 1; + calib = &cal_nt5cc128m16fp_dii_128x32_s; + break; + default: + printf("DRAM strap 0x%x (invalid)\n", dram_strap); + break; + } + + if (!mem) { + puts("Error: Invalid Memory Configuration\n"); + hang(); + } + if (!calib) { + puts("Error: Invalid Board Calibration Configuration\n"); + hang(); + } + + mx6sdl_dram_iocfg(16 << sysinfo.dsize, + &ddr_iomux_s, + &grp_iomux_s); + + mx6_dram_cfg(&sysinfo, calib, mem); +} + +static iomux_v3_cfg_t const board_pads_spl[] = { + /* UART#1 PADS */ + MUXDESC(PAD_CSI0_DAT10__UART1_TX_DATA, UART_PAD_CTRL), + MUXDESC(PAD_CSI0_DAT11__UART1_RX_DATA, UART_PAD_CTRL), + /* ESCPI#1 PADS */ + MUXDESC(PAD_EIM_D16__ECSPI1_SCLK, ECSPI_PAD_CTRL), + MUXDESC(PAD_EIM_D17__ECSPI1_MISO, ECSPI_PAD_CTRL), + MUXDESC(PAD_EIM_D18__ECSPI1_MOSI, ECSPI_PAD_CTRL), + MUXDESC(PAD_EIM_D19__GPIO3_IO19, ECSPI_PAD_CTRL), + /* USDHC#4 PADS */ + MUXDESC(PAD_SD4_CLK__SD4_CLK, USDHC_PAD_CTRL), + MUXDESC(PAD_SD4_CMD__SD4_CMD, USDHC_PAD_CTRL), + MUXDESC(PAD_SD4_DAT0__SD4_DATA0, USDHC_PAD_CTRL), + MUXDESC(PAD_SD4_DAT1__SD4_DATA1, USDHC_PAD_CTRL), + MUXDESC(PAD_SD4_DAT2__SD4_DATA2, USDHC_PAD_CTRL), + MUXDESC(PAD_SD4_DAT3__SD4_DATA3, USDHC_PAD_CTRL), + MUXDESC(PAD_SD4_DAT4__SD4_DATA4, USDHC_PAD_CTRL), + MUXDESC(PAD_SD4_DAT5__SD4_DATA5, USDHC_PAD_CTRL), + MUXDESC(PAD_SD4_DAT6__SD4_DATA6, USDHC_PAD_CTRL), + MUXDESC(PAD_SD4_DAT7__SD4_DATA7, USDHC_PAD_CTRL), + /* HWID*/ + MUXDESC(PAD_NANDF_D0__GPIO2_IO00, GPIO_PAD_CTRL_PU), + MUXDESC(PAD_NANDF_D1__GPIO2_IO01, GPIO_PAD_CTRL_PU), + MUXDESC(PAD_NANDF_D2__GPIO2_IO02, GPIO_PAD_CTRL_PU), + MUXDESC(PAD_NANDF_D3__GPIO2_IO03, GPIO_PAD_CTRL_PU), +}; + +void spl_board_init(void) +{ + preloader_console_init(); +} + +static void ccgr_init(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + /* + * We don't use DMA in SPL, but we do need it in U-Boot. U-Boot + * initializes DMA very early (before all board code), so the only + * opportunity we have to initialize APBHDMA clocks is in SPL. + * setbits_le32(&ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); + */ + + writel(0x00C03F3F, &ccm->CCGR0); + writel(0x00F0FC03, &ccm->CCGR1); + writel(0x0FFFF000, &ccm->CCGR2); + writel(0x3FF00000, &ccm->CCGR3); + writel(0x00FFF300, &ccm->CCGR4); + writel(0x0F0030C3, &ccm->CCGR5); + writel(0x000003F0, &ccm->CCGR6); +} + +void board_init_f(ulong dummy) +{ + ccgr_init(); + arch_cpu_init(); + timer_init(); + gpr_init(); + + SETUP_IOMUX_PADS(board_pads_spl); + spl_dram_init(); +} + +void reset_cpu(ulong addr) +{ +} +#endif /* CONFIG_SPL_BUILD */ diff --git a/board/BuR/brppt2/config.mk b/board/BuR/brppt2/config.mk new file mode 100644 index 0000000..fa973db --- /dev/null +++ b/board/BuR/brppt2/config.mk @@ -0,0 +1,36 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2019 Hannes Schmelzer <oe5hpm(a)oevsv.at> - +# B&R Industrial Automation GmbH - http://www.br-automation.com +# + +hw-platform-y :=$(shell echo $(CONFIG_DEFAULT_DEVICE_TREE) | sed -e 's/imx6dl-//') + +payload_off :=$(shell printf "%d" $(CONFIG_SYS_SPI_U_BOOT_OFFS)) + +quiet_cmd_prodbin = PRODBIN $@ $(payload_off) +cmd_prodbin = \ + dd if=/dev/zero ibs=1M count=2 2>/dev/null | tr "\000" "\377" >$@ && \ + dd conv=notrunc bs=1 if=SPL of=$@ seek=1024 2>/dev/null && \ + dd bs=1 if=u-boot-dtb.img of=$@ seek=$(payload_off) 2>/dev/null + +quiet_cmd_prodzip = SAPZIP $@ +cmd_prodzip = \ + test -d misc && rm -r misc; \ + mkdir misc && \ + cp SPL misc/ && \ + cp u-boot-dtb.img misc/ && \ + zip -9 -r $@ misc/* >/dev/null $< + +ifeq ($(hw-platform-y),brppt2) +ifneq ($(CONFIG_SPL_BUILD),y) +ALL-y += $(hw-platform-y)_prog.bin +ALL-y += $(hw-platform-y)_prod.zip +endif +endif + +$(hw-platform-y)_prog.bin: u-boot-dtb.img spl SPL + $(call if_changed,prodbin) + +$(hw-platform-y)_prod.zip: $(hw-platform-y)_prog.bin + $(call if_changed,prodzip) diff --git a/configs/brppt2_defconfig b/configs/brppt2_defconfig new file mode 100644 index 0000000..f426317 --- /dev/null +++ b/configs/brppt2_defconfig @@ -0,0 +1,92 @@ +CONFIG_ARM=y +# CONFIG_SPL_SYS_THUMB_BUILD is not set +CONFIG_SYS_L2CACHE_OFF=y +CONFIG_ARCH_MX6=y +CONFIG_SPL_LDSCRIPT="arch/$(ARCH)/cpu/u-boot-spl.lds" +CONFIG_SYS_TEXT_BASE=0x17800000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x1000 +CONFIG_TARGET_BRPPT2=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +# CONFIG_CMD_BMODE is not set +CONFIG_DEFAULT_DEVICE_TREE="imx6dl-brppt2" +CONFIG_NR_DRAM_BANKS=1 +CONFIG_TPL_SYS_MALLOC_F_LEN=0x0 +# CONFIG_EXPERT is not set +CONFIG_OF_BOARD_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" +CONFIG_SPI_BOOT=y +CONFIG_BOOTDELAY=0 +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="run b_default" +CONFIG_VERSION_VARIABLE=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_ENV_EXISTS is not set +CONFIG_CMD_MEMINFO=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +# CONFIG_CMD_NFS is not set +CONFIG_CMD_MII=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clocks clock-names interrupt-parent interrupts dmas dma-names" +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_NET_RANDOM_ETHADDR=y +# CONFIG_DM_DEVICE_REMOVE is not set +CONFIG_SPL_DM_SEQ_ALIAS=y +# CONFIG_OF_TRANSLATE is not set +# CONFIG_SPL_BLK is not set +CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y +CONFIG_SYS_BOOTCOUNT_ADDR=0x020CC068 +CONFIG_SYS_I2C_MXC=y +CONFIG_MMC_BROKEN_CD=y +# CONFIG_SPL_DM_MMC is not set +CONFIG_FSL_ESDHC=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_PHYLIB=y +CONFIG_PHY_FIXED=y +CONFIG_FEC_MXC=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +# CONFIG_REQUIRE_SERIAL_CONSOLE is not set +CONFIG_DM_SERIAL=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_MXC_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_SPL_TINY_MEMSET=y +# CONFIG_EFI_LOADER is not set diff --git a/include/configs/brppt2.h b/include/configs/brppt2.h new file mode 100644 index 0000000..7849ca2 --- /dev/null +++ b/include/configs/brppt2.h @@ -0,0 +1,125 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Config file for BuR BRPP2_IMX6 board + * + * Copyright (C) 2018 + * B&R Industrial Automation GmbH - http://www.br-automation.com/ + */ +#ifndef __CONFIG_BRPP2_IMX6_H +#define __CONFIG_BRPP2_IMX6_H + +#include <configs/bur_cfg_common.h> +#include <asm/arch/imx-regs.h> + +/* -- i.mx6 specifica -- */ +#ifndef CONFIG_SYS_L2CACHE_OFF +#define CONFIG_SYS_L2_PL310 +#define CONFIG_SYS_PL310_BASE L2_PL310_BASE +#endif /* !CONFIG_SYS_L2CACHE_OFF */ + +#define CONFIG_BOARD_POSTCLK_INIT +#define CONFIG_MXC_GPT_HCLK + +#define CONFIG_LOADADDR 0x10700000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* MMC */ +#define CONFIG_FSL_USDHC + +/* Boot */ +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_MACH_TYPE 0xFFFFFFFF + +/* misc */ +#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) + +/* Environment */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_ENV_SECT_SIZE 0x10000 +#define CONFIG_ENV_SIZE 0x10000 +#define CONFIG_ENV_OFFSET 0x20000 + +#define CONFIG_EXTRA_ENV_SETTINGS \ +BUR_COMMON_ENV \ +"autoload=0\0" \ +"cfgaddr=0x106F0000\0" \ +"scraddr=0x10700000\0" \ +"loadaddr=0x10800000\0" \ +"dtbaddr=0x12000000\0" \ +"ramaddr=0x12100000\0" \ +"cfgscr=mw ${loadaddr} 0 128\0" \ +"cfgscrl=fdt addr ${dtbaddr} &&"\ +" sf probe; sf read ${cfgaddr} 0x40000 0x10000 && source ${cfgaddr}\0" \ +"console=ttymxc0,115200n8 consoleblank=0 quiet\0" \ +"t50args#0=setenv bootargs b_mode=${b_mode} console=${console} " \ + " root=/dev/mmcblk0p2 rootfstype=ext4 rootwait panic=2 \0" \ +"b_t50lgcy#0=" \ + "load ${loaddev}:2 ${loadaddr} /boot/zImage && " \ + "load ${loaddev}:2 ${dtbaddr} /boot/imx6dl-brppt50.dtb; " \ + "run t50args#0; run cfgscrl; bootz ${loadaddr} - ${dtbaddr}\0" \ +"t50args#1=setenv bootargs console=${console} b_mode=${b_mode}" \ + " rootwait panic=2\0" \ +"b_t50lgcy#1=" \ + "load ${loaddev}:1 ${loadaddr} zImage && " \ + "load ${loaddev}:1 ${dtbaddr} imx6dl-brppt50.dtb && " \ + "load ${loaddev}:1 ${ramaddr} rootfsPPT50.uboot && " \ + "run t50args#1; run cfgscrl; bootz ${loadaddr} ${ramaddr} ${dtbaddr}\0"\ +"b_mmc0=load ${loaddev}:1 ${scraddr} bootscr.img && source ${scraddr}\0" \ +"b_mmc1=load ${loaddev}:1 ${scraddr} /boot/bootscr.img && source ${scraddr}\0" \ +"b_usb0=usb start && load usb 0 ${scraddr} bootscr.img && source ${scraddr}\0" \ +"b_net=tftp ${scraddr} netscript.img && source ${scraddr}\0" \ +"b_tgts_std=mmc0 mmc1 t50lgcy#0 t50lgcy#1 usb0 net\0" \ +"b_tgts_rcy=t50lgcy#1 usb0 net\0" \ +"b_tgts_pme=net usb0 mmc0 mmc1\0" \ +"b_mode=4\0" \ +"b_break=0\0" \ +"b_deftgts=if test ${b_mode} = 12; then setenv b_tgts ${b_tgts_pme};" \ +" elif test ${b_mode} = 0; then setenv b_tgts ${b_tgts_rcy};" \ +" else setenv b_tgts ${b_tgts_std}; fi\0" \ +"b_default=run b_deftgts; for target in ${b_tgts};"\ +" do echo \"### booting ${target} ###\"; run b_${target};" \ +" if test ${b_break} = 1; then; exit; fi; done\0" \ +"loaddev=mmc 0\0" \ +"altbootcmd=setenv b_mode 0; run b_default;\0" \ +"bootlimit=1\0" \ +"net2nor=sf probe && dhcp &&" \ +" tftp ${loadaddr} SPL && sf erase 0 +${filesize} &&" \ +" sf write ${loadaddr} 400 ${filesize} &&" \ +" tftp ${loadaddr} u-boot-dtb.img && sf erase 0x100000 +${filesize} &&" \ +" sf write ${loadaddr} 0x100000 ${filesize}\0" + +/* RAM */ +#define PHYS_SDRAM_1 MMDC0_ARB_BASE_ADDR +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_MEMTEST_START 0x10000000 +#define CONFIG_SYS_MEMTEST_END 0x10010000 +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* Ethernet */ +#define CONFIG_MII +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_FEC_FIXED_SPEED _1000BASET +#define CONFIG_ARP_TIMEOUT 1500UL + +/* USB Configs */ +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) + +/* SPL */ +#ifdef CONFIG_SPL +#include "imx6_spl.h" + +/* SPI support */ +#if defined(CONFIG_SPL_SPI_SUPPORT) +# define CONFIG_SYS_SPI_U_BOOT_OFFS 0x100000 +#endif + +#endif /* CONFIG_SPL */ +#endif /* __CONFIG_BRPP2_IMX6_H */ -- 2.7.4

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[U-Boot] [PATCH v2 1/2] mach-imx: Adding new argument for SIP call interface
by Anatolij Gustschin 04 Nov '19

04 Nov '19

From: Ye Li <ye.li(a)nxp.com> Need to pass total 5 arguments for SIP HAB call on i.MX8MQ, so update the interface to add new argument. Signed-off-by: Ye Li <ye.li(a)nxp.com> [agust: fixed imx8m-power-domain build] Signed-off-by: Anatolij Gustschin <agust(a)denx.de> Reviewed-by: Patrick Wildt <patrick(a)blueri.se> --- Changes in v2: - fix build breakage in imx8m-power-domain.c arch/arm/include/asm/mach-imx/sys_proto.h | 3 ++- arch/arm/mach-imx/imx_bootaux.c | 4 ++-- arch/arm/mach-imx/sip.c | 4 +++- drivers/misc/imx8/fuse.c | 2 +- drivers/power/domain/imx8m-power-domain.c | 6 ++++-- 5 files changed, 12 insertions(+), 7 deletions(-) diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h index aa66fdc88f..139a7638c1 100644 --- a/arch/arm/include/asm/mach-imx/sys_proto.h +++ b/arch/arm/include/asm/mach-imx/sys_proto.h @@ -143,7 +143,8 @@ int mxs_wait_mask_set(struct mxs_register_32 *reg, u32 mask, u32 timeout); int mxs_wait_mask_clr(struct mxs_register_32 *reg, u32 mask, u32 timeout); unsigned long call_imx_sip(unsigned long id, unsigned long reg0, - unsigned long reg1, unsigned long reg2); + unsigned long reg1, unsigned long reg2, + unsigned long reg3); unsigned long call_imx_sip_ret2(unsigned long id, unsigned long reg0, unsigned long *reg1, unsigned long reg2, unsigned long reg3); diff --git a/arch/arm/mach-imx/imx_bootaux.c b/arch/arm/mach-imx/imx_bootaux.c index 18d7e6819c..3d9422d5a2 100644 --- a/arch/arm/mach-imx/imx_bootaux.c +++ b/arch/arm/mach-imx/imx_bootaux.c @@ -26,7 +26,7 @@ int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data) /* Enable M4 */ #ifdef CONFIG_IMX8M - call_imx_sip(IMX_SIP_SRC, IMX_SIP_SRC_M4_START, 0, 0); + call_imx_sip(IMX_SIP_SRC, IMX_SIP_SRC_M4_START, 0, 0, 0); #else clrsetbits_le32(SRC_BASE_ADDR + SRC_M4_REG_OFFSET, SRC_M4C_NON_SCLR_RST_MASK, SRC_M4_ENABLE_MASK); @@ -38,7 +38,7 @@ int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data) int arch_auxiliary_core_check_up(u32 core_id) { #ifdef CONFIG_IMX8M - return call_imx_sip(IMX_SIP_SRC, IMX_SIP_SRC_M4_STARTED, 0, 0); + return call_imx_sip(IMX_SIP_SRC, IMX_SIP_SRC_M4_STARTED, 0, 0, 0); #else unsigned int val; diff --git a/arch/arm/mach-imx/sip.c b/arch/arm/mach-imx/sip.c index 968e7cf309..fca520c671 100644 --- a/arch/arm/mach-imx/sip.c +++ b/arch/arm/mach-imx/sip.c @@ -7,7 +7,8 @@ #include <asm/arch/sys_proto.h> unsigned long call_imx_sip(unsigned long id, unsigned long reg0, - unsigned long reg1, unsigned long reg2) + unsigned long reg1, unsigned long reg2, + unsigned long reg3) { struct pt_regs regs; @@ -15,6 +16,7 @@ unsigned long call_imx_sip(unsigned long id, unsigned long reg0, regs.regs[1] = reg0; regs.regs[2] = reg1; regs.regs[3] = reg2; + regs.regs[4] = reg3; smc_call(&regs); diff --git a/drivers/misc/imx8/fuse.c b/drivers/misc/imx8/fuse.c index 2f2fad2c17..1309215d4d 100644 --- a/drivers/misc/imx8/fuse.c +++ b/drivers/misc/imx8/fuse.c @@ -74,7 +74,7 @@ int fuse_prog(u32 bank, u32 word, u32 val) } return call_imx_sip(FSL_SIP_OTP_WRITE, (unsigned long)word, - (unsigned long)val, 0); + (unsigned long)val, 0, 0); } int fuse_override(u32 bank, u32 word, u32 val) diff --git a/drivers/power/domain/imx8m-power-domain.c b/drivers/power/domain/imx8m-power-domain.c index 164fb3d31d..40ece9ee3f 100644 --- a/drivers/power/domain/imx8m-power-domain.c +++ b/drivers/power/domain/imx8m-power-domain.c @@ -37,7 +37,8 @@ static int imx8m_power_domain_on(struct power_domain *power_domain) if (pdata->has_pd) power_domain_on(&pdata->pd); - call_imx_sip(IMX_SIP_GPC, IMX_SIP_GPC_PM_DOMAIN, pdata->resource_id, 1); + call_imx_sip(IMX_SIP_GPC, IMX_SIP_GPC_PM_DOMAIN, + pdata->resource_id, 1, 0); return 0; } @@ -51,7 +52,8 @@ static int imx8m_power_domain_off(struct power_domain *power_domain) if (pdata->resource_id < 0) return -EINVAL; - call_imx_sip(IMX_SIP_GPC, IMX_SIP_GPC_PM_DOMAIN, pdata->resource_id, 0); + call_imx_sip(IMX_SIP_GPC, IMX_SIP_GPC_PM_DOMAIN, + pdata->resource_id, 0, 0); if (pdata->has_pd) power_domain_off(&pdata->pd); -- 2.17.1

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[U-Boot] [PATCH 1/3] imx8: Add AHAB secure boot support
by sbabic＠denx.de 04 Nov '19

04 Nov '19

> Add function and new command "auth_cntr" for secure boot support. > When booting with life cycle set to OEM closed, we need to use > this function to authenticate the OS container and load kernel & FDT > from OS container to their destination. > Also add image authentication call when loading container images. > Users can set CONFIG_AHAB_BOOT=y to enable the feature. It is not > set at default. > Signed-off-by: Ye Li <ye.li(a)nxp.com> > Signed-off-by: Peng Fan <peng.fan(a)nxp.com> Applied to u-boot-imx, master, thanks ! Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic(a)denx.de =====================================================================

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[U-Boot] [PATCH v1] imx: defconfig: Enable CONFIG_SPL_FORCE_MMC_BOOT on display5
by Lukasz Majewski 04 Nov '19

04 Nov '19

After the following commit: commit 772b55723bcb ("imx: Introduce CONFIG_SPL_FORCE_MMC_BOOT to force MMC boot on falcon mode") it is possible to set the CONFIG_SPL_FORCE_MMC_BOOT flag, which allows using MMC device as boot device regardless of the device used by Boot ROM (FBL) as the first boot medium. Display5 board needs this flag set to allow falcon boot from eMMC device. Signed-off-by: Lukasz Majewski <lukma(a)denx.de> --- configs/display5_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/display5_defconfig b/configs/display5_defconfig index 3227249413e4..91b369532d94 100644 --- a/configs/display5_defconfig +++ b/configs/display5_defconfig @@ -30,6 +30,7 @@ CONFIG_SPL_DMA_SUPPORT=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_SAVEENV=y CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_FORCE_MMC_BOOT=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000 -- 2.20.1

2 1