September 2018 - U-Boot

[U-Boot] [PATCH v3] serial: omap: Introduce DM specific omap serial
by Lokesh Vutla 11 Sep '18

11 Sep '18

Add driver model support for OMAP_SERIAL while reusing the functions in ns16550.c Signed-off-by: Lokesh Vutla <lokeshvutla(a)ti.com> --- Based on the conclusion on the thread[1], added a separate driver for omap uart. [1] https://patchwork.ozlabs.org/patch/944756/ Changes since v2: - Dropped enabling OMAP_SERIAL by default for SOC_DA8XX. drivers/serial/Kconfig | 9 +++ drivers/serial/Makefile | 1 + drivers/serial/ns16550.c | 47 +------------ drivers/serial/serial_omap.c | 126 +++++++++++++++++++++++++++++++++++ 4 files changed, 139 insertions(+), 44 deletions(-) create mode 100644 drivers/serial/serial_omap.c diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 766e5ced03..41f43af01f 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -625,6 +625,15 @@ config MSM_SERIAL for example APQ8016 and MSM8916. Single baudrate is supported in current implementation (115200). +config OMAP_SERIAL + bool "Support for OMAP specific UART" + depends on DM_SERIAL + default y if ARCH_OMAP2PLUS + select SYS_NS16550 + help + If you have an TI based SoC and want to use the on-chip serial + port, say Y to this option. If unsure say N. + config OWL_SERIAL bool "Actions Semi OWL UART" depends on DM_SERIAL && ARCH_OWL diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 9fa81d855d..03dc29ee2e 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -65,6 +65,7 @@ obj-$(CONFIG_MVEBU_A3700_UART) += serial_mvebu_a3700.o obj-$(CONFIG_MPC8XX_CONS) += serial_mpc8xx.o obj-$(CONFIG_NULLDEV_SERIAL) += serial_nulldev.o obj-$(CONFIG_OWL_SERIAL) += serial_owl.o +obj-$(CONFIG_OMAP_SERIAL) += serial_omap.o ifndef CONFIG_SPL_BUILD obj-$(CONFIG_USB_TTY) += usbtty.o diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index 9c80090aa7..f9041aa626 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -175,7 +175,7 @@ void NS16550_init(NS16550_t com_port, int baud_divisor) ; serial_out(CONFIG_SYS_NS16550_IER, &com_port->ier); -#if defined(CONFIG_ARCH_OMAP2PLUS) +#if defined(CONFIG_ARCH_OMAP2PLUS) || defined(CONFIG_OMAP_SERIAL) serial_out(0x7, &com_port->mdr1); /* mode select reset TL16C750*/ #endif @@ -183,7 +183,8 @@ void NS16550_init(NS16550_t com_port, int baud_divisor) serial_out(ns16550_getfcr(com_port), &com_port->fcr); if (baud_divisor != -1) NS16550_setbrg(com_port, baud_divisor); -#if defined(CONFIG_ARCH_OMAP2PLUS) || defined(CONFIG_SOC_DA8XX) +#if defined(CONFIG_ARCH_OMAP2PLUS) || defined(CONFIG_SOC_DA8XX) || \ + defined(CONFIG_OMAP_SERIAL) /* /16 is proper to hit 115200 with 48MHz */ serial_out(0, &com_port->mdr1); #endif @@ -279,42 +280,6 @@ DEBUG_UART_FUNCS #endif -#ifdef CONFIG_DEBUG_UART_OMAP - -#include <debug_uart.h> - -static inline void _debug_uart_init(void) -{ - struct NS16550 *com_port = (struct NS16550 *)CONFIG_DEBUG_UART_BASE; - int baud_divisor; - - baud_divisor = ns16550_calc_divisor(com_port, CONFIG_DEBUG_UART_CLOCK, - CONFIG_BAUDRATE); - serial_dout(&com_port->ier, CONFIG_SYS_NS16550_IER); - serial_dout(&com_port->mdr1, 0x7); - serial_dout(&com_port->mcr, UART_MCRVAL); - serial_dout(&com_port->fcr, UART_FCR_DEFVAL); - - serial_dout(&com_port->lcr, UART_LCR_BKSE | UART_LCRVAL); - serial_dout(&com_port->dll, baud_divisor & 0xff); - serial_dout(&com_port->dlm, (baud_divisor >> 8) & 0xff); - serial_dout(&com_port->lcr, UART_LCRVAL); - serial_dout(&com_port->mdr1, 0x0); -} - -static inline void _debug_uart_putc(int ch) -{ - struct NS16550 *com_port = (struct NS16550 *)CONFIG_DEBUG_UART_BASE; - - while (!(serial_din(&com_port->lsr) & UART_LSR_THRE)) - ; - serial_dout(&com_port->thr, ch); -} - -DEBUG_UART_FUNCS - -#endif - #ifdef CONFIG_DM_SERIAL static int ns16550_serial_putc(struct udevice *dev, const char ch) { @@ -489,12 +454,6 @@ static const struct udevice_id ns16550_serial_ids[] = { { .compatible = "ingenic,jz4780-uart", .data = PORT_JZ4780 }, { .compatible = "nvidia,tegra20-uart", .data = PORT_NS16550 }, { .compatible = "snps,dw-apb-uart", .data = PORT_NS16550 }, - { .compatible = "ti,omap2-uart", .data = PORT_NS16550 }, - { .compatible = "ti,omap3-uart", .data = PORT_NS16550 }, - { .compatible = "ti,omap4-uart", .data = PORT_NS16550 }, - { .compatible = "ti,am3352-uart", .data = PORT_NS16550 }, - { .compatible = "ti,am4372-uart", .data = PORT_NS16550 }, - { .compatible = "ti,dra742-uart", .data = PORT_NS16550 }, {} }; #endif /* OF_CONTROL && !OF_PLATDATA */ diff --git a/drivers/serial/serial_omap.c b/drivers/serial/serial_omap.c new file mode 100644 index 0000000000..d8a047bb71 --- /dev/null +++ b/drivers/serial/serial_omap.c @@ -0,0 +1,126 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Texas Instruments' OMAP serial driver + * + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + * Lokesh Vutla <lokeshvutla(a)ti.com> + */ + +#include <common.h> +#include <debug_uart.h> +#include <dm.h> +#include <dt-structs.h> +#include <ns16550.h> +#include <serial.h> +#include <clk.h> + +#ifndef CONFIG_SYS_NS16550_CLK +#define CONFIG_SYS_NS16550_CLK 0 +#endif + +#ifdef CONFIG_DEBUG_UART_OMAP + +#include <debug_uart.h> + +static inline void _debug_uart_init(void) +{ + struct NS16550 *com_port = (struct NS16550 *)CONFIG_DEBUG_UART_BASE; + int baud_divisor; + + baud_divisor = ns16550_calc_divisor(com_port, CONFIG_DEBUG_UART_CLOCK, + CONFIG_BAUDRATE); + serial_dout(&com_port->ier, CONFIG_SYS_NS16550_IER); + serial_dout(&com_port->mdr1, 0x7); + serial_dout(&com_port->mcr, UART_MCRVAL); + serial_dout(&com_port->fcr, UART_FCR_DEFVAL); + + serial_dout(&com_port->lcr, UART_LCR_BKSE | UART_LCRVAL); + serial_dout(&com_port->dll, baud_divisor & 0xff); + serial_dout(&com_port->dlm, (baud_divisor >> 8) & 0xff); + serial_dout(&com_port->lcr, UART_LCRVAL); + serial_dout(&com_port->mdr1, 0x0); +} + +static inline void _debug_uart_putc(int ch) +{ + struct NS16550 *com_port = (struct NS16550 *)CONFIG_DEBUG_UART_BASE; + + while (!(serial_din(&com_port->lsr) & UART_LSR_THRE)) + ; + serial_dout(&com_port->thr, ch); +} + +DEBUG_UART_FUNCS + +#endif + +#if CONFIG_IS_ENABLED(DM_SERIAL) + +#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +static int omap_serial_ofdata_to_platdata(struct udevice *dev) +{ + struct ns16550_platdata *plat = dev->platdata; + fdt_addr_t addr; + struct clk clk; + int err; + + /* try Processor Local Bus device first */ + addr = dev_read_addr(dev); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + plat->base = (unsigned long)map_physmem(addr, 0, MAP_NOCACHE); + + plat->reg_offset = dev_read_u32_default(dev, "reg-offset", 0); + plat->reg_shift = 2; + + err = clk_get_by_index(dev, 0, &clk); + if (!err) { + err = clk_get_rate(&clk); + if (!IS_ERR_VALUE(err)) + plat->clock = err; + } else if (err != -ENOENT && err != -ENODEV && err != -ENOSYS) { + debug("omap serial failed to get clock\n"); + return err; + } + + if (!plat->clock) + plat->clock = dev_read_u32_default(dev, "clock-frequency", + CONFIG_SYS_NS16550_CLK); + if (!plat->clock) { + debug("omap serial clock not defined\n"); + return -EINVAL; + } + + plat->fcr = UART_FCR_DEFVAL; + + return 0; +} + +static const struct udevice_id omap_serial_ids[] = { + { .compatible = "ti,omap2-uart", }, + { .compatible = "ti,omap3-uart", }, + { .compatible = "ti,omap4-uart", }, + { .compatible = "ti,am3352-uart", }, + { .compatible = "ti,am4372-uart", }, + { .compatible = "ti,dra742-uart", }, + {} +}; +#endif /* OF_CONTROL && !OF_PLATDATA */ + +#if CONFIG_IS_ENABLED(SERIAL_PRESENT) +U_BOOT_DRIVER(omap_serial) = { + .name = "omap_serial", + .id = UCLASS_SERIAL, +#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) + .of_match = omap_serial_ids, + .ofdata_to_platdata = omap_serial_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct ns16550_platdata), +#endif + .priv_auto_alloc_size = sizeof(struct NS16550), + .probe = ns16550_serial_probe, + .ops = &ns16550_serial_ops, + .flags = DM_FLAG_PRE_RELOC, +}; +#endif +#endif /* DM_SERIAL */ -- 2.18.0

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[U-Boot] [PATCH] omap3: pandora: Enable DM_SERIAL
by Grazvydas Ignotas 11 Sep '18

11 Sep '18

This patch enables DM_SERIAL for the pandora board. Verified that the default kernel can still be booted with this. Signed-off-by: Grazvydas Ignotas <notasas(a)gmail.com> --- board/pandora/pandora.c | 14 ++++++++++++++ configs/omap3_pandora_defconfig | 4 +++- include/configs/omap3_pandora.h | 17 ----------------- 3 files changed, 17 insertions(+), 18 deletions(-) diff --git a/board/pandora/pandora.c b/board/pandora/pandora.c index 4f91dc3bee..a9aae7951d 100644 --- a/board/pandora/pandora.c +++ b/board/pandora/pandora.c @@ -13,6 +13,8 @@ * Texas Instruments, <www.ti.com> */ #include <common.h> +#include <dm.h> +#include <ns16550.h> #include <twl4030.h> #include <asm/io.h> #include <asm/gpio.h> @@ -33,6 +35,18 @@ DECLARE_GLOBAL_DATA_PTR; #define GPIO_IO_PWRDNZ (1 << 6) #define PBIASLITEVMODE1 (1 << 8) +static const struct ns16550_platdata pandora_serial = { + .base = OMAP34XX_UART3, + .reg_shift = 2, + .clock = V_NS16550_CLK, + .fcr = UART_FCR_DEFVAL, +}; + +U_BOOT_DEVICE(pandora_uart) = { + "ns16550_serial", + &pandora_serial +}; + /* * Routine: board_init * Description: Early hardware init. diff --git a/configs/omap3_pandora_defconfig b/configs/omap3_pandora_defconfig index 6dce53834d..c2b4a4f0d2 100644 --- a/configs/omap3_pandora_defconfig +++ b/configs/omap3_pandora_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_OMAP2PLUS=y CONFIG_SYS_TEXT_BASE=0x80008000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_TARGET_OMAP3_PANDORA=y CONFIG_DISTRO_DEFAULTS=y CONFIG_NR_DRAM_BANKS=2 @@ -25,11 +26,12 @@ CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(xloader),1920k(uboot),128k(uboot-env),10m(boot),-(rootfs)" CONFIG_CMD_UBI=y CONFIG_ENV_IS_IN_NAND=y +CONFIG_DM=y CONFIG_TWL4030_LED=y CONFIG_MMC_OMAP_HS=y CONFIG_NAND=y CONFIG_SYS_NAND_BUSWIDTH_16BIT=y -CONFIG_CONS_INDEX=3 +CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_OMAP3_SPI=y diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h index 5a82cbee71..82c66c4b8c 100644 --- a/include/configs/omap3_pandora.h +++ b/include/configs/omap3_pandora.h @@ -19,23 +19,6 @@ #define CONFIG_SYS_DEVICE_NULLDEV 1 -/* - * Hardware drivers - */ - -/* TWL4030 LED */ - -/* - * NS16550 Configuration - */ -#undef CONFIG_SYS_NS16550_CLK -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK -#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 - -/* commands to include */ - /* * Board NAND Info. */ -- 2.17.1

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[U-Boot] [PATCH] board: arm: Add support for Broadcom BCM7260
by Thomas Fitzsimmons 11 Sep '18

11 Sep '18

Add support for loading U-Boot on the Broadcom 7260 SoC. This port assumes Broadcom's BOLT bootloader is acting as the second stage bootloader, and U-Boot is acting as the third stage bootloader, loaded as an ELF program by BOLT. Signed-off-by: Thomas Fitzsimmons <fitzsim(a)fitzsim.org> --- arch/arm/mach-bcmstb/Kconfig | 13 ++++++++++--- configs/bcm7260_defconfig | 23 +++++++++++++++++++++++ include/configs/bcm7260.h | 35 +++++++++++++++++++++++++++++++++++ include/configs/bcmstb.h | 10 ++++++++-- 4 files changed, 76 insertions(+), 5 deletions(-) create mode 100644 configs/bcm7260_defconfig create mode 100644 include/configs/bcm7260.h diff --git a/arch/arm/mach-bcmstb/Kconfig b/arch/arm/mach-bcmstb/Kconfig index 6c7952f..0a56c3c 100644 --- a/arch/arm/mach-bcmstb/Kconfig +++ b/arch/arm/mach-bcmstb/Kconfig @@ -7,8 +7,14 @@ config TARGET_BCM7445 Support for the Broadcom 7445 SoC. This port assumes BOLT is acting as the second stage bootloader, and U-Boot is acting as the third stage bootloader (TSBL), loaded by BOLT. - This port may work on other BCM7xxx boards with - configuration changes. + +config TARGET_BCM7260 + bool "Broadcom 7260 TSBL" + depends on ARCH_BCMSTB + help + Support for the Broadcom 7260 SoC. This port assumes BOLT + is acting as the second stage bootloader, and U-Boot is + acting as the third stage bootloader (TSBL), loaded by BOLT. config SYS_CPU default "armv7" @@ -23,7 +29,8 @@ config SYS_SOC default "bcmstb" config SYS_CONFIG_NAME - default "bcm7445" + default "bcm7445" if TARGET_BCM7445 + default "bcm7260" if TARGET_BCM7260 config SYS_FDT_SAVE_ADDRESS hex "Address to which the prior stage provided DTB will be copied" diff --git a/configs/bcm7260_defconfig b/configs/bcm7260_defconfig new file mode 100644 index 0000000..a04f700 --- /dev/null +++ b/configs/bcm7260_defconfig @@ -0,0 +1,23 @@ +CONFIG_ARM=y +CONFIG_ARCH_BCMSTB=y +CONFIG_TARGET_BCM7260=y +CONFIG_USE_PRIVATE_LIBGCC=y +CONFIG_OF_CONTROL=y +CONFIG_OF_PRIOR_STAGE=y +CONFIG_DM=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_RSA=y +CONFIG_BLK=n +CONFIG_SDHCI=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_BCMSTB=y +CONFIG_CONS_INDEX=3 +CONFIG_BOOTDELAY=1 +CONFIG_SYS_PROMPT="U-Boot>" +CONFIG_HUSH_PARSER=y +CONFIG_SYS_TEXT_BASE=0x10100000 +CONFIG_SYS_NS16550_COM3=0xf040c000 +CONFIG_EFI_LOADER=n +CONFIG_EFI_PARTITION=y diff --git a/include/configs/bcm7260.h b/include/configs/bcm7260.h new file mode 100644 index 0000000..1a5eab1 --- /dev/null +++ b/include/configs/bcm7260.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2018 Cisco Systems, Inc. + * + * Author: Thomas Fitzsimmons <fitzsim(a)fitzsim.org> + * + * Configuration settings for the Broadcom BCM7260 SoC family. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_SYS_NS16550_COM3 0xf040c000 + +#define CONFIG_NR_DRAM_BANKS 1 + +#define CONFIG_SYS_TEXT_BASE 0x10100000 +#define CONFIG_SYS_INIT_RAM_ADDR 0x10200000 + +#define CONFIG_SYS_MALLOC_LEN ((40 * 1024) << 10) /* 40 MiB */ + +#include "bcmstb.h" + +#define BCMSTB_SDHCI_BASE 0xf0200300 +#define BCMSTB_TIMER_LOW 0xf0412008 +#define BCMSTB_TIMER_HIGH 0xf041200c +#define BCMSTB_TIMER_FREQUENCY 0xf0412020 +#define BCMSTB_HIF_MSPI_BASE 0xf0203c00 +#define BCMSTB_BSPI_BASE 0xf0203a00 +#define BCMSTB_HIF_SPI_INTR2 0xf0201a00 +#define BCMSTB_CS_REG 0xf0200920 + +#define CONFIG_CMD_GPT + +#endif /* __CONFIG_H */ diff --git a/include/configs/bcmstb.h b/include/configs/bcmstb.h index c74fe40..2dcefb8 100644 --- a/include/configs/bcmstb.h +++ b/include/configs/bcmstb.h @@ -158,9 +158,15 @@ extern phys_addr_t prior_stage_fdt_address; */ #define CONFIG_SYS_REDUNDAND_ENVIRONMENT -#define CONFIG_ENV_OFFSET 0x1e0000 #define CONFIG_ENV_SIZE (64 << 10) /* 64 KiB */ -#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE +#if defined(CONFIG_ENV_IS_IN_MMC) +# define CONFIG_SYS_MMC_ENV_DEV 0 +# define CONFIG_SYS_MMC_ENV_PART 0 +# define CONFIG_ENV_OFFSET (0x000040a4 * 512) +#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH) +# define CONFIG_ENV_OFFSET 0x1e0000 +# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE +#endif #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) #define CONFIG_ENV_OVERWRITE -- 1.8.3.1

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[U-Boot] [PATCH] ARM: CPU: arm926ejs: Consolidate cache routines to common file
by Adam Ford 11 Sep '18

11 Sep '18

Four different boards had different options for enabling cache that were virtually all the same. This consolidates these common functions into arch/arm/cpu/arm926ejs/cache.c This also has the positive side-effect of enabling cache on the Davinci (da850) boards. Signed-off-by: Adam Ford <aford173(a)gmail.com> --- arch/arm/cpu/arm926ejs/cache.c | 23 +++++++++++++++++++++++ arch/arm/cpu/arm926ejs/mx25/generic.c | 8 -------- arch/arm/cpu/arm926ejs/mx27/generic.c | 8 -------- arch/arm/cpu/arm926ejs/mxs/mxs.c | 10 ---------- arch/arm/cpu/arm926ejs/spear/cpu.c | 10 ---------- 5 files changed, 23 insertions(+), 36 deletions(-) diff --git a/arch/arm/cpu/arm926ejs/cache.c b/arch/arm/cpu/arm926ejs/cache.c index 3b89391c37..22a55f52e0 100644 --- a/arch/arm/cpu/arm926ejs/cache.c +++ b/arch/arm/cpu/arm926ejs/cache.c @@ -65,3 +65,26 @@ __weak void l2_cache_disable(void) {} #if CONFIG_IS_ENABLED(SYS_THUMB_BUILD) __weak void invalidate_l2_cache(void) {} #endif + +#ifndef CONFIG_SYS_ICACHE_OFF +/* Invalidate entire I-cache and branch predictor array */ +void invalidate_icache_all(void) +{ + unsigned long i = 0; + + asm ("mcr p15, 0, %0, c7, c5, 0" : : "r" (i)); +} +#else +void invalidate_icache_all(void) {} +#endif + +void enable_caches(void) +{ +#ifndef CONFIG_SYS_ICACHE_OFF + icache_enable(); +#endif +#ifndef CONFIG_SYS_DCACHE_OFF + dcache_enable(); +#endif +} + diff --git a/arch/arm/cpu/arm926ejs/mx25/generic.c b/arch/arm/cpu/arm926ejs/mx25/generic.c index e6eef36c0e..2795a5f22e 100644 --- a/arch/arm/cpu/arm926ejs/mx25/generic.c +++ b/arch/arm/cpu/arm926ejs/mx25/generic.c @@ -214,14 +214,6 @@ int print_cpuinfo(void) } #endif -void enable_caches(void) -{ -#ifndef CONFIG_SYS_DCACHE_OFF - /* Enable D-cache. I-cache is already enabled in start.S */ - dcache_enable(); -#endif -} - #if defined(CONFIG_FEC_MXC) /* * Initializes on-chip ethernet controllers. diff --git a/arch/arm/cpu/arm926ejs/mx27/generic.c b/arch/arm/cpu/arm926ejs/mx27/generic.c index a593283438..08b1b4de71 100644 --- a/arch/arm/cpu/arm926ejs/mx27/generic.c +++ b/arch/arm/cpu/arm926ejs/mx27/generic.c @@ -374,11 +374,3 @@ void mx27_sd2_init_pins(void) } #endif /* CONFIG_MMC_MXC */ - -#ifndef CONFIG_SYS_DCACHE_OFF -void enable_caches(void) -{ - /* Enable D-cache. I-cache is already enabled in start.S */ - dcache_enable(); -} -#endif /* CONFIG_SYS_DCACHE_OFF */ diff --git a/arch/arm/cpu/arm926ejs/mxs/mxs.c b/arch/arm/cpu/arm926ejs/mxs/mxs.c index f42f311cbc..85c65dcb44 100644 --- a/arch/arm/cpu/arm926ejs/mxs/mxs.c +++ b/arch/arm/cpu/arm926ejs/mxs/mxs.c @@ -49,16 +49,6 @@ void reset_cpu(ulong ignored) ; } -void enable_caches(void) -{ -#ifndef CONFIG_SYS_ICACHE_OFF - icache_enable(); -#endif -#ifndef CONFIG_SYS_DCACHE_OFF - dcache_enable(); -#endif -} - /* * This function will craft a jumptable at 0x0 which will redirect interrupt * vectoring to proper location of U-Boot in RAM. diff --git a/arch/arm/cpu/arm926ejs/spear/cpu.c b/arch/arm/cpu/arm926ejs/spear/cpu.c index 0970aca2ef..e852a88881 100644 --- a/arch/arm/cpu/arm926ejs/spear/cpu.c +++ b/arch/arm/cpu/arm926ejs/spear/cpu.c @@ -55,16 +55,6 @@ int arch_cpu_init(void) return 0; } -void enable_caches(void) -{ -#ifndef CONFIG_SYS_ICACHE_OFF - icache_enable(); -#endif -#ifndef CONFIG_SYS_DCACHE_OFF - dcache_enable(); -#endif -} - #ifdef CONFIG_DISPLAY_CPUINFO int print_cpuinfo(void) { -- 2.17.1

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[U-Boot] [PATCH] serial: arm_dcc: Add DCC support for V7R based cores
by Lokesh Vutla 11 Sep '18

11 Sep '18

DCC is supported on Cortex R series as well. Enable DCC support for V7R. Signed-off-by: Lokesh Vutla <lokeshvutla(a)ti.com> --- drivers/serial/arm_dcc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/serial/arm_dcc.c b/drivers/serial/arm_dcc.c index c83a3fe8ee..43e8691a93 100644 --- a/drivers/serial/arm_dcc.c +++ b/drivers/serial/arm_dcc.c @@ -19,7 +19,7 @@ #include <dm.h> #include <serial.h> -#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V7A) +#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V7A) || defined(CONFIG_CPU_V7R) /* * ARMV6 & ARMV7 */ -- 2.18.0

2 1

[U-Boot] [PATCH] pinctrl: Fix build warning with ARM64
by Lokesh Vutla 11 Sep '18

11 Sep '18

Following build warning appears when pinctrl-single is built for ARM64: In file included from drivers/pinctrl/pinctrl-single.c:10:0: drivers/pinctrl/pinctrl-single.c: In function ‘single_configure_pins’: ./arch/arm/include/asm/io.h:43:28: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] #define __arch_getw(a) (*(volatile unsigned short *)(a)) Fix this by using phys_addr_t for variable reg instead of u32 Signed-off-by: Lokesh Vutla <lokeshvutla(a)ti.com> --- drivers/pinctrl/pinctrl-single.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index 296eb63cc4..d80c6eda70 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -43,13 +43,13 @@ static int single_configure_pins(struct udevice *dev, { struct single_pdata *pdata = dev->platdata; int count = size / sizeof(struct single_fdt_pin_cfg); - int n, reg; + phys_addr_t n, reg; u32 val; for (n = 0; n < count; n++, pins++) { reg = fdt32_to_cpu(pins->reg); if ((reg < 0) || (reg > pdata->offset)) { - dev_dbg(dev, " invalid register offset 0x%08x\n", reg); + dev_dbg(dev, " invalid register offset 0x%pa\n", &reg); continue; } reg += pdata->base; @@ -66,7 +66,7 @@ static int single_configure_pins(struct udevice *dev, pdata->width); continue; } - dev_dbg(dev, " reg/val 0x%08x/0x%08x\n",reg, val); + dev_dbg(dev, " reg/val 0x%pa/0x%08x\n", &reg, val); } return 0; } -- 2.18.0

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[U-Boot] [PATCH 0/4] dm: omap-timer: Make timer driver SoC independent
by Lokesh Vutla 11 Sep '18

11 Sep '18

Make omap timer driver independent of SoC, so that new generation TI SoCs can use this driver without any dependencies. Lokesh Vutla (4): arm: omap4+: Move SCLK to include/configs dm: omap-timer: Do not include asm/arch/clock.h dm: omap-timer: Use 64bit for counter values dm: omap-timer: Update clock rate only if not populated arch/arm/include/asm/arch-omap4/clock.h | 4 ---- arch/arm/include/asm/arch-omap5/clock.h | 8 -------- drivers/timer/omap-timer.c | 7 ++++--- include/configs/ti_omap4_common.h | 4 ++++ include/configs/ti_omap5_common.h | 8 ++++++++ 5 files changed, 16 insertions(+), 15 deletions(-) -- 2.18.0

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[U-Boot] [PATCH 1/2] ARM: dts: Makefile: fix build for at91family
by Eugen Hristev 11 Sep '18

11 Sep '18

For at91family, makefile was building unwanted DTBs Moved them under specific target configuration. Signed-off-by: Eugen Hristev <eugen.hristev(a)microchip.com> --- arch/arm/dts/Makefile | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index ebfa227..79fdc0d 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1,9 +1,9 @@ # SPDX-License-Identifier: GPL-2.0+ -dtb-$(CONFIG_AT91FAMILY) += at91sam9260-smartweb.dtb \ - at91sam9g20-taurus.dtb \ - at91sam9g45-corvus.dtb \ - at91sam9g45-gurnard.dtb +dtb-$(CONFIG_TARGET_SMARTWEB) += at91sam9260-smartweb.dtb +dtb-$(CONFIG_TARGET_TAURUS) += at91sam9g20-taurus.dtb +dtb-$(CONFIG_TARGET_CORVUS) += at91sam9g45-corvus.dtb +dtb-$(CONFIG_TARGET_GURNARD) += at91sam9g45-gurnard.dtb dtb-$(CONFIG_S5PC100) += s5pc1xx-smdkc100.dtb dtb-$(CONFIG_S5PC110) += s5pc1xx-goni.dtb -- 2.7.4

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[U-Boot] [PATCH] gpio: stm32f7: replace ODR update by BSRR write
by Patrice Chotard 11 Sep '18

11 Sep '18

Replace clrsetbits on ODR register (2 operations: one read + one write) by writing on the correct bit (SET or RESET) of the BSRR register (only 1 write operation). Moreover this register if safe for simultaneous access by 2 master on the bus. Signed-off-by: Patrick Delaunay <patrick.delaunay(a)st.com> Signed-off-by: Patrice Chotard <patrice.chotard(a)st.com> --- drivers/gpio/stm32f7_gpio.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/drivers/gpio/stm32f7_gpio.c b/drivers/gpio/stm32f7_gpio.c index 5b08e7ee275c..4c0786fff88d 100644 --- a/drivers/gpio/stm32f7_gpio.c +++ b/drivers/gpio/stm32f7_gpio.c @@ -18,7 +18,7 @@ #define STM32_GPIOS_PER_BANK 16 #define MODE_BITS(gpio_pin) (gpio_pin * 2) #define MODE_BITS_MASK 3 -#define IN_OUT_BIT_INDEX(gpio_pin) (1UL << (gpio_pin)) +#define BSRR_BIT(gpio_pin, value) BIT(gpio_pin + (value ? 0 : 16)) static int stm32_gpio_direction_input(struct udevice *dev, unsigned offset) { @@ -41,8 +41,8 @@ static int stm32_gpio_direction_output(struct udevice *dev, unsigned offset, int mask = MODE_BITS_MASK << bits_index; clrsetbits_le32(&regs->moder, mask, STM32_GPIO_MODE_OUT << bits_index); - mask = IN_OUT_BIT_INDEX(offset); - clrsetbits_le32(&regs->odr, mask, value ? mask : 0); + + writel(BSRR_BIT(offset, value), &regs->bsrr); return 0; } @@ -52,16 +52,15 @@ static int stm32_gpio_get_value(struct udevice *dev, unsigned offset) struct stm32_gpio_priv *priv = dev_get_priv(dev); struct stm32_gpio_regs *regs = priv->regs; - return readl(&regs->idr) & IN_OUT_BIT_INDEX(offset) ? 1 : 0; + return readl(&regs->idr) & BIT(offset) ? 1 : 0; } static int stm32_gpio_set_value(struct udevice *dev, unsigned offset, int value) { struct stm32_gpio_priv *priv = dev_get_priv(dev); struct stm32_gpio_regs *regs = priv->regs; - int mask = IN_OUT_BIT_INDEX(offset); - clrsetbits_le32(&regs->odr, mask, value ? mask : 0); + writel(BSRR_BIT(offset, value), &regs->bsrr); return 0; } -- 1.9.1

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[U-Boot] [PATCH v2 u-boot 0/2] Add the VPU Power Domain support
by Neil Armstrong 11 Sep '18

11 Sep '18

The Amlogic Meson SoCs embeds a specific Power Domain dedicated to the Video Processing Unit. The first patch implements support for this power domain in preparation of the future support for the Video display support in U-Boot. The second patch adds changes in the clock driver to handle the setup of the VPU and VAPB clocks configured from DT using assigned-clocks entries. Changes since v1: - Fixed "format '%d' expects argument of type 'int', but argument 4 has type 'long unsigned int'" in clk_meson.c Neil Armstrong (2): power: domain: Add the VPU Power Domain driver clk: clk_meson: Add mux and div support for reparent and rate setting drivers/clk/clk_meson.c | 533 ++++++++++++++++++++++++++++++- drivers/power/domain/Kconfig | 7 + drivers/power/domain/Makefile | 1 + drivers/power/domain/meson-gx-pwrc-vpu.c | 198 ++++++++++++ 4 files changed, 734 insertions(+), 5 deletions(-) create mode 100644 drivers/power/domain/meson-gx-pwrc-vpu.c -- 2.7.4

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