September 2018 - U-Boot

[U-Boot] [RESEND PATCH v2 00/15] riscv: Add QEMU virt board support
by Bin Meng 18 Sep '18

18 Sep '18

This series adds QEMU RISC-V 'virt' board target support, with the hope of helping people easily test U-Boot on RISC-V. Some existing RISC-V codes have been changed to make it easily to support new targets. Some spotted coding style issues are fixed. This series is available at u-boot-x86/riscv-working for testing. Resend v2 to rebase on top of v2018.09 release with Tom's tree on github, as the git.denx.de is still out of sync ... Changes in v2: - Change Linux kernel entry parameters' type to support 32/64 bit - new patch to remove CSR read/write defines in encoding.h - new patch to pass mhartid CSR value to kernel - new patch to move do_reset() to a common place Bin Meng (15): riscv: kconfig: Normalize architecture name spelling riscv: Remove setup.h riscv: bootm: Correct the 1st kernel argument to hart id riscv: Remove mach type riscv: Move the linker script to the CPU root directory riscv: Fix coding style issues in the linker script riscv: Explicitly pass -march and -mabi to the compiler riscv: Add a helper routine to print CPU information riscv: Remove CSR read/write defines in encoding.h riscv: bootm: Pass mhartid CSR value to kernel riscv: Make start.S available for all targets riscv: ae350: Clean up mixed tabs and spaces in the dts riscv: kconfig: Select DM and OF_CONTROL riscv: Add QEMU virt board support riscv: Move do_reset() to a common place arch/Kconfig | 5 +- arch/riscv/Kconfig | 10 +- arch/riscv/Makefile | 3 +- arch/riscv/config.mk | 9 +- arch/riscv/cpu/Makefile | 7 ++ arch/riscv/cpu/ax25/Makefile | 2 - arch/riscv/cpu/ax25/cpu.c | 9 -- arch/riscv/cpu/cpu.c | 49 ++++++++ arch/riscv/cpu/qemu/Makefile | 6 + arch/riscv/cpu/qemu/cpu.c | 21 ++++ arch/riscv/cpu/qemu/dram.c | 17 +++ arch/riscv/cpu/{ax25 => }/start.S | 0 arch/riscv/cpu/{ax25 => }/u-boot.lds | 60 +++++----- arch/riscv/dts/ae350.dts | 177 +++++++++++++++-------------- arch/riscv/include/asm/bootm.h | 13 --- arch/riscv/include/asm/csr.h | 124 ++++++++++++++++++++ arch/riscv/include/asm/encoding.h | 50 +------- arch/riscv/include/asm/mach-types.h | 29 ----- arch/riscv/include/asm/setup.h | 194 -------------------------------- arch/riscv/include/asm/u-boot.h | 1 - arch/riscv/lib/Makefile | 1 + arch/riscv/lib/bootm.c | 20 +--- arch/riscv/lib/reset.c | 14 +++ board/AndesTech/ax25-ae350/ax25-ae350.c | 2 - board/emulation/qemu-riscv/Kconfig | 21 ++++ board/emulation/qemu-riscv/MAINTAINERS | 7 ++ board/emulation/qemu-riscv/Makefile | 5 + board/emulation/qemu-riscv/qemu-riscv.c | 23 ++++ cmd/bdinfo.c | 1 - configs/ax25-ae350_defconfig | 2 - configs/qemu-riscv32_defconfig | 10 ++ configs/qemu-riscv64_defconfig | 11 ++ doc/README.qemu-riscv | 46 ++++++++ include/configs/qemu-riscv.h | 21 ++++ 34 files changed, 532 insertions(+), 438 deletions(-) create mode 100644 arch/riscv/cpu/Makefile create mode 100644 arch/riscv/cpu/cpu.c create mode 100644 arch/riscv/cpu/qemu/Makefile create mode 100644 arch/riscv/cpu/qemu/cpu.c create mode 100644 arch/riscv/cpu/qemu/dram.c rename arch/riscv/cpu/{ax25 => }/start.S (100%) rename arch/riscv/cpu/{ax25 => }/u-boot.lds (54%) delete mode 100644 arch/riscv/include/asm/bootm.h create mode 100644 arch/riscv/include/asm/csr.h delete mode 100644 arch/riscv/include/asm/mach-types.h delete mode 100644 arch/riscv/include/asm/setup.h create mode 100644 arch/riscv/lib/reset.c create mode 100644 board/emulation/qemu-riscv/Kconfig create mode 100644 board/emulation/qemu-riscv/MAINTAINERS create mode 100644 board/emulation/qemu-riscv/Makefile create mode 100644 board/emulation/qemu-riscv/qemu-riscv.c create mode 100644 configs/qemu-riscv32_defconfig create mode 100644 configs/qemu-riscv64_defconfig create mode 100644 doc/README.qemu-riscv create mode 100644 include/configs/qemu-riscv.h -- 2.7.4

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[U-Boot] [PATCH v2] armv8: fsl-layerscape: reorder rgmii dpmacs' enablement
by Pankaj Bansal 18 Sep '18

18 Sep '18

some dpmacs in armv8a based freescale layerscape SOCs can be configured via both serdes(sgmii, xfi, xlaui etc) bits and via EC*_PMUX(rgmii) bits in RCW. e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits Now if a dpmac is enabled by serdes bits then it takes precedence over EC*_PMUX bits. i.e. in LX2160A if we select serdes protocol that configures dpmac17 as SGMII and set the EC1_PMUX as RGMII, then the dpmac is SGMII and not RGMII. Therefore, move the fsl_rgmii_init after fsl_serdes_init. in fsl_rgmii_init function of SOC, we will check if the dpmac is enabled or not? if it is (fsl_serdes_init has already enabled the dpmac), then don't enable it. Signed-off-by: Pankaj Bansal <pankaj.bansal(a)nxp.com> --- Notes: V2: - as per review comments, add commit message as inline comments. arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 22 ++++++++++++++++++---- 1 file changed, 18 insertions(+), 4 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 052e0708d4..3fe7f885e8 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -553,15 +553,29 @@ int arch_early_init_r(void) printf("Did not wake secondary cores\n"); } -#ifdef CONFIG_SYS_FSL_HAS_RGMII - fsl_rgmii_init(); -#endif - config_core_prefetch(); #ifdef CONFIG_SYS_HAS_SERDES fsl_serdes_init(); #endif +#ifdef CONFIG_SYS_FSL_HAS_RGMII + /* some dpmacs in armv8a based freescale layerscape SOCs can be + * configured via both serdes(sgmii, xfi, xlaui etc) bits and via + * EC*_PMUX(rgmii) bits in RCW. + * e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from + * serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits + * Now if a dpmac is enabled by serdes bits then it takes precedence + * over EC*_PMUX bits. i.e. in LX2160A if we select serdes protocol + * that configures dpmac17 as SGMII and set the EC1_PMUX as RGMII, + * then the dpmac is SGMII and not RGMII. + * + * Therefore, move the fsl_rgmii_init after fsl_serdes_init. in + * fsl_rgmii_init function of SOC, we will check if the dpmac is enabled + * or not? if it is (fsl_serdes_init has already enabled the dpmac), + * then don't enable it. + */ + fsl_rgmii_init(); +#endif #ifdef CONFIG_FMAN_ENET fman_enet_init(); #endif -- 2.17.1

1 0

[U-Boot] [RFC PATCH v1] tools: Add a tool to get an overview of the usage of CONFIG options
by Jean-Jacques Hiblot 18 Sep '18

18 Sep '18

scan_configs.py is tool that allow to check how some options are used for a particular subset of platforms. The purpose is to identify the targets that are actually using one or more options of interest. For example, it can tell what targets are still using CONFIG_DM_I2_COMPAT. This is much slower that greping the configs directory but is actually more accurate as it relies on the information found in u-boot.cfg instead. It can also perform diffs between u-boot.cfg and spl/u-boot.cfg (sometimes platforms change the CONFIG options in the header file for the SPL) and diffs between .config and u-boot.cfg. This last is useful to identify options that could be moved to defconfigs. usage: scan_configs.py [-h] [--soc SOC] [--vendor VENDOR] [--arch ARCH] [--cpu CPU] [--board BOARD] [--target TARGET] [-j JOBS] [-v] [-p] [--keep] [--nobuild] [--uboot | --spl | --spldiff | --dotconfdiff] OPTION [OPTION ...] all filtering parameters (OPTION, vendor, arch, ...) accept regexp. ex: scan_configs.py .*DM_I2C.* --soc 'omap[2345]|k3' will match CONFIG_DM_I2C and CONFIG_DM_I2C_COMPAT and look for it only for targets using the omap2, omap3, omap4, omap5 or k3 SOCs. Signed-off-by: Jean-Jacques Hiblot <jjhiblot(a)ti.com> --- I wrote this tool because I was struggling keeping in mind all the platforms that were impacted by a WIP on DM_I2C_COMPAT for TI platforms. You may find it useful too. limitations: - must be executed at the root of the source tree - the source tree must be clean (make mrproper) - only supports CSV format. visualization in terminal sould be added. But LibreOffice calc is better suited with all its ordering/ filtering capabilities. tools/scan_configs.py | 379 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 379 insertions(+) create mode 100755 tools/scan_configs.py diff --git a/tools/scan_configs.py b/tools/scan_configs.py new file mode 100755 index 0000000..9f9e71e --- /dev/null +++ b/tools/scan_configs.py @@ -0,0 +1,379 @@ +#!/usr/bin/env python3 +# SPDX-License-Identifier: GPL-2.0+ +# +# Author: JJ Hiblot <jjhiblot(a)ti.com> +# + +""" +scan the configuration of specified targets (ie defconfigs) and outputs a summary in a csv file. +Useful tool to check what platform is using a particular set of options. + +examples: + +1) Get an overview of the usage of CONFIG_DM, CONFIG_SPL_DM, and DM/I2C related + options for platforms with omap5 or k3 SOC + +$ scan_configs.py CONFIG_SPL_DM CONFIG_DM CONFIG_DM_I2C.* --vendor ti \ + --soc 'omap5|k3' > dummy.csv + +target soc vendor CONFIG_SPL_DM CONFIG_DM CONFIG_DM_I2C_COMPAT CONFIG_DM_I2C +am65x_evm_a53 k3 ti X X +am57xx_evm omap5 ti X X X X +am57xx_hs_evm omap5 ti X X X X +dra7xx_evm omap5 ti X X X X +dra7xx_hs_evm omap5 ti X X X X +omap5_uevm omap5 ti + +This shows quickly that DM is not supported at all for omap5_uevm, and that +only am65x_evm_a53 in not using DM_I2C. +Also all the other platforms use CONFIG_DM_I2C_COMPAT. + +2) Check differences in config between SPL and u-boot (--spldiff option) + +Some platforms may disable/enable stuff in the configuration header files if +in SPl. This makes it hard to know the usage of a variable by just looking at +the .config. This is specially true for DM stuff. + +$ scan_configs.py CONFIG_SPL_DM CONFIG_DM CONFIG_DM_I2C.* --vendor ti \ + --soc 'omap5|k3' --spldiff > dummy.csv + +target soc vendor CONFIG_DM_I2C_COMPAT CONFIG_DM_I2C +am65x_evm_a53 k3 ti +am57xx_evm omap5 ti U-Boot U-Boot +am57xx_hs_evm omap5 ti U-Boot U-Boot +dra7xx_evm omap5 ti U-Boot U-Boot +dra7xx_hs_evm omap5 ti U-Boot U-Boot +omap5_uevm omap5 ti + +3) Check differences between .config and u-boot.cfg (--dotconfigdiff option) + +This option can be used to help identify CONFIG options that should be moved +out of the header configuration file to the defconfig. + +$ scan_configs.py .*EEPROM.* --vendor ti --soc 'omap5|k3' --dotconfdiff > dummy.csv + +target soc vendor CONFIG_SYS_I2C_EEPROM_ADDR CONFIG_SYS_I2C_EEPROM_ADDR_LEN CONFIG_ENV_EEPROM_IS_ON_I2C +am65x_evm_a53 k3 ti +am57xx_evm omap5 ti U-Boot.cfg U-Boot.cfg U-Boot.cfg +am57xx_hs_evm omap5 ti U-Boot.cfg U-Boot.cfg U-Boot.cfg +dra7xx_evm omap5 ti U-Boot.cfg U-Boot.cfg U-Boot.cfg +dra7xx_hs_evm omap5 ti U-Boot.cfg U-Boot.cfg U-Boot.cfg +omap5_uevm omap5 ti + +""" + +import queue +import signal +import threading +import re +import shutil +import csv +import sys +import argparse +import os +from tempfile import TemporaryDirectory +from collections import OrderedDict +import multiprocessing + +left_columns = ['target','soc','vendor'] + +class cfg_parser: + """ Parser for a cfg file """ + def __init__(self, config_filters): + """ initialize the parser to look for limited set of options + + The config_filters is a list of regexp to match the options we are + interested in. + """ + self.rules = [re.compile("#define {} ".format(cfg_opt)) + for cfg_opt in config_filters] + + def parse(self, filename): + """ Read a cfg file, and for each line, check if match any of our + criteria. If so add the option and its value to a dictionary. + The result is a dictionary that looks like: + { "CONFIG_DM":"1", "CONFIG_SYS_LOAD_ADDR":"0x82000000" } + """ + dic = {} + with open(filename, 'r') as f: + lines = f.readlines() + for r in self.rules: + for l in lines: + m = r.match(l) + if m: + dic[l.split()[1]] = ' '.join(l.split()[2:]) + return dic + +class dotconfig_parser: + def __init__(self, config_filters): + """ initialize the parser to look for limited set of options + + The config_filters is a list of regexp to match the options we are + interested in. + """ + self.rules = [re.compile("{}=".format(cfg_opt)) + for cfg_opt in config_filters] + def parse(self, filename): + """ Read a .config file, and for each line, check if match any of our + criteria. If so add the option and its value to a dictionary. + The result is a dictionary that looks like: + { "CONFIG_DM":"1", "CONFIG_SYS_LOAD_ADDR":"0x82000000" } + """ + dic = {} + with open(filename, 'r') as f: + lines = f.readlines() + for r in self.rules: + for l in lines: + m = r.match(l) + if m: + cfg = l.split('=')[0] + val = l[len(cfg)+1:].strip() + dic[cfg] = val if val != "y" else "1" + return dic + +def cmp_options_dic(dic1,name1,dic2,name2): + """ Compare 2 options dictionaries. + The result is another dictionary that summarises the difference (values differ, only in dic1, only in dic2""" + s1 = set(dic1.keys()) + s2 = set(dic2.keys()) + + common_options = list(s1 & s2) + only_in_dic1 = list(s1 - s2) + only_in_dic2 = list(s2 - s1) + + diff_dic = {} + for opt in common_options: + if dic1[opt] != dic2[opt]: + diff_dic[opt] = "Diff '{}' vs '{}'".format(dic1[opt],dic2[opt]) + + for opt in only_in_dic1: + diff_dic[opt] = "{} only".format(name1) + for opt in only_in_dic2: + diff_dic[opt] = "{} only".format(name2) + return diff_dic + +class board: + def __init__(self, status, arch, cpu, soc, vendor, board, target): + self.status = status + self.arch = arch + self.cpu = cpu + self.soc = soc + self.vendor = vendor + self.board = board + self.target = target + self.result_dic = None + self.temp_dir = "./.scan_config_workdir/{}".format(self.target) + + def __repr__(self): + return "{} {} {}".format(self.target, self.vendor,self.soc) + + def cleanup(self): + """ remove the directory in which the cfg files have been built """ + shutil.rmtree(self.temp_dir) + + def match(self,rules): + """ return True if the board match all the criteria """ + for prop,r in rules: + if not r.match(getattr(self,prop)): + return False + return True + + def make_uboot_cfg(self, u_boot, spl): + """ configure for the board/target and build the required cfg files""" + u_boot_target = "u-boot.cfg" if u_boot else "" + spl_target = "spl/u-boot.cfg" if spl else "" + + r = os.system("make {}_config {} {} KBUILD_OUTPUT={} \ + > /dev/null".format(self.target, u_boot_target, + spl_target,self.temp_dir)) + + if r == signal.SIGINT: + raise KeyboardInterrupt + + if r == 0: + return True + else: + return False + + def path(self, f): + return self.temp_dir + '/' + f + +def get_boards(): + """ extract a list of boards from 'boards.cfg' """ + result = [] + if not os.path.isfile("boards.cfg"): + os.system('tools/genboardscfg.py') + + with open('boards.cfg', 'r') as f: + for l in f.readlines(): + if not l or l[0] == "#": + continue + props = l.split() + if not props: + continue + result.append(board(props[0], props[1], props[2], props[3], + props[4], props[5],props[6])) + return result + +def check_clean_directory(): + """Exit if the source tree is not clean.""" + for f in ('.config', 'include/config'): + if os.path.exists(f): + sys.exit("source tree is not clean, please run 'make mrproper'") + +def main(): + parser = argparse.ArgumentParser(description="Show CONFIG options usage") + parser.add_argument("options", metavar='OPTION', type=str, nargs='+', + help="regexp to filter on options.\ + ex: CONFIG_DM_I2C_COMPAT or '.*DM_MMC.*'") + parser.add_argument("--soc", + help="regexp to filter on SoC.\ + ex: 'omap[45]' to inspect omap5 and omap5 targets") + parser.add_argument("--vendor",help="regexp to filter on Vendor.") + parser.add_argument("--arch", help="regexp to filter on Arch") + parser.add_argument("--cpu", help="regexp to filter on CPU") + parser.add_argument("--board", help="regexp to filter on Board") + parser.add_argument("--target", + help="regexp to filter on Target (config file)") + parser.add_argument("-j","--jobs", + help="number of jobs. default to nb of cpus", + default=multiprocessing.cpu_count()) + parser.add_argument("-v","--values", + help="show the values instead of a 'X' in the csv", + action="store_true") + parser.add_argument("-p","--progress", + help="display progress information", + action="store_true") + parser.add_argument("--keep", help="Don't erase generated configs.", + action="store_true") + parser.add_argument("--nobuild", + help="Don't generate configs, use existing ones. \ + (imply --keep)", action="store_true") + group = parser.add_mutually_exclusive_group() + group.add_argument("--uboot", help="use the u-boot config (default)", + action="store_true", default=True) + group.add_argument("--spl", help="use the SPL config", + action="store_true") + group.add_argument("--spldiff", + help="show only the options that differs between \ + u-boot and SPL", action="store_true") + group.add_argument("--dotconfdiff", + help="show only the options that differs between \ + u-boot.cfg and .config", + action="store_true") + args = parser.parse_args() + + # for some reason making u-boot.cfg doesn't work well if the directory + # is not clean + check_clean_directory() + + #compile a list of regexp used to filter the targets + rules = [] + for f in ["soc","vendor","arch","cpu","board","target"]: + if getattr(args,f): + rules.append((f,re.compile("\\b{}\\b".format(getattr(args,f))))) + + #display the rules to filter the targets + if rules and args.progress: + print("filtering on:", file=sys.stderr) + for prop,r in rules: + print("- {}: {}".format(prop,r.pattern), file=sys.stderr) + + #get a list of boards matching the rules + boards = [b for b in get_boards() if b.match(rules)] + + #create the parsers + cfg_p = cfg_parser(args.options) + dotconfig_p = dotconfig_parser(args.options) + + def process_one_board(b): + if args.dotconfdiff: + if args.nobuild or b.make_uboot_cfg(u_boot = True, spl = True): + uboot_cfg_dic = cfg_p.parse(b.path("u-boot.cfg")) + uboot_dotconf_dic = dotconfig_p.parse(b.path(".config")) + b.result_dic = cmp_options_dic(uboot_cfg_dic,"u-boot.cfg", + uboot_dotconf_dic,".config") + elif args.spldiff: + if args.nobuild or b.make_uboot_cfg(u_boot = True, spl = True): + uboot_dic = cfg_p.parse(b.path("u-boot.cfg")) + spl_dic = cfg_p.parse(b.path("spl/u-boot.cfg")) + b.result_dic = cmp_options_dic(uboot_dic, "U-Boot", + spl_dic, "SPL") + elif args.spl: + if args.nobuild or b.make_uboot_cfg(u_boot = False, spl = True): + b.result_dic = cfg_p.parse(b.path("spl/u-boot.cfg")) + else: + if args.nobuild or b.make_uboot_cfg(u_boot = True, spl = False): + b.result_dic = cfg_p.parse(b.path("u-boot.cfg")) + def worker(): + while True: + b = q.get() + if b is None: + break + try: + if args.progress: + print("{} / {}. Processing {}".format( + len(boards) - (q.qsize() - args.jobs), + len(boards), b.target), file=sys.stderr) + process_one_board(b) + except KeyboardInterrupt: + break + if not args.keep and not args.nobuild: + b.cleanup() + q.task_done() + + q = queue.Queue() + threads = [] + for b in boards: + q.put(b) + # insert "stop worker" markers + for i in range(args.jobs): + q.put(None) + + for i in range(args.jobs): + t = threading.Thread(target=worker) + t.start() + threads.append(t) + + for t in threads: + t.join() + + # create a list of all the options matching our rules and used by at + # least one target + all_options = [] + for b in boards: + if b.result_dic: + all_options.extend(list(b.result_dic.keys())) + + + #generate the CSV file + if args.progress: + print("Generating the CSV", file=sys.stderr) + + csv_columns = list(left_columns) + csv_columns.extend(list(OrderedDict.fromkeys(all_options))) + + dict_data = [] + for b in boards: + d = dict() + if not b.result_dic: + d.update({"target": "{} build failed".format(b.target)}) + continue + for e in left_columns: + d.update({e:getattr(b,e)}) + if args.values: + d.update({k:v if len(v) else "-defined-" for (k,v) in b.result_dic.items()}) + else: + if args.spldiff or args.dotconfdiff: + d.update({k:v.split()[0] for (k,v) in b.result_dic.items()}) + else: + d.update({k:'X' for (k,v) in b.result_dic.items()}) + dict_data.append(d) + + writer = csv.DictWriter(sys.stdout, fieldnames=csv_columns) + writer.writeheader() + for data in dict_data: + writer.writerow(data) + +if __name__ == '__main__': + main() -- 2.7.4

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[U-Boot] [PATCH] dm: fix alignment in DM dump when 2-digit index exists
by Masahiro Yamada 18 Sep '18

18 Sep '18

If there exist 10 or more nodes of the same type, the alignment of "dm tree" command is broken. Signed-off-by: Masahiro Yamada <yamada.masahiro(a)socionext.com> --- drivers/core/dump.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/core/dump.c b/drivers/core/dump.c index d7cdb14..c86f889 100644 --- a/drivers/core/dump.c +++ b/drivers/core/dump.c @@ -16,7 +16,7 @@ static void show_devices(struct udevice *dev, int depth, int last_flag) struct udevice *child; /* print the first 11 characters to not break the tree-format. */ - printf(" %-10.10s %d [ %c ] %-10.10s ", dev->uclass->uc_drv->name, + printf(" %-10.10s %2d [ %c ] %-10.10s ", dev->uclass->uc_drv->name, dev_get_uclass_index(dev, NULL), dev->flags & DM_FLAG_ACTIVATED ? '+' : ' ', dev->driver->name); -- 2.7.4

4 3

[U-Boot] [PATCH] armv8: lx2160a: Add LX2160A SoC Support
by Priyanka Jain 18 Sep '18

18 Sep '18

LX2160A Soc is based on Layerscape Chassis Generation 3.2 Architecture. Features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, two 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao(a)nxp.com> Signed-off-by: Yinbo Zhu <yinbo.zhu(a)nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou(a)nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal(a)nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma(a)nxp.com> Signed-off-by: Sriram Dash <sriram.dash(a)nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain(a)nxp.com> --- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 50 ++++++- arch/arm/cpu/armv8/fsl-layerscape/Makefile | 6 +- arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc | 57 ++++++++ .../cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c | 36 ++++++ arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c | 132 +++++++++++++++++++ arch/arm/dts/fsl-lx2160a.dtsi | 143 +++++++++++++++++++++ arch/arm/include/asm/arch-fsl-layerscape/config.h | 56 ++++++++ arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 3 + .../include/asm/arch-fsl-layerscape/fsl_serdes.h | 28 ++++ .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 28 +++- arch/arm/include/asm/arch-fsl-layerscape/soc.h | 8 +- .../asm/arch-fsl-layerscape/stream_id_lsch3.h | 9 +- drivers/net/ldpaa_eth/Makefile | 3 +- drivers/net/ldpaa_eth/lx2160a.c | 107 +++++++++++++++ 14 files changed, 655 insertions(+), 11 deletions(-) create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c create mode 100644 arch/arm/dts/fsl-lx2160a.dtsi create mode 100644 drivers/net/ldpaa_eth/lx2160a.c diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 81eec78..6c0d6fe 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -170,6 +170,41 @@ config ARCH_LS2080A imply DISTRO_DEFAULTS imply PANIC_HANG +config ARCH_LX2160A + bool + select ARMV8_SET_SMPEN + select FSL_LSCH3 + select NXP_LSCH3_2 + select SYS_HAS_SERDES + select SYS_FSL_SRDS_1 + select SYS_FSL_SRDS_2 + select SYS_NXP_SRDS_3 + select SYS_FSL_DDR + select SYS_FSL_DDR_LE + select SYS_FSL_DDR_VER_50 + select SYS_FSL_EC1 + select SYS_FSL_EC2 + select SYS_FSL_HAS_RGMII + select SYS_FSL_HAS_SEC + select SYS_FSL_HAS_DDR4 + select SYS_FSL_SEC_COMPAT_5 + select SYS_FSL_SEC_LE + select ARCH_EARLY_INIT_R + select BOARD_EARLY_INIT_F + select SYS_I2C_MXC + select SYS_I2C_MXC_I2C1 + select SYS_I2C_MXC_I2C2 + select SYS_I2C_MXC_I2C3 + select SYS_I2C_MXC_I2C4 + select SYS_I2C_MXC_I2C5 + select SYS_I2C_MXC_I2C6 + select SYS_I2C_MXC_I2C7 + select SYS_I2C_MXC_I2C8 + imply DISTRO_DEFAULTS + imply PANIC_HANG + imply SCSI + imply SCSI_AHCI + config FSL_LSCH2 bool select SYS_FSL_HAS_CCI400 @@ -185,7 +220,7 @@ config FSL_LSCH3_2 config FSL_MC_ENET bool "Management Complex network" - depends on ARCH_LS2080A || ARCH_LS1088A + depends on ARCH_LS2080A || ARCH_LS1088A || ARCH_LX2160A default y select RESV_RAM help @@ -202,6 +237,7 @@ config FSL_PCIE_COMPAT default "fsl,ls1046a-pcie" if ARCH_LS1046A default "fsl,ls2080a-pcie" if ARCH_LS2080A default "fsl,ls1088a-pcie" if ARCH_LS1088A + default "fsl,lx2160a-pcie" if ARCH_LX2160A help This compatible is used to find pci controller node in Kernel DT to complete fixup. @@ -300,6 +336,7 @@ config MAX_CPUS default 4 if ARCH_LS1046A default 16 if ARCH_LS2080A default 8 if ARCH_LS1088A + default 16 if ARCH_LX2160A default 1 help Set this number to the maximum number of possible CPUs in the SoC. @@ -404,6 +441,7 @@ config SYS_FSL_DSPI_CLK_DIV config SYS_FSL_DUART_CLK_DIV int "DUART clock divider" default 1 if ARCH_LS1043A + default 4 if ARCH_LX2160A default 2 help This is the divider that is used to derive DUART clock from Platform @@ -464,13 +502,15 @@ config RESV_RAM config SYS_FSL_EC1 bool help - Ethernet controller 1, this is connected to MAC3. + Ethernet controller 1, this is connected to + MAC17 for LX2160A or to MAC3 for other SoCs Provides DPAA2 capabilities config SYS_FSL_EC2 bool help - Ethernet controller 2, this is connected to MAC4. + Ethernet controller 2, this is connected to + MAC18 for LX2160A or to MAC4 for other SoCs Provides DPAA2 capabilities config SYS_FSL_ERRATUM_A008336 @@ -506,13 +546,13 @@ config SYS_FSL_HAS_RGMII config SYS_MC_RSV_MEM_ALIGN hex "Management Complex reserved memory alignment" depends on RESV_RAM - default 0x20000000 if ARCH_LS2080A || ARCH_LS1088A + default 0x20000000 if ARCH_LS2080A || ARCH_LS1088A || ARCH_LX2160A help Reserved memory needs to be aligned for MC to use. Default value is 512MB. config SPL_LDSCRIPT - default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A + default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || ARCH_LX2160A config HAS_FSL_XHCI_USB bool diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile index 5d6f68a..4eaa90c 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0+ -# +# Copyright 2018 NXP # Copyright 2014-2015, Freescale Semiconductor obj-y += cpu.o @@ -22,6 +22,10 @@ obj-$(CONFIG_SYS_HAS_SERDES) += fsl_lsch2_serdes.o endif endif +ifneq ($(CONFIG_ARCH_LX2160A),) +obj-$(CONFIG_SYS_HAS_SERDES) += lx2160a_serdes.o +endif + ifneq ($(CONFIG_ARCH_LS2080A),) obj-$(CONFIG_SYS_HAS_SERDES) += ls2080a_serdes.o endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc index 276ab90..a0e2621 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc +++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc @@ -7,6 +7,7 @@ SoC overview 5. LS1046A 6. LS2088A 7. LS2081A + 8. LX2160A LS1043A --------- @@ -271,3 +272,59 @@ Refer to LS2084A(LS2088A) section above for details. It has one more similar SoC personality 1)LS2041A, few difference w.r.t. LS2081A: a) Four 64-bit ARM v8 Cortex-A72 CPUs + +LX2160A +-------- +The QorIQ LX2160A processor is built in the 16FFC process on +the Layerscape architecture combining sixteen ARM A72 processor +cores with advanced, high-performance datapath acceleration and +network, peripheral interfaces required for networking, wireless +infrastructure, storage, and general-purpose embedded applications. + +LX2160A is compliant with the Layerscape Chassis Generation 3.2. + +The LX2160A SoC includes the following function and features: + Sixteen 32-bit / 64-bit ARM v8 A72 CPUs + Cache Coherent Interconnect Fabric (CCN508 aka “Eliot”) + Two 64-bit 3.2GT/s DDR4 SDRAM memory controllers with ECC. + Data path acceleration architecture (DPAA2) + 24 Serdes lanes at up to 25 GHz + Ethernet interfaces + Single WRIOP tile supporting 130Gbps using 18 MACs + Support for 10G-SXGMII (aka USXGMII). + Support for SGMII (and 1000Base-KX) + Support for XFI (and 10GBase-KR) + Support for CAUI4 (100G); CAUI2 (50G) and 25G-AUI(25G). + Support for XLAUI (and 40GBase-KR4) for 40G. + Support for two RGMII parallel interfaces. + Energy efficient Ethernet support (802.3az) + IEEE 1588 support. + High-speed peripheral interfaces + Two PCIe Gen 4.0 8-lane controllers supporting SR-IOV, + Four PCIe Gen 4.0 4-lane controllers. + Four serial ATA (SATA 3.0) controllers. + Two USB 3.0 controllers with integrated PHY + Two Enhanced secure digital host controllers + Two Controller Area Network (CAN) modules + Flexible Serial peripheral interface (FlexSPI) controller. + Three Serial peripheral interface (SPI) controllers. + Eight I2C Controllers. + Four PL011 UARTs supporting two 4-pin UART ports or four 2-pin UART ports. + General Purpose IO (GPIO) + Support for hardware virtualization and partitioning (ARM MMU-500) + Support for GIC (ARM GIC-500) + QorIQ platform Trust Architecture 3.0 + One Secure WatchDog timer and one Non-Secure Watchdog timer. + ARM Generic Timer + Two Flextimers + Debug supporting run control, data acquisition, high-speed trace, + performance/event monitoring + Thermal Monitor Unit (TMU) with +/- 2C accuracy + Support for Voltage ID (VID) for yield improvement + +LX2160A SoC has 2 more similar SoC personalities +1)LX2120A, few difference w.r.t. LX2160A: + a) Twelve 64-bit ARM v8 Cortex-A72 CPUs + +2)LX2080A, few difference w.r.t. LX2160A: + a) Eight 64-bit ARM v8 Cortex-A72 CPUs diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c index bfd2868..a157c47 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c @@ -22,9 +22,18 @@ static u8 serdes3_prtcl_map[SERDES_PRCTL_COUNT]; #endif #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) +#ifdef CONFIG_ARCH_LX2160A +int xfi_dpmac[XFI14 + 1]; +int sgmii_dpmac[SGMII18 + 1]; +int a25gaui_dpmac[_25GE10 + 1]; +int xlaui_dpmac[_40GE2 + 1]; +int caui2_dpmac[_50GE2 + 1]; +int caui4_dpmac[_100GE2 + 1]; +#else int xfi_dpmac[XFI8 + 1]; int sgmii_dpmac[SGMII16 + 1]; #endif +#endif __weak void wriop_init_dpmac_qsgmii(int sd, int lane_prtcl) { @@ -146,6 +155,32 @@ void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 sd_prctl_mask, else { serdes_prtcl_map[lane_prtcl] = 1; #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) +#ifdef CONFIG_ARCH_LX2160A + if (lane_prtcl >= XFI1 && lane_prtcl <= XFI14) + wriop_init_dpmac(sd, xfi_dpmac[lane_prtcl], + (int)lane_prtcl); + + if (lane_prtcl >= SGMII1 && lane_prtcl <= SGMII18) + wriop_init_dpmac(sd, sgmii_dpmac[lane_prtcl], + (int)lane_prtcl); + + if (lane_prtcl >= _25GE1 && lane_prtcl <= _25GE10) + wriop_init_dpmac(sd, a25gaui_dpmac[lane_prtcl], + (int)lane_prtcl); + + if (lane_prtcl >= _40GE1 && lane_prtcl <= _40GE2) + wriop_init_dpmac(sd, xlaui_dpmac[lane_prtcl], + (int)lane_prtcl); + + if (lane_prtcl >= _50GE1 && lane_prtcl <= _50GE2) + wriop_init_dpmac(sd, caui2_dpmac[lane_prtcl], + (int)lane_prtcl); + + if (lane_prtcl >= _100GE1 && lane_prtcl <= _100GE2) + wriop_init_dpmac(sd, caui4_dpmac[lane_prtcl], + (int)lane_prtcl); + +#else switch (lane_prtcl) { case QSGMII_A: case QSGMII_B: @@ -167,6 +202,7 @@ void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 sd_prctl_mask, break; } #endif +#endif } } diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c new file mode 100644 index 0000000..a04a370 --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +#include <common.h> +#include <asm/arch/fsl_serdes.h> + +struct serdes_config { + u8 protocol; + u8 lanes[SRDS_MAX_LANES]; +}; + +static struct serdes_config serdes1_cfg_tbl[] = { + /* SerDes 1 */ + {0x01, {PCIE2, PCIE2, PCIE2, PCIE2, PCIE1, PCIE1, PCIE1, PCIE1 } }, + {0x02, {PCIE2, PCIE2, PCIE2, PCIE2, SGMII6, SGMII5, SGMII4, SGMII3 } }, + {0x03, {PCIE2, PCIE2, PCIE2, PCIE2, XFI6, XFI5, XFI4, + XFI3 } }, + {0x04, {SGMII10, SGMII9, SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, + SGMII3 } }, + {0x05, {XFI10, XFI9, XFI8, XFI7, PCIE1, PCIE1, PCIE1, + PCIE1 } }, + {0x06, {SGMII10, SGMII9, SGMII8, SGMII7, SGMII6, SGMII5, XFI4, + XFI3 } }, + {0x07, {SGMII10, SGMII9, SGMII8, SGMII7, XFI6, XFI5, XFI4, + XFI3 } }, + {0x08, {XFI10, XFI9, XFI8, XFI7, XFI6, XFI5, XFI4, XFI3 } }, + {0x09, {SGMII10, SGMII9, SGMII8, PCIE2, SGMII6, SGMII5, SGMII4, + PCIE1 } }, + {0x0A, {XFI10, XFI9, XFI8, PCIE2, XFI6, XFI5, XFI4, PCIE1 } }, + {0x0B, {SGMII10, SGMII9, PCIE2, PCIE2, SGMII6, SGMII5, PCIE1, PCIE1 } }, + {0x0C, {SGMII10, SGMII9, PCIE2, PCIE2, PCIE1, PCIE1, PCIE1, PCIE1 } }, + {0x0D, {_100GE2, _100GE2, _100GE2, _100GE2, _100GE1, _100GE1, _100GE1, + _100GE1 } }, + {0x0E, {PCIE2, PCIE2, PCIE2, PCIE2, _100GE1, _100GE1, _100GE1, + _100GE1 } }, + {0x0F, {PCIE2, PCIE2, PCIE2, PCIE2, _50GE2, _50GE2, _50GE1, _50GE1 } }, + {0x10, {PCIE2, PCIE2, PCIE2, PCIE2, _25GE6, _25GE5, _50GE1, _50GE1 } }, + {0x11, {PCIE2, PCIE2, PCIE2, PCIE2, _25GE6, _25GE5, _25GE4, _25GE3 } }, + {0x12, {XFI10, XFI9, XFI8, XFI7, _25GE6, _25GE5, XFI4, + XFI3 } }, + {0x13, {_40GE2, _40GE2, _40GE2, _40GE2, _25GE6, _25GE5, XFI4, XFI3 } }, + {0x14, {_40GE2, _40GE2, _40GE2, _40GE2, _40GE1, _40GE1, _40GE1, + _40GE1 } }, + {0x15, {_25GE10, _25GE9, PCIE2, PCIE2, _25GE6, _25GE5, _25GE4, + _25GE3 } }, + {0x16, {XFI10, XFI9, PCIE2, PCIE2, XFI6, XFI5, XFI4, XFI3 } }, + {} +}; + +static struct serdes_config serdes2_cfg_tbl[] = { + /* SerDes 2 */ + {0x01, {PCIE3, PCIE3, SATA1, SATA2, PCIE4, PCIE4, PCIE4, PCIE4 } }, + {0x02, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3 } }, + {0x03, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4 } }, + {0x04, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2 } }, + {0x05, {PCIE3, PCIE3, PCIE3, PCIE3, SATA3, SATA4, SATA1, SATA2 } }, + {0x06, {PCIE3, PCIE3, PCIE3, PCIE3, SGMII15, SGMII16, XFI13, + XFI14 } }, + {0x07, {PCIE3, SGMII12, SGMII17, SGMII18, PCIE4, SGMII16, XFI13, + XFI14 } }, + {0x08, {NONE, NONE, SATA1, SATA2, SATA3, SATA4, XFI13, XFI14 } }, + {0x09, {SGMII11, SGMII12, SGMII17, SGMII18, SGMII15, SGMII16, SGMII13, + SGMII14} }, + {0x0A, {SGMII11, SGMII12, SGMII17, SGMII18, PCIE4, PCIE4, PCIE4, + PCIE4 } }, + {0x0B, {PCIE3, SGMII12, SGMII17, SGMII18, PCIE4, SGMII16, SGMII13, + SGMII14 } }, + {0x0C, {SGMII11, SGMII12, SGMII17, SGMII18, PCIE4, PCIE4, SATA1, + SATA2 } }, + {0x0D, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SGMII13, SGMII14 } }, + {0x0E, {PCIE3, PCIE3, SGMII17, SGMII18, PCIE4, PCIE4, SGMII13, + SGMII14 } }, + {} +}; + +static struct serdes_config serdes3_cfg_tbl[] = { + /* SerDes 3 */ + {0x02, {PCIE5, PCIE5, PCIE5, PCIE5, PCIE5, PCIE5, PCIE5, PCIE5 } }, + {0x03, {PCIE5, PCIE5, PCIE5, PCIE5, PCIE6, PCIE6, PCIE6, PCIE6 } }, + {} +}; + +static struct serdes_config *serdes_cfg_tbl[] = { + serdes1_cfg_tbl, + serdes2_cfg_tbl, + serdes3_cfg_tbl, +}; + +enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane) +{ + struct serdes_config *ptr; + + if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) + return 0; + + ptr = serdes_cfg_tbl[serdes]; + while (ptr->protocol) { + if (ptr->protocol == cfg) + return ptr->lanes[lane]; + ptr++; + } + + return 0; +} + +int is_serdes_prtcl_valid(int serdes, u32 prtcl) +{ + int i; + struct serdes_config *ptr; + + if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) + return 0; + + ptr = serdes_cfg_tbl[serdes]; + while (ptr->protocol) { + if (ptr->protocol == prtcl) + break; + ptr++; + } + + if (!ptr->protocol) + return 0; + + for (i = 0; i < SRDS_MAX_LANES; i++) { + if (ptr->lanes[i] != NONE) + return 1; + } + + return 0; +} diff --git a/arch/arm/dts/fsl-lx2160a.dtsi b/arch/arm/dts/fsl-lx2160a.dtsi new file mode 100644 index 0000000..db2c274 --- /dev/null +++ b/arch/arm/dts/fsl-lx2160a.dtsi @@ -0,0 +1,143 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP lx2160a SOC common device tree source + * + * Copyright 2018 NXP + * + */ + +/ { + compatible = "fsl,lx2160a"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0 0x80000000>; + /* DRAM space - 1, size : 2 GB DRAM */ + }; + + sysclk: sysclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "sysclk"; + }; + + clockgen: clocking@1300000 { + compatible = "fsl,ls2080a-clockgen"; + reg = <0 0x1300000 0 0xa0000>; + #clock-cells = <2>; + clocks = <&sysclk>; + }; + + gic: interrupt-controller@6000000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ + <0x0 0x06200000 0 0x100000>; /* GICR */ + #interrupt-cells = <3>; + interrupt-controller; + interrupts = <1 9 0x4>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */ + <1 14 0x8>, /* Physical NS PPI, active-low */ + <1 11 0x8>, /* Virtual PPI, active-low */ + <1 10 0x8>; /* Hypervisor PPI, active-low */ + }; + + uart0: serial@21c0000 { + compatible = "arm,pl011"; + reg = <0x0 0x21c0000 0x0 0x1000>; + clocks = <&clockgen 4 0>; + }; + + uart1: serial@21d0000 { + compatible = "arm,pl011"; + reg = <0x0 0x21d0000 0x0 0x1000>; + clocks = <&clockgen 4 0>; + }; + + uart2: serial@21e0000 { + compatible = "arm,pl011"; + reg = <0x0 0x21e0000 0x0 0x1000>; + clocks = <&clockgen 4 0>; + status = "disabled"; + }; + + uart3: serial@21f0000 { + compatible = "arm,pl011"; + reg = <0x0 0x21f0000 0x0 0x1000>; + clocks = <&clockgen 4 0>; + status = "disabled"; + }; + + esdhc0: esdhc@2140000 { + compatible = "fsl,esdhc"; + reg = <0x0 0x2140000 0x0 0x10000>; + interrupts = <0 28 0x4>; /* Level high type */ + clocks = <&clockgen 4 1>; + voltage-ranges = <1800 1800 3300 3300>; + sdhci,auto-cmd12; + little-endian; + bus-width = <4>; + status = "disabled"; + }; + + esdhc1: esdhc@2150000 { + compatible = "fsl,esdhc"; + reg = <0x0 0x2150000 0x0 0x10000>; + interrupts = <0 63 0x4>; /* Level high type */ + clocks = <&clockgen 4 1>; + voltage-ranges = <1800 1800 3300 3300>; + sdhci,auto-cmd12; + non-removable; + little-endian; + bus-width = <4>; + status = "disabled"; + }; + + dspi0: dspi@2100000 { + compatible = "fsl,vf610-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2100000 0x0 0x10000>; + interrupts = <0 26 0x4>; /* Level high type */ + num-cs = <6>; + }; + + dspi1: dspi@2110000 { + compatible = "fsl,vf610-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2110000 0x0 0x10000>; + interrupts = <0 240 0x4>; /* Level high type */ + num-cs = <6>; + }; + + dspi2: dspi@2120000 { + compatible = "fsl,vf610-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2120000 0x0 0x10000>; + interrupts = <0 241 0x4>; /* Level high type */ + num-cs = <6>; + }; + + usb0: usb3@3100000 { + compatible = "fsl,layerscape-dwc3"; + reg = <0x0 0x3100000 0x0 0x10000>; + interrupts = <0 80 0x4>; /* Level high type */ + dr_mode = "host"; + }; + + usb1: usb3@3110000 { + compatible = "fsl,layerscape-dwc3"; + reg = <0x0 0x3110000 0x0 0x10000>; + interrupts = <0 81 0x4>; /* Level high type */ + dr_mode = "host"; + }; +}; diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 8a05148..dbfad99 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* + * Copyright 2018 NXP * Copyright 2015, Freescale Semiconductor */ @@ -176,6 +177,61 @@ #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */ #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */ +/* LX2160A Soc Support */ +#elif defined(CONFIG_ARCH_LX2160A) +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_EARLY_INIT +#define SRDS_MAX_LANES 8 +#ifndef L1_CACHE_BYTES +#define L1_CACHE_SHIFT 6 +#define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT) +#endif +#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2 +#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1, 4, 4, 4, 4 } +#define CONFIG_SYS_FSL_NUM_CC_PLLS 4 + +#define CONFIG_SYS_PAGE_SIZE 0x10000 + +#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ +#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */ +#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00040000 /* Real size 256K */ + +/* DDR */ +#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) +#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE + +#define CONFIG_SYS_FSL_CCSR_GUR_LE +#define CONFIG_SYS_FSL_CCSR_SCFG_LE +#define CONFIG_SYS_FSL_ESDHC_LE +#define CONFIG_SYS_FSL_PEX_LUT_LE + +#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN + +/* Generic Interrupt Controller Definitions */ +#define GICD_BASE 0x06000000 +#define GICR_BASE 0x06200000 + +/* SMMU Definitions */ +#define SMMU_BASE 0x05000000 /* GR0 Base */ + +/* SFP */ +#define CONFIG_SYS_FSL_SFP_VER_3_4 +#define CONFIG_SYS_FSL_SFP_LE +#define CONFIG_SYS_FSL_SRK_LE + +/* Security Monitor */ +#define CONFIG_SYS_FSL_SEC_MON_LE + +/* Secure Boot */ +#define CONFIG_ESBC_HDR_LS + +/* DCFG - GUR */ +#define CONFIG_SYS_FSL_CCSR_GUR_LE + +#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 + +/* end LX2160A Soc Support */ + #elif defined(CONFIG_FSL_LSCH2) #define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */ #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h index ed1a21d..271d077 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h @@ -27,6 +27,9 @@ static struct cpu_type cpu_type_list[] = { CPU_TYPE_ENTRY(LS1084A, LS1084A, 8), CPU_TYPE_ENTRY(LS1048A, LS1048A, 4), CPU_TYPE_ENTRY(LS1044A, LS1044A, 4), + CPU_TYPE_ENTRY(LX2160A, LX2160A, 16), + CPU_TYPE_ENTRY(LX2120A, LX2120A, 12), + CPU_TYPE_ENTRY(LX2080A, LX2080A, 8), }; #ifndef CONFIG_SYS_DCACHE_OFF diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h index bec35e8..8dbabd7 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h @@ -20,8 +20,12 @@ enum srds_prtcl { PCIE2, PCIE3, PCIE4, + PCIE5, + PCIE6, SATA1, SATA2, + SATA3, + SATA4, XAUI1, XAUI2, XFI1, @@ -32,6 +36,12 @@ enum srds_prtcl { XFI6, XFI7, XFI8, + XFI9, + XFI10, + XFI11, + XFI12, + XFI13, + XFI14, SGMII1, SGMII2, SGMII3, @@ -48,10 +58,28 @@ enum srds_prtcl { SGMII14, SGMII15, SGMII16, + SGMII17, + SGMII18, QSGMII_A, QSGMII_B, QSGMII_C, QSGMII_D, + _25GE1, + _25GE2, + _25GE3, + _25GE4, + _25GE5, + _25GE6, + _25GE7, + _25GE8, + _25GE9, + _25GE10, + _40GE1, + _40GE2, + _50GE1, + _50GE2, + _100GE1, + _100GE2, SERDES_PRCTL_COUNT }; diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 8740dd7..56b2deb 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -2,7 +2,7 @@ /* * LayerScape Internal Memory Map * - * Copyright (C) 2017 NXP Semiconductors + * Copyright 2017-2018 NXP * Copyright 2014 Freescale Semiconductor, Inc. */ @@ -15,7 +15,11 @@ #define CONFIG_SYS_FSL_DDR3_ADDR 0x08210000 #define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00E00000) #define CONFIG_SYS_FSL_PMU_ADDR (CONFIG_SYS_IMMR + 0x00E30000) +#ifdef CONFIG_ARCH_LX2160A +#define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00e88180) +#else #define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00E60000) +#endif #define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR (CONFIG_SYS_IMMR + 0x00300000) #define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR (CONFIG_SYS_IMMR + 0x00310000) #define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x00370000) @@ -275,6 +279,28 @@ struct ccsr_gur { #define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT #define FSL_CHASSIS3_SRDS1_REGSR 29 #define FSL_CHASSIS3_SRDS2_REGSR 29 +#elif defined(CONFIG_ARCH_LX2160A) +#define FSL_CHASSIS3_EC1_REGSR 27 +#define FSL_CHASSIS3_EC2_REGSR 27 +#define FSL_CHASSIS3_EC1_REGSR_PRTCL_MASK 0x00000003 +#define FSL_CHASSIS3_EC1_REGSR_PRTCL_SHIFT 0 +#define FSL_CHASSIS3_EC2_REGSR_PRTCL_MASK 0x00000007 +#define FSL_CHASSIS3_EC2_REGSR_PRTCL_SHIFT 2 +#define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK 0x001F0000 +#define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT 16 +#define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK 0x03E00000 +#define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT 21 +#define FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_MASK 0x7C000000 +#define FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_SHIFT 26 +#define FSL_CHASSIS3_SRDS1_PRTCL_MASK FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK +#define FSL_CHASSIS3_SRDS1_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT +#define FSL_CHASSIS3_SRDS2_PRTCL_MASK FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK +#define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT +#define FSL_CHASSIS3_SRDS3_PRTCL_MASK FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_MASK +#define FSL_CHASSIS3_SRDS3_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_SHIFT +#define FSL_CHASSIS3_SRDS1_REGSR 29 +#define FSL_CHASSIS3_SRDS2_REGSR 29 +#define FSL_CHASSIS3_SRDS3_REGSR 29 #elif defined(CONFIG_ARCH_LS1088A) #define FSL_CHASSIS3_EC1_REGSR 26 #define FSL_CHASSIS3_EC2_REGSR 26 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index 61b6e4b..3de7c56 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2017 NXP + * Copyright 2017-2018 NXP * Copyright 2015 Freescale Semiconductor */ @@ -74,12 +74,18 @@ struct cpu_type { #define SVR_LS2044A 0x870930 #define SVR_LS2081A 0x870918 #define SVR_LS2041A 0x870914 +#define SVR_LX2160A 0x873601 +#define SVR_LX2120A 0x873621 +#define SVR_LX2080A 0x873603 #define SVR_MAJ(svr) (((svr) >> 4) & 0xf) #define SVR_MIN(svr) (((svr) >> 0) & 0xf) #define SVR_REV(svr) (((svr) >> 0) & 0xff) #define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E) #define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1)) +#ifdef CONFIG_ARCH_LX2160A +#define IS_C_PROCESSOR(svr) (!((svr >> 12) & 0x1)) +#endif #define IS_SVR_REV(svr, maj, min) \ ((SVR_MAJ(svr) == (maj)) && (SVR_MIN(svr) == (min))) #define SVR_DEV(svr) ((svr) >> 8) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h index afea9b8..227b438 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* + * Copyright 2018 NXP * Copyright 2014 Freescale Semiconductor, Inc. * */ @@ -66,11 +67,11 @@ #define FSL_SDMMC_STREAM_ID 3 #define FSL_SATA1_STREAM_ID 4 -#if defined(CONFIG_ARCH_LS2080A) +#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A) #define FSL_SATA2_STREAM_ID 5 #endif -#if defined(CONFIG_ARCH_LS2080A) +#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A) #define FSL_DMA_STREAM_ID 6 #elif defined(CONFIG_ARCH_LS1088A) #define FSL_DMA_STREAM_ID 5 @@ -79,6 +80,10 @@ /* PCI - programmed in PEXn_LUT */ #define FSL_PEX_STREAM_ID_START 7 +#ifdef CONFIG_ARCH_LX2160A +#define FSL_PEX_STREAM_ID_NUM (0x100) +#endif + #if defined(CONFIG_ARCH_LS2080A) #define FSL_PEX_STREAM_ID_END 22 #elif defined(CONFIG_ARCH_LS1088A) diff --git a/drivers/net/ldpaa_eth/Makefile b/drivers/net/ldpaa_eth/Makefile index 477ee4f..8e00f17 100644 --- a/drivers/net/ldpaa_eth/Makefile +++ b/drivers/net/ldpaa_eth/Makefile @@ -1,8 +1,9 @@ # SPDX-License-Identifier: GPL-2.0+ -# +# Copyright 2018 NXP # Copyright 2014 Freescale Semiconductor, Inc. obj-y += ldpaa_wriop.o obj-y += ldpaa_eth.o obj-$(CONFIG_ARCH_LS2080A) += ls2080a.o obj-$(CONFIG_ARCH_LS1088A) += ls1088a.o +obj-$(CONFIG_ARCH_LX2160A) += lx2160a.o diff --git a/drivers/net/ldpaa_eth/lx2160a.c b/drivers/net/ldpaa_eth/lx2160a.c new file mode 100644 index 0000000..7dd46c0 --- /dev/null +++ b/drivers/net/ldpaa_eth/lx2160a.c @@ -0,0 +1,107 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ +#include <common.h> +#include <phy.h> +#include <fsl-mc/ldpaa_wriop.h> +#include <asm/io.h> +#include <asm/arch/fsl_serdes.h> +#include <asm/arch/soc.h> + +u32 dpmac_to_devdisr[] = { + [WRIOP1_DPMAC1] = FSL_CHASSIS3_DEVDISR2_DPMAC1, + [WRIOP1_DPMAC2] = FSL_CHASSIS3_DEVDISR2_DPMAC2, + [WRIOP1_DPMAC3] = FSL_CHASSIS3_DEVDISR2_DPMAC3, + [WRIOP1_DPMAC4] = FSL_CHASSIS3_DEVDISR2_DPMAC4, + [WRIOP1_DPMAC5] = FSL_CHASSIS3_DEVDISR2_DPMAC5, + [WRIOP1_DPMAC6] = FSL_CHASSIS3_DEVDISR2_DPMAC6, + [WRIOP1_DPMAC7] = FSL_CHASSIS3_DEVDISR2_DPMAC7, + [WRIOP1_DPMAC8] = FSL_CHASSIS3_DEVDISR2_DPMAC8, + [WRIOP1_DPMAC9] = FSL_CHASSIS3_DEVDISR2_DPMAC9, + [WRIOP1_DPMAC10] = FSL_CHASSIS3_DEVDISR2_DPMAC10, + [WRIOP1_DPMAC11] = FSL_CHASSIS3_DEVDISR2_DPMAC11, + [WRIOP1_DPMAC12] = FSL_CHASSIS3_DEVDISR2_DPMAC12, + [WRIOP1_DPMAC13] = FSL_CHASSIS3_DEVDISR2_DPMAC13, + [WRIOP1_DPMAC14] = FSL_CHASSIS3_DEVDISR2_DPMAC14, + [WRIOP1_DPMAC15] = FSL_CHASSIS3_DEVDISR2_DPMAC15, + [WRIOP1_DPMAC16] = FSL_CHASSIS3_DEVDISR2_DPMAC16, + [WRIOP1_DPMAC17] = FSL_CHASSIS3_DEVDISR2_DPMAC17, + [WRIOP1_DPMAC18] = FSL_CHASSIS3_DEVDISR2_DPMAC18, +}; + +static int is_device_disabled(int dpmac_id) +{ + struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; + u32 devdisr2 = in_le32(&gur->devdisr2); + + return dpmac_to_devdisr[dpmac_id] & devdisr2; +} + +void wriop_dpmac_disable(int dpmac_id) +{ + struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; + + setbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]); +} + +void wriop_dpmac_enable(int dpmac_id) +{ + struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; + + clrbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]); +} + +phy_interface_t wriop_dpmac_enet_if(int dpmac_id, int lane_prtcl) +{ + enum srds_prtcl; + + if (is_device_disabled(dpmac_id + 1)) + return PHY_INTERFACE_MODE_NONE; + + if (lane_prtcl >= SGMII1 && lane_prtcl <= SGMII18) + return PHY_INTERFACE_MODE_SGMII; + + if (lane_prtcl >= XFI1 && lane_prtcl <= XFI14) + return PHY_INTERFACE_MODE_XGMII; + + if (lane_prtcl >= _25GE1 && lane_prtcl <= _25GE10) + return PHY_INTERFACE_MODE_25G_AUI; + + if (lane_prtcl >= _40GE1 && lane_prtcl <= _40GE2) + return PHY_INTERFACE_MODE_XLAUI; + + if (lane_prtcl >= _50GE1 && lane_prtcl <= _50GE2) + return PHY_INTERFACE_MODE_CAUI2; + + if (lane_prtcl >= _100GE1 && lane_prtcl <= _100GE2) + return PHY_INTERFACE_MODE_CAUI4; + + return PHY_INTERFACE_MODE_NONE; +} + +#ifdef CONFIG_SYS_FSL_HAS_RGMII +void fsl_rgmii_init(void) +{ + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + u32 ec; + +#ifdef CONFIG_SYS_FSL_EC1 + ec = gur_in32(&gur->rcwsr[FSL_CHASSIS3_EC1_REGSR - 1]) + & FSL_CHASSIS3_EC1_REGSR_PRTCL_MASK; + ec >>= FSL_CHASSIS3_EC1_REGSR_PRTCL_SHIFT; + + if (!ec) + wriop_init_dpmac_enet_if(17, PHY_INTERFACE_MODE_RGMII_ID); +#endif + +#ifdef CONFIG_SYS_FSL_EC2 + ec = gur_in32(&gur->rcwsr[FSL_CHASSIS3_EC2_REGSR - 1]) + & FSL_CHASSIS3_EC2_REGSR_PRTCL_MASK; + ec >>= FSL_CHASSIS3_EC2_REGSR_PRTCL_SHIFT; + + if (!ec) + wriop_init_dpmac_enet_if(18, PHY_INTERFACE_MODE_RGMII_ID); +#endif +} +#endif -- 2.7.4

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[U-Boot] git clone http://git.denx.de/u-boot-dm.git fails.
by Heinrich Schuchardt 17 Sep '18

17 Sep '18

Hello Wolfgang, I have a slight problem with the U-Boot git: git clone http://git.denx.de/u-boot-dm.git fails. Why is this incorrect link shown on http://git.denx.de/?p=u-boot/u-boot-dm.git;a=summary? $ git clone http://git.denx.de/u-boot-dm.git foo Cloning into 'foo'... warning: alternate disabled by http.followRedirects: http://git.denx.de/u-boot.git/ error: Unable to find be360d9824d653780ebd3ffc08f1938a8e3dd747 under http://git.denx.de/u-boot-dm.git Cannot obtain needed object be360d9824d653780ebd3ffc08f1938a8e3dd747 while processing commit c23172cd972acc921156034cd0e4a9a16d2a4f56. error: fetch failed. Using git://git.denx.de/u-boot-dm.git is not an option because port 9418 is not available through many firewalls. I suggest to use https as transfer protocol. Best regards Heinrich

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[U-Boot] Modulos and rsquared in rsa-verify.c
by Bondugula, Naga Raju Rajesh 17 Sep '18

17 Sep '18

Hi team, I am trying to use rsa utility functions and need help in using modulus and rsquared in right format Say this is modulus that I need to incorporate. How should the modules buffer look like? modulus: 00:d8:63:96:ce:e5:ec:04:af:17:83:f2:54:e3:49: f1:27:26:31:48:fc:43:78:8a:fd:35:5c:ba:05:77: d9:ca:df:61:8c:65:a5:9c:8c:b1:09:c6:2e:81:cd: 2d:14:a4:72:1a:2b:1c:ed:bf:fc:4e:47:87:e8:94: 50:12:34:c7:5b There are 4 possible options. (considering all orders). Which is the right way to use modulus value. I plan to hardcode in the code instead of using I from dtsi (for testing) 1. Ptr[0] wil have digits with highest value Uint32_t *ptr = {0xd86396ce, …., …., …. , 0x1234c75b} 1. Same as 1) but with different endian ness. Uint32_t *ptr = {0xce9663d8, …, …, …, 0x5bc73412} 1. pre[0] will have digits with lowest value. Uint32_t *ptr = {0x1234c75b, …., …., …. , 0xd86396ce } 1. Same as 3) but with different endian ness. Uint32_t *ptr = {0x5bc73412, …, …, …, 0xce9663d8}

1 0

[U-Boot] [PATCH v2 1/1] efi_loader: refactor efi_setup_loaded_image()
by Heinrich Schuchardt 17 Sep '18

17 Sep '18

Create the handle of loaded images and the EFI_LOADED_IMAGE_PROTOCOL inside efi_setup_loaded_image(). Do not use local variables. Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- v2 avoid unused variables if configured without CONFIG_EFI_SELFTEST --- cmd/bootefi.c | 61 +++++++++++++++++++---------------- include/efi_loader.h | 8 ++--- lib/efi_loader/efi_boottime.c | 48 ++++++++++++++------------- 3 files changed, 64 insertions(+), 53 deletions(-) diff --git a/cmd/bootefi.c b/cmd/bootefi.c index a890f414e8..719efc16f3 100644 --- a/cmd/bootefi.c +++ b/cmd/bootefi.c @@ -342,19 +342,26 @@ static efi_status_t efi_install_fdt(ulong fdt_addr) return ret; } -/* - * Load an EFI payload into a newly allocated piece of memory, register all - * EFI objects it would want to access and jump to it. +/** + * do_bootefi_exec() - execute EFI binary + * + * @efi: address of the binary + * @device_path: path of the device from which the binary was loaded + * @image_path: device path of the binary + * Return: status code + * + * Load the EFI binary into a newly assigned memory unwinding the relocation + * information, install the loaded image protocol, and call the binary. */ static efi_status_t do_bootefi_exec(void *efi, struct efi_device_path *device_path, struct efi_device_path *image_path) { - struct efi_loaded_image loaded_image_info = {}; - struct efi_object loaded_image_info_obj = {}; efi_handle_t mem_handle = NULL; struct efi_device_path *memdp = NULL; efi_status_t ret; + efi_handle_t image_handle; + struct efi_loaded_image *loaded_image_info; EFIAPI efi_status_t (*entry)(efi_handle_t image_handle, struct efi_system_table *st); @@ -384,8 +391,8 @@ static efi_status_t do_bootefi_exec(void *efi, assert(device_path && image_path); } - efi_setup_loaded_image(&loaded_image_info, &loaded_image_info_obj, - device_path, image_path); + efi_setup_loaded_image(device_path, image_path, &image_handle, + &loaded_image_info); /* * gd lives in a fixed register which may get clobbered while we execute @@ -394,9 +401,9 @@ static efi_status_t do_bootefi_exec(void *efi, efi_save_gd(); /* Transfer environment variable bootargs as load options */ - set_load_options(&loaded_image_info, "bootargs"); + set_load_options(loaded_image_info, "bootargs"); /* Load the EFI payload */ - entry = efi_load_pe(efi, &loaded_image_info); + entry = efi_load_pe(efi, loaded_image_info); if (!entry) { ret = EFI_LOAD_ERROR; goto exit; @@ -404,10 +411,10 @@ static efi_status_t do_bootefi_exec(void *efi, if (memdp) { struct efi_device_path_memory *mdp = (void *)memdp; - mdp->memory_type = loaded_image_info.image_code_type; - mdp->start_address = (uintptr_t)loaded_image_info.image_base; + mdp->memory_type = loaded_image_info->image_code_type; + mdp->start_address = (uintptr_t)loaded_image_info->image_base; mdp->end_address = mdp->start_address + - loaded_image_info.image_size; + loaded_image_info->image_size; } /* we don't support much: */ @@ -417,8 +424,8 @@ static efi_status_t do_bootefi_exec(void *efi, /* Call our payload! */ debug("%s:%d Jumping to 0x%lx\n", __func__, __LINE__, (long)entry); - if (setjmp(&loaded_image_info.exit_jmp)) { - ret = loaded_image_info.exit_status; + if (setjmp(&loaded_image_info->exit_jmp)) { + ret = loaded_image_info->exit_status; goto exit; } @@ -430,7 +437,7 @@ static efi_status_t do_bootefi_exec(void *efi, /* Move into EL2 and keep running there */ armv8_switch_to_el2((ulong)entry, - (ulong)&loaded_image_info_obj.handle, + (ulong)&image_handle, (ulong)&systab, 0, (ulong)efi_run_in_el2, ES_TO_AARCH64); @@ -447,7 +454,7 @@ static efi_status_t do_bootefi_exec(void *efi, secure_ram_addr(_do_nonsec_entry)( efi_run_in_hyp, (uintptr_t)entry, - (uintptr_t)loaded_image_info_obj.handle, + (uintptr_t)image_handle, (uintptr_t)&systab); /* Should never reach here, efi exits with longjmp */ @@ -455,11 +462,12 @@ static efi_status_t do_bootefi_exec(void *efi, } #endif - ret = efi_do_enter(loaded_image_info_obj.handle, &systab, entry); + ret = efi_do_enter(image_handle, &systab, entry); exit: /* image has returned, loaded-image obj goes *poof*: */ - list_del(&loaded_image_info_obj.link); + if (image_handle) + efi_delete_handle(image_handle); if (mem_handle) efi_delete_handle(mem_handle); @@ -544,8 +552,8 @@ static int do_bootefi(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #endif #ifdef CONFIG_CMD_BOOTEFI_SELFTEST if (!strcmp(argv[1], "selftest")) { - struct efi_loaded_image loaded_image_info = {}; - struct efi_object loaded_image_info_obj = {}; + efi_handle_t image_handle; + struct efi_loaded_image *loaded_image_info; /* Construct a dummy device path. */ bootefi_device_path = efi_dp_from_mem(EFI_RESERVED_MEMORY_TYPE, @@ -553,9 +561,8 @@ static int do_bootefi(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) (uintptr_t)&efi_selftest); bootefi_image_path = efi_dp_from_file(NULL, 0, "\\selftest"); - efi_setup_loaded_image(&loaded_image_info, - &loaded_image_info_obj, - bootefi_device_path, bootefi_image_path); + efi_setup_loaded_image(bootefi_device_path, bootefi_image_path, + &image_handle, &loaded_image_info); /* * gd lives in a fixed register which may get clobbered while we * execute the payload. So save it here and restore it on every @@ -563,12 +570,12 @@ static int do_bootefi(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) */ efi_save_gd(); /* Transfer environment variable efi_selftest as load options */ - set_load_options(&loaded_image_info, "efi_selftest"); + set_load_options(loaded_image_info, "efi_selftest"); /* Execute the test */ - r = efi_selftest(loaded_image_info_obj.handle, &systab); + r = efi_selftest(image_handle, &systab); efi_restore_gd(); - free(loaded_image_info.load_options); - list_del(&loaded_image_info_obj.link); + free(loaded_image_info->load_options); + efi_delete_handle(image_handle); return r != EFI_SUCCESS; } else #endif diff --git a/include/efi_loader.h b/include/efi_loader.h index f0d086daff..e5bc7d043e 100644 --- a/include/efi_loader.h +++ b/include/efi_loader.h @@ -342,10 +342,10 @@ int efi_memory_init(void); /* Adds new or overrides configuration table entry to the system table */ efi_status_t efi_install_configuration_table(const efi_guid_t *guid, void *table); /* Sets up a loaded image */ -efi_status_t efi_setup_loaded_image( - struct efi_loaded_image *info, struct efi_object *obj, - struct efi_device_path *device_path, - struct efi_device_path *file_path); +efi_status_t efi_setup_loaded_image(struct efi_device_path *device_path, + struct efi_device_path *file_path, + efi_handle_t *handle_ptr, + struct efi_loaded_image **info_ptr); efi_status_t efi_load_image_from_path(struct efi_device_path *file_path, void **buffer); /* Print information about a loaded image */ diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c index 3bcea647c8..730124a119 100644 --- a/lib/efi_loader/efi_boottime.c +++ b/lib/efi_loader/efi_boottime.c @@ -1478,18 +1478,34 @@ static efi_status_t EFIAPI efi_install_configuration_table_ext(efi_guid_t *guid, * * Return: status code */ -efi_status_t efi_setup_loaded_image( - struct efi_loaded_image *info, struct efi_object *obj, - struct efi_device_path *device_path, - struct efi_device_path *file_path) +efi_status_t efi_setup_loaded_image(struct efi_device_path *device_path, + struct efi_device_path *file_path, + efi_handle_t *handle_ptr, + struct efi_loaded_image **info_ptr) { efi_status_t ret; + struct efi_loaded_image *info; + struct efi_object *obj; + + info = calloc(1, sizeof(*info)); + if (!info) + return EFI_OUT_OF_RESOURCES; + obj = calloc(1, sizeof(*obj)); + if (!obj) { + free(info); + return EFI_OUT_OF_RESOURCES; + } /* Add internal object to object list */ efi_add_handle(obj); /* efi_exit() assumes that the handle points to the info */ obj->handle = info; + if (handle_ptr) + *handle_ptr = obj->handle; + if (info_ptr) + *info_ptr = info; + info->revision = EFI_LOADED_IMAGE_PROTOCOL_REVISION; info->file_path = file_path; info->system_table = &systab; @@ -1629,7 +1645,6 @@ static efi_status_t EFIAPI efi_load_image(bool boot_policy, efi_handle_t *image_handle) { struct efi_loaded_image *info; - struct efi_object *obj; efi_status_t ret; EFI_ENTRY("%d, %p, %pD, %p, %zd, %p", boot_policy, parent_image, @@ -1645,18 +1660,6 @@ static efi_status_t EFIAPI efi_load_image(bool boot_policy, goto error; } - info = calloc(1, sizeof(*info)); - if (!info) { - ret = EFI_OUT_OF_RESOURCES; - goto error; - } - obj = calloc(1, sizeof(*obj)); - if (!obj) { - free(info); - ret = EFI_OUT_OF_RESOURCES; - goto error; - } - if (!source_buffer) { struct efi_device_path *dp, *fp; @@ -1668,16 +1671,17 @@ static efi_status_t EFIAPI efi_load_image(bool boot_policy, * file parts: */ efi_dp_split_file_path(file_path, &dp, &fp); - ret = efi_setup_loaded_image(info, obj, dp, fp); + ret = efi_setup_loaded_image(dp, fp, image_handle, &info); if (ret != EFI_SUCCESS) goto failure; } else { /* In this case, file_path is the "device" path, i.e. * something like a HARDWARE_DEVICE:MEMORY_MAPPED */ - ret = efi_setup_loaded_image(info, obj, file_path, NULL); + ret = efi_setup_loaded_image(file_path, NULL, image_handle, + &info); if (ret != EFI_SUCCESS) - goto failure; + goto error; } info->reserved = efi_load_pe(source_buffer, info); if (!info->reserved) { @@ -1686,11 +1690,11 @@ static efi_status_t EFIAPI efi_load_image(bool boot_policy, } info->system_table = &systab; info->parent_handle = parent_image; - *image_handle = obj->handle; return EFI_EXIT(EFI_SUCCESS); failure: + efi_delete_handle(*image_handle); + *image_handle = NULL; free(info); - efi_delete_handle(obj); error: return EFI_EXIT(ret); } -- 2.18.0

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[U-Boot] [PATCH 1/1] efi_loader: refactor efi_setup_loaded_image()
by Heinrich Schuchardt 17 Sep '18

17 Sep '18

Create the handle of loaded images and the EFI_LOADED_IMAGE_PROTOCOL inside efi_setup_loaded_image(). Do not use local variables. Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- cmd/bootefi.c | 61 +++++++++++++++++++---------------- include/efi_loader.h | 8 ++--- lib/efi_loader/efi_boottime.c | 48 ++++++++++++++------------- 3 files changed, 64 insertions(+), 53 deletions(-) diff --git a/cmd/bootefi.c b/cmd/bootefi.c index a890f414e8..db753aaf7c 100644 --- a/cmd/bootefi.c +++ b/cmd/bootefi.c @@ -342,19 +342,26 @@ static efi_status_t efi_install_fdt(ulong fdt_addr) return ret; } -/* - * Load an EFI payload into a newly allocated piece of memory, register all - * EFI objects it would want to access and jump to it. +/** + * do_bootefi_exec() - execute EFI binary + * + * @efi: address of the binary + * @device_path: path of the device from which the binary was loaded + * @image_path: device path of the binary + * Return: status code + * + * Load the EFI binary into a newly assigned memory unwinding the relocation + * information, install the loaded image protocol, and call the binary. */ static efi_status_t do_bootefi_exec(void *efi, struct efi_device_path *device_path, struct efi_device_path *image_path) { - struct efi_loaded_image loaded_image_info = {}; - struct efi_object loaded_image_info_obj = {}; efi_handle_t mem_handle = NULL; struct efi_device_path *memdp = NULL; efi_status_t ret; + efi_handle_t image_handle; + struct efi_loaded_image *loaded_image_info; EFIAPI efi_status_t (*entry)(efi_handle_t image_handle, struct efi_system_table *st); @@ -384,8 +391,8 @@ static efi_status_t do_bootefi_exec(void *efi, assert(device_path && image_path); } - efi_setup_loaded_image(&loaded_image_info, &loaded_image_info_obj, - device_path, image_path); + efi_setup_loaded_image(device_path, image_path, &image_handle, + &loaded_image_info); /* * gd lives in a fixed register which may get clobbered while we execute @@ -394,9 +401,9 @@ static efi_status_t do_bootefi_exec(void *efi, efi_save_gd(); /* Transfer environment variable bootargs as load options */ - set_load_options(&loaded_image_info, "bootargs"); + set_load_options(loaded_image_info, "bootargs"); /* Load the EFI payload */ - entry = efi_load_pe(efi, &loaded_image_info); + entry = efi_load_pe(efi, loaded_image_info); if (!entry) { ret = EFI_LOAD_ERROR; goto exit; @@ -404,10 +411,10 @@ static efi_status_t do_bootefi_exec(void *efi, if (memdp) { struct efi_device_path_memory *mdp = (void *)memdp; - mdp->memory_type = loaded_image_info.image_code_type; - mdp->start_address = (uintptr_t)loaded_image_info.image_base; + mdp->memory_type = loaded_image_info->image_code_type; + mdp->start_address = (uintptr_t)loaded_image_info->image_base; mdp->end_address = mdp->start_address + - loaded_image_info.image_size; + loaded_image_info->image_size; } /* we don't support much: */ @@ -417,8 +424,8 @@ static efi_status_t do_bootefi_exec(void *efi, /* Call our payload! */ debug("%s:%d Jumping to 0x%lx\n", __func__, __LINE__, (long)entry); - if (setjmp(&loaded_image_info.exit_jmp)) { - ret = loaded_image_info.exit_status; + if (setjmp(&loaded_image_info->exit_jmp)) { + ret = loaded_image_info->exit_status; goto exit; } @@ -430,7 +437,7 @@ static efi_status_t do_bootefi_exec(void *efi, /* Move into EL2 and keep running there */ armv8_switch_to_el2((ulong)entry, - (ulong)&loaded_image_info_obj.handle, + (ulong)&image_handle, (ulong)&systab, 0, (ulong)efi_run_in_el2, ES_TO_AARCH64); @@ -447,7 +454,7 @@ static efi_status_t do_bootefi_exec(void *efi, secure_ram_addr(_do_nonsec_entry)( efi_run_in_hyp, (uintptr_t)entry, - (uintptr_t)loaded_image_info_obj.handle, + (uintptr_t)image_handle, (uintptr_t)&systab); /* Should never reach here, efi exits with longjmp */ @@ -455,11 +462,12 @@ static efi_status_t do_bootefi_exec(void *efi, } #endif - ret = efi_do_enter(loaded_image_info_obj.handle, &systab, entry); + ret = efi_do_enter(image_handle, &systab, entry); exit: /* image has returned, loaded-image obj goes *poof*: */ - list_del(&loaded_image_info_obj.link); + if (image_handle) + efi_delete_handle(image_handle); if (mem_handle) efi_delete_handle(mem_handle); @@ -500,6 +508,8 @@ static int do_bootefi(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) char *saddr; efi_status_t r; unsigned long fdt_addr; + efi_handle_t image_handle; + struct efi_loaded_image *loaded_image_info; /* Allow unaligned memory access */ allow_unaligned(); @@ -544,8 +554,6 @@ static int do_bootefi(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #endif #ifdef CONFIG_CMD_BOOTEFI_SELFTEST if (!strcmp(argv[1], "selftest")) { - struct efi_loaded_image loaded_image_info = {}; - struct efi_object loaded_image_info_obj = {}; /* Construct a dummy device path. */ bootefi_device_path = efi_dp_from_mem(EFI_RESERVED_MEMORY_TYPE, @@ -553,9 +561,8 @@ static int do_bootefi(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) (uintptr_t)&efi_selftest); bootefi_image_path = efi_dp_from_file(NULL, 0, "\\selftest"); - efi_setup_loaded_image(&loaded_image_info, - &loaded_image_info_obj, - bootefi_device_path, bootefi_image_path); + efi_setup_loaded_image(bootefi_device_path, bootefi_image_path, + &image_handle, &loaded_image_info); /* * gd lives in a fixed register which may get clobbered while we * execute the payload. So save it here and restore it on every @@ -563,12 +570,12 @@ static int do_bootefi(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) */ efi_save_gd(); /* Transfer environment variable efi_selftest as load options */ - set_load_options(&loaded_image_info, "efi_selftest"); + set_load_options(loaded_image_info, "efi_selftest"); /* Execute the test */ - r = efi_selftest(loaded_image_info_obj.handle, &systab); + r = efi_selftest(image_handle, &systab); efi_restore_gd(); - free(loaded_image_info.load_options); - list_del(&loaded_image_info_obj.link); + free(loaded_image_info->load_options); + efi_delete_handle(image_handle); return r != EFI_SUCCESS; } else #endif diff --git a/include/efi_loader.h b/include/efi_loader.h index f0d086daff..e5bc7d043e 100644 --- a/include/efi_loader.h +++ b/include/efi_loader.h @@ -342,10 +342,10 @@ int efi_memory_init(void); /* Adds new or overrides configuration table entry to the system table */ efi_status_t efi_install_configuration_table(const efi_guid_t *guid, void *table); /* Sets up a loaded image */ -efi_status_t efi_setup_loaded_image( - struct efi_loaded_image *info, struct efi_object *obj, - struct efi_device_path *device_path, - struct efi_device_path *file_path); +efi_status_t efi_setup_loaded_image(struct efi_device_path *device_path, + struct efi_device_path *file_path, + efi_handle_t *handle_ptr, + struct efi_loaded_image **info_ptr); efi_status_t efi_load_image_from_path(struct efi_device_path *file_path, void **buffer); /* Print information about a loaded image */ diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c index 3bcea647c8..730124a119 100644 --- a/lib/efi_loader/efi_boottime.c +++ b/lib/efi_loader/efi_boottime.c @@ -1478,18 +1478,34 @@ static efi_status_t EFIAPI efi_install_configuration_table_ext(efi_guid_t *guid, * * Return: status code */ -efi_status_t efi_setup_loaded_image( - struct efi_loaded_image *info, struct efi_object *obj, - struct efi_device_path *device_path, - struct efi_device_path *file_path) +efi_status_t efi_setup_loaded_image(struct efi_device_path *device_path, + struct efi_device_path *file_path, + efi_handle_t *handle_ptr, + struct efi_loaded_image **info_ptr) { efi_status_t ret; + struct efi_loaded_image *info; + struct efi_object *obj; + + info = calloc(1, sizeof(*info)); + if (!info) + return EFI_OUT_OF_RESOURCES; + obj = calloc(1, sizeof(*obj)); + if (!obj) { + free(info); + return EFI_OUT_OF_RESOURCES; + } /* Add internal object to object list */ efi_add_handle(obj); /* efi_exit() assumes that the handle points to the info */ obj->handle = info; + if (handle_ptr) + *handle_ptr = obj->handle; + if (info_ptr) + *info_ptr = info; + info->revision = EFI_LOADED_IMAGE_PROTOCOL_REVISION; info->file_path = file_path; info->system_table = &systab; @@ -1629,7 +1645,6 @@ static efi_status_t EFIAPI efi_load_image(bool boot_policy, efi_handle_t *image_handle) { struct efi_loaded_image *info; - struct efi_object *obj; efi_status_t ret; EFI_ENTRY("%d, %p, %pD, %p, %zd, %p", boot_policy, parent_image, @@ -1645,18 +1660,6 @@ static efi_status_t EFIAPI efi_load_image(bool boot_policy, goto error; } - info = calloc(1, sizeof(*info)); - if (!info) { - ret = EFI_OUT_OF_RESOURCES; - goto error; - } - obj = calloc(1, sizeof(*obj)); - if (!obj) { - free(info); - ret = EFI_OUT_OF_RESOURCES; - goto error; - } - if (!source_buffer) { struct efi_device_path *dp, *fp; @@ -1668,16 +1671,17 @@ static efi_status_t EFIAPI efi_load_image(bool boot_policy, * file parts: */ efi_dp_split_file_path(file_path, &dp, &fp); - ret = efi_setup_loaded_image(info, obj, dp, fp); + ret = efi_setup_loaded_image(dp, fp, image_handle, &info); if (ret != EFI_SUCCESS) goto failure; } else { /* In this case, file_path is the "device" path, i.e. * something like a HARDWARE_DEVICE:MEMORY_MAPPED */ - ret = efi_setup_loaded_image(info, obj, file_path, NULL); + ret = efi_setup_loaded_image(file_path, NULL, image_handle, + &info); if (ret != EFI_SUCCESS) - goto failure; + goto error; } info->reserved = efi_load_pe(source_buffer, info); if (!info->reserved) { @@ -1686,11 +1690,11 @@ static efi_status_t EFIAPI efi_load_image(bool boot_policy, } info->system_table = &systab; info->parent_handle = parent_image; - *image_handle = obj->handle; return EFI_EXIT(EFI_SUCCESS); failure: + efi_delete_handle(*image_handle); + *image_handle = NULL; free(info); - efi_delete_handle(obj); error: return EFI_EXIT(ret); } -- 2.18.0

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[U-Boot] [PATCH] configs: mx7: Remove CONFIG_DBG_MONITOR
by Fabio Estevam 17 Sep '18

17 Sep '18

Remove all CONFIG_DBG_MONITOR references as it is not used anywhere. Signed-off-by: Fabio Estevam <festevam(a)gmail.com> --- include/configs/cl-som-imx7.h | 2 -- include/configs/colibri-imx6ull.h | 1 - include/configs/colibri_imx7.h | 2 -- include/configs/mx7dsabresd.h | 1 - scripts/config_whitelist.txt | 1 - 5 files changed, 7 deletions(-) diff --git a/include/configs/cl-som-imx7.h b/include/configs/cl-som-imx7.h index 1b2eee3..f84a112 100644 --- a/include/configs/cl-som-imx7.h +++ b/include/configs/cl-som-imx7.h @@ -10,8 +10,6 @@ #include "mx7_common.h" -#define CONFIG_DBG_MONITOR - #define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR /* Size of malloc() pool */ diff --git a/include/configs/colibri-imx6ull.h b/include/configs/colibri-imx6ull.h index f2db039..7cf550c 100644 --- a/include/configs/colibri-imx6ull.h +++ b/include/configs/colibri-imx6ull.h @@ -13,7 +13,6 @@ #include "mx6_common.h" #define CONFIG_IOMUX_LPSR -/* #define CONFIG_DBG_MONITOR*/ #define PHYS_SDRAM_SIZE SZ_512M /* Size of malloc() pool */ diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h index 02849ba..c31cf28 100644 --- a/include/configs/colibri_imx7.h +++ b/include/configs/colibri_imx7.h @@ -13,8 +13,6 @@ #include "mx7_common.h" -/*#define CONFIG_DBG_MONITOR*/ - /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h index 87241ef..ad919a6 100644 --- a/include/configs/mx7dsabresd.h +++ b/include/configs/mx7dsabresd.h @@ -10,7 +10,6 @@ #include "mx7_common.h" -#define CONFIG_DBG_MONITOR #define PHYS_SDRAM_SIZE SZ_1G #define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 30c79a6..8de01da 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -310,7 +310,6 @@ CONFIG_D2NET_V2 CONFIG_DA850_AM18X_EVM CONFIG_DA850_EVM_MAX_CPU_CLK CONFIG_DBGU -CONFIG_DBG_MONITOR CONFIG_DB_784MP_GP CONFIG_DCACHE CONFIG_DCACHE_OFF -- 2.7.4

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