September 2018 - U-Boot

[U-Boot] [PATCH v2] spi: designware_spi: Add reset ctrl to driver
by Ley Foon Tan 20 Sep '18

20 Sep '18

Add code to reset all reset signals as in SPI DT node. A reset property is an optional feature, so only print out a warning and do not fail if a reset property is not present. If a reset property is discovered, then use it to deassert, thus bringing the IP out of reset. Release reset when _remove(). Signed-off-by: Ley Foon Tan <ley.foon.tan(a)intel.com> Acked-by: Marek Vasut <marex(a)denx.de> Reviewed-by: Jagan Teki <jagan(a)openedev.com> --- v2: - Fix multi-lines comment style --- drivers/spi/designware_spi.c | 43 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c index d8b73ea..5cca414 100644 --- a/drivers/spi/designware_spi.c +++ b/drivers/spi/designware_spi.c @@ -17,6 +17,7 @@ #include <malloc.h> #include <spi.h> #include <fdtdec.h> +#include <reset.h> #include <linux/compat.h> #include <linux/iopoll.h> #include <asm/io.h> @@ -111,6 +112,8 @@ struct dw_spi_priv { void *tx_end; void *rx; void *rx_end; + + struct reset_ctl_bulk resets; }; static inline u32 dw_read(struct dw_spi_priv *priv, u32 offset) @@ -231,6 +234,34 @@ err_rate: return -EINVAL; } +static int dw_spi_reset(struct udevice *bus) +{ + int ret; + struct dw_spi_priv *priv = dev_get_priv(bus); + + ret = reset_get_bulk(bus, &priv->resets); + if (ret) { + /* + * Return 0 if error due to !CONFIG_DM_RESET and reset + * DT property is not present. + */ + if (ret == -ENOENT || ret == -ENOTSUPP) + return 0; + + dev_warn(bus, "Can't get reset: %d\n", ret); + return ret; + } + + ret = reset_deassert_bulk(&priv->resets); + if (ret) { + reset_release_bulk(&priv->resets); + dev_err(bus, "Failed to reset: %d\n", ret); + return ret; + } + + return 0; +} + static int dw_spi_probe(struct udevice *bus) { struct dw_spi_platdata *plat = dev_get_platdata(bus); @@ -244,6 +275,10 @@ static int dw_spi_probe(struct udevice *bus) if (ret) return ret; + ret = dw_spi_reset(bus); + if (ret) + return ret; + /* Currently only bits_per_word == 8 supported */ priv->bits_per_word = 8; @@ -478,6 +513,13 @@ static int dw_spi_set_mode(struct udevice *bus, uint mode) return 0; } +static int dw_spi_remove(struct udevice *bus) +{ + struct dw_spi_priv *priv = dev_get_priv(bus); + + return reset_release_bulk(&priv->resets); +} + static const struct dm_spi_ops dw_spi_ops = { .xfer = dw_spi_xfer, .set_speed = dw_spi_set_speed, @@ -502,4 +544,5 @@ U_BOOT_DRIVER(dw_spi) = { .platdata_auto_alloc_size = sizeof(struct dw_spi_platdata), .priv_auto_alloc_size = sizeof(struct dw_spi_priv), .probe = dw_spi_probe, + .remove = dw_spi_remove, }; -- 2.2.2

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[U-Boot] [PULL] Please pull u-boot-imx
by Stefano Babic 20 Sep '18

20 Sep '18

Hi Tom, please pull from u-boot-imx with following changes: - changes in pico-* boards - fix imx6ull pinmux Thanks, Stefano The following changes since commit b57f1895b669e3fbdca486e7c40dfea00f22bb93: Merge git://git.denx.de/u-boot-x86 (2018-09-17 08:04:25 -0400) are available in the Git repository at: git://www.denx.de/git/u-boot-imx.git master for you to fetch changes up to f7df8932ccaec97c8c422de8adadb3a0491543ed: pico-imx7d: Add a new defconfig with PICO-Hobbit selected (2018-09-18 16:55:21 +0200) ---------------------------------------------------------------- Fabio Estevam (8): pico-imx6ul: Convert to distro config pico-imx6ul: Convert to SPL pico-imx6ul: Add fastboot support pico-imx6ul: Add bmode support pico-imx6ul: Add support for the 512MB module pico-imx6ul: Update the README file wandboard: README: Include the mx6qp variant in the list pico-imx6ul: Add instructions for booting in Falcon mode Heiko Schocher (1): imx: imx6ull: fix pinmux input_val for uart5 rx pin Lukasz Majewski (4): ARM: bootscript: Remove hard-coded rootpath from K+P's tpcboot.cmd ARM: bootscript: Replace tftpboot with dhcp when downloading kernel ARM: bootscript: Fix the nfsargs and addip in K+P's tpcboot.cmd ARM: bootscript: For nfsargs only use rootpath (and remove not needed serverip) Otavio Salvador (13): pico-imx6ul: Sync defconfig with new changes pico-imx6ul: Add bootmenu to choose the baseboard pico-imx6ul: Improve default DFU settings pico-imx6ul: Sync README with pico-imx7d pico-imx6ul: Add new pico-hobbit config pico-imx6ul: Remove CONFIG_FSL_USDHC from .h pico-imx6ul: Add Falcon mode support pico-imx6ul: Fix TechNexion spelling on MAINTAINERS file pico-imx6ul: Add PICO-Pi baseboard support pico-imx6ul: Add a new defconfig with PICO-Pi selected pico-imx7d: Fix TechNexion spelling on MAINTAINERS file pico-imx7d: Add PICO-Hobbit baseboard support pico-imx7d: Add a new defconfig with PICO-Hobbit selected Stefano Babic (1): Merge branch 'master' of git://git.denx.de/u-boot into master arch/arm/include/asm/arch-mx6/mx6ull_pins.h | 2 +- arch/arm/mach-imx/mx6/Kconfig | 1 + board/k+p/bootscripts/tpcboot.cmd | 12 +++----- board/technexion/pico-imx6ul/MAINTAINERS | 12 +++++++- board/technexion/pico-imx6ul/Makefile | 2 +- board/technexion/pico-imx6ul/README | 138 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++------------ board/technexion/pico-imx6ul/spl.c | 144 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ board/technexion/pico-imx7d/MAINTAINERS | 9 ++++-- board/wandboard/README | 2 +- configs/pico-hobbit-imx6ul_defconfig | 53 ++++++++++++++++++++++++++++++++++ configs/pico-hobbit-imx7d_defconfig | 61 +++++++++++++++++++++++++++++++++++++++ configs/pico-imx6ul_defconfig | 39 +++++++++++++++---------- configs/pico-pi-imx6ul_defconfig | 53 ++++++++++++++++++++++++++++++++++ include/configs/pico-imx6ul.h | 107 +++++++++++++++++++++++++++++++++----------------------------------- include/configs/pico-imx7d.h | 5 +++- 15 files changed, 536 insertions(+), 104 deletions(-) create mode 100644 board/technexion/pico-imx6ul/spl.c create mode 100644 configs/pico-hobbit-imx6ul_defconfig create mode 100644 configs/pico-hobbit-imx7d_defconfig create mode 100644 configs/pico-pi-imx6ul_defconfig -- ===================================================================== DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic(a)denx.de =====================================================================

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[U-Boot] Please pull u-boot-marvell/master
by Stefan Roese 20 Sep '18

20 Sep '18

Hi Tom, please pull the Marvell U-Boot patches with these changes: - Multiples updates to the turris boards / platform - Changes / enhancements to the Marvell PHY drivers, mainly to support the turris platform - Many fixes and enhancements to the pxa3xx NAND driver - Fixes for the UART boot mode in kwboot - Misc minor changes to other 32bit and 64bit boards Thanks, Stefan The following changes since commit b57f1895b669e3fbdca486e7c40dfea00f22bb93: Merge git://git.denx.de/u-boot-x86 (2018-09-17 08:04:25 -0400) are available in the Git repository at: git://www.denx.de/git/u-boot-marvell.git for you to fetch changes up to e32ac37119394f2d3c579b2cdd549bed59fb583f: arm: mvebu: clearfog: enable eMMC boot partitions support (2018-09-19 14:00:06 +0200) ---------------------------------------------------------------- Baruch Siach (4): doc/git-mailrc: add Stefan Roese to the kirkwood alias arm64: mvebu: armada-8k: support environment in SD/eMMC dts: mvebu: mcbin: drop redundant SD slot node arm: mvebu: clearfog: enable eMMC boot partitions support Boris Brezillon (1): mtd: nand: pxa3xx: Fix READOOB implementation Chris Packham (2): Revert "arm: mvebu: fix boot from UART when in fallback mode" ARM: mach-mvebu: handle fall-back to UART boot David Sniatkiwicz (1): fix: nand: pxa3xx: Add WA for eliminating flash ready timeout Evgeni Dobrev (1): Kirkwood: NAS220: remove bootdelay from CONFIG_EXTRA_ENV_SETTINGS Jon Nettleton (1): tools: kwboot: Make kwboot more robust on a38x Konstantin Porotchkin (7): mtd: nand: pxa3xx: add support for Toshiba flash fix: nand: Replace hardcoded page chunk size with calculated one nand: pxa3xx: cosmetic: add comments to the timing layout structures nand: pxa3xx: Add support for 8KB page 4 and 8 bit ECC NAND fix: env: Fix the SPI flash device setup for DM mode fix: mvebu: Add SPI parameters for environment setup fix: cmd: mvebu: Exclude mvebu commands from SPL builds Marek Behún (6): phy: marvell: Support changing SERDES map in board file clk: armada-37xx-periph: Support changing clock parent and rate board: turris_mox: Fix watchdog macro name board: turris_mox: Enable PCI in defconfig arch/arm/dts: Update Turris Mox device tree board: turris_mox: Fixup U-Boot's device tree if PCIe connected Ofer Heifetz (10): mtd: nand: pxa3xx_nand: Increase initial buffer size mtd: nand: pxa3xx_nand: use nand_to_mtd() mtd: nand: pxa3xx_nand: sync pxa3xx_nand_set_sdr_timing() mtd: nand: pxa3xx_nand: fix early spurious interrupt mtd: nand: pxa3xx-nand: fix random command timeouts nand: pxa3xx: Increase READ_ID buffer and make the size static mtd: pxa3xx_nand: Increase the initial chunk size mtd: pxa3xx_nand: Fix initial controller configuration mtd: pxa3xx_nand: Simplify pxa3xx_nand_scan mtd: nand: pxa3xx_nand: add support for partial chunks Rabeeh Khoury (1): phy: marvell: add SATA comphy RX/TX polarity invert support Victor Axelrod (1): mtd: nand: pxa3xx: add support for 2KB 8-bit flash MAINTAINERS | 3 +- arch/arm/dts/armada-3720-turris-mox.dts | 17 +- arch/arm/dts/armada-8040-mcbin.dts | 8 - arch/arm/mach-mvebu/armada8k/cpu.c | 24 ++ arch/arm/mach-mvebu/include/mach/soc.h | 8 +- arch/arm/mach-mvebu/spl.c | 15 +- board/CZ.NIC/turris_mox/turris_mox.c | 88 ++++- cmd/Makefile | 3 +- configs/turris_mox_defconfig | 6 + doc/git-mailrc | 2 +- drivers/clk/mvebu/armada-37xx-periph.c | 130 ++++++- drivers/mtd/nand/pxa3xx_nand.c | 447 ++++++++++++++++-------- drivers/phy/marvell/comphy_a3700.h | 2 +- drivers/phy/marvell/comphy_core.c | 12 +- drivers/phy/marvell/{comphy.h => comphy_core.h} | 16 +- drivers/phy/marvell/comphy_cp110.c | 21 +- drivers/phy/marvell/comphy_hpipe.h | 6 + drivers/phy/marvell/comphy_mux.c | 2 +- env/sf.c | 3 +- include/configs/clearfog.h | 4 + include/configs/db-88f6820-gp.h | 6 + include/configs/mvebu_armada-8k.h | 3 + include/configs/nas220.h | 1 - include/mvebu/comphy.h | 22 ++ tools/kwboot.c | 14 +- 25 files changed, 664 insertions(+), 199 deletions(-) rename drivers/phy/marvell/{comphy.h => comphy_core.h} (96%) create mode 100644 include/mvebu/comphy.h

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[U-Boot] [PATCH v3 1/1] ARM: opos6ul: make the board boot again
by Sébastien Szymanski 20 Sep '18

20 Sep '18

Commit 9faa43c4b5e5 ("ARM: dts: i.MX6UL: U-Boot specific dts for u-boot, dm-spl") removes the u-boot,dm-spl properties from the imx6ul.dtsi file and breaks the OPOS6UL board. Add the u-boot,dm-spl properties into *-u-boot.dts files to make the board boot again. Fixes: commit 9faa43c4b5e5 ("ARM: dts: i.MX6UL: U-Boot specific dts for u-boot, dm-spl") Signed-off-by: Sébastien Szymanski <sebastien.szymanski(a)armadeus.com> --- Changes for v3: - use the automatic inclusion of -u-boot.dtsi mechanism of U-Boot. Changes for v2: - put u-boot,dm-spl properties into -u-boot.dts files arch/arm/dts/imx6ul-opos6ul-u-boot.dtsi | 28 ++++++++++++++++++++++++++++ arch/arm/dts/imx6ul-opos6ul.dtsi | 2 -- arch/arm/dts/imx6ul-opos6uldev-u-boot.dtsi | 24 ++++++++++++++++++++++++ arch/arm/dts/imx6ul-opos6uldev.dts | 2 -- 4 files changed, 52 insertions(+), 4 deletions(-) create mode 100644 arch/arm/dts/imx6ul-opos6ul-u-boot.dtsi create mode 100644 arch/arm/dts/imx6ul-opos6uldev-u-boot.dtsi diff --git a/arch/arm/dts/imx6ul-opos6ul-u-boot.dtsi b/arch/arm/dts/imx6ul-opos6ul-u-boot.dtsi new file mode 100644 index 0000000000..4918de388e --- /dev/null +++ b/arch/arm/dts/imx6ul-opos6ul-u-boot.dtsi @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source extras for U-Boot for the OPOS6UL SoM + * + * Copyright (C) 2018 Armadeus Systems <support(a)armadeus.com> + */ + +/ { + soc { + u-boot,dm-spl; + }; +}; + +&aips2 { + u-boot,dm-spl; +}; + +&iomuxc { + u-boot,dm-spl; +}; + +&pinctrl_usdhc1 { + u-boot,dm-spl; +}; + +&usdhc1 { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/imx6ul-opos6ul.dtsi b/arch/arm/dts/imx6ul-opos6ul.dtsi index d51ad4de20..8f16a0a81c 100644 --- a/arch/arm/dts/imx6ul-opos6ul.dtsi +++ b/arch/arm/dts/imx6ul-opos6ul.dtsi @@ -99,7 +99,6 @@ /* eMMC */ &usdhc1 { - u-boot,dm-spl; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc1>; bus-width = <8>; @@ -162,7 +161,6 @@ }; pinctrl_usdhc1: usdhc1grp { - u-boot,dm-spl; fsl,pins = < MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 diff --git a/arch/arm/dts/imx6ul-opos6uldev-u-boot.dtsi b/arch/arm/dts/imx6ul-opos6uldev-u-boot.dtsi new file mode 100644 index 0000000000..da8b0392ef --- /dev/null +++ b/arch/arm/dts/imx6ul-opos6uldev-u-boot.dtsi @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source extras for U-Boot for the OPOS6ULDev board + * + * Copyright (C) 2018 Armadeus Systems <support(a)armadeus.com> + */ + +#include "imx6ul-opos6ul-u-boot.dtsi" + +&aips1 { + u-boot,dm-spl; + + spba-bus@02000000 { + u-boot,dm-spl; + }; +}; + +&pinctrl_uart1 { + u-boot,dm-spl; +}; + +&uart1 { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/imx6ul-opos6uldev.dts b/arch/arm/dts/imx6ul-opos6uldev.dts index 9a51d1e54f..0e59ee57fd 100644 --- a/arch/arm/dts/imx6ul-opos6uldev.dts +++ b/arch/arm/dts/imx6ul-opos6uldev.dts @@ -228,7 +228,6 @@ }; &uart1 { - u-boot,dm-spl; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; status = "okay"; @@ -374,7 +373,6 @@ }; pinctrl_uart1: uart1grp { - u-boot,dm-spl; fsl,pins = < MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 -- 2.16.4

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[U-Boot] [PATCH v2] spi: designware_spi: Disable and free clock when remove driver
by Ley Foon Tan 20 Sep '18

20 Sep '18

Disable and free clock when remove driver. Signed-off-by: Ley Foon Tan <ley.foon.tan(a)intel.com> --- v2: - Check return value from clk_free() and return 0 when exit function --- drivers/spi/designware_spi.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c index 5cca414..8f0c602 100644 --- a/drivers/spi/designware_spi.c +++ b/drivers/spi/designware_spi.c @@ -516,8 +516,22 @@ static int dw_spi_set_mode(struct udevice *bus, uint mode) static int dw_spi_remove(struct udevice *bus) { struct dw_spi_priv *priv = dev_get_priv(bus); + int ret; + + ret = reset_release_bulk(&priv->resets); + if (ret) + return ret; - return reset_release_bulk(&priv->resets); +#if CONFIG_IS_ENABLED(CLK) + ret = clk_disable(&priv->clk); + if (ret) + return ret; + + ret = clk_free(&priv->clk); + if (ret) + return ret; +#endif + return 0; } static const struct dm_spi_ops dw_spi_ops = { -- 2.2.2

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[U-Boot] build u-boot failed with config CONFIG_ARMV8_PSCI by aarch linux gcc 8.1
by Li, Meng 20 Sep '18

20 Sep '18

Hi All maintainers, Could you please help to have a look whether below issue is valuable? I got u-boot source code from https://github.com/u-boot/u-boot.git, branch is master. I got toolchain from https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/8.1.0/ I built stratix10(socfpga) platform with below commands: export CROSS_COMPILE=xxx/gcc-8.1.0-nolibc/aarch64-linux/bin/aarch64-linux- export ARCH=arm64 make mrproper make socfpga_stratix10_defconfig make there will be below error: LD u-boot /home/wrsadmin/Project/Native/SDK/Altera-Arria-10/gcc-8.1.0-nolibc/aarch64-linux/bin/aarch64-linux-ld.bfd: arch/arm/cpu/armv8/built-in.o: relocation R_AARCH64_ABS32 against `psci_cpu_suspend' can not be used when making a shared object /home/wrsadmin/Project/Native/SDK/Altera-Arria-10/gcc-8.1.0-nolibc/aarch64-linux/bin/aarch64-linux-ld.bfd: arch/arm/mach-socfpga/built-in.o: relocation R_AARCH64_ABS32 against `el3_exception_vectors' can not be used when making a shared object arch/arm/mach-socfpga/built-in.o: In function `wfi_loop': smmu_s10.c:(._secure.text+0x758): dangerous relocation: unsupported relocation smmu_s10.c:(._secure.text+0x760): dangerous relocation: unsupported relocation arch/arm/mach-socfpga/built-in.o:(._secure_svc_tbl_entries+0x8): dangerous relocation: unsupported relocation arch/arm/mach-socfpga/built-in.o:(._secure_svc_tbl_entries+0x18): dangerous relocation: unsupported relocation arch/arm/mach-socfpga/built-in.o:(._secure_svc_tbl_entries+0x28): dangerous relocation: unsupported relocation arch/arm/mach-socfpga/built-in.o:(._secure_svc_tbl_entries+0x38): dangerous relocation: unsupported relocation arch/arm/mach-socfpga/built-in.o:(._secure_svc_tbl_entries+0x48): dangerous relocation: unsupported relocation arch/arm/mach-socfpga/built-in.o:(._secure_svc_tbl_entries+0x58): dangerous relocation: unsupported relocation arch/arm/mach-socfpga/built-in.o:(._secure_svc_tbl_entries+0x68): dangerous relocation: unsupported relocation arch/arm/mach-socfpga/built-in.o:(._secure_svc_tbl_entries+0x78): dangerous relocation: unsupported relocation arch/arm/mach-socfpga/built-in.o:(._secure_svc_tbl_entries+0x88): dangerous relocation: unsupported relocation arch/arm/mach-socfpga/built-in.o:(._secure_svc_tbl_entries+0x98): dangerous relocation: unsupported relocation arch/arm/mach-socfpga/built-in.o:/home/wrsadmin/Project/Native/SDK/Altera-Arria-10/u-boot-socfpga/arch/arm/mach-socfpga/clock_manager.c:68:(.u_boot_list_2_cmd_2_clocks+0x0): dangerous relocation: unsupported relocation arch/arm/mach-socfpga/built-in.o:(.u_boot_list_2_cmd_2_clocks+0x10): dangerous relocation: unsupported relocation arch/arm/mach-socfpga/built-in.o:(.u_boot_list_2_cmd_2_clocks+0x18): dangerous relocation: unsupported relocation arch/arm/mach-socfpga/built-in.o:(.u_boot_list_2_cmd_2_clocks+0x20): dangerous relocation: unsupported relocation arch/arm/mach-socfpga/built-in.o:/home/wrsadmin/Project/Native/SDK/Altera-Arria-10/u-boot-socfpga/arch/arm/mach-socfpga/misc_s10.c:382:(.u_boot_list_2_cmd_2_bridge+0x0): dangerous relocation: unsupported relocation arch/arm/mach-socfpga/built-in.o:(.u_boot_list_2_cmd_2_bridge+0x10): dangerous relocation: unsupported relocation arch/arm/mach-socfpga/built-in.o:(.u_boot_list_2_cmd_2_bridge+0x18): dangerous relocation: unsupported relocation arch/arm/mach-socfpga/built-in.o:(.u_boot_list_2_cmd_2_bridge+0x20): dangerous relocation: unsupported relocation arch/arm/mach-socfpga/built-in.o:(.data.mem_map+0x0): dangerous relocation: unsupported relocation arch/arm/mach-socfpga/built-in.o:/home/wrsadmin/Project/Native/SDK/Altera-Arria-10/u-boot-socfpga/arch/arm/mach-socfpga/rsu_s10.c:262:(.u_boot_list_2_cmd_2_rsu+0x0): dangerous relocation: unsupported relocation arch/arm/mach-socfpga/built-in.o:(.u_boot_list_2_cmd_2_rsu+0x10): dangerous relocation: unsupported relocation arch/arm/mach-socfpga/built-in.o:(.u_boot_list_2_cmd_2_rsu+0x18): dangerous relocation: unsupported relocation arch/arm/mach-socfpga/built-in.o:(.u_boot_list_2_cmd_2_rsu+0x20): dangerous relocation: unsupported relocation Makefile:1255: recipe for target 'u-boot' failed make: *** [u-boot] Error 1 I found out this build error is caused by enable CONFIG_ARMV8_PSCI. Could you please tell me whether you also encountered this issue before? I try lower version GCC toolchain, it works fine. Thanks, Limeng

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Re: [U-Boot] [RESEND PATCH v2 15/15] riscv: Move do_reset() to a common place
by Rick Chen 20 Sep '18

20 Sep '18

> From: Bin Meng [mailto:bmeng.cn@gmail.com] > Sent: Tuesday, September 11, 2018 12:55 PM > To: Rick Jian-Zhi Chen(陳建志); U-Boot Mailing List > Cc: Lukas Auer > Subject: [RESEND PATCH v2 15/15] riscv: Move do_reset() to a common place > > We don't have a reset method on any RISC-V board yet. Instead of adding the > same 'unsupported' message for each CPU variant it might make more sense to > add a generic do_reset function for all CPU variants to lib/, similar to the one for > ARM (arch/arm/lib/reset.c). > > Suggested-by: Lukas Auer <lukas.auer(a)aisec.fraunhofer.de> > Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> > > --- > > Changes in v2: > - new patch to move do_reset() to a common place > > arch/riscv/cpu/ax25/cpu.c | 9 --------- arch/riscv/cpu/qemu/cpu.c | 8 -------- > arch/riscv/lib/Makefile | 1 + > arch/riscv/lib/reset.c | 14 ++++++++++++++ > 4 files changed, 15 insertions(+), 17 deletions(-) create mode 100644 > arch/riscv/lib/reset.c > > diff --git a/arch/riscv/cpu/ax25/cpu.c b/arch/riscv/cpu/ax25/cpu.c index > ab05b57..fddcc15 100644 > --- a/arch/riscv/cpu/ax25/cpu.c > +++ b/arch/riscv/cpu/ax25/cpu.c > @@ -6,9 +6,6 @@ > > /* CPU specific code */ > #include <common.h> > -#include <command.h> > -#include <watchdog.h> > -#include <asm/cache.h> > > /* > * cleanup_before_linux() is called just before we call linux @@ -24,9 +21,3 > @@ int cleanup_before_linux(void) > > return 0; > } > - > -int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ > - disable_interrupts(); > - panic("ax25-ae350 wdt not support yet.\n"); > -} > diff --git a/arch/riscv/cpu/qemu/cpu.c b/arch/riscv/cpu/qemu/cpu.c index > a064639..6c7a327 100644 > --- a/arch/riscv/cpu/qemu/cpu.c > +++ b/arch/riscv/cpu/qemu/cpu.c > @@ -4,7 +4,6 @@ > */ > > #include <common.h> > -#include <command.h> > > /* > * cleanup_before_linux() is called just before we call linux @@ -20,10 +19,3 > @@ int cleanup_before_linux(void) > > return 0; > } > - > -int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ > - printf("reset unsupported yet\n"); > - > - return 0; > -} > diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile index > cc562f9..b58db89 100644 > --- a/arch/riscv/lib/Makefile > +++ b/arch/riscv/lib/Makefile > @@ -10,6 +10,7 @@ obj-$(CONFIG_CMD_BOOTM) += bootm.o > obj-$(CONFIG_CMD_GO) += boot.o > obj-y += cache.o > obj-y += interrupts.o > +obj-y += reset.o > obj-y += setjmp.o > > # For building EFI apps > diff --git a/arch/riscv/lib/reset.c b/arch/riscv/lib/reset.c new file mode 100644 > index 0000000..5d9b99c > --- /dev/null > +++ b/arch/riscv/lib/reset.c > @@ -0,0 +1,14 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright (C) 2018, Bin Meng <bmeng.cn(a)gmail.com> */ > + > +#include <common.h> > +#include <command.h> > + > +int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) > +{ > + printf("reset unsupported yet\n"); > + > + return 0; > +} Reviewed-by: Rick Chen <rick(a)andestech.com> > -- > 2.7.4

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Re: [U-Boot] [RESEND PATCH v2 10/15] riscv: bootm: Pass mhartid CSR value to kernel
by Rick Chen 20 Sep '18

20 Sep '18

> From: Bin Meng [mailto:bmeng.cn@gmail.com] > Sent: Tuesday, September 11, 2018 12:55 PM > To: Rick Jian-Zhi Chen(陳建志); U-Boot Mailing List > Cc: Lukas Auer > Subject: [RESEND PATCH v2 10/15] riscv: bootm: Pass mhartid CSR value to kernel > > So far this is hardcoded to zero, and we should read the value from mhartid CSR > and pass it to Linux kernel. > > Suggested-by: Lukas Auer <lukas.auer(a)aisec.fraunhofer.de> > Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> > > --- > > Changes in v2: > - new patch to pass mhartid CSR value to kernel > > arch/riscv/lib/bootm.c | 5 +++-- > 1 file changed, 3 insertions(+), 2 deletions(-) > > > diff --git a/arch/riscv/lib/bootm.c b/arch/riscv/lib/bootm.c index > 6893108..a7a9fb9 100644 > --- a/arch/riscv/lib/bootm.c > +++ b/arch/riscv/lib/bootm.c > @@ -11,6 +11,7 @@ > #include <image.h> > #include <u-boot/zlib.h> > #include <asm/byteorder.h> > +#include <asm/csr.h> > > DECLARE_GLOBAL_DATA_PTR; > > @@ -57,9 +58,9 @@ int do_bootm_linux(int flag, int argc, char *argv[], > bootm_headers_t *images) > printf("\nStarting kernel ...\n\n"); > > cleanup_before_linux(); > - /* TODO: hardcode the hart id to zero for now */ > + > if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) > - kernel(0, images->ft_addr); > + kernel(csr_read(mhartid), images->ft_addr); > > /* does not return */ > Reviewed-by: Rick Chen <rick(a)andestech.com> > > -- > 2.7.4

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Re: [U-Boot] [RESEND PATCH v2 00/15] riscv: Add QEMU virt board support
by Rick Chen 20 Sep '18

20 Sep '18

> Hi Rick, > > On Tue, Sep 11, 2018 at 12:50 PM Bin Meng <bmeng.cn(a)gmail.com> wrote: > > > > This series adds QEMU RISC-V 'virt' board target support, with the > > hope of helping people easily test U-Boot on RISC-V. > > > > Some existing RISC-V codes have been changed to make it easily to > > support new targets. Some spotted coding style issues are fixed. > > > > This series is available at u-boot-x86/riscv-working for testing. > > > > Resend v2 to rebase on top of v2018.09 release with Tom's tree on > > github, as the git.denx.de is still out of sync ... > > > > Changes in v2: > > - Change Linux kernel entry parameters' type to support 32/64 bit > > - new patch to remove CSR read/write defines in encoding.h > > - new patch to pass mhartid CSR value to kernel > > - new patch to move do_reset() to a common place > > Any comments for the v2? Hi Bin Sorry for late response! I have reviewed the v2 patch sets, it looks fine. And also verify the riscv-linux booting feature on ax25-ae350 board via bootm command. The verification is OK. :) B.R Rick > > Regards, > Bin

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Re: [U-Boot] [RESEND PATCH v2 09/15] riscv: Remove CSR read/write defines in encoding.h
by Rick Chen 20 Sep '18

20 Sep '18

> From: Bin Meng [mailto:bmeng.cn@gmail.com] > Sent: Tuesday, September 11, 2018 12:55 PM > To: Rick Jian-Zhi Chen(陳建志); U-Boot Mailing List > Cc: Lukas Auer > Subject: [RESEND PATCH v2 09/15] riscv: Remove CSR read/write defines in > encoding.h > > There is no reason to keep two versions of CSR read/write defines in encoding.h. > We already have one set of defines in csr.h, which is from Linux kernel, and let's > drop the one in encoding.h. > > Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> > > --- > > Changes in v2: > - new patch to remove CSR read/write defines in encoding.h > > arch/riscv/include/asm/encoding.h | 50 ++++----------------------------------- > 1 file changed, 4 insertions(+), 46 deletions(-) > > diff --git a/arch/riscv/include/asm/encoding.h > b/arch/riscv/include/asm/encoding.h > index f237a72..9ea50ce 100644 > --- a/arch/riscv/include/asm/encoding.h > +++ b/arch/riscv/include/asm/encoding.h > @@ -128,6 +128,7 @@ > ((SUPERVISOR) ? PTE_SR(PTE) : PTE_UR(PTE))) > > #ifdef __riscv > + > #ifdef CONFIG_64BIT > # define MSTATUS_SD MSTATUS64_SD > # define SSTATUS_SD SSTATUS64_SD > @@ -141,53 +142,10 @@ > # define MCAUSE_INT MCAUSE32_INT > # define MCAUSE_CAUSE MCAUSE32_CAUSE > #endif > + > #define RISCV_PGSHIFT 12 > #define RISCV_PGSIZE BIT(RISCV_PGSHIFT) > > -#ifndef __ASSEMBLER__ > - > -#ifdef __GNUC__ > - > -#define read_csr(reg) ({ unsigned long __tmp; \ > - asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ > - __tmp; }) > - > -#define write_csr(reg, _val) ({ \ > -typeof(_val) (val) = (_val); \ > -if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ > - asm volatile ("csrw " #reg ", %0" :: "i"(val)); \ > -else \ > - asm volatile ("csrw " #reg ", %0" :: "r"(val)); }) > - > -#define swap_csr(reg, _val) ({ unsigned long __tmp; \ > -typeof(_val) (val) = (_val); \ > -if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ > - asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "i"(val)); \ > -else \ > - asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \ > - __tmp; }) > - > -#define set_csr(reg, _bit) ({ unsigned long __tmp; \ > -typeof(_bit) (bit) = (_bit); \ > -if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ > - asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ > -else \ > - asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ > - __tmp; }) > - > -#define clear_csr(reg, _bit) ({ unsigned long __tmp; \ > -typeof(_bit) (bit) = (_bit); \ > -if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ > - asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ > -else \ > - asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ > - __tmp; }) > - > -#define rdtime() read_csr(time) > -#define rdcycle() read_csr(cycle) > -#define rdinstret() read_csr(instret) > +#endif /* __riscv */ > > -#endif > -#endif > -#endif > -#endif > +#endif /* RISCV_CSR_ENCODING_H */ Reviewed-by: Rick Chen <rick(a)andestech.com> > -- > 2.7.4

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